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path: root/drivers/net/phy
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2019-04-19net: mdio: rename mdio_device reset to reset_gpioDavid Bauer3-7/+7
This renames the GPIO reset of mdio devices from 'reset' to 'reset_gpio' to better differentiate between GPIO and reset-controller driven reset line. Signed-off-by: David Bauer <mail@david-bauer.net> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-04-19net: phy: add support for reset-controllerDavid Bauer2-4/+36
This commit adds support for PHY reset pins handled by a reset controller. Signed-off-by: David Bauer <mail@david-bauer.net> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-04-19net: phy: remove dead code from phy_sanitize_settingsHeiner Kallweit1-4/+0
phy_sanitize_settings() is called from phy_start_aneg() only, and only if phydev->autoneg isn't set. Therefore the removed code does nothing. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-04-19net: phy: don't set autoneg if it's not supportedHeiner Kallweit1-0/+4
In phy_device_create() we set phydev->autoneg = 1. This isn't changed even if the PHY doesn't support autoneg. This seems to affect very few PHY's, and they disable phydev->autoneg in their config_init callback. So it's more of an improvement, therefore net-next. The patch also wouldn't apply to older kernel versions because the link mode bitmaps have been introduced recently. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-04-17net: phy: micrel: add Asym Pause workaroundAntoine Tenart1-1/+26
The Micrel KSZ9031 PHY may fail to establish a link when the Asymmetric Pause capability is set. This issue is described in a Silicon Errata (DS80000691D or DS80000692D), which advises to always disable the capability. This patch implements the workaround by defining a KSZ9031 specific get_feature callback to force the Asymmetric Pause capability bit to be cleared. This fixes issues where the link would not come up at boot time, or when the Asym Pause bit was set later on. Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-04-16net: phy: switch drivers to use dynamic feature detectionHeiner Kallweit30-120/+120
Recently genphy_read_abilities() has been added that dynamically detects clause 22 PHY abilities. I *think* this detection should work with all supported PHY's, at least for the ones with basic features sets, i.e. PHY_BASIC_FEATURES and PHY_GBIT_FEATURES. So let's remove setting these features explicitly and rely on phylib feature detection. I don't have access to most of these PHY's, therefore I'd appreciate regression testing. v2: - make the feature constant a comment so that readers know which features are supported by the respective PHY Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-04-14phy: warn if phylib and ethtool PHY mode definitions are out of syncHeiner Kallweit1-0/+5
If new PHY modes are added people may miss to update all relevant places in the kernel. Therefore add a build bug check for new modes in enum ethtool_link_mode_bit_indices that haven't been added to phylib yet. Suggested-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-04-14net: phy: add support for new modes in phylibHeiner Kallweit1-0/+18
Recently new modes have been added to ethtool.h, but the related extension to phylib hasn't been done yet. So add support for these modes. v2: - add missing 100Gbps and 50Gbps modes Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-04-14net: phy: shrink PHY settings arrayHeiner Kallweit1-202/+45
The definition of array settings[] is quite lengthy meanwhile. Add a macro to shrink the definition. v2: - Fix an indentation issue Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-04-09net: phy: remove unnecessary callback settings in C45 driversHeiner Kallweit2-15/+0
genphy_c45_aneg_done() is used by phylib as fallback for c45 PHY's if callback aneg_done isn't defined. So we don't have to set this explicitly. Same for genphy_c45_pma_read_abilities(). Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-04-09net: phy: fix setting autoneg_complete in genphy_update_linkHeiner Kallweit1-6/+4
The original patch didn't set phydev->autoneg_complete in one exit path. Fix this. Fixes: 4950c2ba49cc ("net: phy: fix autoneg mismatch case in genphy_read_status") Reported-by: Simon Horman <horms@verge.net.au> Tested-by: Simon Horman <horms@verge.net.au> Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-04-09net: phy: replace genphy_10g_driver with genphy_c45_driverHeiner Kallweit2-22/+11
Recently a number of generic functions for Clause 45 PHY's has been added. So let's replace the old very limited genphy_10g_driver with a genphy_c45_driver. This driver isn't limited to 10G, however it's worth to be noted that Clause 45 doesn't cover 1000Base-T. For using 1000Base-T with a Clause 45 PHY a dedicated PHY driver using vendor registers is needed. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-04-09net: phy: improve link partner capability detectionHeiner Kallweit1-4/+8
genphy_read_status() so far checks phydev->supported, not the actual PHY capabilities. This can make a difference if the supported speeds have been limited by of_set_phy_supported() or phy_set_max_speed(). It seems that this issue only affects the link partner advertisements as displayed by ethtool. Also this patch wouldn't apply to older kernels because linkmode bitmaps have been introduced recently. Therefore net-next. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-04-07net: phy: meson-gxl: clean-up gxl variant driverJerome Brunet1-4/+2
The purpose of this change is to align the gxl and g12a driver declaration. Like on the g12a variant, remove genphy_aneg_done() from the driver declaration as the net phy framework will default to it anyway. Also, the gxl phy id should be an exact match as well, so let's change this and use the macro provided. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-04-07net: phy: meson-gxl: add g12a supportJerome Brunet1-0/+11
The g12a SoC family uses the type of internal PHY that was used on the gxl family. The quirks of gxl family, like the LPA register corruption, appear to have been resolved on this new SoC generation. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-04-07net: phy: add amlogic g12a mdio mux supportJerome Brunet3-0/+392
Add support for the mdio mux and internal phy glue of the g12a SoC family Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> # clk parts Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-04-05net: phy: realtek: remove setting callback get_features and use phylib fallbackHeiner Kallweit1-10/+0
Now that phylib uses genphy_read_abilities() as fallback, we don't have to set callback get_features any longer. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-04-05net: phy: allow a PHY driver to define neither features nor get_featuresHeiner Kallweit1-7/+12
Meanwhile we have generic functions for reading the abilities of Clause 22 / 45 PHY's. This allows to use them as fallback in case callback get_features isn't set. Benefit is the reduction of boilerplate code in PHY drivers. v2: - adjust the comment in phy_driver_register to match the code Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-04-04net: phy: fix autoneg mismatch case in genphy_read_statusHeiner Kallweit1-5/+3
The original patch didn't consider the case that autoneg process finishes successfully but both link partners have no mode in common. In this case there's no link, nevertheless we may be interested in what the link partner advertised. Like phydev->link we set phydev->autoneg_complete in genphy_update_link() and use the stored value in genphy_read_status(). This way we don't have to read register BMSR again. Fixes: b6163f194c69 ("net: phy: improve genphy_read_status") Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-04-04net: phy: marvell10g: add the suspend/resume callbacks for the 88x2210Antoine Tenart1-0/+2
When the 88x2110 PHY support was added, the suspend and resume callbacks were forgotten. This patch adds them to the 88x2110 PHY callback definition. Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-04-04net: phy: marvell10g: implement suspend/resume callbacksAntoine Tenart1-1/+11
This patch adds the suspend/resume callbacks for Marvell 10G PHYs. The three PCS (base-t, base-r and 1000base-x) are set in low power (the PCS are powered down) when the PHY isn't used. Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com> Reviewed-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-04-02net: phy: deal properly with autoneg incomplete in genphy_c45_read_lpaHeiner Kallweit1-0/+11
The link partner advertisement registers are not guaranteed to contain valid values if autoneg is incomplete. Therefore, if MDIO_AN_STAT1_COMPLETE isn't set, let's clear all link partner capability bits. This also avoids unnecessary register reads if link is down and phylib is in polling mode. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-04-02net: phy: use c45 standard to detect link partner autoneg capabilityHeiner Kallweit1-1/+8
Currently mii_lpa_mod_linkmode_lpa_t() checks bit LPA_LPACK to detect whether link partner supports autoneg. This doesn't work correctly at least on Aquantia AQCS109 when it negotiates 1000Base-T2 mode. The "link partner is autoneg-capable" bit as defined by clause 45 is set however. Better let's switch in general to use the clause 45 standard for link partner autoneg detection. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-04-02net: phy: realtek: use genphy_read_abilitiesHeiner Kallweit1-24/+12
Use new function genphy_read_abilities(). This allows to remove all calls to genphy_config_init(). Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-04-02net: phy: use genphy_read_abilities in genphy driverHeiner Kallweit1-2/+1
Currently the genphy driver populates phydev->supported like this: First all possible feature bits are set, then genphy_config_init() reads the available features from the chip and remove all unsupported features from phydev->supported. This can be simplified by using genphy_read_abilities(). Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-04-02net: phy: add genphy_read_abilitiesHeiner Kallweit1-0/+48
Similar to genphy_c45_pma_read_abilities() add a function to dynamically detect the abilities of a Clause 22 PHY. This is mainly copied from genphy_config_init(). Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-04-02net: phy: aquantia: add SGMII statisticsHeiner Kallweit1-2/+112
The AQR107 family has SGMII statistics counters. Let's expose them to ethtool. To interpret the counters correctly one has to be aware that rx on SGMII side is tx on ethernet side. The counters are populated by the chip in 100Mbps/1Gbps mode only. v2: - add constant AQR107_SGMII_STAT_SZ - add struct aqr107_priv to be prepared for more private data fields - let aqr107_get_stat() return U64_MAX in case of an error Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-04-02net: phy: improve genphy_read_statusHeiner Kallweit1-15/+8
This patch improves few aspects of genphy_read_status(): - Don't initialize lpagb, it's not needed. - Move initializing phydev->speed et al before the if clause. - In auto-neg case, skip populating lp_advertising if we don't have a link. This avoids quite some unnecessary MDIO reads in case of phylib polling mode. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-04-02net: phy: aquantia: add suspend / resume callbacks for AQR107 familyHeiner Kallweit1-0/+16
Add suspend / resume callbacks for AQR107 family. Suspend powers down the complete chip except MDIO and internal CPU. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-03-28Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/netDavid S. Miller4-15/+37
2019-03-28net: phy: mdio-bcm-unimac: remove redundant !timeout checkColin Ian King1-4/+1
The check for zero timeout is always true at the end of the proceeding while loop; the only other exit path in the loop is if the unimac MDIO is not busy. Remove the redundant zero timeout check and always return -ETIMEDOUT on this timeout return path. Signed-off-by: Colin Ian King <colin.king@canonical.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-03-27net: phy: marvell: add PHY tunable fast link down support for 88E1540Heiner Kallweit1-0/+108
1000BaseT standard requires that a link is reported as down earliest after 750ms. Several use case however require a much faster detecion of a broken link. Fast Link Down supports this by intentionally violating a the standard. This patch exposes the Fast Link Down feature of 88E1540 and 88E6390. These PHY's can be found as internal PHY's in several switches: 88E6352, 88E6240, 88E6176, 88E6172, and 88E6390(X). Fast Link Down and EEE are mutually exclusive. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-03-26net: phy: aquantia: inform about proprietary 1000Base-T2 mode being in useHeiner Kallweit1-1/+13
The AQCS109 supports a proprietary 2-pair 1Gbps mode. The standard registers don't allow to tell between 1000BaseT and 1000BaseT2. Add reporting this proprietary mode based on a vendor register. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-03-26net: phy: aquantia: report PHY details like firmware versionHeiner Kallweit1-0/+62
Add reporting firmware details. These details are available only once the firmware has finished initializing the chip. This can take some time and we need to poll for init completion. v2: - Propagate timeout in aqr107_wait_reset_complete(). Don't bail out completely on timeout because chip may be functional even w/o firmware image. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-03-26net: phy: aquantia: print remote capabilities if link partner is Aquantia PHYHeiner Kallweit1-0/+49
If both link partners are Aquantia PHY's then additional information is exchanged as part of the auto-negotiation. Report remote capabilities if link partner is Aquantia PHY. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-03-26net: phy: bcm54xx: Encode link speed and activity into LEDsVladimir Oltean1-0/+13
Previously the green and amber LEDs on this quad PHY were solid, to indicate an encoding of the link speed (10/100/1000). This keeps the LEDs always on just as before, but now they flash on Rx/Tx activity. Signed-off-by: Vladimir Oltean <olteanv@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-03-26net: phy: aquantia: simplify aqr_config_anegHeiner Kallweit1-32/+13
Simplify aqr_config_aneg(). Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-03-26net: phy: don't clear BMCR in genphy_soft_resetHeiner Kallweit1-1/+1
So far we effectively clear the BMCR register. Some PHY's can deal with this (e.g. because they reset BMCR to a default as part of a soft-reset) whilst on others this causes issues because e.g. the autoneg bit is cleared. Marvell is an example, see also thread [0]. So let's be a little bit more gentle and leave all bits we're not interested in as-is. This change is needed for PHY drivers to properly deal with the original patch. [0] https://marc.info/?t=155264050700001&r=1&w=2 Fixes: 6e2d85ec0559 ("net: phy: Stop with excessive soft reset") Tested-by: Phil Reid <preid@electromag.com.au> Tested-by: liweihang <liweihang@hisilicon.com> Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-03-24net: phy: Re-parent menus for MDIO bus drivers correctlyFlorian Fainelli1-0/+3
After 90eff9096c01 ("net: phy: Allow splitting MDIO bus/device support from PHYs") the various MDIO bus drivers were no longer parented with config PHYLIB but with config MDIO_BUS which is not a menuconfig, fix this by depending on MDIO_DEVICE which is a menuconfig. This is visually nicer and less confusing for users. Fixes: 90eff9096c01 ("net: phy: Allow splitting MDIO bus/device support from PHYs") Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-03-24net: phy: Correct Cygnus/Omega PHY driver promptFlorian Fainelli1-2/+1
The tristate prompt should have been replaced rather than defined a few lines below, rebase mistake. Fixes: 17cc9821766c ("net: phy: Move Omega PHY entry to Cygnus PHY driver") Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-03-22net: phy: aquantia: add downshift supportHeiner Kallweit1-10/+145
Aquantia PHY's of the AQR107 family support the downshift feature. Add support for it as standard PHY tunable so that it can be controlled via ethtool. The AQCS109 supports a proprietary 2-pair 1Gbps mode. If two such PHY's are connected to each other with a 2-pair cable, they may not be able to establish a link if both advertise modes > 1Gbps. v2: - add downshift event detection - warn if downshift occurred - read downshifted rate from vendor register - enable downshift per default on all AQR107 family members Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-03-21net: phy: Move Omega PHY entry to Cygnus PHY driverFlorian Fainelli3-4/+149
Cygnus and Omega are part of the same business unit and product line, it makes sense to group PHY entries by products such that a platform can select only the drivers that it needs. Bring all the functionality that the BCM7XXX_28NM_GPHY() macro hides for us and remove the Omega PHY entry from bcm7xxx.c. As an added bonus, we now have a proper mdio_device_id entry to permit auto-loading. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Scott Branden <scott.branden@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-03-21net: phy: Prepare for moving Omega out of bcm7xxxFlorian Fainelli3-71/+76
The Omega PHY entry was added to bcm7xxx.c out of convenience and this breaks the one driver per product line paradigm that was applied up until now. Since the AFE initialization is shared between Omega and BCM7xxx move the relevant functions to bcm-phy-lib.[ch]. No functional changes introduced. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Scott Branden <scott.branden@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-03-21net: phy: mdio-bcm-unimac: Remove print of base addressFlorian Fainelli1-1/+1
Since commit ad67b74d2469 ("printk: hash addresses printed with %p") pointers are being hashed when printed. Displaying the virtual memory at bootup time is not helpful, especially given we use a dev_info() which already displays the platform device's address. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-03-21net: phy: Add DP83825I to the DP83822 driverDan Murphy1-14/+20
Add the DP83825I ethernet PHY to the DP83822 driver. These devices share the same WoL register bits and addresses. The phy_driver init was made into a macro as there may be future devices appended to this driver that will share the register space. http://www.ti.com/lit/gpn/dp83825i Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Dan Murphy <dmurphy@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-03-20net: phy: aquantia: check for changed interface mode in read_statusNikita Yushchenko1-2/+44
Depending on the auto-negotiated speed the PHY may change the interface mode. Check for new mode and set phydev->interface accordingly. Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com> Signed-off-by: Andrew Lunn <andrew@lunn.ch> [hkallweit1@gmail.com: picked from bigger patch and reworked] Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-03-20net: phy: aquantia: check for supported interface modes in config_initAndrew Lunn1-0/+17
Let config_init check for unsupported interface modes on AQR107/AQCS109. Signed-off-by: Andrew Lunn <andrew@lunn.ch> [hkallweit1@gmail.com: adjusted for AQR107/AQCS109 specifics] Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-03-20net: phy: improve handling link_change_notify callbackHeiner Kallweit3-50/+15
Currently the Phy driver's link_change_notify callback is called whenever the state machine is run (every second if polling), no matter whether the state changed or not. This isn't needed and may confuse users considering the name of the callback. Actually it contradicts its kernel-doc description. Therefore let's change the behavior and call this callback only in case of an actual state change. This requires changes to the at803x and rockchip drivers. at803x can be simplified so that it reacts on a state change to PHY_NOLINK only. The rockchip driver can also be much simplified. We simply re-init the AFE/DSP registers whenever we change to PHY_RUNNING and speed is 100Mbps. This causes very small overhead because we do this even if the speed was 100Mbps already. But this is negligible and I think justified by the much simpler code. Changes are compile-tested only. A little bit problematic seems to be to find somebody with the hardware to test the changes to the two PHY drivers. See also [0]. David may be able to test the Rockchip driver. [0] https://marc.info/?t=153782508800006&r=1&w=2 Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-03-16net: phy: meson-gxl: fix interrupt supportJerome Brunet1-0/+6
If an interrupt is already pending when the interrupt is enabled on the GXL phy, no IRQ will ever be triggered. The fix is simply to make sure pending IRQs are cleared before setting up the irq mask. Fixes: cf127ff20af1 ("net: phy: meson-gxl: add interrupt support") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-03-05phy: mdio-mux: fix Kconfig dependenciesArnd Bergmann1-1/+1
MDIO_BUS_MUX can only be selected if OF_MDIO is already turned on: WARNING: unmet direct dependencies detected for MDIO_BUS_MUX Depends on [n]: NETDEVICES [=y] && MDIO_BUS [=m] && OF_MDIO [=n] Selected by [m]: - MDIO_BUS_MUX_MULTIPLEXER [=m] && NETDEVICES [=y] && MDIO_BUS [=m] && OF [=y] Fixes: 7865ad6551c9 ("drivers: net: phy: mdio-mux: Add support for Generic Mux controls") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: David S. Miller <davem@davemloft.net>
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