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path: root/drivers/phy/amlogic/phy-meson-axg-pcie.c
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2020-11-30phy: amlogic: replace devm_reset_control_array_get()Yejune Deng1-1/+1
devm_reset_control_array_get_exclusive() looks more readable Signed-off-by: Yejune Deng <yejune.deng@gmail.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/1605666995-16462-1-git-send-email-yejune.deng@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-17phy: amlogic: Revert "phy: amlogic: Replace devm_reset_control_array_get()"Vinod Koul1-1/+1
This reverts commit 3cc8e86721ad ("phy: amlogic: Replace devm_reset_control_array_get()") as it caused build failure drivers/soc/amlogic/meson-ee-pwrc.c: In function 'meson_ee_pwrc_init_domain': drivers/soc/amlogic/meson-ee-pwrc.c:416:65: error: expected ';' before 'if' Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-16phy: amlogic: Replace devm_reset_control_array_get()Yejune Deng1-1/+1
devm_reset_control_array_get_exclusive() looks more readable Signed-off-by: Yejune Deng <yejune.deng@gmail.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/1604378274-6860-1-git-send-email-yejune.deng@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-16phy: amlogic: convert to devm_platform_ioremap_resourceChunfeng Yun1-3/+1
Use devm_platform_ioremap_resource to simplify code Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Remi Pommarel <repk@triplefau.lt> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/1604642930-29019-2-git-send-email-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-03-04phy: amlogic: Add Amlogic AXG PCIE PHY DriverRemi Pommarel1-0/+192
This adds support for the PCI PHY found in the Amlogic AXG SoC Family. This will allow to mutualize code in pci-meson.c between AXG and G12A SoC. This PHY also uses and chains an analog PHY, which on AXG platform is needed to have reliable PCIe communication. Signed-off-by: Remi Pommarel <repk@triplefau.lt> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>