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2024-01-31pinctrl: amd: Add IRQF_ONESHOT to the interrupt requestMario Limonciello1-1/+1
On some systems the interrupt is shared between GPIO controller and ACPI SCI. When the interrupt is shared with the ACPI SCI the flags need to be identical. This should fix the GPIO controller failing to work after commit 7a36b901a6eb ("ACPI: OSL: Use a threaded interrupt handler for SCI"). ``` [ 0.417335] genirq: Flags mismatch irq 9. 00000088 (pinctrl_amd) vs. 00002080 (acpi) [ 0.420073] amd_gpio: probe of AMDI0030:00 failed with error -16 ``` Cc: Rafael J. Wysocki <rafael@kernel.org> Reported-by: Christian Heusel <christian@heusel.eu> Closes: https://bugzilla.kernel.org/show_bug.cgi?id=218407 Fixes: 7a36b901a6eb ("ACPI: OSL: Use a threaded interrupt handler for SCI") Link: https://lore.kernel.org/linux-acpi/CAJZ5v0iRqUXeuKmC_+dAJtDBLWQ3x15n4gRH48y7MEaLoXF+UA@mail.gmail.com/T/#mc5506014141b61e472b24e095889535a04458083 Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Acked-by: Rafael J. Wysocki <rafael@kernel.org> Tested-by: Christian Heusel <christian@heusel.eu> Link: https://lore.kernel.org/r/20240123180818.3994-1-mario.limonciello@amd.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-01-18Merge tag 'pinctrl-v6.8-1' of ↵Linus Torvalds95-884/+7451
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "For this kernel cycle I managed an immutable branch for the PEF2256 WAN framer that has some pin control portions. It already landed in your tree through the net pull request but here it is mentioned again. The most interesting is perhaps the Samsung Exynos subdrivers for the Tensor SoC used in Google Pixel 6 and the ExynosAuto subdriver for automotive. Along with the earlier merged Tesla FSD subdriver it shows some of the versatile uses of the Samsung Exynos silicon. It is also used in the latest version of Axis Communications ARTPEC chips so it is a very widely deployed SoC family. We also have the Intel Meteor Lake SoC which I think is for laptops. It's a pretty interesting chip with Xe graphics and integrated PCH. Core changes: - A new PINCTRL_GROUP_DESC() infrastructure macro is added and used in different drivers, generic group description struct group_desc is now used all over the place. New drivers: - New driver for the Texas Instruments TPS6494 Power Management IC. - New driver for the Lantic PEF2256 framer pin multiplexer. This IC has some pins that can be reconfigured in different ways. The actual driver comes on an immutable branch with the net WAN parts, the IC is some latest-and-greatest serial line funnel for e.g. wireless access points. - New subdriver for the Samsung Exynos Auto V920 pin controller, used for automotive applications. - New subdriver for the Samsung "GS101" SoC pin controller, this is the Google "Tensor" SoC used in the Google Pixel 6. - New subdriver for the Intel Meteor Point SoC pin controller. - New subdriver for the Qualcomm SM8650 top level (TLMM) and LPASS pin controllers. - New subdriver for the Qualcomm X1E80100 top level (TLMM) pin controller. - New subdriver for the Qualcomm SM4450 top level (TLMM) pin controller. - The "single" pin controller now supports the Texas Instruments J7200 SoC. Improvements: - Intel has created a new (Intel-)generic pin controller driver that is now used by all contemporary Intel platforms. - Intel is now also making use of some cleanup helpers. - Enble 910 Ohm bias in the Intel Tangier driver. - The Samsung driver now suppors irq_set_affinity() in it's IRQ chip giving support for non wake up external gpio interrupts" * tag 'pinctrl-v6.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (112 commits) pinctrl: samsung: constify iomem pointers pinctrl: cy8c95x0: Cache muxed registers dt-bindings: pinctrl: xilinx: Rename *gpio to *gpio-grp pinctrl: qcom: lpass-lpi: remove duplicated include dt-bindings: pinctrl: qcom: drop common properties and allow wakeup-parent dt-bindings: pinctrl: qcom: drop common properties dt-bindings: pinctrl: qcom,ipq5018-tlmm: use common TLMM bindings dt-bindings: pinctrl: qcom,x1e80100-tlmm: restrict number of interrupts dt-bindings: pinctrl: qcom,sm8650-tlmm: restrict number of interrupts dt-bindings: pinctrl: qcom,sm8550-tlmm: restrict number of interrupts dt-bindings: pinctrl: qcom,sdx75-tlmm: restrict number of interrupts dt-bindings: pinctrl: qcom,sa8775p-tlmm: restrict number of interrupts dt-bindings: pinctrl: qcom,qdu1000-tlmm: restrict number of interrupts dt-bindings: pinctrl: qcom: create common LPASS LPI schema pinctrl: qcom: sm4450: dd SM4450 pinctrl driver dt-bindings: pinctrl: qcom: Add SM4450 pinctrl dt-bindings: pinctrl: qcom,pmic-mpp: clean up example pinctrl: intel: Add Intel Meteor Point pin controller and GPIO support pinctrl: renesas: rzg2l: Add input enable to the Ethernet pins pinctrl: renesas: rzg2l: Add output enable support ...
2024-01-13Merge tag 'gpio-updates-for-v6.8-rc1' of ↵Linus Torvalds4-13/+23
git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux Pull gpio updates from Bartosz Golaszewski: "We have two new drivers, an assortment of updates and cleanups to many others, and first part of the big rework of the core GPIOLIB that's currently underway. Add to that some code shrink in the character device module and updates to DT bindings and that's pretty much it. Core GPIOLIB: - protect the global list of GPIO devices with a read-write semaphore as it is rarely modified but can be traversed by multiple readers at once - remove GPIO devices from the global list when they are *unregistered* and not when they are *released* (which only happens when the last reference is dropped) as this may lead to a successful lookup of an unregistered device - remove the unnecessary "extra_checks" switch - rename functions that are called with a lock taken - remove duplicate includes Character device handling: - use locking guards to reduce the code size - allocate the big linereq structure using the more suitable kvzalloc() - redulce the size of critical sections - improve documentation - move the debounce_period_us field out of struct gpio_desc New drivers: - Nuvoton NPCM SGPIO driver for BMC NPCM7xx/NPCM8xx - Realtek DHC (Digital Home Center) SoC GPIO driver Driver improvements: - replace gpiochip_is_requested() with a safer alternative in the form of gpiochip_dup_line_label() as the former returns a pointer to a string that can be deleted - implement the dbg_show() callback in gpio-sim - improve the coding style for local variables by removing unnecessary tabs - use generic device properties instead of OF variants in gpio-mmio - use the preferred coding style for __free() in gpio-mockup - reuse PM ops from the gpio-tangier in gpio-elkhartlake - rework PM and use cleanup helpers in gpio-tangier - fix the EIC configuration in gpio-pmic-eic-sprd - remove the unneeded call to platform_set_drvdata() in gpio-sifive - use generic GPIO helpers for driver callbacks in gpio-dwapb - add clock support on certain pins of gpio-ixp4xx - don't use the core-specific DEBUG_GPIO switch in drivers - kerneldoc improvements DT bindings: - add bindings for the new Realtek and Nuvoton devices - allow gpio-ranges in gpio-dwapb - support GPIO hogs in gpio-rockchip - describe the label property in gpio-zynqmp-modepin Other: - header cleanups - forward declarations cleanups" * tag 'gpio-updates-for-v6.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux: (55 commits) gpiolib: replace the GPIO device mutex with a read-write semaphore gpiolib: remove the GPIO device from the list when it's unregistered gpio: nuvoton: Add Nuvoton NPCM sgpio driver dt-bindings: gpio: add NPCM sgpio driver bindings gpio: rtd: Add support for Realtek DHC(Digital Home Center) RTD SoCs dt-bindings: gpio: realtek: Add realtek,rtd-gpio gpio: pmic-eic-sprd: Configure the bit corresponding to the EIC through offset gpio: dwapb: Use generic request, free and set_config gpio: sysfs: drop tabs from local variable declarations gpiolib: drop tabs from local variable declarations gpiolib: remove extra_checks gpio: tps65219: don't use CONFIG_DEBUG_GPIO gpiolib: cdev: replace locking wrappers for gpio_device with guards gpiolib: cdev: replace locking wrappers for config_mutex with guards gpiolib: cdev: allocate linereq using kvzalloc() gpiolib: cdev: include overflow.h gpiolib: cdev: reduce locking in gpio_desc_to_lineinfo() gpiolib: cdev: improve documentation of get/set values gpiolib: cdev: fully adopt guard() and scoped_guard() gpiolib: remove debounce_period_us from struct gpio_desc ...
2024-01-05Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski6-5/+39
Cross-merge networking fixes after downstream PR. Conflicts: drivers/net/ethernet/broadcom/bnxt/bnxt.c e009b2efb7a8 ("bnxt_en: Remove mis-applied code from bnxt_cfg_ntp_filters()") 0f2b21477988 ("bnxt_en: Fix compile error without CONFIG_RFS_ACCEL") https://lore.kernel.org/all/20240105115509.225aa8a2@canb.auug.org.au/ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2023-12-29pinctrl: samsung: constify iomem pointersKrzysztof Kozlowski2-4/+4
Constify few pointers to iomem, where the destination memory is not modified, for code safety and readability. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20231223191902.22857-1-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-12-27Merge tag 'v6.7-rc7' into gpio/for-nextBartosz Golaszewski11-16/+59
Linux 6.7-rc7
2023-12-21pinctrl: at91-pio4: use dedicated lock class for IRQAlexis Lothoré1-0/+8
Trying to suspend to RAM on SAMA5D27 EVK leads to the following lockdep warning: ============================================ WARNING: possible recursive locking detected 6.7.0-rc5-wt+ #532 Not tainted -------------------------------------------- sh/92 is trying to acquire lock: c3cf306c (&irq_desc_lock_class){-.-.}-{2:2}, at: __irq_get_desc_lock+0xe8/0x100 but task is already holding lock: c3d7c46c (&irq_desc_lock_class){-.-.}-{2:2}, at: __irq_get_desc_lock+0xe8/0x100 other info that might help us debug this: Possible unsafe locking scenario: CPU0 ---- lock(&irq_desc_lock_class); lock(&irq_desc_lock_class); *** DEADLOCK *** May be due to missing lock nesting notation 6 locks held by sh/92: #0: c3aa0258 (sb_writers#6){.+.+}-{0:0}, at: ksys_write+0xd8/0x178 #1: c4c2df44 (&of->mutex){+.+.}-{3:3}, at: kernfs_fop_write_iter+0x138/0x284 #2: c32684a0 (kn->active){.+.+}-{0:0}, at: kernfs_fop_write_iter+0x148/0x284 #3: c232b6d4 (system_transition_mutex){+.+.}-{3:3}, at: pm_suspend+0x13c/0x4e8 #4: c387b088 (&dev->mutex){....}-{3:3}, at: __device_suspend+0x1e8/0x91c #5: c3d7c46c (&irq_desc_lock_class){-.-.}-{2:2}, at: __irq_get_desc_lock+0xe8/0x100 stack backtrace: CPU: 0 PID: 92 Comm: sh Not tainted 6.7.0-rc5-wt+ #532 Hardware name: Atmel SAMA5 unwind_backtrace from show_stack+0x18/0x1c show_stack from dump_stack_lvl+0x34/0x48 dump_stack_lvl from __lock_acquire+0x19ec/0x3a0c __lock_acquire from lock_acquire.part.0+0x124/0x2d0 lock_acquire.part.0 from _raw_spin_lock_irqsave+0x5c/0x78 _raw_spin_lock_irqsave from __irq_get_desc_lock+0xe8/0x100 __irq_get_desc_lock from irq_set_irq_wake+0xa8/0x204 irq_set_irq_wake from atmel_gpio_irq_set_wake+0x58/0xb4 atmel_gpio_irq_set_wake from irq_set_irq_wake+0x100/0x204 irq_set_irq_wake from gpio_keys_suspend+0xec/0x2b8 gpio_keys_suspend from dpm_run_callback+0xe4/0x248 dpm_run_callback from __device_suspend+0x234/0x91c __device_suspend from dpm_suspend+0x224/0x43c dpm_suspend from dpm_suspend_start+0x9c/0xa8 dpm_suspend_start from suspend_devices_and_enter+0x1e0/0xa84 suspend_devices_and_enter from pm_suspend+0x460/0x4e8 pm_suspend from state_store+0x78/0xe4 state_store from kernfs_fop_write_iter+0x1a0/0x284 kernfs_fop_write_iter from vfs_write+0x38c/0x6f4 vfs_write from ksys_write+0xd8/0x178 ksys_write from ret_fast_syscall+0x0/0x1c Exception stack(0xc52b3fa8 to 0xc52b3ff0) 3fa0: 00000004 005a0ae8 00000001 005a0ae8 00000004 00000001 3fc0: 00000004 005a0ae8 00000001 00000004 00000004 b6c616c0 00000020 0059d190 3fe0: 00000004 b6c61678 aec5a041 aebf1a26 This warning is raised because pinctrl-at91-pio4 uses chained IRQ. Whenever a wake up source configures an IRQ through irq_set_irq_wake, it will lock the corresponding IRQ desc, and then call irq_set_irq_wake on "parent" IRQ which will do the same on its own IRQ desc, but since those two locks share the same class, lockdep reports this as an issue. Fix lockdep false positive by setting a different class for parent and children IRQ Fixes: 776180848b57 ("pinctrl: introduce driver for Atmel PIO4 controller") Signed-off-by: Alexis Lothoré <alexis.lothore@bootlin.com> Link: https://lore.kernel.org/r/20231215-lockdep_warning-v1-1-8137b2510ed5@bootlin.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-12-20pinctrl: cy8c95x0: Cache muxed registersPatrick Rudolph1-143/+315
Currently the port specific registers behind the PORTSEL mux aren't cached in the regmap and thus the typical setup time for a single pin on cy8c9560 is about 200msec on our system. The hotspot is the IRQ (un)masking, which causes lots of R/W operations. Introduce a separate regmap for muxed registers and helper functions to use the newly introduced regmap for muxed register access under the i2c lock. With the new cache in place the typical pin setup time is reduced to 20msec, making it about 10 times faster. As a side effect the system boot time is also reduced by 50%. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Link: https://lore.kernel.org/r/20231219125350.4031370-1-patrick.rudolph@9elements.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-12-20pinctrl: cy8c95x0: Fix get_pincfgPatrick Rudolph1-0/+2
Invert the register value for PIN_CONFIG_OUTPUT_ENABLE to return the opposite of PIN_CONFIG_INPUT_ENABLE. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Link: https://lore.kernel.org/r/20231219125120.4028862-3-patrick.rudolph@9elements.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-12-20pinctrl: cy8c95x0: Fix regressionPatrick Rudolph1-0/+10
Commit 1fa3df901f2c ("pinctrl: cy8c95x0: Remove custom ->set_config()") removed support for PIN_CONFIG_INPUT_ENABLE and PIN_CONFIG_OUTPUT. Add the following options to restore functionality: - PIN_CONFIG_INPUT_ENABLE - PIN_CONFIG_OUTPUT_ENABLE Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Link: https://lore.kernel.org/r/20231219125120.4028862-2-patrick.rudolph@9elements.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-12-20pinctrl: cy8c95x0: Fix typoPatrick Rudolph1-1/+1
Fix typo to make pinctrl-cy8c95x compile again. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Link: https://lore.kernel.org/r/20231219125120.4028862-1-patrick.rudolph@9elements.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-12-20pinctrl: qcom: lpass-lpi: remove duplicated includeWang Jinchao1-1/+0
remove the second #include <linux/seq_file.h> Signed-off-by: Wang Jinchao <wangjinchao@xfusion.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/202312151810+0800-wangjinchao@xfusion.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-12-20pinctrl: qcom: sm4450: dd SM4450 pinctrl driverTengfei Fan3-0/+1023
Add pinctrl driver for TLMM block found in SM4450 SoC. Can Guo helped out in reviewing the driver. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com> Link: https://lore.kernel.org/r/20231212094900.12615-3-quic_tengfan@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-12-19Merge tag 'intel-pinctrl-v6.8-1' of ↵Linus Walleij24-279/+888
git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel intel-pinctrl for v6.8-1 * New agnostic driver to support Lunar Lake and newer platforms * New driver for Intel Meteor Point-S (PCH for Meteor Lake-S) * Update drivers to use new PM helpers * Use RAII for locking in a few drivers (Raag, Andy) * Reduce locking scope in some functions (Raag) * Miscellaneous cleanups (Raag) The following is an automated git shortlog grouped by driver: alderlake: - Switch to use Intel pin control PM ops baytrail: - Simplify code with cleanup helpers - Move default strength assignment to a switch-case - Factor out byt_gpio_force_input_mode() - Fix types of config value in byt_pin_config_set() broxton: - Switch to use Intel pin control PM ops cannonlake: - Switch to use Intel pin control PM ops cedarfork: - Switch to use Intel pin control PM ops denverton: - Switch to use Intel pin control PM ops elkhartlake: - Switch to use Intel pin control PM ops emmitsburg: - Switch to use Intel pin control PM ops geminilake: - Switch to use Intel pin control PM ops icelake: - Switch to use Intel pin control PM ops intel: - Add Intel Meteor Point pin controller and GPIO support - use the correct _PM_OPS() export macro - Add a generic Intel pin control platform driver - Revert "Unexport intel_pinctrl_probe()" - allow independent COMPILE_TEST - Refactor intel_pinctrl_get_soc_data() - Move default strength assignment to a switch-case - Make PM ops functions static - Provide Intel pin control wide PM ops structure jasperlake: - Switch to use Intel pin control PM ops lakefield: - Switch to use Intel pin control PM ops lewisburg: - Switch to use Intel pin control PM ops lynxpoint: - Simplify code with cleanup helpers meteorlake: - Switch to use Intel pin control PM ops sunrisepoint: - Switch to use Intel pin control PM ops tangier: - simplify locking using cleanup helpers - Move default strength assignment to a switch-case - Enable 910 Ohm bias tigerlake: - Switch to use Intel pin control PM ops Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-12-18Merge tag 'samsung-pinctrl-6.8' of ↵Linus Walleij5-9/+426
https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel Samsung pinctrl drivers changes for v6.8 1. New hardware: Add pin controllers for Samsung ExynosAutov920 and Google Tensor GS101. 2. Few DT bindings cleanups: add specific compatibles for each device using generic compatible as fallback. This affects only DTS, no driver changes are needed. 3. Allow setting affinity on non wake-up external GPIO interrupts. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-12-18Merge tag 'renesas-pinctrl-for-v6.8-tag2' of ↵Linus Walleij1-19/+145
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v6.8 (take two) - Add pinmux groups, power source, and input/output enable support for Ethernet pins on RZ/G2L SoCs, - Miscellaneous fixes and improvements. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-12-15pinctrl: intel: Add Intel Meteor Point pin controller and GPIO supportAndy Shevchenko3-0/+475
This driver supports pinctrl/GPIO hardware found on Intel Meteor Point (a Meteor Lake PCH) providing users a pinctrl and GPIO interfaces including GPIO interrupts. Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2023-12-15pinctrl: renesas: rzg2l: Add input enable to the Ethernet pinsClaudiu Beznea1-2/+2
Some of the RZ/G3S Ethernet pins (P1_0, P7_0) can be configured with input enable. Enable this functionality for these pins. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20231207070700.4156557-8-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-12-15pinctrl: renesas: rzg2l: Add output enable supportClaudiu Beznea1-2/+85
Some of the Ethernet pins on RZ/G3S (but also valid for RZ/G2L) need to have the direction of the IO buffer set as output for Ethernet to work properly. On RZ/G3S, these pins are P1_0/P7_0, P1_1/P7_1, and can have the following Ethernet functions: TXC/TX_CLK or TX_CTL/TX_EN. As the pins supporting output enable are SoC specific, and there is a limited number of these pins (TXC/TX_CLK and/or TX_CTL/TX_EN), specify output enable capable port limits in the platform-based configuration data structure, to ensure proper validation. The OEN support has been intantiated for RZ/G3S at the moment. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20231207070700.4156557-7-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-12-15pinctrl: renesas: rzg2l: Add support to select power source for Ethernet pinsClaudiu Beznea1-3/+39
The GPIO controller available on RZ/G3S (but also on RZ/G2L) supports setting the power source for Ethernet pins. Based on the interface b/w the Ethernet controller and the Ethernet PHY, and on board design, a specific power source needs to be selected. The GPIO controller supports 1.8V, 2.5V, and 3.3V power source selection for the Ethernet pins. This can be selected though the ETHx_POC registers (x={0, 1}). Adjust the driver to support this, and to do proper instantiation for the RZ/G3S and RZ/G2L SoCs. On RZ/G2L only the get operation has been tested at the moment. While at it, as the power registers on RZ/G2L support access sizes of 8 bits, and these registers on RZ/G3S support access sizes of 8/16/32 bits, replace writel()/readl() on these registers with writeb()/readb(). This should allow us to use the same code on both SoCs w/o any issues. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20231207070700.4156557-6-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-12-15pinctrl: renesas: rzg2l: Add pin configuration support for pinmux groupsClaudiu Beznea1-1/+14
On RZ/G3S different Ethernet pins need to be configured with different settings (e.g. power-source needs to be set, RGMII TXC and TX_CTL pins need output-enable). Adjust the driver to allow specifying pin configuration for pinmux groups. With this, DT settings like the following are taken into account by the driver: eth0_pins: eth0 { tx_ctl { pinmux = <RZG2L_PORT_PINMUX(1, 1, 1)>; /* ET0_TX_CTL */ power-source = <1800>; output-enable; drive-strength-microamp = <5200>; }; }; Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20231207070700.4156557-5-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-12-13pinctrl: renesas: rzg2l: Move arg and index in the main function blockClaudiu Beznea1-13/+7
Move arg and index in the main block of the function as they are used by more than one case block of switch-case (3 out of 4 for arg, 2 out of 4 for index). In this way some lines of code are removed. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20231207070700.4156557-4-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-12-13pinctrl: samsung: add exynosautov920 pinctrlJaewon Kim5-1/+190
Add pinctrl data for ExynosAutov920 SoC. It has a newly applied pinctrl register layer for ExynosAuto series. Pinctrl data for ExynosAutoV920 SoC. - GPA0,GPA1 (10): External wake up interrupt - GPQ0 (2): SPMI (PMIC I/F) - GPB0,GPB1,GPB2,GPB3,GPB4,GPB5,GPB6 (47): I2S Audio - GPH0,GPH1,GPH2,GPH3,GPH4,GPH5,GPH6,GPH8 (49): PCIE, UFS, Ethernet - GPG0,GPG1,GPG2,GPG3,GPG4,GPG5 (29): General purpose - GPP0,GPP1,GPP2,GPP3,GPP4,GPP5,GPP6,GPP7,GPP8,GPP9,GPP10 (77): USI Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com> Link: https://lore.kernel.org/r/20231211114145.106255-3-jaewon02.kim@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-12-13pinctrl: samsung: support ExynosAuto GPIO structureJaewon Kim3-8/+79
New ExynosAuto series GPIO have a different register structure. In the existing Exynos series, EINT control register is enumerated after a specific offset (e.g EXYNOS_GPIO_ECON_OFFSET, EXYNOS_GPIO_EMASK_OFFSET). However, from ExynosAutov920 SoC, the register that controls EINT belongs to each GPIO bank, and each GPIO bank has 0x1000 align. This is a structure to protect the GPIO bank using S2MPU in VM environment, and will only be applied in ExynosAuto series SoCs. -------------------------------------------------------------- | Original Exynos | ExynosAuto | |------------------------------------------------------------| | 0x0 GPIO_CON | 0x0 GPIO_CON | | 0x4 GPIO_DAT | 0x4 GPIO_DAT | | 0x8 GPIO_PUD | 0x8 GPIO_PUD | | 0xc GPIO_DRV | 0xc GPIO_DRV | | 0x10 GPIO_CONPDN | 0x10 GPIO_CONPDN | | 0x14 GPIO_PUDPDN | 0x14 GPIO_PUDPDN | |----------------------------| 0x18 EINT_CON (per_bank) | | ... | 0x1c EINT_FLTCON0 (per_bank) | | ... | 0x20 EINT_FLTCON1 (per_bank) | | ... | 0x24 EINT_MASK (per_bank) | | ... | 0x28 EINT_PEND (per_bank) | |----------------------------|-------------------------------| | 0x700 EINT_CON (global) | ... | | 0x800 EINT_FLTCON (global) | ... | | 0x900 EINT_MASK (global) | ... | | 0xa00 EINT_FEND (global) | ... | -------------------------------------------------------------- Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com> Link: https://lore.kernel.org/r/20231211114145.106255-2-jaewon02.kim@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-12-13Merge tag 'pef2256-framer' of ↵Jakub Kicinski3-0/+374
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Linus Walleij says: ==================== Immutable tag for the PEF2256 framer * tag 'pef2256-framer' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: MAINTAINERS: Add the Lantiq PEF2256 driver entry pinctrl: Add support for the Lantic PEF2256 pinmux net: wan: framer: Add support for the Lantiq PEF2256 framer dt-bindings: net: Add the Lantiq PEF2256 E1/T1/J1 framer net: wan: Add framer framework support ==================== Link: https://lore.kernel.org/all/CACRpkdYT1J7noFUhObFgfA60XQAfL4rb=knEmWS__TKKtCMh7Q@mail.gmail.com/ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2023-12-13Merge tag 'pef2256-framer' into develLinus Walleij3-0/+374
Immutable tag for the PEF2256 framer
2023-12-13pinctrl: Add support for the Lantic PEF2256 pinmuxHerve Codina3-0/+374
The Lantiq PEF2256 is a framer and line interface component designed to fulfill all required interfacing between an analog E1/T1/J1 line and the digital PCM system highway/H.100 bus. This kind of component can be found in old telecommunication system. It was used to digital transmission of many simultaneous telephone calls by time-division multiplexing. Also using HDLC protocol, WAN networks can be reached through the framer. This pinmux support handles the pin muxing part (pins RP(A..D) and pins XP(A..D)) of the PEF2256. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20231128132534.258459-5-herve.codina@bootlin.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-12-12pinctrl: samsung: Add gs101 SoC pinctrl configurationPeter Griffin3-0/+143
Add support for the pin-controller found on the gs101 SoC used in Pixel 6 phones. Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20231211162331.435900-10-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-12-12pinctrl: core: Remove unused members from struct group_descAndy Shevchenko2-18/+0
All drivers are converted to use embedded struct pingroup. Remove unused members from struct group_desc. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20231211190321.307330-14-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-12-12pinctrl: starfive: Convert to use grp memberAndy Shevchenko2-8/+8
Convert drivers to use grp member embedded in struct group_desc, because other members will be removed to avoid duplication and desynchronisation of the generic pin group description. Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20231211190321.307330-13-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-12-12pinctrl: renesas: Convert to use grp memberAndy Shevchenko4-10/+10
Convert drivers to use grp member embedded in struct group_desc, because other members will be removed to avoid duplication and desynchronisation of the generic pin group description. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20231211190321.307330-12-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-12-12pinctrl: mediatek: Convert to use grp memberAndy Shevchenko3-13/+8
Convert drivers to use grp member embedded in struct group_desc, because other members will be removed to avoid duplication and desynchronisation of the generic pin group description. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20231211190321.307330-11-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-12-12pinctrl: keembay: Convert to use grp memberAndy Shevchenko1-1/+1
Convert drivers to use grp member embedded in struct group_desc, because other members will be removed to avoid duplication and desynchronisation of the generic pin group description. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20231211190321.307330-10-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-12-12pinctrl: ingenic: Convert to use grp memberAndy Shevchenko1-15/+11
Convert drivers to use grp member embedded in struct group_desc, because other members will be removed to avoid duplication and desynchronisation of the generic pin group description. Acked-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20231211190321.307330-9-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-12-12pinctrl: imx: Convert to use grp memberAndy Shevchenko1-17/+14
Convert drivers to use grp member embedded in struct group_desc, because other members will be removed to avoid duplication and desynchronisation of the generic pin group description. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20231211190321.307330-8-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-12-12pinctrl: equilibrium: Convert to use grp memberAndy Shevchenko1-2/+2
Convert drivers to use grp member embedded in struct group_desc, because other members will be removed to avoid duplication and desynchronisation of the generic pin group description. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20231211190321.307330-7-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-12-12pinctrl: bcm: Convert to use grp memberAndy Shevchenko1-2/+2
Convert drivers to use grp member embedded in struct group_desc, because other members will be removed to avoid duplication and desynchronisation of the generic pin group description. Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20231211190321.307330-6-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-12-12pinctrl: core: Embed struct pingroup into struct group_descAndy Shevchenko2-3/+17
struct group_desc is a particular version of the struct pingroup with associated opaque data. Start switching pin control core and drivers to use it explicitly. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20231211190321.307330-5-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-12-12pinctrl: ingenic: Use C99 initializers in PINCTRL_PIN_GROUP()Andy Shevchenko1-8/+13
For the better flexibility use C99 initializers in PINCTRL_PIN_GROUP(). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20231211190321.307330-4-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-12-12pinctrl: mediatek: Use C99 initializers in PINCTRL_PIN_GROUP()Andy Shevchenko2-12/+12
For the better flexibility use C99 initializers in PINCTRL_PIN_GROUP(). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20231211190321.307330-3-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-12-12pinctrl: core: Add a convenient define PINCTRL_GROUP_DESC()Andy Shevchenko2-4/+10
Add PINCTRL_GROUP_DESC() macro for inline use. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20231211190321.307330-2-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-12-12Merge tag 'gpio-remove-gpiochip_is_requested-for-v6.8-rc1' of ↵Linus Walleij4-13/+23
git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux into devel gpio: remove gpiochip_is_requested() - provide a safer alternative to gpiochip_is_requested() - convert all existing users - remove gpiochip_is_requested()
2023-12-08pinctrl: sppctl: use gpiochip_dup_line_label()Bartosz Golaszewski1-5/+5
Use the new gpiochip_dup_line_label() helper to safely retrieve the descriptor label. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2023-12-08pinctrl: baytrail: use gpiochip_dup_line_label()Bartosz Golaszewski1-5/+6
Use the new gpiochip_dup_line_label() helper to safely retrieve the descriptor label. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2023-12-08pinctrl: nomadik: use gpiochip_dup_line_label()Bartosz Golaszewski1-1/+5
Use the new gpiochip_dup_line_label() helper to safely retrieve the descriptor label. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2023-12-08pinctrl: abx500: use gpiochip_dup_line_label()Bartosz Golaszewski1-2/+7
Use the new gpiochip_dup_line_label() helper to safely retrieve the descriptor label. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2023-12-07pinctrl: nuvoton: Convert to use struct pingroup and PINCTRL_PINGROUP()Andy Shevchenko1-5/+4
The pin control header provides struct pingroup and PINCTRL_PINGROUP() macro. Utilize them instead of open coded variants in the driver. Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20231204160033.1872569-6-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-12-07pinctrl: keembay: Convert to use struct pingroupAndy Shevchenko1-2/+2
The pin control header provides struct pingroup. Utilize it instead of open coded variants in the driver. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20231204160033.1872569-5-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-12-07pinctrl: equilibrium: Convert to use struct pingroupAndy Shevchenko1-13/+13
The pin control header provides struct pingroup. Utilize it instead of open coded variants in the driver. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20231204160033.1872569-4-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2023-12-07pinctrl: core: Make pins const unsigned int pointer in struct group_descAndy Shevchenko2-3/+3
It's unclear why it's not a const unsigned int pointer from day 1. Make the pins member const unsigned int pointer in struct group_desc. Update necessary APIs. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20231204160033.1872569-3-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>