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2019-03-28net: phy: mdio-bcm-unimac: remove redundant !timeout checkColin Ian King1-4/+1
The check for zero timeout is always true at the end of the proceeding while loop; the only other exit path in the loop is if the unimac MDIO is not busy. Remove the redundant zero timeout check and always return -ETIMEDOUT on this timeout return path. Signed-off-by: Colin Ian King <colin.king@canonical.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-03-27net: phy: marvell: add PHY tunable fast link down support for 88E1540Heiner Kallweit1-0/+108
1000BaseT standard requires that a link is reported as down earliest after 750ms. Several use case however require a much faster detecion of a broken link. Fast Link Down supports this by intentionally violating a the standard. This patch exposes the Fast Link Down feature of 88E1540 and 88E6390. These PHY's can be found as internal PHY's in several switches: 88E6352, 88E6240, 88E6176, 88E6172, and 88E6390(X). Fast Link Down and EEE are mutually exclusive. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-03-27net: dsa: mv88e6xxx: remove unneeded cmode initializationHeiner Kallweit2-12/+0
This partially reverts ed8fe20205ac ("net: dsa: mv88e6xxx: prevent interrupt storm caused by mv88e6390x_port_set_cmode"). I missed that chip->ports[].cmode is overwritten anyway by the cmode caching in mv88e6xxx_setup(). Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-03-27bnx2x: Utilize FW 7.13.11.0.Sudarsana Reddy Kalluru1-7/+14
Commit 8fcf0ec44c11f "bnx2x: Add FW 7.13.11.0" added said .bin FW to linux-firmware; This patch incorporates the FW in the bnx2x driver. This introduces few FW fixes and the support for Tx VLAN filtering. Please consider applying it to 'net-next' tree. Signed-off-by: Sudarsana Reddy Kalluru <skalluru@marvell.com> Signed-off-by: Ariel Elior <aelior@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-03-27Merge branch '100GbE' of ↵David S. Miller9-187/+630
git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/next-queue Jeff Kirsher says: ==================== 100GbE Intel Wired LAN Driver Updates 2019-03-26 This series contains more updates to the ice driver only. Jeremiah provides his first patch to the Linux kernel to clean up un-necessary newlines in driver log messages. Mitch updates the ice driver to use existing status codes in the iavf driver so that when errors occur, it will not report nonsensical results. Adds support for VF admin queue interrupts by programming the VPINT_MBX_CTL register array. Brett adds a check for a bit that we set while preparing for a reset, to ensure we are prepared to do a proper reset. Also implemented PCI error handling operations. Went through and audited the hot path with pahole and made modifications based on the results since 2 structures were taking up more space than necessary due to cache alignment issues. Fixed an issue where when flow control was disabled, the state of flow control was being displayed as "Unknown". Anirudh fixes adaptive interrupt moderation changes by adding code that was missed, that should have been added in the initial patch to add that support. Cleaned up a function prototype that was never implemented. Did additional code cleanup by removing unneeded braces and redundant code comments. Akeem fixes an issue that occurs when the VF is attempting to remove the default LAN/MAC address, which is programmed by the administrator by updating the error message to explicitly say that the VF cannot change the MAC programmed by the PF. Preethi fixes the driver to not fall into the error path when a added filter already exists, but instead continue to process the rest of the function and add appropriate checks after adding MAC filters. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
2019-03-27net: mvpp2: cls: Rework C2 engine macrosMaxime Chevallier1-21/+7
The C2 classification engine has a 256 entry TCAM, used for ternary matches on an 8 byte Header Extracted Key. For now, we compute the various indices for classification and RSS that use this engine thanks to a set of macros. This commit mainly renames the macros used to make it clear that they should be used with the C2 engine, but also make use of the full 256 entries in the engine. For now, the C2 entries are only used for RSS. These entries are put at the end of the TCAM range, in case we want to add higher priority matches later on. Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-03-27net: mvpp2: cls: Initialize lookup priorities for all entries in the flowMaxime Chevallier1-13/+24
When classifying a packet pertaining to a given flow, the classifier will issue multiple lookup commands until it finds one with the 'last' bit set. It expects all prorities to be assign continuously (although not necessarily in an ordered fashion) from 0 to the number of lookups. We can initialize this once, and make sure unused lookups are given an empty port map. This avoids having to maintain priorities and the information of which lookup is the last. Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-03-27net: mvpp2: cls: Invalidate all C2 entries except the ones we useMaxime Chevallier3-0/+30
C2 TCAM entries can be invalidated to avoid unwanted matches. Make sure all entries are invalidated at init, then validate only the ones we use. Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-03-27net: mvpp2: cls: Rename the flow table macrosMaxime Chevallier3-15/+14
The Flow Table dictates what lookups will be issued for each flow type. The lookup sequence for each flow is similar, and the index of each lookup is computed by some macros. There are similar mechanisms for the C2 TCAM lookups, so in order to avoid confusion, rename the flow table index computing macros with a common prefix. The only difference in behaviour is that we now use the very first entry in the flow for the RSS lookup (the first entry was previously unused). Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-03-27net: mvpp2: cls: Don't use the sequence attribute for classificationMaxime Chevallier2-18/+0
The classifier allows to combine multiple lookups in one "sequence" that is counted as a single lookup to an engine, with a single result. We don't actually use that feature, so remove any places where we set this field, so that the classifier doesn't try to interpret these fields. Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-03-27net: mvpp2: cls: Rename classifer per-port functionsMaxime Chevallier3-10/+9
This commit renames some of the classifier functions to follow the naming 'mvpp2_port_*' that's used for function that act on a given port. This commit is purely cosmetic. Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-03-27net: mvpp2: cls: Move C2 read/write helpers aroundMaxime Chevallier1-41/+41
Move C2 read/write helpers higher in the file to ease future work that rely on these helpers Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-03-27net: mvpp2: cls: Write C2 TCAM data last when writing a C2 entryMaxime Chevallier1-7/+7
When writing a C2 entry to hardware, some registers writes will only take effect when the TCAM_DATA4 register is written. This includes all C2 TCAM registers, and the C2 invalidate register. To make sure we always write C2 entries correctly, document that behaviour with a comment, and move TCAM writes to the end of the mvpp2_cls_c2_write helper. Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-03-27net: mvpp2: cls: Use iterators to go through the cls_tableMaxime Chevallier2-8/+25
The cls_table is a global read-only table containing the different parameters that are used by various tables in the classifier. It describes the links between the Header Parser, the decoding table and the flow_table. There are several possible way we want to iterate over that table, depending on wich classifier engine we want to configure. For the Header Parser, we want to iterate over each entry. For the Decoding table, we want to iterate over each entry having a unique flow_id. Finally, when configuring an ethtool flow, we want to iterate over each entry having a unique flow_id and that has a given flow_type. This commit introduces some iterator to both provide syntactic sugar and also clarify the way we want to iterate over the table. Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-03-27net: mvpp2: debugfs: Allow reading the C2 engine table from debugfsMaxime Chevallier1-17/+59
PPv2's Classifier uses multiple engines to perform classification. So far, only the C2 engine is used, which has a 256 entries TCAM. So far, we only accessed the relevant entries from the C2 engines, which are the one implementing RSS. To implement and debug ntuple classification offload, beaing able to see the hit count for each C2 entry is helpful, so this commit moves the logic to a dedicated directory allowing to access each entry. Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-03-27net: mvpp2: debugfs: Allow reading the flow table from debugfsMaxime Chevallier1-6/+63
The Classifier flow table is the central part of the PPv2 Classifier, since it describes all classification steps performed for each flow. It has 512 entries, shared between all ports, which are divided into sequences that are pointed-to by the decoding table. Being able to see which entries in the flow table were hit is a key point when implementing and debugging classification offload. This commit allows reading each flow table entry's hit count independently, with a clear-on-read behaviour. Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-03-27net: mvpp2: debugfs: Store debugfs entries data in mvpp2 structMaxime Chevallier2-72/+26
The current way to store the required private data needed to access various debugfs entries is to alloc them on the fly, share them within the entries that need to access them, and finally have one entry free that data upon closing. This leads to hard to maintain code, and is very error-prone. This commit stores all debugfs related data in the same place, making sure this is allocated only when the debugfs directory is successfully created, so that we don't waste memory when we don't use this feature. Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-03-27net: mvpp2: cls: Make the flow definitions constMaxime Chevallier3-14/+15
The cls_flow table represent the overall configuration of the classifier, used to match the different traffic classes in the Parsing and Classification engines. This configuration is static, and applies to all PPv2 instances, we must therefore keep it const so that no modifications of this table are performed at runtime. Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-03-27net: mvpp2: cls: Rename MVPP2_N_FLOWS to MVPP2_N_PRS_FLOWSMaxime Chevallier4-7/+10
The macro definition MVPP2_N_FLOWS is ambiguous because it really represents the number of entries in the Header Parser that are used to identify the classification flows. Rename the macro to clearly state that we represent the number of flows in the Header Parser. Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-03-27net: mvpp2: cls: use Lookup Type in classification enginesMaxime Chevallier3-0/+21
The PPv2 classifier allows to perform multiple lookups on the same engine when classifying a packet. These lookups can match similar parts of a packet header, but perform different actions upon matching. To differentiate these types of lookups, it's possible to specify a Lookup Type in the flow table entries, which will be part of the key for the lookup engines. This commit introduces the use of Lookup Types for C2 matches. Since for now we only perform C2 lookups to enable RSS, we only need one Lookup Type. Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-03-27net: mvpp2: cls: Start cls flow entries from beginning of tableMaxime Chevallier1-3/+5
The Classifier flow table has 512 entries, that contains lookups commands executed consecutively for every flow. Since we have 21 different flows, we have to carefully manage the flow table use. As of today, the start index of a lookup sequence is computed directly based in the flow->id. There are 8 reserved flow ids, from 0-7, which don't have any corresponding sequence in the flow table. We can therefore ignore them when computing the index, and make so that the first non-reserved flow point to the very beginning of the flow table. Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Suggested-by: Alan Winkowski <walan@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-03-27net: mvpp2: cls: Add missing MAC_DA field extractionMaxime Chevallier1-0/+3
PPv2's classifier supports extracting the MAC Destination Address from the L2 header to perform RSS and flow steering. Add the missing case when setting the Header Extracted Key fields in the flow table. Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-03-27net: mvpp2: Don't use an int to store netdev_features_tMaxime Chevallier1-1/+1
int is not long enough to store all netdev_features, use the correct dedicated type to store them when building the list of dev->features. Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-03-27ice: Remove "2 BITS" commentAnirudh Venkataramanan1-6/+6
Some enums in ice_tx_desc_cmd_bits have a trailing /* 2 BITS */ comment, but the value has just one bit set (ex. ICE_TX_DESC_CMD_L4T_EOFT_SCTP has the value 0x200 (i.e. only bit 9 is set). This is confusing and misleading. So remove the comment. Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
2019-03-27ice: Update comment regarding the ITR_GRAN_SBrett Creeley1-1/+1
Since the driver now hard codes the ITR granularity to 2 us in the GLINT_CTL register the comment next to ITR_GRAN_S needs to be updated. Signed-off-by: Brett Creeley <brett.creeley@intel.com> Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
2019-03-27ice: Update function header for __ice_vsi_get_qsAnirudh Venkataramanan1-4/+3
Remove some redundant text in the function header for __ice_vsi_get_qs Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
2019-03-27ice: Remove unnecessary bracesAnirudh Venkataramanan1-2/+1
Single statement if conditions don't need braces. Remove it. Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
2019-03-27ice: Remove unused function prototypeAnirudh Venkataramanan1-2/+0
Commit 37bb83901286 ("ice: Move common functions out of ice_main.c part 7/7") seems to have inadvertently introduced a function prototype for ice_vsi_cfg_tc without a corresponding function implementation. Remove it. Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
2019-03-27ice: Add missing case in print_link_msg for printing flow controlBrett Creeley1-0/+3
Currently we aren't checking for the ICE_FC_NONE case for the current flow control mode. This is causing "Unknown" to be printed for the current flow control method if flow control is disabled. Fix this by adding the case for ICE_FC_NONE to print "None". Signed-off-by: Brett Creeley <brett.creeley@intel.com> Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
2019-03-27ice: Audit hotpath structures with paholeBrett Creeley4-20/+15
Currently the ice_q_vector structure and ice_ring_container structure are taking up more space than necessary due to cache alignment holes and unnecessary variables respectively. This is not helping the driver's performance. The following fixes were done to improve cache alignment, reduce wasted space, and increase performance. 1. Remove the ice_latency_range enum as it is unused. 2. Remove the latency_range variable in the ice_ring_container structure. 3. Change the size of the itr_idx in the ice_ring_container structure from an int to an u16. This reduced the size of ice_ring_container structure to 32 Bytes so it has no holes or padding. 4. Re-arrange the ice_q_vector structure using pahole to align members as best as possible in regards to 64 Byte cache line size. Signed-off-by: Brett Creeley <brett.creeley@intel.com> Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
2019-03-27ice: Do not bail out when filter already existsPreethi Banala1-1/+5
If filter already exists, do not go through error path flow but instead continue to process rest of the function. Hence have an appropriate check after adding MAC filters. Signed-off-by: Preethi Banala <preethi.banala@intel.com> Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
2019-03-27ice: Fix issue with VF attempt to delete default MAC addressAkeem G Abodunrin1-8/+7
This patch fixes issue that occurs when VF is attempting to remove default LAN/MAC address, which is programmed by the administrator. We shouldn't return error for the call by the VF, but continue with the remaining steps to handle MAC opcode. Also update the dev_err message to explicitly say that VF can't change MAC programmed by PF. Also change "mac" to "MAC" for kernel print statements in the same file. Signed-off-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com> Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
2019-03-27ice: enable VF admin queue interruptsMitch Williams2-0/+6
The VPINT_MBX_CTL register array must be programmed to enable VF admin queue interrupts. Without this, VFs never get interrupts on vector 0, and some VF drivers will fail to init. Signed-off-by: Mitch Williams <mitch.a.williams@intel.com> Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
2019-03-27ice: Fix for adaptive interrupt moderationAnirudh Venkataramanan3-24/+275
commit 63f545ed1285 ("ice: Add support for adaptive interrupt moderation") was meant to add support for adaptive interrupt moderation but there was an error on my part while formatting the patch, and thus only part of the patch ended up being submitted. This patch rectifies the error by adding the rest of the code. Fixes: 63f545ed1285 ("ice: Add support for adaptive interrupt moderation") Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
2019-03-26ice: Implement pci_error_handler opsBrett Creeley1-0/+151
This patch implements the following pci_error_handler ops: .error_detected = ice_pci_err_detected .slot_reset = ice_pci_err_slot_reset .reset_notify = ice_pci_err_reset_notify .reset_prepare = ice_pci_err_reset_prepare .reset_done = ice_pci_err_reset_done .resume = ice_pci_err_resume Signed-off-by: Brett Creeley <brett.creeley@intel.com> Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
2019-03-26ice: Put __ICE_PREPARED_FOR_RESET check in ice_prepare_for_resetBrett Creeley1-2/+5
Currently we check if the __ICE_PREPARED_FOR_RESET bit is set prior to calling ice_prepare_for_reset in ice_reset_subtask(), but we aren't checking that bit in ice_do_reset() before calling ice_prepare_for_reset(). This is not consistent and can cause issues if ice_prepare_for_reset() is called prior to ice_do_reset(). Fix this by checking if the __ICE_PREPARED_FOR_RESET bit is set internal to ice_prepare_for_reset(). Signed-off-by: Brett Creeley <brett.creeley@intel.com> Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
2019-03-26ice: use virt channel status codesMitch Williams1-119/+154
When communicating with the AVF driver, we need to use the status codes from virtchnl.h, not our own ice-specific codes. Without this, when an error occurs, the VF will report nonsensical results. NOTE: this depends on changes made to include/linux/avf/virtchnl.h by commit bb58fd7eeffc ("i40e: Update status codes") Signed-off-by: Mitch Williams <mitch.a.williams@intel.com> Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
2019-03-26ice: Remove unnecessary newlines from log messagesJeremiah Kyle1-2/+2
Two log messages contained newlines in the middle of the message. This resulted in unexpected driver log output. This patch removes the newlines to restore consistency with the rest of the driver log messages. Signed-off-by: Jeremiah Kyle <jeremiah.kyle@intel.com> Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
2019-03-26dpaa2-eth: use netif_receive_skb_listIoana Ciornei2-1/+8
Take advantage of the software Rx batching by using netif_receive_skb_list instead of napi_gro_receive. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-03-26net: phy: aquantia: inform about proprietary 1000Base-T2 mode being in useHeiner Kallweit1-1/+13
The AQCS109 supports a proprietary 2-pair 1Gbps mode. The standard registers don't allow to tell between 1000BaseT and 1000BaseT2. Add reporting this proprietary mode based on a vendor register. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-03-26net: phy: aquantia: report PHY details like firmware versionHeiner Kallweit1-0/+62
Add reporting firmware details. These details are available only once the firmware has finished initializing the chip. This can take some time and we need to poll for init completion. v2: - Propagate timeout in aqr107_wait_reset_complete(). Don't bail out completely on timeout because chip may be functional even w/o firmware image. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-03-26net: phy: aquantia: print remote capabilities if link partner is Aquantia PHYHeiner Kallweit1-0/+49
If both link partners are Aquantia PHY's then additional information is exchanged as part of the auto-negotiation. Report remote capabilities if link partner is Aquantia PHY. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-03-26net: phy: aquantia: simplify aqr_config_anegHeiner Kallweit1-32/+13
Simplify aqr_config_aneg(). Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2019-03-25ice: Create a generic name for the ice_rx_flg64_bits structureChinh T Cao2-30/+30
This structure is used to define the packet flags. These flags are applicable for both TX and RX packet. Thus, this patch changes its name from ice_rx_flag64_bits to ice_flg64_bits, and its member definition. Signed-off-by: Chinh T Cao <chinh.t.cao@intel.com> Reviewed-by: Bruce Allan <bruce.w.allan@intel.com> Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
2019-03-25ice: add and use new ice_for_each_traffic_class() macroBruce Allan4-4/+7
There are numerous for() loops iterating over each of the max traffic classes. Use a simple iterator macro instead to make the code cleaner. Signed-off-by: Bruce Allan <bruce.w.allan@intel.com> Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
2019-03-25ice: change VF VSI tc info along with num_queuesPreethi Banala1-0/+3
Update VF VSI tc info along with vsi->num_txq/num_rxq when VF requests to configure queues. Signed-off-by: Preethi Banala <preethi.banala@intel.com> Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
2019-03-25ice: Prevent unintended multiple chain resetsDave Ertman1-2/+8
In the current implementation of ice_reset_subtask, if multiple reset types are set in the pf->state, the most intrusive one is meant to be performed only, but the bits requesting the other types are not being cleared. This would lead to another reset being performed the next time the service task is scheduled. Change the flow of ice_reset_subtask so that all reset request bits in pf->state are cleared, and we still perform the most intrusive of the resets requested. Signed-off-by: Dave Ertman <david.m.ertman@intel.com> Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
2019-03-25ice: map Rx buffer pages with DMA attributesMaciej Fijalkowski2-4/+23
Provide DMA_ATTR_WEAK_ORDERING and DMA_ATTR_SKIP_CPU_SYNC attributes to the DMA API during the mapping operations on Rx side. With this change the non-x86 platforms will be able to sync only with what is being used (2k buffer) instead of entire page. This should yield a slight performance improvement. Furthermore, DMA unmap may destroy the changes that were made to the buffer by CPU when platform is not a x86 one. DMA_ATTR_SKIP_CPU_SYNC attribute usage fixes this issue. Also add a sync_single_for_device call during the Rx buffer assignment, to make sure that the cache lines are cleared before device attempting to write to the buffer. Signed-off-by: Maciej Fijalkowski <maciej.fijalkowski@intel.com> Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
2019-03-25ice: Limit the ice_add_rx_frag to frag additionMaciej Fijalkowski1-81/+79
Refactor ice_fetch_rx_buf and ice_add_rx_frag in a way that we have standalone functions that do either the skb construction or frag addition to previously constructed skb. The skb handling between rx_bufs is spread among various functions. The ice_get_rx_buf will retrieve the skb pointer from rx_buf and if it is a NULL pointer then we do the ice_construct_skb, otherwise we add a frag to the current skb via ice_add_rx_frag. Then, on the ice_put_rx_buf the skb pointer that belongs to rx_buf will be cleared. Moving further, if the current frame is not EOP frame we assign the current skb to the rx_buf that is pointed by updated next_to_clean indicator. What is more during the buffer reuse let's assign each member of ice_rx_buf individually so we avoid the unnecessary copy of skb. Last but not least, this logic split will allow us for better code reuse when adding a support for build_skb. Signed-off-by: Maciej Fijalkowski <maciej.fijalkowski@intel.com> Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
2019-03-25ice: Gather the rx buf clean-up logic for better reuseMaciej Fijalkowski1-26/+50
Pull out the code responsible for page counting and buffer recycling so that it will be possible to clean up the Rx buffers in cases where we won't allocate skb (ex. XDP) Signed-off-by: Maciej Fijalkowski <maciej.fijalkowski@intel.com> Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>