index
:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
include
/
linux
/
clk
/
tegra.h
Age
Commit message (
Expand
)
Author
Files
Lines
2017-03-20
clk: tegra: Add SATA seq input control
Peter De Schrijver
1
-0
/
+1
2017-03-20
clk: tegra: Handle UTMIPLL IDDQ
Peter De Schrijver
1
-0
/
+2
2016-04-28
clk: tegra: Add interface to enable hardware control of SATA/XUSB PLLs
Andrew Bresticker
1
-0
/
+5
2015-07-20
clk: tegra: Properly include clk.h
Stephen Boyd
1
-1
/
+2
2015-02-02
clk: tegra: make tegra_clocks_apply_init_table() arch_initcall
Peter De Schrijver
1
-2
/
+0
2013-12-12
clk: tegra: remove legacy reset APIs
Stephen Warren
1
-7
/
+0
2013-06-25
clk: tegra: fix ifdef for tegra_periph_reset_assert inline
Stephen Warren
1
-1
/
+1
2013-06-22
clk: tegra: provide tegra_periph_reset_assert alternative
Arnd Bergmann
1
-0
/
+5
2013-05-31
clk: tegra: Use common of_clk_init function
Prashant Gaikwad
1
-1
/
+0
2013-04-05
clk: tegra: defer application of init table
Stephen Warren
1
-0
/
+1
2013-01-28
ARM: tegra: remove legacy clock code
Prashant Gaikwad
1
-2
/
+0
2013-01-28
ARM: tegra: migrate to new clock code
Prashant Gaikwad
1
-0
/
+5
2013-01-28
ARM: tegra: move tegra_cpu_car.h to linux/clk/tegra.h
Prashant Gaikwad
1
-0
/
+124