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Now the core has been migrated across to the new direct clock
specification we can move the drivers back to the normal set_fmt
callback.
Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20220519154318.2153729-41-ckeepax@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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As part of updating the core to directly tell drivers if they are clock
provider or consumer update these CPU side drivers to use the new direct
callback.
Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20220519154318.2153729-14-ckeepax@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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cppcheck reports the following warning:
sound/soc/mediatek/mt8195/mt8195-dai-etdm.c:1299:10: style: Variable
'ret' is assigned a value that is never used. [unreadVariable]
int ret = 0;
^
The suggested change aligns the implementation of
mt8195_afe_disable_etdm() with mt8195_afe_enable_etdm() - same
negative return value upon error.
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20211025185933.144327-8-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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The pointer etdm_data is being inintialized with a value that is never
read, it is later being re-assigned a new value. Remove the redundant
initialization.
Addresses-Coverity: ("Unused value")
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Acked-by: Trevor Wu <trevor.wu@mediatek.com>
Link: https://lore.kernel.org/r/20210903114928.11743-1-colin.king@canonical.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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There is a spelling mistake in a dev_dbg message. Fix it.
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Link: https://lore.kernel.org/r/20210826112611.10356-1-colin.king@canonical.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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This patch adds mt8195 tdm/i2s dai driver.
MCLK clock tree is as follows.
PLL -> MUX -> DIVIDER -> MCLK
For PLL source of MCLK, driver only supports APLL1 and APLL2 now.
APLL3 and APLL4 are used to track external clock source, so they are
only used when slave input is connected.
For example,
case 1: (HDMI RX connected)
DL memif (a1sys) -> etdm out2 (clk from apll1/apll2) -> codec
case 2: (HDMI RX disconnected)
HDMI RX -> a3sys -> UL memif (a3sys) -> DL memif (a3sys) -> .... ->
etdm out2 (clk from apll3) -> codec
We keep all modules in the pipeline working on the same clock domain.
MCLK is expected to output the clock generated from the same clock
source as the pipeline, so dynamic reparenting is required for MCLK
configuration.
As a result, clk_set_parent() is used to select PLL source,
and clk_set_rate() is used to configure divider to get MCLK output rate.
Signed-off-by: Trevor Wu <trevor.wu@mediatek.com>
Link: https://lore.kernel.org/r/20210819084144.18483-4-trevor.wu@mediatek.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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