index
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starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
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/
tools
/
testing
/
cxl
/
test
/
mock.c
Age
Commit message (
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Author
Files
Lines
2024-02-17
cxl/test: Add support for qos_class checking
Dave Jiang
1
-0
/
+14
2023-06-26
Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxl
Dan Williams
1
-11
/
+33
2023-06-26
Revert "cxl/port: Enable the HDM decoder capability for switch ports"
Dan Williams
1
-15
/
+0
2023-06-25
cxl: Rename 'uport' to 'uport_dev'
Dan Williams
1
-5
/
+5
2023-06-25
cxl/rch: Prepare for caching the MMIO mapped PCIe AER capability
Dan Williams
1
-1
/
+3
2023-06-25
cxl/acpi: Probe RCRB later during RCH downstream port creation
Robert Richter
1
-7
/
+27
2023-05-18
cxl/port: Enable the HDM decoder capability for switch ports
Dan Williams
1
-0
/
+15
2023-05-13
tools/testing/cxl: Use DEFINE_STATIC_SRCU()
Dan Williams
1
-1
/
+1
2023-02-15
cxl/hdm: Create emulated cxl_hdm for devices that do not have HDM decoders
Dave Jiang
1
-3
/
+5
2023-02-15
cxl/hdm: Emulate HDM decoder from DVSEC range registers
Dave Jiang
1
-3
/
+4
2023-02-15
cxl/port: Export cxl_dvsec_rr_decode() to cxl_port
Dave Jiang
1
-2
/
+19
2022-12-03
cxl/acpi: Extract component registers of restricted hosts from RCRB
Robert Richter
1
-0
/
+19
2022-06-29
tools/testing/cxl: Fix cxl_hdm_decode_init() calling convention
Dan Williams
1
-3
/
+5
2022-05-19
cxl/port: Reuse 'struct cxl_hdm' context for hdm init
Dan Williams
1
-2
/
+3
2022-05-19
cxl/pci: Drop @info argument to cxl_hdm_decode_init()
Dan Williams
1
-6
/
+3
2022-05-19
cxl/mem: Merge cxl_dvsec_ranges() and cxl_hdm_decode_init()
Dan Williams
1
-4
/
+4
2022-05-19
cxl/mem: Consolidate CXL DVSEC Range enumeration in the core
Dan Williams
1
-0
/
+16
2022-05-19
cxl/pci: Move cxl_await_media_ready() to the core
Dan Williams
1
-0
/
+15
2022-02-09
cxl/core/port: Remove @host argument for dport + decoder enumeration
Dan Williams
1
-16
/
+12
2022-02-09
cxl/core/hdm: Add CXL standard decoder enumeration to the core
Dan Williams
1
-0
/
+50
2022-02-09
cxl/core: Generalize dport enumeration in the core
Dan Williams
1
-26
/
+19
2021-11-15
cxl/test: Mock acpi_table_parse_cedt()
Dan Williams
1
-21
/
+9
2021-09-21
tools/testing/cxl: Introduce a mocked-up CXL port hierarchy
Dan Williams
1
-0
/
+171