From 0c4d19b125401957123989a25094972cf0e77670 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 21 Mar 2024 16:46:37 +0530 Subject: ARM: dts: qcom: ipq8064: Add PCIe bridge node On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-17-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi index 2eb6758b6a3a..f128510d8445 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi @@ -1121,6 +1121,16 @@ status = "disabled"; perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1: pcie@1b700000 { @@ -1172,6 +1182,16 @@ status = "disabled"; perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie2: pcie@1b900000 { @@ -1223,6 +1243,16 @@ status = "disabled"; perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; qsgmii_csr: syscon@1bb00000 { -- cgit v1.2.3