From e25b469367343a650799c8da14daa9c1f2a1ecad Mon Sep 17 00:00:00 2001 From: Emil Renner Berthing Date: Sat, 22 Jul 2023 16:36:17 +0200 Subject: riscv: dts: starfive: Add JH7100 USB node Add the device tree node for the USB 3.0 peripheral on the StarFive JH7100 SoC. Signed-off-by: Emil Renner Berthing --- arch/riscv/boot/dts/starfive/jh7100-common.dtsi | 5 +++++ arch/riscv/boot/dts/starfive/jh7100.dtsi | 26 +++++++++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi index ae1a6aeb0aea..98da35d95094 100644 --- a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi @@ -398,3 +398,8 @@ pinctrl-0 = <&uart3_pins>; status = "okay"; }; + +&usb3 { + dr_mode = "host"; + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi index 1e7f33dcdf2f..7fc7bf6b3830 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -255,6 +255,32 @@ #reset-cells = <1>; }; + usb3: usb@104c0000 { + compatible = "starfive,jh7100-usb"; + ranges = <0x0 0x0 0x104c0000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&audclk JH7100_AUDCLK_USB_LPM>, + <&audclk JH7100_AUDCLK_USB_STB>, + <&clkgen JH7100_CLK_USB_AXI>, + <&clkgen JH7100_CLK_USBNOC_AXI>; + clock-names = "lpm", "stb", "axi", "nocaxi"; + resets = <&rstgen JH7100_RSTN_USB_AXI>, + <&rstgen JH7100_RSTN_USBNOC_AXI>; + reset-names = "axi", "nocaxi"; + status = "disabled"; + + usb_cdns3: usb@0 { + compatible = "cdns,usb3"; + reg = <0x00000 0x10000>, + <0x10000 0x10000>, + <0x20000 0x10000>; + reg-names = "otg", "xhci", "dev"; + interrupts = <44>, <52>, <43>; + interrupt-names = "host", "peripheral", "otg"; + }; + }; + clkgen: clock-controller@11800000 { compatible = "starfive,jh7100-clkgen"; reg = <0x0 0x11800000 0x0 0x10000>; -- cgit v1.2.3