From e387d448e4899f4bbf7c8151472a2fed72063d82 Mon Sep 17 00:00:00 2001 From: Chanho Park Date: Mon, 18 Oct 2021 21:42:04 +0900 Subject: scsi: ufs: ufs-exynos: Change pclk available max value To support 167MHz PCLK, we need to adjust the maximum value. Link: https://lore.kernel.org/r/20211018124216.153072-4-chanho61.park@samsung.com Reviewed-by: Alim Akhtar Reviewed-by: Inki Dae Signed-off-by: Chanho Park Signed-off-by: Martin K. Petersen --- drivers/scsi/ufs/ufs-exynos.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/scsi/ufs/ufs-exynos.h b/drivers/scsi/ufs/ufs-exynos.h index dadf4fd10dd8..0a31f77a5f48 100644 --- a/drivers/scsi/ufs/ufs-exynos.h +++ b/drivers/scsi/ufs/ufs-exynos.h @@ -99,7 +99,7 @@ struct exynos_ufs; #define PA_HIBERN8TIME_VAL 0x20 #define PCLK_AVAIL_MIN 70000000 -#define PCLK_AVAIL_MAX 133000000 +#define PCLK_AVAIL_MAX 167000000 struct exynos_ufs_uic_attr { /* TX Attributes */ -- cgit v1.2.3