From 83adc98ec0d8aaa527cac57c9102363a24876783 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Fri, 30 Jun 2023 13:52:29 +0530 Subject: dt-bindings: dma: Add support for SM6115 and QCM2290 SoCs Add new compatible for BAM DMA engine version v1.7.4 which is found on Qualcomm SM6115 and QCM2290 SoCs. Since its very similar to v1.7.0 used on SM8150 like SoCs, mark the comptible scheme accordingly. While at it, also update qcom,bam-dma bindings to add comments which describe the BAM DMA versions used in SM8150 and SM8250 SoCs. This provides an easy reference for identifying the actual BAM DMA version available on Qualcomm SoCs. Acked-by: Rob Herring Tested-by: Anders Roxell Tested-by: Linux Kernel Functional Testing Signed-off-by: Bhupesh Sharma Link: https://lore.kernel.org/r/20230630082230.2264698-2-bhupesh.sharma@linaro.org Signed-off-by: Vinod Koul --- .../devicetree/bindings/dma/qcom,bam-dma.yaml | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) (limited to 'Documentation/devicetree/bindings/dma') diff --git a/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml b/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml index f1ddcf672261..c663b6102f50 100644 --- a/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml +++ b/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml @@ -15,13 +15,19 @@ allOf: properties: compatible: - enum: - # APQ8064, IPQ8064 and MSM8960 - - qcom,bam-v1.3.0 - # MSM8974, APQ8074 and APQ8084 - - qcom,bam-v1.4.0 - # MSM8916 and SDM845 - - qcom,bam-v1.7.0 + oneOf: + - enum: + # APQ8064, IPQ8064 and MSM8960 + - qcom,bam-v1.3.0 + # MSM8974, APQ8074 and APQ8084 + - qcom,bam-v1.4.0 + # MSM8916, SDM630 + - qcom,bam-v1.7.0 + - items: + - enum: + # SDM845, SM6115, SM8150, SM8250 and QCM2290 + - qcom,bam-v1.7.4 + - const: qcom,bam-v1.7.0 clocks: maxItems: 1 -- cgit v1.2.3 From fbac8ceb441508a0100888fd62f98c32a1d9f506 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Fri, 30 Jun 2023 13:52:30 +0530 Subject: dt-bindings: dma: Increase iommu maxItems for BAM DMA Since SM8250 BAM DMA engine supports six iommu entries, increase the maxItems in the iommu property section, without which 'dtbs_check' would throw errors. Acked-by: Krzysztof Kozlowski Tested-by: Anders Roxell Tested-by: Linux Kernel Functional Testing Signed-off-by: Bhupesh Sharma Link: https://lore.kernel.org/r/20230630082230.2264698-3-bhupesh.sharma@linaro.org Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation/devicetree/bindings/dma') diff --git a/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml b/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml index c663b6102f50..6433f2892ae4 100644 --- a/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml +++ b/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml @@ -44,7 +44,7 @@ properties: iommus: minItems: 1 - maxItems: 4 + maxItems: 6 num-channels: $ref: /schemas/types.yaml#/definitions/uint32 -- cgit v1.2.3 From dfcfe386d025fe94ee4373777c6b84eba8988a38 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Sat, 17 Jun 2023 15:36:15 +0200 Subject: dt-bindings: dma: convert bcm2835-dma bindings to YAML Convert the DT binding document for bcm2835-dma from .txt to YAML. Signed-off-by: Stefan Wahren Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20230617133620.53129-3-stefan.wahren@i2se.com Signed-off-by: Vinod Koul --- .../devicetree/bindings/dma/brcm,bcm2835-dma.txt | 83 ----------------- .../devicetree/bindings/dma/brcm,bcm2835-dma.yaml | 102 +++++++++++++++++++++ 2 files changed, 102 insertions(+), 83 deletions(-) delete mode 100644 Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt create mode 100644 Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.yaml (limited to 'Documentation/devicetree/bindings/dma') diff --git a/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt b/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt deleted file mode 100644 index b6a8cc0978cd..000000000000 --- a/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt +++ /dev/null @@ -1,83 +0,0 @@ -* BCM2835 DMA controller - -The BCM2835 DMA controller has 16 channels in total. -Only the lower 13 channels have an associated IRQ. -Some arbitrary channels are used by the firmware -(1,3,6,7 in the current firmware version). -The channels 0,2 and 3 have special functionality -and should not be used by the driver. - -Required properties: -- compatible: Should be "brcm,bcm2835-dma". -- reg: Should contain DMA registers location and length. -- interrupts: Should contain the DMA interrupts associated - to the DMA channels in ascending order. -- interrupt-names: Should contain the names of the interrupt - in the form "dmaXX". - Use "dma-shared-all" for the common interrupt line - that is shared by all dma channels. -- #dma-cells: Must be <1>, the cell in the dmas property of the - client device represents the DREQ number. -- brcm,dma-channel-mask: Bit mask representing the channels - not used by the firmware in ascending order, - i.e. first channel corresponds to LSB. - -Example: - -dma: dma@7e007000 { - compatible = "brcm,bcm2835-dma"; - reg = <0x7e007000 0xf00>; - interrupts = <1 16>, - <1 17>, - <1 18>, - <1 19>, - <1 20>, - <1 21>, - <1 22>, - <1 23>, - <1 24>, - <1 25>, - <1 26>, - /* dma channel 11-14 share one irq */ - <1 27>, - <1 27>, - <1 27>, - <1 27>, - /* unused shared irq for all channels */ - <1 28>; - interrupt-names = "dma0", - "dma1", - "dma2", - "dma3", - "dma4", - "dma5", - "dma6", - "dma7", - "dma8", - "dma9", - "dma10", - "dma11", - "dma12", - "dma13", - "dma14", - "dma-shared-all"; - - #dma-cells = <1>; - brcm,dma-channel-mask = <0x7f35>; -}; - - -DMA clients connected to the BCM2835 DMA controller must use the format -described in the dma.txt file, using a two-cell specifier for each channel. - -Example: - -bcm2835_i2s: i2s@7e203000 { - compatible = "brcm,bcm2835-i2s"; - reg = < 0x7e203000 0x24>; - clocks = <&clocks BCM2835_CLOCK_PCM>; - - dmas = <&dma 2>, - <&dma 3>; - dma-names = "tx", "rx"; -}; diff --git a/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.yaml b/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.yaml new file mode 100644 index 000000000000..c9b9a5490826 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.yaml @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/brcm,bcm2835-dma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: BCM2835 DMA controller + +maintainers: + - Nicolas Saenz Julienne + +description: + The BCM2835 DMA controller has 16 channels in total. Only the lower + 13 channels have an associated IRQ. Some arbitrary channels are used by the + VideoCore firmware (1,3,6,7 in the current firmware version). The channels + 0, 2 and 3 have special functionality and should not be used by the driver. + +allOf: + - $ref: dma-controller.yaml# + +properties: + compatible: + const: brcm,bcm2835-dma + + reg: + maxItems: 1 + + interrupts: + description: + Should contain the DMA interrupts associated to the DMA channels in + ascending order. + minItems: 1 + maxItems: 16 + + interrupt-names: + minItems: 1 + maxItems: 16 + + '#dma-cells': + description: The single cell represents the DREQ number. + const: 1 + + brcm,dma-channel-mask: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Bitmask of available DMA channels in ascending order that are + not reserved by firmware and are available to the + kernel. i.e. first channel corresponds to LSB. + +unevaluatedProperties: false + +required: + - compatible + - reg + - interrupts + - "#dma-cells" + - brcm,dma-channel-mask + +examples: + - | + dma-controller@7e007000 { + compatible = "brcm,bcm2835-dma"; + reg = <0x7e007000 0xf00>; + interrupts = <1 16>, + <1 17>, + <1 18>, + <1 19>, + <1 20>, + <1 21>, + <1 22>, + <1 23>, + <1 24>, + <1 25>, + <1 26>, + /* dma channel 11-14 share one irq */ + <1 27>, + <1 27>, + <1 27>, + <1 27>, + /* unused shared irq for all channels */ + <1 28>; + interrupt-names = "dma0", + "dma1", + "dma2", + "dma3", + "dma4", + "dma5", + "dma6", + "dma7", + "dma8", + "dma9", + "dma10", + "dma11", + "dma12", + "dma13", + "dma14", + "dma-shared-all"; + #dma-cells = <1>; + brcm,dma-channel-mask = <0x7f35>; + }; + +... -- cgit v1.2.3 From 3533913ae5390f02ba3db989ad3bfed23f436d57 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 26 Jun 2023 16:56:45 +0200 Subject: dt-bindings: dma: qcom,bam: require one of control methods The BAM DMA resources can be controlled remotely (e.g. by trusted environment; needs qcom,powered-remotely or qcom,controlled-remotely properties) or locally. In the latter case we need to provide its clock. Require one of methods of such control to properly validate DTS. Signed-off-by: Krzysztof Kozlowski Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20230626145645.646136-1-krzysztof.kozlowski@linaro.org Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'Documentation/devicetree/bindings/dma') diff --git a/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml b/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml index 6433f2892ae4..20fc8c16ded8 100644 --- a/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml +++ b/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml @@ -87,6 +87,15 @@ required: - qcom,ee - reg +anyOf: + - required: + - qcom,powered-remotely + - required: + - qcom,controlled-remotely + - required: + - clocks + - clock-names + additionalProperties: false examples: -- cgit v1.2.3 From 0f264ab788ed9a39aabb36c0b35e5821b94bcdc8 Mon Sep 17 00:00:00 2001 From: Varshini Rajendran Date: Fri, 28 Jul 2023 15:54:51 +0530 Subject: dt-bindings: dmaengine: at_xdmac: add compatible with microchip,sam9x7 Add compatible for sam9x7. Signed-off-by: Varshini Rajendran Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230728102451.265869-1-varshini.rajendran@microchip.com Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/dma/atmel-xdma.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree/bindings/dma') diff --git a/Documentation/devicetree/bindings/dma/atmel-xdma.txt b/Documentation/devicetree/bindings/dma/atmel-xdma.txt index 510b7f25ba24..76d649b3a25d 100644 --- a/Documentation/devicetree/bindings/dma/atmel-xdma.txt +++ b/Documentation/devicetree/bindings/dma/atmel-xdma.txt @@ -3,7 +3,8 @@ * XDMA Controller Required properties: - compatible: Should be "atmel,sama5d4-dma", "microchip,sam9x60-dma" or - "microchip,sama7g5-dma". + "microchip,sama7g5-dma" or + "microchip,sam9x7-dma", "atmel,sama5d4-dma". - reg: Should contain DMA registers location and length. - interrupts: Should contain DMA interrupt. - #dma-cells: Must be <1>, used to represent the number of integer cells in -- cgit v1.2.3 From 94afcfb819b3a07e55d463c29e2d594316f40b4a Mon Sep 17 00:00:00 2001 From: Radhey Shyam Pandey Date: Mon, 7 Aug 2023 11:21:40 +0530 Subject: dt-bindings: dmaengine: xilinx_dma:Add xlnx,axistream-connected property Add an optional AXI DMA property 'xlnx,axistream-connected'. This can be specified to indicate that DMA is connected to a streaming IP in the hardware design and dma driver needs to do some additional handling i.e pass metadata and perform streaming IP specific configuration. Signed-off-by: Radhey Shyam Pandey Acked-by: Rob Herring Link: https://lore.kernel.org/r/1691387509-2113129-2-git-send-email-radhey.shyam.pandey@amd.com Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation/devicetree/bindings/dma') diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt index d1700a5c36bf..fea5b09a439d 100644 --- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt @@ -49,6 +49,10 @@ Optional properties for AXI DMA and MCDMA: register as configured in h/w. Takes values {8...26}. If the property is missing or invalid then the default value 23 is used. This is the maximum value that is supported by all IP versions. + +Optional properties for AXI DMA: +- xlnx,axistream-connected: Tells whether DMA is connected to AXI stream IP. + Optional properties for VDMA: - xlnx,flush-fsync: Tells which channel to Flush on Frame sync. It takes following values: -- cgit v1.2.3 From e8cfa385054c6aa7ae8dd743d8ea980039a0fc0b Mon Sep 17 00:00:00 2001 From: Radhey Shyam Pandey Date: Mon, 7 Aug 2023 11:21:41 +0530 Subject: dt-bindings: dmaengine: xilinx_dma: Add xlnx,irq-delay property Add an optional AXI DMA property 'xlnx,irq-delay'. It specifies interrupt timeout value and causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs. This property is useful when AXI DMA is connected to the streaming IP i.e axiethernet where inter packet latency is critical while still taking the benefit of interrupt coalescing. Signed-off-by: Radhey Shyam Pandey Acked-by: Rob Herring Link: https://lore.kernel.org/r/1691387509-2113129-3-git-send-email-radhey.shyam.pandey@amd.com Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree/bindings/dma') diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt index fea5b09a439d..590d1948f202 100644 --- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt @@ -52,7 +52,9 @@ Optional properties for AXI DMA and MCDMA: Optional properties for AXI DMA: - xlnx,axistream-connected: Tells whether DMA is connected to AXI stream IP. - +- xlnx,irq-delay: Tells the interrupt delay timeout value. Valid range is from + 0-255. Setting this value to zero disables the delay timer interrupt. + 1 timeout interval = 125 * clock period of SG clock. Optional properties for VDMA: - xlnx,flush-fsync: Tells which channel to Flush on Frame sync. It takes following values: -- cgit v1.2.3 From 6eb439dff645a1f61a710abfc0d37a50e4d43d1a Mon Sep 17 00:00:00 2001 From: Frank Li Date: Mon, 21 Aug 2023 12:16:16 -0400 Subject: dt-bindings: fsl-dma: fsl-edma: add edma3 compatible string Extend Freescale eDMA driver bindings to support eDMA3 IP blocks in i.MX8QM and i.MX8QXP SoCs. In i.MX93, both eDMA3 and eDMA4 are now. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Frank Li Link: https://lore.kernel.org/r/20230821161617.2142561-12-Frank.Li@nxp.com Signed-off-by: Vinod Koul --- .../devicetree/bindings/dma/fsl,edma.yaml | 106 +++++++++++++++++++-- 1 file changed, 99 insertions(+), 7 deletions(-) (limited to 'Documentation/devicetree/bindings/dma') diff --git a/Documentation/devicetree/bindings/dma/fsl,edma.yaml b/Documentation/devicetree/bindings/dma/fsl,edma.yaml index 5fd8fc604261..437db0c62339 100644 --- a/Documentation/devicetree/bindings/dma/fsl,edma.yaml +++ b/Documentation/devicetree/bindings/dma/fsl,edma.yaml @@ -21,32 +21,41 @@ properties: - enum: - fsl,vf610-edma - fsl,imx7ulp-edma + - fsl,imx8qm-adma + - fsl,imx8qm-edma + - fsl,imx93-edma3 + - fsl,imx93-edma4 - items: - const: fsl,ls1028a-edma - const: fsl,vf610-edma reg: - minItems: 2 + minItems: 1 maxItems: 3 interrupts: - minItems: 2 - maxItems: 17 + minItems: 1 + maxItems: 64 interrupt-names: - minItems: 2 - maxItems: 17 + minItems: 1 + maxItems: 64 "#dma-cells": - const: 2 + enum: + - 2 + - 3 dma-channels: - const: 32 + minItems: 1 + maxItems: 64 clocks: + minItems: 1 maxItems: 2 clock-names: + minItems: 1 maxItems: 2 big-endian: @@ -65,6 +74,29 @@ required: allOf: - $ref: dma-controller.yaml# + - if: + properties: + compatible: + contains: + enum: + - fsl,imx8qm-adma + - fsl,imx8qm-edma + - fsl,imx93-edma3 + - fsl,imx93-edma4 + then: + properties: + "#dma-cells": + const: 3 + # It is not necessary to write the interrupt name for each channel. + # instead, you can simply maintain the sequential IRQ numbers as + # defined for the DMA channels. + interrupt-names: false + clock-names: + items: + - const: dma + clocks: + maxItems: 1 + - if: properties: compatible: @@ -72,18 +104,26 @@ allOf: const: fsl,vf610-edma then: properties: + clocks: + minItems: 2 clock-names: items: - const: dmamux0 - const: dmamux1 interrupts: + minItems: 2 maxItems: 2 interrupt-names: items: - const: edma-tx - const: edma-err reg: + minItems: 2 maxItems: 3 + "#dma-cells": + const: 2 + dma-channels: + const: 32 - if: properties: @@ -92,14 +132,22 @@ allOf: const: fsl,imx7ulp-edma then: properties: + clock: + minItems: 2 clock-names: items: - const: dma - const: dmamux0 interrupts: + minItems: 2 maxItems: 17 reg: + minItems: 2 maxItems: 2 + "#dma-cells": + const: 2 + dma-channels: + const: 32 unevaluatedProperties: false @@ -153,3 +201,47 @@ examples: clock-names = "dma", "dmamux0"; clocks = <&pcc2 IMX7ULP_CLK_DMA1>, <&pcc2 IMX7ULP_CLK_DMA_MUX1>; }; + + - | + #include + #include + + dma-controller@44000000 { + compatible = "fsl,imx93-edma3"; + reg = <0x44000000 0x200000>; + #dma-cells = <3>; + dma-channels = <31>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&clk IMX93_CLK_EDMA1_GATE>; + clock-names = "dma"; + }; -- cgit v1.2.3