From 6bc6af375c7025663fbc36bcb7e91f3af653742b Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 15 Nov 2022 16:27:19 +0100 Subject: dt-bindings: arm-smmu: Allow 3 power domains on SM6375 MMU500 The SMMU on SM6375 requires 3 power domains to be active. Add an appropriate description of that. Signed-off-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Acked-by: Will Deacon Link: https://lore.kernel.org/r/20221115152727.9736-2-konrad.dybcio@linaro.org Signed-off-by: Will Deacon --- .../devicetree/bindings/iommu/arm,smmu.yaml | 23 +++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree/bindings/iommu') diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index b28c5c2b0ff2..895ec8418465 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -201,7 +201,8 @@ properties: maxItems: 7 power-domains: - maxItems: 1 + minItems: 1 + maxItems: 3 nvidia,memory-controller: description: | @@ -366,6 +367,26 @@ allOf: - description: interface clock required to access smmu's registers through the TCU's programming interface. + - if: + properties: + compatible: + contains: + const: qcom,sm6375-smmu-500 + then: + properties: + power-domains: + items: + - description: SNoC MMU TBU RT GDSC + - description: SNoC MMU TBU NRT GDSC + - description: SNoC TURING MMU TBU0 GDSC + + required: + - power-domains + else: + properties: + power-domains: + maxItems: 1 + examples: - |+ /* SMMU with stream matching or stream indexing */ -- cgit v1.2.3