From 2529085831b01fcd02ff58ab4e2596d3b31bcf80 Mon Sep 17 00:00:00 2001 From: William Qiu Date: Fri, 22 Dec 2023 17:45:45 +0800 Subject: dt-bindings: pwm: Add bindings for OpenCores PWM Controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add bindings for OpenCores PWM Controller. Signed-off-by: William Qiu Reviewed-by: Hal Feng Reviewed-by: Conor Dooley Reviewed-by: Uwe Kleine-König Acked-by: Uwe Kleine-König Signed-off-by: Conor Dooley --- .../devicetree/bindings/pwm/opencores,pwm.yaml | 55 ++++++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/opencores,pwm.yaml (limited to 'Documentation/devicetree/bindings/pwm') diff --git a/Documentation/devicetree/bindings/pwm/opencores,pwm.yaml b/Documentation/devicetree/bindings/pwm/opencores,pwm.yaml new file mode 100644 index 000000000000..0b85dd861dfd --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/opencores,pwm.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/opencores,pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: OpenCores PWM controller + +maintainers: + - William Qiu + +description: + The OpenCores PTC ip core contains a PWM controller. When operating in PWM + mode, the PTC core generates binary signal with user-programmable low and + high periods. All PTC counters and registers are 32-bit. + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + items: + - enum: + - starfive,jh7100-pwm + - starfive,jh7110-pwm + - const: opencores,pwm-v1 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + "#pwm-cells": + const: 3 + +required: + - compatible + - reg + - clocks + +additionalProperties: false + +examples: + - | + pwm@12490000 { + compatible = "starfive,jh7110-pwm", "opencores,pwm-v1"; + reg = <0x12490000 0x10000>; + clocks = <&clkgen 181>; + resets = <&rstgen 109>; + #pwm-cells = <3>; + }; -- cgit v1.2.3 From d0653996b7ea1286678efed9351dd2fc24752e32 Mon Sep 17 00:00:00 2001 From: Ji Sheng Teoh Date: Mon, 26 Feb 2024 11:39:45 +0800 Subject: dt-bindings: pwm: opencores: Add compatible for StarFive JH8100 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit StarFive JH8100 uses the same OpenCores PWM controller as JH7110. Mark JH8100 as compatible to the OpenCores PWM controller. Signed-off-by: Ley Foon Tan Signed-off-by: Ji Sheng Teoh Acked-by: Uwe Kleine-König Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/pwm/opencores,pwm.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/devicetree/bindings/pwm') diff --git a/Documentation/devicetree/bindings/pwm/opencores,pwm.yaml b/Documentation/devicetree/bindings/pwm/opencores,pwm.yaml index 0b85dd861dfd..52a59d245cdb 100644 --- a/Documentation/devicetree/bindings/pwm/opencores,pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/opencores,pwm.yaml @@ -23,6 +23,7 @@ properties: - enum: - starfive,jh7100-pwm - starfive,jh7110-pwm + - starfive,jh8100-pwm - const: opencores,pwm-v1 reg: -- cgit v1.2.3