From 781885fdf09f55ff14172749258f7380f859f2ba Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Mon, 15 Jun 2020 08:50:22 +0200 Subject: docs: sh: convert register-banks.txt to ReST - Add a SPDX header; - Adjust document title to follow ReST style; - Add blank lines to make ReST markup happy - Add it to sh/index.rst. Signed-off-by: Mauro Carvalho Chehab Link: https://lore.kernel.org/r/adf117cf1edd7f43cb839ff2800f4315dfbcce13.1592203650.git.mchehab+huawei@kernel.org Signed-off-by: Jonathan Corbet --- Documentation/sh/index.rst | 1 + Documentation/sh/register-banks.rst | 40 +++++++++++++++++++++++++++++++++++++ Documentation/sh/register-banks.txt | 33 ------------------------------ 3 files changed, 41 insertions(+), 33 deletions(-) create mode 100644 Documentation/sh/register-banks.rst delete mode 100644 Documentation/sh/register-banks.txt (limited to 'Documentation/sh') diff --git a/Documentation/sh/index.rst b/Documentation/sh/index.rst index 967acad9ff5e..b5933fd399f3 100644 --- a/Documentation/sh/index.rst +++ b/Documentation/sh/index.rst @@ -8,6 +8,7 @@ SuperH Interfaces Guide :maxdepth: 1 new-machine + register-banks Memory Management ================= diff --git a/Documentation/sh/register-banks.rst b/Documentation/sh/register-banks.rst new file mode 100644 index 000000000000..2bef5c8fcbbc --- /dev/null +++ b/Documentation/sh/register-banks.rst @@ -0,0 +1,40 @@ +.. SPDX-License-Identifier: GPL-2.0 + +========================================== +Notes on register bank usage in the kernel +========================================== + +Introduction +------------ + +The SH-3 and SH-4 CPU families traditionally include a single partial register +bank (selected by SR.RB, only r0 ... r7 are banked), whereas other families +may have more full-featured banking or simply no such capabilities at all. + +SR.RB banking +------------- + +In the case of this type of banking, banked registers are mapped directly to +r0 ... r7 if SR.RB is set to the bank we are interested in, otherwise ldc/stc +can still be used to reference the banked registers (as r0_bank ... r7_bank) +when in the context of another bank. The developer must keep the SR.RB value +in mind when writing code that utilizes these banked registers, for obvious +reasons. Userspace is also not able to poke at the bank1 values, so these can +be used rather effectively as scratch registers by the kernel. + +Presently the kernel uses several of these registers. + + - r0_bank, r1_bank (referenced as k0 and k1, used for scratch + registers when doing exception handling). + + - r2_bank (used to track the EXPEVT/INTEVT code) + + - Used by do_IRQ() and friends for doing irq mapping based off + of the interrupt exception vector jump table offset + + - r6_bank (global interrupt mask) + + - The SR.IMASK interrupt handler makes use of this to set the + interrupt priority level (used by local_irq_enable()) + + - r7_bank (current) diff --git a/Documentation/sh/register-banks.txt b/Documentation/sh/register-banks.txt deleted file mode 100644 index a6719f2f6594..000000000000 --- a/Documentation/sh/register-banks.txt +++ /dev/null @@ -1,33 +0,0 @@ - Notes on register bank usage in the kernel - ========================================== - -Introduction ------------- - -The SH-3 and SH-4 CPU families traditionally include a single partial register -bank (selected by SR.RB, only r0 ... r7 are banked), whereas other families -may have more full-featured banking or simply no such capabilities at all. - -SR.RB banking -------------- - -In the case of this type of banking, banked registers are mapped directly to -r0 ... r7 if SR.RB is set to the bank we are interested in, otherwise ldc/stc -can still be used to reference the banked registers (as r0_bank ... r7_bank) -when in the context of another bank. The developer must keep the SR.RB value -in mind when writing code that utilizes these banked registers, for obvious -reasons. Userspace is also not able to poke at the bank1 values, so these can -be used rather effectively as scratch registers by the kernel. - -Presently the kernel uses several of these registers. - - - r0_bank, r1_bank (referenced as k0 and k1, used for scratch - registers when doing exception handling). - - r2_bank (used to track the EXPEVT/INTEVT code) - - Used by do_IRQ() and friends for doing irq mapping based off - of the interrupt exception vector jump table offset - - r6_bank (global interrupt mask) - - The SR.IMASK interrupt handler makes use of this to set the - interrupt priority level (used by local_irq_enable()) - - r7_bank (current) - -- cgit v1.2.3