From 274707b773378f4ce8ba214002b3d67a4d0785ae Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 30 Aug 2023 14:48:41 +0200 Subject: dt-bindings: qcom: geni-se: Allow dma-coherent On SM8550, the QUP controller is coherent with the CPU. Allow specifying that. Signed-off-by: Konrad Dybcio Acked-by: Rob Herring Link: https://lore.kernel.org/r/20230830-topic-8550_dmac2-v1-2-49bb25239fb1@linaro.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml index 8a4b7ba3aaf6..7b031ef09669 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml @@ -52,6 +52,8 @@ properties: iommus: maxItems: 1 + dma-coherent: true + required: - compatible - reg -- cgit v1.2.3 From 8e2506d0123149a7b7846fbabbf4295b6005faf4 Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Wed, 30 Aug 2023 16:26:49 +0530 Subject: dt-bindings: cache: qcom,llcc: Add LLCC compatible for QDU1000/QRU1000 Add LLCC compatible for QDU1000/QRU1000 SoCs and add optional nvmem-cells and nvmem-cell-names properties to support multiple configurations for multi channel DDR. Signed-off-by: Komal Bajaj Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230830105654.28057-2-quic_kbajaj@quicinc.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/cache/qcom,llcc.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml index 44892aa589fd..580f9a97ddf7 100644 --- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml @@ -20,6 +20,7 @@ description: | properties: compatible: enum: + - qcom,qdu1000-llcc - qcom,sc7180-llcc - qcom,sc7280-llcc - qcom,sc8180x-llcc @@ -44,6 +45,14 @@ properties: interrupts: maxItems: 1 + nvmem-cells: + items: + - description: Reference to an nvmem node for multi channel DDR + + nvmem-cell-names: + items: + - const: multi-chan-ddr + required: - compatible - reg @@ -92,6 +101,7 @@ allOf: compatible: contains: enum: + - qcom,qdu1000-llcc - qcom,sc8180x-llcc - qcom,sc8280xp-llcc then: -- cgit v1.2.3 From eb3da369ccd07c0e3d65cd9cd31ca44f9f709673 Mon Sep 17 00:00:00 2001 From: Danila Tikhonov Date: Wed, 13 Sep 2023 22:44:18 +0300 Subject: dt-bindings: firmware: document Qualcomm SM7150 SCM Document the compatible for Qualcomm SM7150 SCM. Signed-off-by: Danila Tikhonov Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230913194418.30272-1-danila@jiaxyga.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml index 4233ea839bfc..0c073335f8ff 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -56,6 +56,7 @@ properties: - qcom,scm-sm6125 - qcom,scm-sm6350 - qcom,scm-sm6375 + - qcom,scm-sm7150 - qcom,scm-sm8150 - qcom,scm-sm8250 - qcom,scm-sm8350 -- cgit v1.2.3 From 92dab9ea5f389c12828283146c60054642453a91 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Wed, 16 Aug 2023 18:45:38 +0200 Subject: dt-bindings: firmware: qcom,scm: support indicating SDI default state IPQ5018 has SDI (Secure Debug Image) enabled by TZ by default, and that means that WDT being asserted or just trying to reboot will hang the board in the debug mode and only pulling the power and repowering will help. Some IPQ4019 boards like Google WiFI have it enabled as well. So, lets add a boolean property to indicate that SDI is enabled by default and thus needs to be disabled by the kernel. Signed-off-by: Robert Marko Acked-by: Mukesh Ojha Reviewed-by: Krzysztof Kozlowski Reviewed-by: Brian Norris Link: https://lore.kernel.org/r/20230816164641.3371878-1-robimarko@gmail.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml index 0c073335f8ff..cb706145ae04 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -90,6 +90,14 @@ properties: protocol to handle sleeping SCM calls. maxItems: 1 + qcom,sdi-enabled: + description: + Indicates that the SDI (Secure Debug Image) has been enabled by TZ + by default and it needs to be disabled. + If not disabled WDT assertion or reboot will cause the board to hang + in the debug mode. + type: boolean + qcom,dload-mode: $ref: /schemas/types.yaml#/definitions/phandle-array items: -- cgit v1.2.3 From f6aa7386bc40b552eea8ec1b1d2168afe3b31110 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Wed, 16 Aug 2023 18:45:40 +0200 Subject: dt-bindings: firmware: qcom,scm: document IPQ5018 compatible It seems that IPQ5018 compatible was never documented in the bindings. Signed-off-by: Robert Marko Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230816164641.3371878-3-robimarko@gmail.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml index cb706145ae04..0613a37a851a 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -24,6 +24,7 @@ properties: - qcom,scm-apq8064 - qcom,scm-apq8084 - qcom,scm-ipq4019 + - qcom,scm-ipq5018 - qcom,scm-ipq5332 - qcom,scm-ipq6018 - qcom,scm-ipq806x -- cgit v1.2.3 From 6e429adc60b1fa87b6e89d68cb9d1c0a8224d58a Mon Sep 17 00:00:00 2001 From: Ulf Hansson Date: Fri, 25 Aug 2023 13:26:28 +0200 Subject: dt-bindings: arm: cpus: Add a power-domain-name for a performance-domain When an CPU's performance domain is managed through the SCMI firmware, let's enable us describe this as a consumer of a power-domain provider, which is the de-facto standard to use for performance domains. In this case, let's specify a corresponding power-domain-name, to point out the corresponding index for it. Cc: Rob Herring Cc: Krzysztof Kozlowski Cc: Conor Dooley Cc: devicetree@vger.kernel.org Cc: Lorenzo Pieralisi Signed-off-by: Ulf Hansson Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20230825112633.236607-9-ulf.hansson@linaro.org Signed-off-by: Sudeep Holla --- Documentation/devicetree/bindings/arm/cpus.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 0d17cbad9778..ad7fee0245fa 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -308,7 +308,9 @@ properties: power-domains property. For PSCI based platforms, the name corresponding to the index of the PSCI - PM domain provider, must be "psci". + PM domain provider, must be "psci". For SCMI based platforms, the name + corresponding to the index of an SCMI performance domain provider, must be + "perf". qcom,saw: $ref: /schemas/types.yaml#/definitions/phandle -- cgit v1.2.3 From e11c480b6df1942b8f9a6958c2d881d8a9a9fb3b Mon Sep 17 00:00:00 2001 From: Ulf Hansson Date: Fri, 25 Aug 2023 13:26:29 +0200 Subject: dt-bindings: firmware: arm,scmi: Extend bindings for protocol@13 The protocol@13 node is describing the performance scaling option for the ARM SCMI interface, as a clock provider. This is unnecessary limiting, as performance scaling is in many cases not limited to switching a clock's frequency. Therefore, let's extend the binding so the interface can be modelled as a generic performance domain too. The common way to describe this, is to use the power-domain DT bindings, so let's use that. Cc: Rob Herring Cc: Krzysztof Kozlowski Cc: Conor Dooley Cc: devicetree@vger.kernel.org Signed-off-by: Ulf Hansson Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20230825112633.236607-10-ulf.hansson@linaro.org Signed-off-by: Sudeep Holla --- Documentation/devicetree/bindings/firmware/arm,scmi.yaml | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml index b138f3d23df8..563a87dfb31a 100644 --- a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml +++ b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml @@ -149,8 +149,15 @@ properties: '#clock-cells': const: 1 - required: - - '#clock-cells' + '#power-domain-cells': + const: 1 + + oneOf: + - required: + - '#clock-cells' + + - required: + - '#power-domain-cells' protocol@14: $ref: '#/$defs/protocol-node' -- cgit v1.2.3 From 0ead1f3e158c44aa274f2d5c49be947fbfcdffe0 Mon Sep 17 00:00:00 2001 From: Ulf Hansson Date: Fri, 25 Aug 2023 13:26:30 +0200 Subject: dt-bindings: power: Clarify performance capabilities of power-domains The power-domains bindings has in many years been used to describe so called performance-domains too. Rather than using a separate binding it has been convenient to re-use the power-domain bindings, as in some cases it's in fact a combination of the both that would be the best description. Therefore, let's make it more clear that the power-domains bindings can be used to describe a performance-domain too. Cc: "Rafael J. Wysocki" Cc: Kevin Hilman Cc: Rob Herring Cc: Krzysztof Kozlowski Cc: Conor Dooley Cc: devicetree@vger.kernel.org Signed-off-by: Ulf Hansson Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20230825112633.236607-11-ulf.hansson@linaro.org Signed-off-by: Sudeep Holla --- .../devicetree/bindings/power/power-domain.yaml | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/power/power-domain.yaml b/Documentation/devicetree/bindings/power/power-domain.yaml index d1235e562041..8fdb529d560b 100644 --- a/Documentation/devicetree/bindings/power/power-domain.yaml +++ b/Documentation/devicetree/bindings/power/power-domain.yaml @@ -13,8 +13,9 @@ maintainers: description: |+ System on chip designs are often divided into multiple PM domains that can be - used for power gating of selected IP blocks for power saving by reduced leakage - current. + used for power gating of selected IP blocks for power saving by reduced + leakage current. Moreover, in some cases the similar PM domains may also be + capable of scaling performance for a group of IP blocks. This device tree binding can be used to bind PM domain consumer devices with their PM domains provided by PM domain providers. A PM domain provider can be @@ -25,7 +26,7 @@ description: |+ properties: $nodename: - pattern: "^(power-controller|power-domain)([@-].*)?$" + pattern: "^(power-controller|power-domain|performance-domain)([@-].*)?$" domain-idle-states: $ref: /schemas/types.yaml#/definitions/phandle-array @@ -44,11 +45,11 @@ properties: operating-points-v2: description: - Phandles to the OPP tables of power domains provided by a power domain - provider. If the provider provides a single power domain only or all - the power domains provided by the provider have identical OPP tables, - then this shall contain a single phandle. Refer to ../opp/opp-v2-base.yaml - for more information. + Phandles to the OPP tables of power domains that are capable of scaling + performance, provided by a power domain provider. If the provider provides + a single power domain only or all the power domains provided by the + provider have identical OPP tables, then this shall contain a single + phandle. Refer to ../opp/opp-v2-base.yaml for more information. "#power-domain-cells": description: -- cgit v1.2.3 From 3ad96787949a96256931ca59aff73ea604bc0e6c Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Wed, 20 Sep 2023 19:37:30 -0700 Subject: dt-bindings: reserved-memory: rmtfs: Allow guard pages On some Qualcomm platforms the firwmare, or hardware, does not gracefully handle memory protection of the rmtfs memory region when placed adjacent to other protected region. Some DeviceTree authors have worked around this issue by explicitly reserving the space around the region, but this prevents such author to use rely on the OS to place the region, through the use of "size" (instead of a fixed location). Introduce a flag to indicate that guard pages need be carved at the beginning and end of the memory region. The user shall account for the two pages in the defined size. Signed-off-by: Bjorn Andersson Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230920-rmtfs-mem-guard-pages-v3-1-305b37219b78@quicinc.com Signed-off-by: Bjorn Andersson --- .../devicetree/bindings/reserved-memory/qcom,rmtfs-mem.yaml | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/reserved-memory/qcom,rmtfs-mem.yaml b/Documentation/devicetree/bindings/reserved-memory/qcom,rmtfs-mem.yaml index bab982f00485..46407e9c1d4f 100644 --- a/Documentation/devicetree/bindings/reserved-memory/qcom,rmtfs-mem.yaml +++ b/Documentation/devicetree/bindings/reserved-memory/qcom,rmtfs-mem.yaml @@ -26,6 +26,17 @@ properties: description: > identifier of the client to use this region for buffers + qcom,use-guard-pages: + type: boolean + description: > + Indicates that the firmware, or hardware, does not gracefully handle + memory protection of this region when placed adjacent to other protected + memory regions, and that padding around the used portion of the memory + region is necessary. + + When this is set, the first and last page should be left unused, and the + effective size of the region will thereby shrink with two pages. + qcom,vmid: $ref: /schemas/types.yaml#/definitions/uint32-array description: > -- cgit v1.2.3 From 387bb6fdd0af1f853deeb1cdd8331c07b6a66b32 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Mon, 25 Sep 2023 16:26:21 -0500 Subject: dt-bindings: memory-controllers: Make "additionalProperties: true" explicit Make it explicit that child nodes have additional properties and the child node schema is not complete. The complete schemas are applied separately based the compatible strings. Signed-off-by: Rob Herring Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/20230925212626.1974676-1-robh@kernel.org Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/memory-controllers/ingenic,nemc.yaml | 1 + .../devicetree/bindings/memory-controllers/renesas,rpc-if.yaml | 2 ++ Documentation/devicetree/bindings/memory-controllers/ti,gpmc.yaml | 2 +- 3 files changed, 4 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/memory-controllers/ingenic,nemc.yaml b/Documentation/devicetree/bindings/memory-controllers/ingenic,nemc.yaml index b40cec0eb651..ee74a362f4ca 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ingenic,nemc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ingenic,nemc.yaml @@ -40,6 +40,7 @@ patternProperties: ".*@[0-9]+$": type: object $ref: mc-peripheral-props.yaml# + additionalProperties: true required: - compatible diff --git a/Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml b/Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml index 56e62cd0b36a..25f3bb9890ae 100644 --- a/Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml @@ -80,6 +80,8 @@ properties: patternProperties: "flash@[0-9a-f]+$": type: object + additionalProperties: true + properties: compatible: contains: diff --git a/Documentation/devicetree/bindings/memory-controllers/ti,gpmc.yaml b/Documentation/devicetree/bindings/memory-controllers/ti,gpmc.yaml index b049837ee669..c7a8a041da50 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ti,gpmc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ti,gpmc.yaml @@ -130,7 +130,7 @@ patternProperties: bus. The device can be a NAND chip, SRAM device, NOR device or an ASIC. $ref: ti,gpmc-child.yaml - + additionalProperties: true required: - compatible -- cgit v1.2.3 From 6b841f34d51c9e0e69751e023130992687c9fd37 Mon Sep 17 00:00:00 2001 From: Mark Tseng Date: Thu, 21 Sep 2023 13:26:35 +0800 Subject: dt-bindings: soc: mediatek: add mt8188 svs dt-bindings Add mt8188 svs compatible in dt-bindings. Signed-off-by: Mark Tseng Acked-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230921052637.30444-2-chun-jen.tseng@mediatek.com --- Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml b/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml index f21eb907ee90..7eda63d5682f 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml @@ -22,6 +22,7 @@ properties: compatible: enum: - mediatek,mt8183-svs + - mediatek,mt8188-svs - mediatek,mt8192-svs reg: -- cgit v1.2.3 From 6979f88f5a8e6ab1cdbfeb842abb7ce9daecbb8d Mon Sep 17 00:00:00 2001 From: Nikunj Kela Date: Mon, 9 Oct 2023 12:14:36 -0700 Subject: dt-bindings: arm: Add new compatible for smc/hvc transport for SCMI Introduce compatible "qcom,scmi-smc" for SCMI smc/hvc transport channel for Qualcomm virtual platforms. This compatible mandates populating an additional parameter 'capability-id' from the last 8 bytes of the shmem channel. Signed-off-by: Nikunj Kela Reviewed-by: Brian Masney Link: https://lore.kernel.org/r/20231009191437.27926-2-quic_nkela@quicinc.com Signed-off-by: Sudeep Holla --- Documentation/devicetree/bindings/firmware/arm,scmi.yaml | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml index 563a87dfb31a..4591523b51a0 100644 --- a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml +++ b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml @@ -38,6 +38,9 @@ properties: with shmem address(4KB-page, offset) as parameters items: - const: arm,scmi-smc-param + - description: SCMI compliant firmware with Qualcomm SMC/HVC transport + items: + - const: qcom,scmi-smc - description: SCMI compliant firmware with SCMI Virtio transport. The virtio transport only supports a single device. items: @@ -313,6 +316,7 @@ else: enum: - arm,scmi-smc - arm,scmi-smc-param + - qcom,scmi-smc then: required: - arm,smc-id -- cgit v1.2.3