From 1f6ccfff6314672743ad7252160654709e997a2a Mon Sep 17 00:00:00 2001 From: Vineet Gupta Date: Mon, 13 May 2013 18:30:41 +0530 Subject: ARCv2: Support for ARCv2 ISA and HS38x cores The notable features are: - SMP configurations of upto 4 cores with coherency - Optional L2 Cache and IO-Coherency - Revised Interrupt Architecture (multiple priorites, reg banks, auto stack switch, auto regfile save/restore) - MMUv4 (PIPT dcache, Huge Pages) - Instructions for * 64bit load/store: LDD, STD * Hardware assisted divide/remainder: DIV, REM * Function prologue/epilogue: ENTER_S, LEAVE_S * IRQ enable/disable: CLRI, SETI * pop count: FFS, FLS * SETcc, BMSKN, XBFU... Signed-off-by: Vineet Gupta --- arch/arc/kernel/head.S | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/arc/kernel/head.S') diff --git a/arch/arc/kernel/head.S b/arch/arc/kernel/head.S index 64a92e0b1e53..812f95e6ae69 100644 --- a/arch/arc/kernel/head.S +++ b/arch/arc/kernel/head.S @@ -49,8 +49,6 @@ 1: .endm - .cpu A7 - .section .init.text, "ax",@progbits .type stext, @function .globl stext -- cgit v1.2.3