From 2fc35aa0923b899ac2f873d6ae57b99d035a793c Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 27 Mar 2024 09:10:37 +0200 Subject: ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_PER With the clkcsel binding we can drop the custom ti,bit-shift devicetree property in favor of the standard reg property and reduce the number of clocks to update for the make W-1 dtbs warnings. Let's also add a comment for the clocksel clock that matches the documentation. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) (limited to 'arch/arm/boot/dts/ti') diff --git a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi index 632878479798..3c8de5ddb0cb 100644 --- a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi @@ -1399,13 +1399,21 @@ clock-div = <1>; }; - dpll_per_byp_mux: clock-dpll-per-byp-mux-23@14c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clock-output-names = "dpll_per_byp_mux"; - clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>; - ti,bit-shift = <23>; - reg = <0x014c>; + /* CM_CLKSEL_DPLL_PER */ + clock@14c { + compatible = "ti,clksel"; + reg = <0x14c>; + #clock-cells = <2>; + #address-cells = <1>; + #size-cells = <0>; + + dpll_per_byp_mux: clock@23 { + reg = <23>; + compatible = "ti,mux-clock"; + clock-output-names = "dpll_per_byp_mux"; + clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>; + #clock-cells = <0>; + }; }; dpll_per_ck: clock@140 { -- cgit v1.2.3