From 1b6012394bec5dc653d495245c5495db08f817f6 Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Wed, 4 Dec 2013 15:27:47 +0800 Subject: blackfin: Support L1 SRAM parity checking feature on bf60x Move code for the SEC faults from the IRQ hanlders into IRQ actions. refine bfin fault routine handle Signed-off-by: Sonic Zhang Signed-off-by: Steven Miao --- arch/blackfin/include/asm/def_LPBlackfin.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/blackfin/include') diff --git a/arch/blackfin/include/asm/def_LPBlackfin.h b/arch/blackfin/include/asm/def_LPBlackfin.h index ca67145c6a45..c5c8d8a3a5fa 100644 --- a/arch/blackfin/include/asm/def_LPBlackfin.h +++ b/arch/blackfin/include/asm/def_LPBlackfin.h @@ -544,6 +544,7 @@ do { \ #define DCBS_P 0x04 /* L1 Data Cache Bank Select */ #define PORT_PREF0_P 0x12 /* DAG0 Port Preference */ #define PORT_PREF1_P 0x13 /* DAG1 Port Preference */ +#define RDCHK 0x9 /* Enable L1 Parity Check */ /* Masks */ #define ENDM 0x00000001 /* (doesn't really exist) Enable -- cgit v1.2.3