From 41604bfdc9f3f73d15bc19b85e474227c1f86856 Mon Sep 17 00:00:00 2001 From: Thippeswamy Havalige Date: Tue, 25 Oct 2022 12:22:13 +0530 Subject: microblaze/PCI: Remove support for Xilinx PCI host bridge This patch removes support for the Xilinx PCI host bridge IPcore. Signed-off-by: Thippeswamy Havalige Link: https://lore.kernel.org/r/20221025065214.4663-13-thippeswamy.havalige@amd.com Signed-off-by: Michal Simek --- arch/microblaze/Kconfig | 8 --- arch/microblaze/configs/mmu_defconfig | 1 - arch/microblaze/include/asm/pci-bridge.h | 6 -- arch/microblaze/include/asm/pci.h | 5 -- arch/microblaze/pci/Makefile | 1 - arch/microblaze/pci/xilinx_pci.c | 105 ------------------------------- 6 files changed, 126 deletions(-) delete mode 100644 arch/microblaze/pci/xilinx_pci.c (limited to 'arch/microblaze') diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig index 4ebb56d6d959..cc88af6fa7a4 100644 --- a/arch/microblaze/Kconfig +++ b/arch/microblaze/Kconfig @@ -215,11 +215,3 @@ config MB_MANAGER Say N here unless you know what you are doing. endmenu - -menu "Bus Options" - -config PCI_XILINX - bool "Xilinx PCI host bridge support" - depends on PCI - -endmenu diff --git a/arch/microblaze/configs/mmu_defconfig b/arch/microblaze/configs/mmu_defconfig index 8150daf04a76..756feb9369a6 100644 --- a/arch/microblaze/configs/mmu_defconfig +++ b/arch/microblaze/configs/mmu_defconfig @@ -19,7 +19,6 @@ CONFIG_HZ_100=y CONFIG_CMDLINE_BOOL=y CONFIG_CMDLINE_FORCE=y CONFIG_HIGHMEM=y -CONFIG_PCI_XILINX=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set diff --git a/arch/microblaze/include/asm/pci-bridge.h b/arch/microblaze/include/asm/pci-bridge.h index 5db2c6605720..be5f504bead4 100644 --- a/arch/microblaze/include/asm/pci-bridge.h +++ b/arch/microblaze/include/asm/pci-bridge.h @@ -25,7 +25,6 @@ static inline int pcibios_vaddr_is_ioport(void __iomem *address) */ struct pci_controller { struct pci_bus *bus; - struct device_node *dn; struct list_head list_node; void __iomem *io_base_virt; @@ -37,11 +36,6 @@ struct pci_controller { }; #ifdef CONFIG_PCI -static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus) -{ - return bus->sysdata; -} - static inline int isa_vaddr_is_ioport(void __iomem *address) { /* No specific ISA handling on ppc32 at this stage, it diff --git a/arch/microblaze/include/asm/pci.h b/arch/microblaze/include/asm/pci.h index a75bf3b19035..91f1f71c266a 100644 --- a/arch/microblaze/include/asm/pci.h +++ b/arch/microblaze/include/asm/pci.h @@ -38,12 +38,7 @@ extern int pci_proc_domain(struct pci_bus *bus); struct file; -/* This part of code was originally in xilinx-pci.h */ -#ifdef CONFIG_PCI_XILINX -extern void __init xilinx_pci_init(void); -#else static inline void __init xilinx_pci_init(void) { return; } -#endif #endif /* __KERNEL__ */ #endif /* __ASM_MICROBLAZE_PCI_H */ diff --git a/arch/microblaze/pci/Makefile b/arch/microblaze/pci/Makefile index 3cbdf2529b95..293b416c3d8e 100644 --- a/arch/microblaze/pci/Makefile +++ b/arch/microblaze/pci/Makefile @@ -4,4 +4,3 @@ # obj-$(CONFIG_PCI) += pci-common.o iomap.o -obj-$(CONFIG_PCI_XILINX) += xilinx_pci.o diff --git a/arch/microblaze/pci/xilinx_pci.c b/arch/microblaze/pci/xilinx_pci.c deleted file mode 100644 index 5dc41822b2d7..000000000000 --- a/arch/microblaze/pci/xilinx_pci.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * PCI support for Xilinx plbv46_pci soft-core which can be used on - * Xilinx Virtex ML410 / ML510 boards. - * - * Copyright 2009 Roderick Colenbrander - * Copyright 2009 Secret Lab Technologies Ltd. - * - * The pci bridge fixup code was copied from ppc4xx_pci.c and was written - * by Benjamin Herrenschmidt. - * Copyright 2007 Ben. Herrenschmidt , IBM Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include -#include -#include -#include -#include - -#define XPLB_PCI_ADDR 0x10c -#define XPLB_PCI_DATA 0x110 -#define XPLB_PCI_BUS 0x114 - -#define PCI_HOST_ENABLE_CMD (PCI_COMMAND_SERR | PCI_COMMAND_PARITY | \ - PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY) - -static const struct of_device_id xilinx_pci_match[] = { - { .compatible = "xlnx,plbv46-pci-1.03.a", }, - {} -}; - -/** - * xilinx_pci_fixup_bridge - Block Xilinx PHB configuration. - */ -static void xilinx_pci_fixup_bridge(struct pci_dev *dev) -{ - struct pci_controller *hose; - int i; - - if (dev->devfn || dev->bus->self) - return; - - hose = pci_bus_to_host(dev->bus); - if (!hose) - return; - - if (!of_match_node(xilinx_pci_match, hose->dn)) - return; - - /* Hide the PCI host BARs from the kernel as their content doesn't - * fit well in the resource management - */ - for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { - dev->resource[i].start = 0; - dev->resource[i].end = 0; - dev->resource[i].flags = 0; - } - - dev_info(&dev->dev, "Hiding Xilinx plb-pci host bridge resources %s\n", - pci_name(dev)); -} -DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, xilinx_pci_fixup_bridge); - -#ifdef DEBUG -/** - * xilinx_pci_exclude_device - Don't do config access for non-root bus - * - * This is a hack. Config access to any bus other than bus 0 does not - * currently work on the ML510 so we prevent it here. - */ -static int -xilinx_pci_exclude_device(struct pci_controller *hose, u_char bus, u8 devfn) -{ - return (bus != 0); -} -#endif - -/** - * xilinx_pci_init - Find and register a Xilinx PCI host bridge - */ -void __init xilinx_pci_init(void) -{ - struct resource r; - void __iomem *pci_reg; - struct device_node *pci_node; - - pci_node = of_find_matching_node(NULL, xilinx_pci_match); - if (!pci_node) - return; - - if (of_address_to_resource(pci_node, 0, &r)) { - pr_err("xilinx-pci: cannot resolve base address\n"); - return; - } - - /* Set the max bus number to 255, and bus/subbus no's to 0 */ - pci_reg = of_iomap(pci_node, 0); - WARN_ON(!pci_reg); - out_be32(pci_reg + XPLB_PCI_BUS, 0x000000ff); - iounmap(pci_reg); - -} -- cgit v1.2.3