From b3a428b4b18d495a06f39515568850f8db4c98ea Mon Sep 17 00:00:00 2001 From: Hassan Naveed Date: Mon, 29 Oct 2018 18:27:41 -0700 Subject: MIPS: Enable IOREMAP_PROT config option for MIPS cpus Allows the users of ptrace to access memory mapped by the ptraced process using the same cache coherency attributes as the original process. For example while using gdb with ioremap_prot() incorporated, both gdb and the process being traced will have same cache coherency attributes. Signed-off-by: Hassan Naveed Signed-off-by: Paul Burton Patchwork: https://patchwork.linux-mips.org/patch/20955/ Cc: --- arch/mips/include/asm/io.h | 12 ++++++++++++ arch/mips/include/asm/page.h | 1 + 2 files changed, 13 insertions(+) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index 266257d56fb6..b5322f7386bf 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -217,6 +217,18 @@ static inline void __iomem * __ioremap_mode(phys_addr_t offset, unsigned long si #undef __IS_LOW512 } +/* + * ioremap_prot - map bus memory into CPU space + * @offset: bus address of the memory + * @size: size of the resource to map + + * ioremap_prot gives the caller control over cache coherency attributes (CCA) + */ +static inline void __iomem *ioremap_prot(phys_addr_t offset, + unsigned long size, unsigned long prot_val) { + return __ioremap_mode(offset, size, prot_val & _CACHE_MASK); +} + /* * ioremap - map bus memory into CPU space * @offset: bus address of the memory diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h index e8cc328fce2d..6b31c93b5eaa 100644 --- a/arch/mips/include/asm/page.h +++ b/arch/mips/include/asm/page.h @@ -154,6 +154,7 @@ typedef struct { unsigned long pgd; } pgd_t; typedef struct { unsigned long pgprot; } pgprot_t; #define pgprot_val(x) ((x).pgprot) #define __pgprot(x) ((pgprot_t) { (x) } ) +#define pte_pgprot(x) __pgprot(pte_val(x) & ~_PFN_MASK) /* * On R4000-style MMUs where a TLB entry is mapping a adjacent even / odd -- cgit v1.2.3