From 07ba6d1ae524c627ac55bb98d5610d4fc44d3fe7 Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Wed, 28 Jun 2023 14:17:24 +0800 Subject: clk: imx: Add 519.75MHz frequency support for imx9 pll For video pll, it may need 519.75MHz clock frequency for the LVDS display usage. So add 519.75MHz frequency config support for video pll. Signed-off-by: Jacky Bai Reviewed-by: Peng Fan Link: https://lore.kernel.org/r/20230628061724.2056520-3-ping.bai@nxp.com Signed-off-by: Abel Vesa --- drivers/clk/imx/clk-fracn-gppll.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk/imx') diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c index c54f9999da04..44462ab50e51 100644 --- a/drivers/clk/imx/clk-fracn-gppll.c +++ b/drivers/clk/imx/clk-fracn-gppll.c @@ -81,6 +81,7 @@ static const struct imx_fracn_gppll_rate_table fracn_tbl[] = { PLL_FRACN_GP(650000000U, 162, 50, 100, 0, 6), PLL_FRACN_GP(594000000U, 198, 0, 1, 0, 8), PLL_FRACN_GP(560000000U, 140, 0, 1, 0, 6), + PLL_FRACN_GP(519750000U, 173, 25, 100, 1, 8), PLL_FRACN_GP(498000000U, 166, 0, 1, 0, 8), PLL_FRACN_GP(484000000U, 121, 0, 1, 0, 6), PLL_FRACN_GP(445333333U, 167, 0, 1, 0, 9), -- cgit v1.2.3