From 6e8b1dcb0956668e77cc9177b810b7c1f15c6d8d Mon Sep 17 00:00:00 2001 From: Cong Dang Date: Thu, 1 Feb 2024 13:21:55 +0100 Subject: clk: renesas: r8a779h0: Add watchdog clock Add the module clock used by the RCLK Watchdog Timer on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Cong Dang Signed-off-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/f1dbf0f3f484015f2e629d78b746cf377d6f6746.1706790015.git.geert+renesas@glider.be --- drivers/clk/renesas/r8a779h0-cpg-mssr.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk/renesas') diff --git a/drivers/clk/renesas/r8a779h0-cpg-mssr.c b/drivers/clk/renesas/r8a779h0-cpg-mssr.c index 219941047291..322db567d5f8 100644 --- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c @@ -177,6 +177,7 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = { DEF_MOD("hscif1", 515, R8A779H0_CLK_SASYNCPERD1), DEF_MOD("hscif2", 516, R8A779H0_CLK_SASYNCPERD1), DEF_MOD("hscif3", 517, R8A779H0_CLK_SASYNCPERD1), + DEF_MOD("wdt1:wdt0", 907, R8A779H0_CLK_R), DEF_MOD("pfc0", 915, R8A779H0_CLK_CP), DEF_MOD("pfc1", 916, R8A779H0_CLK_CP), DEF_MOD("pfc2", 917, R8A779H0_CLK_CP), -- cgit v1.2.3