From a91bb605ec5f93676e503267c89469d02c5b4cbc Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 20 Apr 2015 15:13:36 +0200 Subject: clk: tegra: Add sor_safe clock The sor_safe clock is a fixed factor (1:17) clock derived from pll_p. It has a gate bit in the peripheral clock registers. While the SOR is being powered up, sor_safe can be used as the source until the SOR brick can generate its own clock. Signed-off-by: Thierry Reding --- drivers/clk/tegra/clk-id.h | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk/tegra/clk-id.h') diff --git a/drivers/clk/tegra/clk-id.h b/drivers/clk/tegra/clk-id.h index fe6c6afcfa60..36c974916d4f 100644 --- a/drivers/clk/tegra/clk-id.h +++ b/drivers/clk/tegra/clk-id.h @@ -307,6 +307,7 @@ enum clk_id { tegra_clk_xusb_ss_div2, tegra_clk_xusb_ssp_src, tegra_clk_sclk_mux, + tegra_clk_sor_safe, tegra_clk_max, }; -- cgit v1.2.3