From ee800010835db23c70acc01000f182955cab27a5 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Wed, 1 Jun 2022 12:49:32 -0700 Subject: cxl/port: Cache CXL host bridge data Region creation has need for checking host-bridge connectivity when adding endpoints to regions. Record, at port creation time, the host-bridge to provide a useful shortcut from any location in the topology to the most-significant ancestor. Reviewed-by: Jonathan Cameron Link: https://lore.kernel.org/r/20220624041950.559155-4-dan.j.williams@intel.com Signed-off-by: Dan Williams --- drivers/cxl/cxl.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/cxl/cxl.h') diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index fd02f9e2a829..79d4c361b54f 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -282,6 +282,7 @@ struct cxl_nvdimm { * decode hierarchy. * @dev: this port's device * @uport: PCI or platform device implementing the upstream port capability + * @host_bridge: Shortcut to the platform attach point for this port * @id: id for port device-name * @dports: cxl_dport instances referenced by decoders * @endpoints: cxl_ep instances, endpoints that are a descendant of this port @@ -293,6 +294,7 @@ struct cxl_nvdimm { struct cxl_port { struct device dev; struct device *uport; + struct device *host_bridge; int id; struct list_head dports; struct list_head endpoints; -- cgit v1.2.3