From 97bda0322b8a91aa8d534763e709571b2334e585 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Mon, 25 Feb 2019 13:26:34 -0500 Subject: drm/amd/display: Add DSC support for Navi (v2) Add support for DCN2 DSC (Display Stream Compression) HW Blocks: +--------++------+ +----------+ | HUBBUB || HUBP | <-- | MMHUBBUB | +--------++------+ +----------+ | ^ v | +--------+ +--------+ | DPP | | DWB | +--------+ +--------+ | v ^ +--------+ | | MPC | | +--------+ | | | v | +-------+ +-------+ | | OPP | <--> | DSC | | +-------+ +-------+ | | | v | +--------+ / | OPTC | -------------- +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ v2: rebase (Alex) Signed-off-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dc_dsc.h | 61 +++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 drivers/gpu/drm/amd/display/dc/dc_dsc.h (limited to 'drivers/gpu/drm/amd/display/dc/dc_dsc.h') diff --git a/drivers/gpu/drm/amd/display/dc/dc_dsc.h b/drivers/gpu/drm/amd/display/dc/dc_dsc.h new file mode 100644 index 000000000000..c3a277c11489 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dc_dsc.h @@ -0,0 +1,61 @@ +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT +#ifndef DC_DSC_H_ +#define DC_DSC_H_ +/* + * Copyright 2019 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Author: AMD + */ +struct dc_dsc_bw_range { + uint32_t min_kbps; + uint32_t min_target_bpp_x16; + uint32_t max_kbps; + uint32_t max_target_bpp_x16; + uint32_t stream_kbps; +}; + + +bool dc_dsc_parse_dsc_dpcd(const uint8_t *dpcd_dsc_data, + struct dsc_dec_dpcd_caps *dsc_sink_caps); + +bool dc_dsc_compute_bandwidth_range( + const struct dc *dc, + const struct dsc_dec_dpcd_caps *dsc_sink_caps, + const struct dc_crtc_timing *timing, + struct dc_dsc_bw_range *range); +bool dc_dsc_compute_config( + const struct dc *dc, + const struct dsc_dec_dpcd_caps *dsc_sink_caps, + int target_bandwidth, + const struct dc_crtc_timing *timing, + struct dc_dsc_config *dsc_cfg); + +bool dc_check_and_fit_timing_into_bandwidth_with_dsc_legacy( + const struct dc *pDC, + const struct dc_link *link, + struct dc_crtc_timing *timing); + +bool dc_setup_dsc_in_timing_legacy(const struct dc *pDC, + const struct dsc_dec_dpcd_caps *dsc_sink_caps, + int available_bandwidth_kbps, + struct dc_crtc_timing *timing); +#endif +#endif -- cgit v1.2.3