From 6ac99a328ee16d3f8cc253f1df62623cee3e9ea5 Mon Sep 17 00:00:00 2001 From: Christoph Manszewski Date: Fri, 21 Sep 2018 14:24:38 +0200 Subject: drm/exynos: mixer: Make plane alpha configurable The mixer hardware supports variable plane alpha. Currently planes are opaque, make this configurable. Tested on Odroid-U3 with Exynos 4412 CPU, kernel next-20180913 using modetest. Signed-off-by: Christoph Manszewski Signed-off-by: Inki Dae --- drivers/gpu/drm/exynos/regs-mixer.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/exynos/regs-mixer.h') diff --git a/drivers/gpu/drm/exynos/regs-mixer.h b/drivers/gpu/drm/exynos/regs-mixer.h index 189cfa2470a8..d2b8194a07bf 100644 --- a/drivers/gpu/drm/exynos/regs-mixer.h +++ b/drivers/gpu/drm/exynos/regs-mixer.h @@ -109,12 +109,15 @@ #define MXR_CFG_SCAN_HD (1 << 0) #define MXR_CFG_SCAN_MASK 0x47 +/* bits for MXR_VIDEO_CFG */ +#define MXR_VID_CFG_BLEND_EN (1 << 16) + /* bits for MXR_GRAPHICn_CFG */ #define MXR_GRP_CFG_COLOR_KEY_DISABLE (1 << 21) #define MXR_GRP_CFG_BLEND_PRE_MUL (1 << 20) #define MXR_GRP_CFG_WIN_BLEND_EN (1 << 17) #define MXR_GRP_CFG_PIXEL_BLEND_EN (1 << 16) -#define MXR_GRP_CFG_MISC_MASK ((3 << 16) | (3 << 20)) +#define MXR_GRP_CFG_MISC_MASK ((3 << 16) | (3 << 20) | 0xff) #define MXR_GRP_CFG_FORMAT_VAL(x) MXR_MASK_VAL(x, 11, 8) #define MXR_GRP_CFG_FORMAT_MASK MXR_GRP_CFG_FORMAT_VAL(~0) #define MXR_GRP_CFG_ALPHA_VAL(x) MXR_MASK_VAL(x, 7, 0) -- cgit v1.2.3