From 62aeaeaa1b267c5149abee6b45967a5df3feed58 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Thu, 6 Apr 2023 15:21:03 +0200 Subject: drm/aperture: Remove primary argument Only really pci devices have a business setting this - it's for figuring out whether the legacy vga stuff should be nuked too. And with the preceding two patches those are all using the pci version of this. Which means for all other callers primary == false and we can remove it now. v2: - Reorder to avoid compile fail (Thomas) - Include gma500, which retained it's called to the non-pci version. v4: - fix Daniel's S-o-b address v5: - add back an S-o-b tag with Daniel's Intel address Signed-off-by: Daniel Vetter Signed-off-by: Daniel Vetter Signed-off-by: Thomas Zimmermann Cc: Thomas Zimmermann Cc: Javier Martinez Canillas Cc: Maarten Lankhorst Cc: Maxime Ripard Cc: Deepak Rawat Cc: Neil Armstrong Cc: Kevin Hilman Cc: Jerome Brunet Cc: Martin Blumenstingl Cc: Thierry Reding Cc: Jonathan Hunter Cc: Emma Anholt Cc: Helge Deller Cc: David Airlie Cc: Daniel Vetter Cc: linux-hyperv@vger.kernel.org Cc: linux-amlogic@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-tegra@vger.kernel.org Cc: linux-fbdev@vger.kernel.org Acked-by: Martin Blumenstingl Acked-by: Thierry Reding Reviewed-by: Javier Martinez Canillas Link: https://patchwork.freedesktop.org/patch/msgid/20230406132109.32050-4-tzimmermann@suse.de --- drivers/gpu/drm/sun4i/sun4i_drv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/sun4i') diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c b/drivers/gpu/drm/sun4i/sun4i_drv.c index e49f78a6a8cf..daa7faf72a4b 100644 --- a/drivers/gpu/drm/sun4i/sun4i_drv.c +++ b/drivers/gpu/drm/sun4i/sun4i_drv.c @@ -98,7 +98,7 @@ static int sun4i_drv_bind(struct device *dev) goto unbind_all; /* Remove early framebuffers (ie. simplefb) */ - ret = drm_aperture_remove_framebuffers(false, &sun4i_drv_driver); + ret = drm_aperture_remove_framebuffers(&sun4i_drv_driver); if (ret) goto unbind_all; -- cgit v1.2.3 From 71ffeafb13380b73f41bc16495962371c0fda596 Mon Sep 17 00:00:00 2001 From: Roman Beranek Date: Fri, 5 May 2023 07:21:09 +0200 Subject: drm: sun4i: rename sun4i_dotclock to sun4i_tcon_dclk While the rate of TCON0's DCLK matches dotclock for parallel and LVDS outputs, this doesn't hold for DSI. The 'D' in DCLK actually stands for 'Data' according to Allwinner's manuals. The clock is mostly referred to as dclk throughout this driver already anyway, so stick with that. Signed-off-by: Roman Beranek Signed-off-by: Maxime Ripard Link: https://patchwork.freedesktop.org/patch/msgid/20230505052110.67514-4-me@crly.cz --- drivers/gpu/drm/sun4i/Makefile | 2 +- drivers/gpu/drm/sun4i/sun4i_dotclock.c | 206 -------------------------------- drivers/gpu/drm/sun4i/sun4i_dotclock.h | 17 --- drivers/gpu/drm/sun4i/sun4i_tcon.c | 10 +- drivers/gpu/drm/sun4i/sun4i_tcon_dclk.c | 206 ++++++++++++++++++++++++++++++++ drivers/gpu/drm/sun4i/sun4i_tcon_dclk.h | 17 +++ 6 files changed, 229 insertions(+), 229 deletions(-) delete mode 100644 drivers/gpu/drm/sun4i/sun4i_dotclock.c delete mode 100644 drivers/gpu/drm/sun4i/sun4i_dotclock.h create mode 100644 drivers/gpu/drm/sun4i/sun4i_tcon_dclk.c create mode 100644 drivers/gpu/drm/sun4i/sun4i_tcon_dclk.h (limited to 'drivers/gpu/drm/sun4i') diff --git a/drivers/gpu/drm/sun4i/Makefile b/drivers/gpu/drm/sun4i/Makefile index 0d04f2447b01..bad7497a0d11 100644 --- a/drivers/gpu/drm/sun4i/Makefile +++ b/drivers/gpu/drm/sun4i/Makefile @@ -19,7 +19,7 @@ sun8i-mixer-y += sun8i_mixer.o sun8i_ui_layer.o \ sun8i_vi_scaler.o sun8i_csc.o sun4i-tcon-y += sun4i_crtc.o -sun4i-tcon-y += sun4i_dotclock.o +sun4i-tcon-y += sun4i_tcon_dclk.o sun4i-tcon-y += sun4i_lvds.o sun4i-tcon-y += sun4i_tcon.o sun4i-tcon-y += sun4i_rgb.o diff --git a/drivers/gpu/drm/sun4i/sun4i_dotclock.c b/drivers/gpu/drm/sun4i/sun4i_dotclock.c deleted file mode 100644 index 417ade3d2565..000000000000 --- a/drivers/gpu/drm/sun4i/sun4i_dotclock.c +++ /dev/null @@ -1,206 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2016 Free Electrons - * Copyright (C) 2016 NextThing Co - * - * Maxime Ripard - */ - -#include -#include - -#include "sun4i_tcon.h" -#include "sun4i_dotclock.h" - -struct sun4i_dclk { - struct clk_hw hw; - struct regmap *regmap; - struct sun4i_tcon *tcon; -}; - -static inline struct sun4i_dclk *hw_to_dclk(struct clk_hw *hw) -{ - return container_of(hw, struct sun4i_dclk, hw); -} - -static void sun4i_dclk_disable(struct clk_hw *hw) -{ - struct sun4i_dclk *dclk = hw_to_dclk(hw); - - regmap_update_bits(dclk->regmap, SUN4I_TCON0_DCLK_REG, - BIT(SUN4I_TCON0_DCLK_GATE_BIT), 0); -} - -static int sun4i_dclk_enable(struct clk_hw *hw) -{ - struct sun4i_dclk *dclk = hw_to_dclk(hw); - - return regmap_update_bits(dclk->regmap, SUN4I_TCON0_DCLK_REG, - BIT(SUN4I_TCON0_DCLK_GATE_BIT), - BIT(SUN4I_TCON0_DCLK_GATE_BIT)); -} - -static int sun4i_dclk_is_enabled(struct clk_hw *hw) -{ - struct sun4i_dclk *dclk = hw_to_dclk(hw); - u32 val; - - regmap_read(dclk->regmap, SUN4I_TCON0_DCLK_REG, &val); - - return val & BIT(SUN4I_TCON0_DCLK_GATE_BIT); -} - -static unsigned long sun4i_dclk_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct sun4i_dclk *dclk = hw_to_dclk(hw); - u32 val; - - regmap_read(dclk->regmap, SUN4I_TCON0_DCLK_REG, &val); - - val >>= SUN4I_TCON0_DCLK_DIV_SHIFT; - val &= (1 << SUN4I_TCON0_DCLK_DIV_WIDTH) - 1; - - if (!val) - val = 1; - - return parent_rate / val; -} - -static long sun4i_dclk_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate) -{ - struct sun4i_dclk *dclk = hw_to_dclk(hw); - struct sun4i_tcon *tcon = dclk->tcon; - unsigned long best_parent = 0; - u8 best_div = 1; - int i; - - for (i = tcon->dclk_min_div; i <= tcon->dclk_max_div; i++) { - u64 ideal = (u64)rate * i; - unsigned long rounded; - - /* - * ideal has overflowed the max value that can be stored in an - * unsigned long, and every clk operation we might do on a - * truncated u64 value will give us incorrect results. - * Let's just stop there since bigger dividers will result in - * the same overflow issue. - */ - if (ideal > ULONG_MAX) - goto out; - - rounded = clk_hw_round_rate(clk_hw_get_parent(hw), - ideal); - - if (rounded == ideal) { - best_parent = rounded; - best_div = i; - goto out; - } - - if (abs(rate - rounded / i) < - abs(rate - best_parent / best_div)) { - best_parent = rounded; - best_div = i; - } - } - -out: - *parent_rate = best_parent; - - return best_parent / best_div; -} - -static int sun4i_dclk_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct sun4i_dclk *dclk = hw_to_dclk(hw); - u8 div = parent_rate / rate; - - return regmap_update_bits(dclk->regmap, SUN4I_TCON0_DCLK_REG, - GENMASK(6, 0), div); -} - -static int sun4i_dclk_get_phase(struct clk_hw *hw) -{ - struct sun4i_dclk *dclk = hw_to_dclk(hw); - u32 val; - - regmap_read(dclk->regmap, SUN4I_TCON0_IO_POL_REG, &val); - - val >>= 28; - val &= 3; - - return val * 120; -} - -static int sun4i_dclk_set_phase(struct clk_hw *hw, int degrees) -{ - struct sun4i_dclk *dclk = hw_to_dclk(hw); - u32 val = degrees / 120; - - val <<= 28; - - regmap_update_bits(dclk->regmap, SUN4I_TCON0_IO_POL_REG, - GENMASK(29, 28), - val); - - return 0; -} - -static const struct clk_ops sun4i_dclk_ops = { - .disable = sun4i_dclk_disable, - .enable = sun4i_dclk_enable, - .is_enabled = sun4i_dclk_is_enabled, - - .recalc_rate = sun4i_dclk_recalc_rate, - .round_rate = sun4i_dclk_round_rate, - .set_rate = sun4i_dclk_set_rate, - - .get_phase = sun4i_dclk_get_phase, - .set_phase = sun4i_dclk_set_phase, -}; - -int sun4i_dclk_create(struct device *dev, struct sun4i_tcon *tcon) -{ - const char *clk_name, *parent_name; - struct clk_init_data init; - struct sun4i_dclk *dclk; - int ret; - - parent_name = __clk_get_name(tcon->sclk0); - ret = of_property_read_string_index(dev->of_node, - "clock-output-names", 0, - &clk_name); - if (ret) - return ret; - - dclk = devm_kzalloc(dev, sizeof(*dclk), GFP_KERNEL); - if (!dclk) - return -ENOMEM; - dclk->tcon = tcon; - - init.name = clk_name; - init.ops = &sun4i_dclk_ops; - init.parent_names = &parent_name; - init.num_parents = 1; - init.flags = CLK_SET_RATE_PARENT; - - dclk->regmap = tcon->regs; - dclk->hw.init = &init; - - tcon->dclk = clk_register(dev, &dclk->hw); - if (IS_ERR(tcon->dclk)) - return PTR_ERR(tcon->dclk); - - return 0; -} -EXPORT_SYMBOL(sun4i_dclk_create); - -int sun4i_dclk_free(struct sun4i_tcon *tcon) -{ - clk_unregister(tcon->dclk); - return 0; -} -EXPORT_SYMBOL(sun4i_dclk_free); diff --git a/drivers/gpu/drm/sun4i/sun4i_dotclock.h b/drivers/gpu/drm/sun4i/sun4i_dotclock.h deleted file mode 100644 index ac60da2455ca..000000000000 --- a/drivers/gpu/drm/sun4i/sun4i_dotclock.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (C) 2015 Free Electrons - * Copyright (C) 2015 NextThing Co - * - * Maxime Ripard - */ - -#ifndef _SUN4I_DOTCLOCK_H_ -#define _SUN4I_DOTCLOCK_H_ - -struct sun4i_tcon; - -int sun4i_dclk_create(struct device *dev, struct sun4i_tcon *tcon); -int sun4i_dclk_free(struct sun4i_tcon *tcon); - -#endif /* _SUN4I_DOTCLOCK_H_ */ diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c index 523a6d787921..eec26b1faa4b 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c @@ -31,12 +31,12 @@ #include #include "sun4i_crtc.h" -#include "sun4i_dotclock.h" #include "sun4i_drv.h" #include "sun4i_lvds.h" #include "sun4i_rgb.h" #include "sun4i_tcon.h" #include "sun6i_mipi_dsi.h" +#include "sun4i_tcon_dclk.h" #include "sun8i_tcon_top.h" #include "sunxi_engine.h" @@ -1237,14 +1237,14 @@ static int sun4i_tcon_bind(struct device *dev, struct device *master, ret = sun4i_tcon_init_irq(dev, tcon); if (ret) { dev_err(dev, "Couldn't init our TCON interrupts\n"); - goto err_free_dotclock; + goto err_free_dclk; } tcon->crtc = sun4i_crtc_init(drm, engine, tcon); if (IS_ERR(tcon->crtc)) { dev_err(dev, "Couldn't create our CRTC\n"); ret = PTR_ERR(tcon->crtc); - goto err_free_dotclock; + goto err_free_dclk; } if (tcon->quirks->has_channel_0) { @@ -1264,7 +1264,7 @@ static int sun4i_tcon_bind(struct device *dev, struct device *master, of_node_put(remote); if (ret < 0) - goto err_free_dotclock; + goto err_free_dclk; } if (tcon->quirks->needs_de_be_mux) { @@ -1290,7 +1290,7 @@ static int sun4i_tcon_bind(struct device *dev, struct device *master, return 0; -err_free_dotclock: +err_free_dclk: if (tcon->quirks->has_channel_0) sun4i_dclk_free(tcon); err_free_clocks: diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon_dclk.c b/drivers/gpu/drm/sun4i/sun4i_tcon_dclk.c new file mode 100644 index 000000000000..03d7de1911cd --- /dev/null +++ b/drivers/gpu/drm/sun4i/sun4i_tcon_dclk.c @@ -0,0 +1,206 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2016 Free Electrons + * Copyright (C) 2016 NextThing Co + * + * Maxime Ripard + */ + +#include +#include + +#include "sun4i_tcon.h" +#include "sun4i_tcon_dclk.h" + +struct sun4i_dclk { + struct clk_hw hw; + struct regmap *regmap; + struct sun4i_tcon *tcon; +}; + +static inline struct sun4i_dclk *hw_to_dclk(struct clk_hw *hw) +{ + return container_of(hw, struct sun4i_dclk, hw); +} + +static void sun4i_dclk_disable(struct clk_hw *hw) +{ + struct sun4i_dclk *dclk = hw_to_dclk(hw); + + regmap_update_bits(dclk->regmap, SUN4I_TCON0_DCLK_REG, + BIT(SUN4I_TCON0_DCLK_GATE_BIT), 0); +} + +static int sun4i_dclk_enable(struct clk_hw *hw) +{ + struct sun4i_dclk *dclk = hw_to_dclk(hw); + + return regmap_update_bits(dclk->regmap, SUN4I_TCON0_DCLK_REG, + BIT(SUN4I_TCON0_DCLK_GATE_BIT), + BIT(SUN4I_TCON0_DCLK_GATE_BIT)); +} + +static int sun4i_dclk_is_enabled(struct clk_hw *hw) +{ + struct sun4i_dclk *dclk = hw_to_dclk(hw); + u32 val; + + regmap_read(dclk->regmap, SUN4I_TCON0_DCLK_REG, &val); + + return val & BIT(SUN4I_TCON0_DCLK_GATE_BIT); +} + +static unsigned long sun4i_dclk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct sun4i_dclk *dclk = hw_to_dclk(hw); + u32 val; + + regmap_read(dclk->regmap, SUN4I_TCON0_DCLK_REG, &val); + + val >>= SUN4I_TCON0_DCLK_DIV_SHIFT; + val &= (1 << SUN4I_TCON0_DCLK_DIV_WIDTH) - 1; + + if (!val) + val = 1; + + return parent_rate / val; +} + +static long sun4i_dclk_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + struct sun4i_dclk *dclk = hw_to_dclk(hw); + struct sun4i_tcon *tcon = dclk->tcon; + unsigned long best_parent = 0; + u8 best_div = 1; + int i; + + for (i = tcon->dclk_min_div; i <= tcon->dclk_max_div; i++) { + u64 ideal = (u64)rate * i; + unsigned long rounded; + + /* + * ideal has overflowed the max value that can be stored in an + * unsigned long, and every clk operation we might do on a + * truncated u64 value will give us incorrect results. + * Let's just stop there since bigger dividers will result in + * the same overflow issue. + */ + if (ideal > ULONG_MAX) + goto out; + + rounded = clk_hw_round_rate(clk_hw_get_parent(hw), + ideal); + + if (rounded == ideal) { + best_parent = rounded; + best_div = i; + goto out; + } + + if (abs(rate - rounded / i) < + abs(rate - best_parent / best_div)) { + best_parent = rounded; + best_div = i; + } + } + +out: + *parent_rate = best_parent; + + return best_parent / best_div; +} + +static int sun4i_dclk_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct sun4i_dclk *dclk = hw_to_dclk(hw); + u8 div = parent_rate / rate; + + return regmap_update_bits(dclk->regmap, SUN4I_TCON0_DCLK_REG, + GENMASK(6, 0), div); +} + +static int sun4i_dclk_get_phase(struct clk_hw *hw) +{ + struct sun4i_dclk *dclk = hw_to_dclk(hw); + u32 val; + + regmap_read(dclk->regmap, SUN4I_TCON0_IO_POL_REG, &val); + + val >>= 28; + val &= 3; + + return val * 120; +} + +static int sun4i_dclk_set_phase(struct clk_hw *hw, int degrees) +{ + struct sun4i_dclk *dclk = hw_to_dclk(hw); + u32 val = degrees / 120; + + val <<= 28; + + regmap_update_bits(dclk->regmap, SUN4I_TCON0_IO_POL_REG, + GENMASK(29, 28), + val); + + return 0; +} + +static const struct clk_ops sun4i_dclk_ops = { + .disable = sun4i_dclk_disable, + .enable = sun4i_dclk_enable, + .is_enabled = sun4i_dclk_is_enabled, + + .recalc_rate = sun4i_dclk_recalc_rate, + .round_rate = sun4i_dclk_round_rate, + .set_rate = sun4i_dclk_set_rate, + + .get_phase = sun4i_dclk_get_phase, + .set_phase = sun4i_dclk_set_phase, +}; + +int sun4i_dclk_create(struct device *dev, struct sun4i_tcon *tcon) +{ + const char *clk_name, *parent_name; + struct clk_init_data init; + struct sun4i_dclk *dclk; + int ret; + + parent_name = __clk_get_name(tcon->sclk0); + ret = of_property_read_string_index(dev->of_node, + "clock-output-names", 0, + &clk_name); + if (ret) + return ret; + + dclk = devm_kzalloc(dev, sizeof(*dclk), GFP_KERNEL); + if (!dclk) + return -ENOMEM; + dclk->tcon = tcon; + + init.name = clk_name; + init.ops = &sun4i_dclk_ops; + init.parent_names = &parent_name; + init.num_parents = 1; + init.flags = CLK_SET_RATE_PARENT; + + dclk->regmap = tcon->regs; + dclk->hw.init = &init; + + tcon->dclk = clk_register(dev, &dclk->hw); + if (IS_ERR(tcon->dclk)) + return PTR_ERR(tcon->dclk); + + return 0; +} +EXPORT_SYMBOL(sun4i_dclk_create); + +int sun4i_dclk_free(struct sun4i_tcon *tcon) +{ + clk_unregister(tcon->dclk); + return 0; +} +EXPORT_SYMBOL(sun4i_dclk_free); diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon_dclk.h b/drivers/gpu/drm/sun4i/sun4i_tcon_dclk.h new file mode 100644 index 000000000000..ac60da2455ca --- /dev/null +++ b/drivers/gpu/drm/sun4i/sun4i_tcon_dclk.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2015 Free Electrons + * Copyright (C) 2015 NextThing Co + * + * Maxime Ripard + */ + +#ifndef _SUN4I_DOTCLOCK_H_ +#define _SUN4I_DOTCLOCK_H_ + +struct sun4i_tcon; + +int sun4i_dclk_create(struct device *dev, struct sun4i_tcon *tcon); +int sun4i_dclk_free(struct sun4i_tcon *tcon); + +#endif /* _SUN4I_DOTCLOCK_H_ */ -- cgit v1.2.3 From 4795c78768bcbd58d4ffab650674d314dc6dd772 Mon Sep 17 00:00:00 2001 From: Roman Beranek Date: Fri, 5 May 2023 07:21:10 +0200 Subject: drm: sun4i: calculate proper DCLK rate for DSI In DSI mode, TCON0's data clock is required to run at 1/4 the per-lane bit rate. Signed-off-by: Roman Beranek Signed-off-by: Maxime Ripard Link: https://patchwork.freedesktop.org/patch/msgid/20230505052110.67514-5-me@crly.cz --- drivers/gpu/drm/sun4i/sun4i_tcon.c | 36 +++++++++++++++++++++--------------- 1 file changed, 21 insertions(+), 15 deletions(-) (limited to 'drivers/gpu/drm/sun4i') diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c index eec26b1faa4b..b263de7a8237 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c @@ -291,18 +291,6 @@ static int sun4i_tcon_get_clk_delay(const struct drm_display_mode *mode, return delay; } -static void sun4i_tcon0_mode_set_common(struct sun4i_tcon *tcon, - const struct drm_display_mode *mode) -{ - /* Configure the dot clock */ - clk_set_rate(tcon->dclk, mode->crtc_clock * 1000); - - /* Set the resolution */ - regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG, - SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) | - SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay)); -} - static void sun4i_tcon0_mode_set_dithering(struct sun4i_tcon *tcon, const struct drm_connector *connector) { @@ -367,10 +355,18 @@ static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon *tcon, u32 block_space, start_delay; u32 tcon_div; + /* + * dclk is required to run at 1/4 the DSI per-lane bit rate. + */ tcon->dclk_min_div = SUN6I_DSI_TCON_DIV; tcon->dclk_max_div = SUN6I_DSI_TCON_DIV; + clk_set_rate(tcon->dclk, mode->crtc_clock * 1000 * (bpp / lanes) + / SUN6I_DSI_TCON_DIV); - sun4i_tcon0_mode_set_common(tcon, mode); + /* Set the resolution */ + regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG, + SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) | + SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay)); /* Set dithering if needed */ sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder)); @@ -438,7 +434,12 @@ static void sun4i_tcon0_mode_set_lvds(struct sun4i_tcon *tcon, tcon->dclk_min_div = 7; tcon->dclk_max_div = 7; - sun4i_tcon0_mode_set_common(tcon, mode); + clk_set_rate(tcon->dclk, mode->crtc_clock * 1000); + + /* Set the resolution */ + regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG, + SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) | + SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay)); /* Set dithering if needed */ sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder)); @@ -515,7 +516,12 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon, tcon->dclk_min_div = tcon->quirks->dclk_min_div; tcon->dclk_max_div = 127; - sun4i_tcon0_mode_set_common(tcon, mode); + clk_set_rate(tcon->dclk, mode->crtc_clock * 1000); + + /* Set the resolution */ + regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG, + SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) | + SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay)); /* Set dithering if needed */ sun4i_tcon0_mode_set_dithering(tcon, connector); -- cgit v1.2.3 From 123ee07ba5b7123e0ce0e0f9d64938026c16a2ce Mon Sep 17 00:00:00 2001 From: XuDong Liu Date: Sun, 30 Apr 2023 19:23:46 +0800 Subject: drm: sun4i_tcon: use devm_clk_get_enabled in `sun4i_tcon_init_clocks` Smatch reports: drivers/gpu/drm/sun4i/sun4i_tcon.c:805 sun4i_tcon_init_clocks() warn: 'tcon->clk' from clk_prepare_enable() not released on lines: 792,801. In the function sun4i_tcon_init_clocks(), tcon->clk and tcon->sclk0 are not disabled in the error handling, which affects the release of these variable. Although sun4i_tcon_bind(), which calls sun4i_tcon_init_clocks(), use sun4i_tcon_free_clocks to disable the variables mentioned, but the error handling branch of sun4i_tcon_init_clocks() ignores the required disable process. To fix this issue, use the devm_clk_get_enabled to automatically balance enable and disabled calls. As original implementation use sun4i_tcon_free_clocks() to disable clk explicitly, we delete the related calls and error handling that are no longer needed. Fixes: 9026e0d122ac ("drm: Add Allwinner A10 Display Engine support") Fixes: b14e945bda8a ("drm/sun4i: tcon: Prepare and enable TCON channel 0 clock at init") Fixes: 8e9240472522 ("drm/sun4i: support TCONs without channel 1") Fixes: 34d698f6e349 ("drm/sun4i: Add has_channel_0 TCON quirk") Signed-off-by: XuDong Liu Reviewed-by: Dongliang Mu Signed-off-by: Maxime Ripard Link: https://patchwork.freedesktop.org/patch/msgid/20230430112347.4689-1-m202071377@hust.edu.cn --- drivers/gpu/drm/sun4i/sun4i_tcon.c | 19 ++++--------------- 1 file changed, 4 insertions(+), 15 deletions(-) (limited to 'drivers/gpu/drm/sun4i') diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c index b263de7a8237..6a52fb12cbfb 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c @@ -784,21 +784,19 @@ static irqreturn_t sun4i_tcon_handler(int irq, void *private) static int sun4i_tcon_init_clocks(struct device *dev, struct sun4i_tcon *tcon) { - tcon->clk = devm_clk_get(dev, "ahb"); + tcon->clk = devm_clk_get_enabled(dev, "ahb"); if (IS_ERR(tcon->clk)) { dev_err(dev, "Couldn't get the TCON bus clock\n"); return PTR_ERR(tcon->clk); } - clk_prepare_enable(tcon->clk); if (tcon->quirks->has_channel_0) { - tcon->sclk0 = devm_clk_get(dev, "tcon-ch0"); + tcon->sclk0 = devm_clk_get_enabled(dev, "tcon-ch0"); if (IS_ERR(tcon->sclk0)) { dev_err(dev, "Couldn't get the TCON channel 0 clock\n"); return PTR_ERR(tcon->sclk0); } } - clk_prepare_enable(tcon->sclk0); if (tcon->quirks->has_channel_1) { tcon->sclk1 = devm_clk_get(dev, "tcon-ch1"); @@ -811,12 +809,6 @@ static int sun4i_tcon_init_clocks(struct device *dev, return 0; } -static void sun4i_tcon_free_clocks(struct sun4i_tcon *tcon) -{ - clk_disable_unprepare(tcon->sclk0); - clk_disable_unprepare(tcon->clk); -} - static int sun4i_tcon_init_irq(struct device *dev, struct sun4i_tcon *tcon) { @@ -1229,14 +1221,14 @@ static int sun4i_tcon_bind(struct device *dev, struct device *master, ret = sun4i_tcon_init_regmap(dev, tcon); if (ret) { dev_err(dev, "Couldn't init our TCON regmap\n"); - goto err_free_clocks; + goto err_assert_reset; } if (tcon->quirks->has_channel_0) { ret = sun4i_dclk_create(dev, tcon); if (ret) { dev_err(dev, "Couldn't create our TCON dot clock\n"); - goto err_free_clocks; + goto err_assert_reset; } } @@ -1299,8 +1291,6 @@ static int sun4i_tcon_bind(struct device *dev, struct device *master, err_free_dclk: if (tcon->quirks->has_channel_0) sun4i_dclk_free(tcon); -err_free_clocks: - sun4i_tcon_free_clocks(tcon); err_assert_reset: reset_control_assert(tcon->lcd_rst); return ret; @@ -1314,7 +1304,6 @@ static void sun4i_tcon_unbind(struct device *dev, struct device *master, list_del(&tcon->list); if (tcon->quirks->has_channel_0) sun4i_dclk_free(tcon); - sun4i_tcon_free_clocks(tcon); } static const struct component_ops sun4i_tcon_ops = { -- cgit v1.2.3