From 666cb873328b5075eb511662858bab02d084ff64 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 8 Dec 2014 16:32:47 +0100 Subject: drm/tegra: dc: Unify enabling the display controller Previously output drivers would enable continuous display mode and power up the display controller at various points during the initialization. This is suboptimal because it accesses display controller registers in output drivers and duplicates a bit of code. Move this code into the display controller driver and enable the display controller as the final step of the ->mode_set_nofb() implementation. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/hdmi.c | 10 ---------- 1 file changed, 10 deletions(-) (limited to 'drivers/gpu/drm/tegra/hdmi.c') diff --git a/drivers/gpu/drm/tegra/hdmi.c b/drivers/gpu/drm/tegra/hdmi.c index 07771956cc94..7e06657ae58b 100644 --- a/drivers/gpu/drm/tegra/hdmi.c +++ b/drivers/gpu/drm/tegra/hdmi.c @@ -1022,16 +1022,6 @@ static void tegra_hdmi_encoder_mode_set(struct drm_encoder *encoder, value |= HDMI_ENABLE; tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); - value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); - value &= ~DISP_CTRL_MODE_MASK; - value |= DISP_CTRL_MODE_C_DISPLAY; - tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); - - value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); - value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | - PW4_ENABLE | PM0_ENABLE | PM1_ENABLE; - tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); - tegra_dc_commit(dc); /* TODO: add HDCP support */ -- cgit v1.2.3