From 296549107e4766bb927debd016527c71fb6faf36 Mon Sep 17 00:00:00 2001 From: Daniele Ceraolo Spurio Date: Thu, 17 Aug 2023 13:18:26 -0700 Subject: drm/xe: base definitions for the GSCCS The first step in introducing the GSCCS is to add all the basic defs for it (name, mmio base, class/instance, lrc size etc). Bspec: 60149, 60421, 63752 Signed-off-by: Daniele Ceraolo Spurio Reviewed-by: Matt Roper Link: https://lore.kernel.org/r/20230817201831.1583172-3-daniele.ceraolospurio@intel.com Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/xe/xe_hw_engine_types.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/drm/xe/xe_hw_engine_types.h') diff --git a/drivers/gpu/drm/xe/xe_hw_engine_types.h b/drivers/gpu/drm/xe/xe_hw_engine_types.h index 97d9ba31b5fc..cd4bc1412a3f 100644 --- a/drivers/gpu/drm/xe/xe_hw_engine_types.h +++ b/drivers/gpu/drm/xe/xe_hw_engine_types.h @@ -53,6 +53,8 @@ enum xe_hw_engine_id { XE_HW_ENGINE_CCS2, XE_HW_ENGINE_CCS3, #define XE_HW_ENGINE_CCS_MASK GENMASK_ULL(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0) + XE_HW_ENGINE_GSCCS0, +#define XE_HW_ENGINE_GSCCS_MASK GENMASK_ULL(XE_HW_ENGINE_GSCCS0, XE_HW_ENGINE_GSCCS0) XE_NUM_HW_ENGINES, }; -- cgit v1.2.3