From 77f5924fc41c243e907c80ce2576902d3a9cb336 Mon Sep 17 00:00:00 2001 From: Martin Kaistra Date: Thu, 14 Mar 2024 17:48:50 +0100 Subject: wifi: rtl8xxxu: enable MFP support In order to connect to networks which require 802.11w, add the MFP_CAPABLE flag and let mac80211 do the actual crypto in software. When a robust management frames is received, rx_dec->swdec is not set, even though the HW did not decrypt it. Extend the check and don't set RX_FLAG_DECRYPTED for these frames in order to use SW decryption. Signed-off-by: Martin Kaistra Reviewed-by: Ping-Ke Shih Signed-off-by: Ping-Ke Shih Link: https://msgid.link/20240314164850.86432-1-martin.kaistra@linutronix.de --- drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'drivers/net/wireless/realtek/rtl8xxxu') diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c index 4a49f8f9d80f..870bd952f590 100644 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c +++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c @@ -6473,7 +6473,9 @@ int rtl8xxxu_parse_rxdesc16(struct rtl8xxxu_priv *priv, struct sk_buff *skb) rx_status->mactime = rx_desc->tsfl; rx_status->flag |= RX_FLAG_MACTIME_START; - if (!rx_desc->swdec) + if (!rx_desc->swdec && + !(_ieee80211_is_robust_mgmt_frame(hdr) && + ieee80211_has_protected(hdr->frame_control))) rx_status->flag |= RX_FLAG_DECRYPTED; if (rx_desc->crc32) rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; @@ -6578,7 +6580,9 @@ int rtl8xxxu_parse_rxdesc24(struct rtl8xxxu_priv *priv, struct sk_buff *skb) rx_status->mactime = rx_desc->tsfl; rx_status->flag |= RX_FLAG_MACTIME_START; - if (!rx_desc->swdec) + if (!rx_desc->swdec && + !(_ieee80211_is_robust_mgmt_frame(hdr) && + ieee80211_has_protected(hdr->frame_control))) rx_status->flag |= RX_FLAG_DECRYPTED; if (rx_desc->crc32) rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; @@ -7998,6 +8002,7 @@ static int rtl8xxxu_probe(struct usb_interface *interface, ieee80211_hw_set(hw, HAS_RATE_CONTROL); ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); ieee80211_hw_set(hw, AMPDU_AGGREGATION); + ieee80211_hw_set(hw, MFP_CAPABLE); wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST); -- cgit v1.2.3 From 08b5d052d17a89bb8706b2888277d0b682dc1610 Mon Sep 17 00:00:00 2001 From: Bitterblue Smith Date: Mon, 15 Apr 2024 23:59:05 +0300 Subject: wifi: rtl8xxxu: Fix the TX power of RTL8192CU, RTL8723AU Don't subtract 1 from the power index. This was added in commit 2fc0b8e5a17d ("rtl8xxxu: Add TX power base values for gen1 parts") for unknown reasons. The vendor drivers don't do this. Also correct the calculations of values written to REG_OFDM0_X{C,D}_TX_IQ_IMBALANCE. According to the vendor driver, these are used for TX power training. With these changes rtl8xxxu sets the TX power of RTL8192CU the same as the vendor driver. None of this appears to have any effect on my RTL8192CU device. Cc: stable@vger.kernel.org Signed-off-by: Bitterblue Smith Reviewed-by: Ping-Ke Shih Signed-off-by: Ping-Ke Shih Link: https://msgid.link/6ae5945b-644e-45e4-a78f-4c7d9c987910@gmail.com --- .../net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c | 25 +++++++++------------- 1 file changed, 10 insertions(+), 15 deletions(-) (limited to 'drivers/net/wireless/realtek/rtl8xxxu') diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c index 870bd952f590..be50e24337aa 100644 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c +++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c @@ -1505,13 +1505,13 @@ rtl8xxxu_gen1_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40) u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS]; u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS]; u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b; - u8 val8; + u8 val8, base; int group, i; group = rtl8xxxu_gen1_channel_to_group(channel); - cck[0] = priv->cck_tx_power_index_A[group] - 1; - cck[1] = priv->cck_tx_power_index_B[group] - 1; + cck[0] = priv->cck_tx_power_index_A[group]; + cck[1] = priv->cck_tx_power_index_B[group]; if (priv->hi_pa) { if (cck[0] > 0x20) @@ -1522,10 +1522,6 @@ rtl8xxxu_gen1_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40) ofdm[0] = priv->ht40_1s_tx_power_index_A[group]; ofdm[1] = priv->ht40_1s_tx_power_index_B[group]; - if (ofdm[0]) - ofdm[0] -= 1; - if (ofdm[1]) - ofdm[1] -= 1; ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a; ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b; @@ -1614,20 +1610,19 @@ rtl8xxxu_gen1_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40) rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs_a + power_base->reg_0e1c); + val8 = u32_get_bits(mcs_a + power_base->reg_0e1c, 0xff000000); for (i = 0; i < 3; i++) { - if (i != 2) - val8 = (mcsbase[0] > 8) ? (mcsbase[0] - 8) : 0; - else - val8 = (mcsbase[0] > 6) ? (mcsbase[0] - 6) : 0; + base = i != 2 ? 8 : 6; + val8 = max_t(int, val8 - base, 0); rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8); } + rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, mcs_b + power_base->reg_0868); + val8 = u32_get_bits(mcs_b + power_base->reg_0868, 0xff000000); for (i = 0; i < 3; i++) { - if (i != 2) - val8 = (mcsbase[1] > 8) ? (mcsbase[1] - 8) : 0; - else - val8 = (mcsbase[1] > 6) ? (mcsbase[1] - 6) : 0; + base = i != 2 ? 8 : 6; + val8 = max_t(int, val8 - base, 0); rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8); } } -- cgit v1.2.3 From 55e2843dd33a55f448579f1ab69aabe6f7077b04 Mon Sep 17 00:00:00 2001 From: Martin Kaistra Date: Thu, 18 Apr 2024 09:18:12 +0200 Subject: Revert "wifi: rtl8xxxu: enable MFP support" This reverts commit 77f5924fc41c243e907c80ce2576902d3a9cb336. There is a more elegant solution to check for not decrypted frames, which is to check the security flag in the RX descriptor. Revert commit 77f5924fc41c ("wifi: rtl8xxxu: enable MFP support") in favor of this to be able to send it to stable. Signed-off-by: Martin Kaistra Signed-off-by: Ping-Ke Shih Link: https://msgid.link/20240418071813.1883174-2-martin.kaistra@linutronix.de --- drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) (limited to 'drivers/net/wireless/realtek/rtl8xxxu') diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c index be50e24337aa..7ad427e430c3 100644 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c +++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c @@ -6468,9 +6468,7 @@ int rtl8xxxu_parse_rxdesc16(struct rtl8xxxu_priv *priv, struct sk_buff *skb) rx_status->mactime = rx_desc->tsfl; rx_status->flag |= RX_FLAG_MACTIME_START; - if (!rx_desc->swdec && - !(_ieee80211_is_robust_mgmt_frame(hdr) && - ieee80211_has_protected(hdr->frame_control))) + if (!rx_desc->swdec) rx_status->flag |= RX_FLAG_DECRYPTED; if (rx_desc->crc32) rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; @@ -6575,9 +6573,7 @@ int rtl8xxxu_parse_rxdesc24(struct rtl8xxxu_priv *priv, struct sk_buff *skb) rx_status->mactime = rx_desc->tsfl; rx_status->flag |= RX_FLAG_MACTIME_START; - if (!rx_desc->swdec && - !(_ieee80211_is_robust_mgmt_frame(hdr) && - ieee80211_has_protected(hdr->frame_control))) + if (!rx_desc->swdec) rx_status->flag |= RX_FLAG_DECRYPTED; if (rx_desc->crc32) rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; @@ -7997,7 +7993,6 @@ static int rtl8xxxu_probe(struct usb_interface *interface, ieee80211_hw_set(hw, HAS_RATE_CONTROL); ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); ieee80211_hw_set(hw, AMPDU_AGGREGATION); - ieee80211_hw_set(hw, MFP_CAPABLE); wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST); -- cgit v1.2.3 From cbfbb4ddbc8503478e0a138f9a31f61686cc5f11 Mon Sep 17 00:00:00 2001 From: Martin Kaistra Date: Thu, 18 Apr 2024 09:18:13 +0200 Subject: wifi: rtl8xxxu: enable MFP support with security flag of RX descriptor In order to connect to networks which require 802.11w, add the MFP_CAPABLE flag and let mac80211 do the actual crypto in software. When a robust management frame is received, rx_dec->swdec is not set, even though the HW did not decrypt it. Extend the check and don't set RX_FLAG_DECRYPTED for these frames in order to use SW decryption. Use the security flag in the RX descriptor for this purpose, like it is done in the rtw88 driver. Cc: stable@vger.kernel.org Signed-off-by: Martin Kaistra Signed-off-by: Ping-Ke Shih Link: https://msgid.link/20240418071813.1883174-3-martin.kaistra@linutronix.de --- drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h | 9 +++++++++ drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c | 7 +++++-- 2 files changed, 14 insertions(+), 2 deletions(-) (limited to 'drivers/net/wireless/realtek/rtl8xxxu') diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h index fd92d23c43d9..16d884a3d87d 100644 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h +++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h @@ -122,6 +122,15 @@ enum rtl8xxxu_rx_type { RX_TYPE_ERROR = -1 }; +enum rtl8xxxu_rx_desc_enc { + RX_DESC_ENC_NONE = 0, + RX_DESC_ENC_WEP40 = 1, + RX_DESC_ENC_TKIP_WO_MIC = 2, + RX_DESC_ENC_TKIP_MIC = 3, + RX_DESC_ENC_AES = 4, + RX_DESC_ENC_WEP104 = 5, +}; + struct rtl8xxxu_rxdesc16 { #ifdef __LITTLE_ENDIAN u32 pktlen:14; diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c index 7ad427e430c3..fbbc97161f5d 100644 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c +++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c @@ -6468,7 +6468,8 @@ int rtl8xxxu_parse_rxdesc16(struct rtl8xxxu_priv *priv, struct sk_buff *skb) rx_status->mactime = rx_desc->tsfl; rx_status->flag |= RX_FLAG_MACTIME_START; - if (!rx_desc->swdec) + if (!rx_desc->swdec && + rx_desc->security != RX_DESC_ENC_NONE) rx_status->flag |= RX_FLAG_DECRYPTED; if (rx_desc->crc32) rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; @@ -6573,7 +6574,8 @@ int rtl8xxxu_parse_rxdesc24(struct rtl8xxxu_priv *priv, struct sk_buff *skb) rx_status->mactime = rx_desc->tsfl; rx_status->flag |= RX_FLAG_MACTIME_START; - if (!rx_desc->swdec) + if (!rx_desc->swdec && + rx_desc->security != RX_DESC_ENC_NONE) rx_status->flag |= RX_FLAG_DECRYPTED; if (rx_desc->crc32) rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; @@ -7993,6 +7995,7 @@ static int rtl8xxxu_probe(struct usb_interface *interface, ieee80211_hw_set(hw, HAS_RATE_CONTROL); ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); ieee80211_hw_set(hw, AMPDU_AGGREGATION); + ieee80211_hw_set(hw, MFP_CAPABLE); wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST); -- cgit v1.2.3 From 110951b8faa0b0ac412f67517d2a5c148ea99abe Mon Sep 17 00:00:00 2001 From: Bitterblue Smith Date: Fri, 19 Apr 2024 01:02:37 +0300 Subject: wifi: rtl8xxxu: Add separate MAC init table for RTL8192CU Until now RTL8192CU family was using the MAC init table from RTL8723AU, but these tables are not identical in the two vendor drivers. Import the correct table for RTL8192CU. Also move the existing MAC init table to rtl8xxxu_8723a.c, which is the only remaining user. Tested with the Netcore NW362 (RTL8192CU). Signed-off-by: Bitterblue Smith Reviewed-by: Ping-Ke Shih Signed-off-by: Ping-Ke Shih Link: https://msgid.link/a53ed8b9-27fc-4871-a20a-ad42c6d210d3@gmail.com --- drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h | 1 - .../net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192c.c | 28 +++++++++++++++++++++- .../net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723a.c | 27 ++++++++++++++++++++- .../net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c | 25 ------------------- 4 files changed, 53 insertions(+), 28 deletions(-) (limited to 'drivers/net/wireless/realtek/rtl8xxxu') diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h index 16d884a3d87d..c28ff9dde625 100644 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h +++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h @@ -2031,7 +2031,6 @@ struct rtl8xxxu_fileops { extern int rtl8xxxu_debug; -extern const struct rtl8xxxu_reg8val rtl8xxxu_gen1_mac_init_table[]; extern const u32 rtl8xxxu_iqk_phy_iq_bb_reg[]; u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr); u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr); diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192c.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192c.c index 3ee7d8f87da6..e54978ca7171 100644 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192c.c +++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192c.c @@ -77,6 +77,32 @@ static struct rtl8xxxu_power_base rtl8188r_power_base = { .reg_0868 = 0x00020204, }; +static const struct rtl8xxxu_reg8val rtl8192cu_mac_init_table[] = { + {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00}, + {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05}, + {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00}, + {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05}, + {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01}, + {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f}, + {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72}, + {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08}, + {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff}, + {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2}, + {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3}, + {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4}, + {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4}, + {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a}, + {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16}, + {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00}, + {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02}, + {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a}, + {0x652, 0x20}, {0x652, 0x20}, {0x63c, 0x08}, {0x63d, 0x08}, + {0x63e, 0x0c}, {0x63f, 0x0c}, {0x66e, 0x05}, {0x700, 0x21}, + {0x701, 0x43}, {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, + {0x709, 0x43}, {0x70a, 0x65}, {0x70b, 0x87}, + {0xffff, 0xff}, +}; + static const struct rtl8xxxu_rfregval rtl8192cu_radioa_2t_init_table[] = { {0x00, 0x00030159}, {0x01, 0x00031284}, {0x02, 0x00098000}, {0x03, 0x00018c63}, @@ -621,7 +647,7 @@ struct rtl8xxxu_fileops rtl8192cu_fops = { .trxff_boundary = 0x27ff, .pbp_rx = PBP_PAGE_SIZE_128, .pbp_tx = PBP_PAGE_SIZE_128, - .mactable = rtl8xxxu_gen1_mac_init_table, + .mactable = rtl8192cu_mac_init_table, .total_page_num = TX_TOTAL_PAGE_NUM, .page_num_hi = TX_PAGE_NUM_HI_PQ, .page_num_lo = TX_PAGE_NUM_LO_PQ, diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723a.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723a.c index ad1bb9377ca2..bf8c34af781f 100644 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723a.c +++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723a.c @@ -54,6 +54,31 @@ static struct rtl8xxxu_power_base rtl8723a_power_base = { .reg_0868 = 0x02040608, }; +static const struct rtl8xxxu_reg8val rtl8723au_mac_init_table[] = { + {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00}, + {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05}, + {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00}, + {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05}, + {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01}, + {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f}, + {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72}, + {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08}, + {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff}, + {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2}, + {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3}, + {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4}, + {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4}, + {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a}, + {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16}, + {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00}, + {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02}, + {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a}, + {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e}, + {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43}, + {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43}, + {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff}, +}; + static const struct rtl8xxxu_rfregval rtl8723au_radioa_1t_init_table[] = { {0x00, 0x00030159}, {0x01, 0x00031284}, {0x02, 0x00098000}, {0x03, 0x00039c63}, @@ -518,7 +543,7 @@ struct rtl8xxxu_fileops rtl8723au_fops = { .trxff_boundary = 0x27ff, .pbp_rx = PBP_PAGE_SIZE_128, .pbp_tx = PBP_PAGE_SIZE_128, - .mactable = rtl8xxxu_gen1_mac_init_table, + .mactable = rtl8723au_mac_init_table, .total_page_num = TX_TOTAL_PAGE_NUM, .page_num_hi = TX_PAGE_NUM_HI_PQ, .page_num_lo = TX_PAGE_NUM_LO_PQ, diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c index fbbc97161f5d..464772866a22 100644 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c +++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c @@ -132,31 +132,6 @@ static struct ieee80211_supported_band rtl8xxxu_supported_band = { .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates), }; -const struct rtl8xxxu_reg8val rtl8xxxu_gen1_mac_init_table[] = { - {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00}, - {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05}, - {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00}, - {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05}, - {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01}, - {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f}, - {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72}, - {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08}, - {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff}, - {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2}, - {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3}, - {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4}, - {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4}, - {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a}, - {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16}, - {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00}, - {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02}, - {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a}, - {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e}, - {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43}, - {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43}, - {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff}, -}; - static const struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = { {0x800, 0x80040000}, {0x804, 0x00000003}, {0x808, 0x0000fc00}, {0x80c, 0x0000000a}, -- cgit v1.2.3 From fbeddb4a767de1d5d6762a1cc54836e1dc8a8fd2 Mon Sep 17 00:00:00 2001 From: Bitterblue Smith Date: Fri, 19 Apr 2024 01:03:35 +0300 Subject: wifi: rtl8xxxu: Add LED control code for RTL8192CU family Also, don't set bit 7 of LEDCFG2 for RTL8192CU. If bit 7 is set the LED never turns on. In this family only RTL8188CUS needs bit 7 of LEDCFG2 set. Software control (on/off) and hardware control (automatic blinking) tested with Netcore NW362 (RTL8192CU). Signed-off-by: Bitterblue Smith Reviewed-by: Ping-Ke Shih Signed-off-by: Ping-Ke Shih Link: https://msgid.link/4b5970cf-d28b-415a-b911-82cdb5e9ce99@gmail.com --- .../net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192c.c | 21 +++++++++++++++++++++ .../net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c | 2 +- 2 files changed, 22 insertions(+), 1 deletion(-) (limited to 'drivers/net/wireless/realtek/rtl8xxxu') diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192c.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192c.c index e54978ca7171..ddf2d9707338 100644 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192c.c +++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192c.c @@ -609,6 +609,26 @@ static int rtl8192cu_power_on(struct rtl8xxxu_priv *priv) return 0; } +static int rtl8192cu_led_brightness_set(struct led_classdev *led_cdev, + enum led_brightness brightness) +{ + struct rtl8xxxu_priv *priv = container_of(led_cdev, + struct rtl8xxxu_priv, + led_cdev); + u8 ledcfg = rtl8xxxu_read8(priv, REG_LEDCFG0); + + if (brightness == LED_OFF) + ledcfg = LEDCFG2_SW_LED_CONTROL | LEDCFG2_SW_LED_DISABLE; + else if (brightness == LED_ON) + ledcfg = LEDCFG2_SW_LED_CONTROL; + else if (brightness == RTL8XXXU_HW_LED_CONTROL) + ledcfg = LEDCFG2_HW_LED_CONTROL | LEDCFG2_HW_LED_ENABLE; + + rtl8xxxu_write8(priv, REG_LEDCFG0, ledcfg); + + return 0; +} + struct rtl8xxxu_fileops rtl8192cu_fops = { .identify_chip = rtl8192cu_identify_chip, .parse_efuse = rtl8192cu_parse_efuse, @@ -635,6 +655,7 @@ struct rtl8xxxu_fileops rtl8192cu_fops = { .report_rssi = rtl8xxxu_gen1_report_rssi, .fill_txdesc = rtl8xxxu_fill_txdesc_v1, .cck_rssi = rtl8723a_cck_rssi, + .led_classdev_brightness_set = rtl8192cu_led_brightness_set, .writeN_block_size = 128, .rx_agg_buf_size = 16000, .tx_desc_size = sizeof(struct rtl8xxxu_txdesc32), diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c index 464772866a22..e72f35a40ab3 100644 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c +++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c @@ -4355,7 +4355,7 @@ static int rtl8xxxu_init_device(struct ieee80211_hw *hw) /* Let the 8051 take control of antenna setting */ if (priv->rtl_chip != RTL8192E && priv->rtl_chip != RTL8188F && - priv->rtl_chip != RTL8710B) { + priv->rtl_chip != RTL8710B && priv->rtl_chip != RTL8192C) { val8 = rtl8xxxu_read8(priv, REG_LEDCFG2); val8 |= LEDCFG2_DPDT_SELECT; rtl8xxxu_write8(priv, REG_LEDCFG2, val8); -- cgit v1.2.3 From feaedb05fc47f3078eecdefa317db8e79a24b0e2 Mon Sep 17 00:00:00 2001 From: Bitterblue Smith Date: Tue, 23 Apr 2024 00:38:35 +0300 Subject: wifi: rtl8xxxu: Add LED control code for RTL8723BU Software control (on/off) and hardware control (automatic blinking) tested with EDUP EP-N8568. Signed-off-by: Bitterblue Smith Signed-off-by: Ping-Ke Shih Link: https://msgid.link/7df66d1f-87a1-4f44-9aac-ce75438abde3@gmail.com --- .../net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'drivers/net/wireless/realtek/rtl8xxxu') diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c index 9640c841d20a..6653f43973cf 100644 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c +++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c @@ -1701,6 +1701,28 @@ static s8 rtl8723b_cck_rssi(struct rtl8xxxu_priv *priv, struct rtl8723au_phy_sta return rx_pwr_all; } +static int rtl8723bu_led_brightness_set(struct led_classdev *led_cdev, + enum led_brightness brightness) +{ + struct rtl8xxxu_priv *priv = container_of(led_cdev, + struct rtl8xxxu_priv, + led_cdev); + u8 ledcfg = rtl8xxxu_read8(priv, REG_LEDCFG2); + + ledcfg &= LEDCFG2_DPDT_SELECT; + + if (brightness == LED_OFF) + ledcfg |= LEDCFG2_SW_LED_CONTROL | LEDCFG2_SW_LED_DISABLE; + else if (brightness == LED_ON) + ledcfg |= LEDCFG2_SW_LED_CONTROL; + else if (brightness == RTL8XXXU_HW_LED_CONTROL) + ledcfg |= LEDCFG2_HW_LED_CONTROL | LEDCFG2_HW_LED_ENABLE; + + rtl8xxxu_write8(priv, REG_LEDCFG2, ledcfg); + + return 0; +} + struct rtl8xxxu_fileops rtl8723bu_fops = { .identify_chip = rtl8723bu_identify_chip, .parse_efuse = rtl8723bu_parse_efuse, @@ -1731,6 +1753,7 @@ struct rtl8xxxu_fileops rtl8723bu_fops = { .fill_txdesc = rtl8xxxu_fill_txdesc_v2, .set_crystal_cap = rtl8723a_set_crystal_cap, .cck_rssi = rtl8723b_cck_rssi, + .led_classdev_brightness_set = rtl8723bu_led_brightness_set, .writeN_block_size = 1024, .tx_desc_size = sizeof(struct rtl8xxxu_txdesc40), .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc24), -- cgit v1.2.3 From a890495b297b64880d34f32c0b8b3668bbf226da Mon Sep 17 00:00:00 2001 From: Kalle Valo Date: Fri, 26 Apr 2024 17:19:38 +0300 Subject: wifi: rtl8xxxu: remove some unused includes I noticed by random that rtl8xxxu includes linux/wireless.h even though it doesn't need it. While investigating a bit more I found even more unused include files: #include #include #include It looks like that the includes are just copied to every file without checking if the file really needs the include. So more includes could be removed but that would need more careful analysis per each file. No functional changes, compile tested only. Signed-off-by: Kalle Valo Reviewed-by: Ping-Ke Shih Signed-off-by: Ping-Ke Shih Link: https://msgid.link/20240426141939.3881678-1-kvalo@kernel.org --- drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188e.c | 4 ---- drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188f.c | 4 ---- drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192c.c | 4 ---- drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c | 4 ---- drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192f.c | 4 ---- drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8710b.c | 4 ---- drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723a.c | 4 ---- drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c | 4 ---- drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c | 4 ---- 9 files changed, 36 deletions(-) (limited to 'drivers/net/wireless/realtek/rtl8xxxu') diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188e.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188e.c index afe9cc1b49dc..43735ca70b7c 100644 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188e.c +++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188e.c @@ -13,9 +13,7 @@ * additional 8xxx chips like the 8192cu, 8188cus, etc. */ -#include #include -#include #include #include #include @@ -24,8 +22,6 @@ #include #include #include -#include -#include #include #include #include diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188f.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188f.c index 464216d007ce..9043e548518f 100644 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188f.c +++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188f.c @@ -11,9 +11,7 @@ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. */ -#include #include -#include #include #include #include @@ -22,8 +20,6 @@ #include #include #include -#include -#include #include #include #include diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192c.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192c.c index ddf2d9707338..49eb1d0a6019 100644 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192c.c +++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192c.c @@ -13,9 +13,7 @@ * additional 8xxx chips like the 8192cu, 8188cus, etc. */ -#include #include -#include #include #include #include @@ -24,8 +22,6 @@ #include #include #include -#include -#include #include #include #include diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c index 63b73ace27ec..26132b6b9331 100644 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c +++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c @@ -13,9 +13,7 @@ * additional 8xxx chips like the 8192cu, 8188cus, etc. */ -#include #include -#include #include #include #include @@ -24,8 +22,6 @@ #include #include #include -#include -#include #include #include #include diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192f.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192f.c index 21e4204769d0..9f1d4a6ee210 100644 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192f.c +++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192f.c @@ -11,9 +11,7 @@ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. */ -#include #include -#include #include #include #include @@ -22,8 +20,6 @@ #include #include #include -#include -#include #include #include #include diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8710b.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8710b.c index 46d57510e9fc..aa27ac4f828b 100644 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8710b.c +++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8710b.c @@ -11,9 +11,7 @@ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. */ -#include #include -#include #include #include #include @@ -22,8 +20,6 @@ #include #include #include -#include -#include #include #include #include diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723a.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723a.c index bf8c34af781f..965c8c3662a6 100644 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723a.c +++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723a.c @@ -13,9 +13,7 @@ * additional 8xxx chips like the 8192cu, 8188cus, etc. */ -#include #include -#include #include #include #include @@ -24,8 +22,6 @@ #include #include #include -#include -#include #include #include #include diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c index 6653f43973cf..3355d8e97870 100644 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c +++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c @@ -13,9 +13,7 @@ * additional 8xxx chips like the 8192cu, 8188cus, etc. */ -#include #include -#include #include #include #include @@ -24,8 +22,6 @@ #include #include #include -#include -#include #include #include #include diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c index e72f35a40ab3..54f955b01475 100644 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c +++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c @@ -13,9 +13,7 @@ * additional 8xxx chips like the 8192cu, 8188cus, etc. */ -#include #include -#include #include #include #include @@ -24,8 +22,6 @@ #include #include #include -#include -#include #include #include #include -- cgit v1.2.3 From 028fa281712d965667c182e741f8cc84d94c8f32 Mon Sep 17 00:00:00 2001 From: Kalle Valo Date: Fri, 26 Apr 2024 17:19:39 +0300 Subject: wifi: rtl8xxxu: remove rtl8xxxu_ prefix from filenames The driver is already in a directory named rtl8xxxu, there's no need to duplicate that in the filename as well. Now file listing looks a lot more reasonable: 8188e.c 8192c.c 8192f.c 8723a.c core.c Makefile rtl8xxxu.h 8188f.c 8192e.c 8710b.c 8723b.c Kconfig regs.h No functional changes, compile tested only. Signed-off-by: Kalle Valo Reviewed-by: Ping-Ke Shih Signed-off-by: Ping-Ke Shih Link: https://msgid.link/20240426141939.3881678-2-kvalo@kernel.org --- drivers/net/wireless/realtek/rtl8xxxu/8188e.c | 1897 +++++ drivers/net/wireless/realtek/rtl8xxxu/8188f.c | 1762 +++++ drivers/net/wireless/realtek/rtl8xxxu/8192c.c | 673 ++ drivers/net/wireless/realtek/rtl8xxxu/8192e.c | 1779 +++++ drivers/net/wireless/realtek/rtl8xxxu/8192f.c | 2103 +++++ drivers/net/wireless/realtek/rtl8xxxu/8710b.c | 1887 +++++ drivers/net/wireless/realtek/rtl8xxxu/8723a.c | 547 ++ drivers/net/wireless/realtek/rtl8xxxu/8723b.c | 1779 +++++ drivers/net/wireless/realtek/rtl8xxxu/Makefile | 6 +- drivers/net/wireless/realtek/rtl8xxxu/core.c | 8302 ++++++++++++++++++++ drivers/net/wireless/realtek/rtl8xxxu/regs.h | 1381 ++++ .../net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188e.c | 1897 ----- .../net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188f.c | 1762 ----- .../net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192c.c | 673 -- .../net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c | 1779 ----- .../net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192f.c | 2103 ----- .../net/wireless/realtek/rtl8xxxu/rtl8xxxu_8710b.c | 1887 ----- .../net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723a.c | 547 -- .../net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c | 1779 ----- .../net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c | 8302 -------------------- .../net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h | 1381 ---- 21 files changed, 22113 insertions(+), 22113 deletions(-) create mode 100644 drivers/net/wireless/realtek/rtl8xxxu/8188e.c create mode 100644 drivers/net/wireless/realtek/rtl8xxxu/8188f.c create mode 100644 drivers/net/wireless/realtek/rtl8xxxu/8192c.c create mode 100644 drivers/net/wireless/realtek/rtl8xxxu/8192e.c create mode 100644 drivers/net/wireless/realtek/rtl8xxxu/8192f.c create mode 100644 drivers/net/wireless/realtek/rtl8xxxu/8710b.c create mode 100644 drivers/net/wireless/realtek/rtl8xxxu/8723a.c create mode 100644 drivers/net/wireless/realtek/rtl8xxxu/8723b.c create mode 100644 drivers/net/wireless/realtek/rtl8xxxu/core.c create mode 100644 drivers/net/wireless/realtek/rtl8xxxu/regs.h delete mode 100644 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188e.c delete mode 100644 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188f.c delete mode 100644 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192c.c delete mode 100644 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c delete mode 100644 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192f.c delete mode 100644 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8710b.c delete mode 100644 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723a.c delete mode 100644 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c delete mode 100644 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c delete mode 100644 drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h (limited to 'drivers/net/wireless/realtek/rtl8xxxu') diff --git a/drivers/net/wireless/realtek/rtl8xxxu/8188e.c b/drivers/net/wireless/realtek/rtl8xxxu/8188e.c new file mode 100644 index 000000000000..60fb0bffd4ed --- /dev/null +++ b/drivers/net/wireless/realtek/rtl8xxxu/8188e.c @@ -0,0 +1,1897 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * RTL8XXXU mac80211 USB driver - 8188e specific subdriver + * + * Copyright (c) 2014 - 2016 Jes Sorensen + * + * Portions, notably calibration code: + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This driver was written as a replacement for the vendor provided + * rtl8723au driver. As the Realtek 8xxx chips are very similar in + * their programming interface, I have started adding support for + * additional 8xxx chips like the 8192cu, 8188cus, etc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "rtl8xxxu.h" +#include "regs.h" + +static const struct rtl8xxxu_reg8val rtl8188e_mac_init_table[] = { + {0x026, 0x41}, {0x027, 0x35}, {0x040, 0x00}, {0x421, 0x0f}, + {0x428, 0x0a}, {0x429, 0x10}, {0x430, 0x00}, {0x431, 0x01}, + {0x432, 0x02}, {0x433, 0x04}, {0x434, 0x05}, {0x435, 0x06}, + {0x436, 0x07}, {0x437, 0x08}, {0x438, 0x00}, {0x439, 0x00}, + {0x43a, 0x01}, {0x43b, 0x02}, {0x43c, 0x04}, {0x43d, 0x05}, + {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01}, + {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f}, + {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72}, + {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x480, 0x08}, + {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff}, {0x4cd, 0xff}, + {0x4ce, 0x01}, {0x4d3, 0x01}, {0x500, 0x26}, {0x501, 0xa2}, + {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3}, + {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4}, + {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4}, + {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a}, + {0x516, 0x0a}, {0x525, 0x4f}, {0x550, 0x10}, {0x551, 0x10}, + {0x559, 0x02}, {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, + {0x609, 0x2a}, {0x620, 0xff}, {0x621, 0xff}, {0x622, 0xff}, + {0x623, 0xff}, {0x624, 0xff}, {0x625, 0xff}, {0x626, 0xff}, + {0x627, 0xff}, {0x63c, 0x08}, {0x63d, 0x08}, {0x63e, 0x0c}, + {0x63f, 0x0c}, {0x640, 0x40}, {0x652, 0x20}, {0x66e, 0x05}, + {0x700, 0x21}, {0x701, 0x43}, {0x702, 0x65}, {0x703, 0x87}, + {0x708, 0x21}, {0x709, 0x43}, {0x70a, 0x65}, {0x70b, 0x87}, + {0xffff, 0xff}, +}; + +static const struct rtl8xxxu_reg32val rtl8188eu_phy_init_table[] = { + {0x800, 0x80040000}, {0x804, 0x00000003}, + {0x808, 0x0000fc00}, {0x80c, 0x0000000a}, + {0x810, 0x10001331}, {0x814, 0x020c3d10}, + {0x818, 0x02200385}, {0x81c, 0x00000000}, + {0x820, 0x01000100}, {0x824, 0x00390204}, + {0x828, 0x00000000}, {0x82c, 0x00000000}, + {0x830, 0x00000000}, {0x834, 0x00000000}, + {0x838, 0x00000000}, {0x83c, 0x00000000}, + {0x840, 0x00010000}, {0x844, 0x00000000}, + {0x848, 0x00000000}, {0x84c, 0x00000000}, + {0x850, 0x00000000}, {0x854, 0x00000000}, + {0x858, 0x569a11a9}, {0x85c, 0x01000014}, + {0x860, 0x66f60110}, {0x864, 0x061f0649}, + {0x868, 0x00000000}, {0x86c, 0x27272700}, + {0x870, 0x07000760}, {0x874, 0x25004000}, + {0x878, 0x00000808}, {0x87c, 0x00000000}, + {0x880, 0xb0000c1c}, {0x884, 0x00000001}, + {0x888, 0x00000000}, {0x88c, 0xccc000c0}, + {0x890, 0x00000800}, {0x894, 0xfffffffe}, + {0x898, 0x40302010}, {0x89c, 0x00706050}, + {0x900, 0x00000000}, {0x904, 0x00000023}, + {0x908, 0x00000000}, {0x90c, 0x81121111}, + {0x910, 0x00000002}, {0x914, 0x00000201}, + {0xa00, 0x00d047c8}, {0xa04, 0x80ff800c}, + {0xa08, 0x8c838300}, {0xa0c, 0x2e7f120f}, + {0xa10, 0x9500bb7e}, {0xa14, 0x1114d028}, + {0xa18, 0x00881117}, {0xa1c, 0x89140f00}, + {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317}, + {0xa28, 0x00000204}, {0xa2c, 0x00d30000}, + {0xa70, 0x101fbf00}, {0xa74, 0x00000007}, + {0xa78, 0x00000900}, {0xa7c, 0x225b0606}, + {0xa80, 0x218075b1}, {0xb2c, 0x80000000}, + {0xc00, 0x48071d40}, {0xc04, 0x03a05611}, + {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c}, + {0xc10, 0x08800000}, {0xc14, 0x40000100}, + {0xc18, 0x08800000}, {0xc1c, 0x40000100}, + {0xc20, 0x00000000}, {0xc24, 0x00000000}, + {0xc28, 0x00000000}, {0xc2c, 0x00000000}, + {0xc30, 0x69e9ac47}, {0xc34, 0x469652af}, + {0xc38, 0x49795994}, {0xc3c, 0x0a97971c}, + {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7}, + {0xc48, 0xec020107}, {0xc4c, 0x007f037f}, + {0xc50, 0x69553420}, {0xc54, 0x43bc0094}, + {0xc58, 0x00013169}, {0xc5c, 0x00250492}, + {0xc60, 0x00000000}, {0xc64, 0x7112848b}, + {0xc68, 0x47c00bff}, {0xc6c, 0x00000036}, + {0xc70, 0x2c7f000d}, {0xc74, 0x020610db}, + {0xc78, 0x0000001f}, {0xc7c, 0x00b91612}, + {0xc80, 0x390000e4}, {0xc84, 0x21f60000}, + {0xc88, 0x40000100}, {0xc8c, 0x20200000}, + {0xc90, 0x00091521}, {0xc94, 0x00000000}, + {0xc98, 0x00121820}, {0xc9c, 0x00007f7f}, + {0xca0, 0x00000000}, {0xca4, 0x000300a0}, + {0xca8, 0x00000000}, {0xcac, 0x00000000}, + {0xcb0, 0x00000000}, {0xcb4, 0x00000000}, + {0xcb8, 0x00000000}, {0xcbc, 0x28000000}, + {0xcc0, 0x00000000}, {0xcc4, 0x00000000}, + {0xcc8, 0x00000000}, {0xccc, 0x00000000}, + {0xcd0, 0x00000000}, {0xcd4, 0x00000000}, + {0xcd8, 0x64b22427}, {0xcdc, 0x00766932}, + {0xce0, 0x00222222}, {0xce4, 0x00000000}, + {0xce8, 0x37644302}, {0xcec, 0x2f97d40c}, + {0xd00, 0x00000740}, {0xd04, 0x00020401}, + {0xd08, 0x0000907f}, {0xd0c, 0x20010201}, + {0xd10, 0xa0633333}, {0xd14, 0x3333bc43}, + {0xd18, 0x7a8f5b6f}, {0xd2c, 0xcc979975}, + {0xd30, 0x00000000}, {0xd34, 0x80608000}, + {0xd38, 0x00000000}, {0xd3c, 0x00127353}, + {0xd40, 0x00000000}, {0xd44, 0x00000000}, + {0xd48, 0x00000000}, {0xd4c, 0x00000000}, + {0xd50, 0x6437140a}, {0xd54, 0x00000000}, + {0xd58, 0x00000282}, {0xd5c, 0x30032064}, + {0xd60, 0x4653de68}, {0xd64, 0x04518a3c}, + {0xd68, 0x00002101}, {0xd6c, 0x2a201c16}, + {0xd70, 0x1812362e}, {0xd74, 0x322c2220}, + {0xd78, 0x000e3c24}, {0xe00, 0x2d2d2d2d}, + {0xe04, 0x2d2d2d2d}, {0xe08, 0x0390272d}, + {0xe10, 0x2d2d2d2d}, {0xe14, 0x2d2d2d2d}, + {0xe18, 0x2d2d2d2d}, {0xe1c, 0x2d2d2d2d}, + {0xe28, 0x00000000}, {0xe30, 0x1000dc1f}, + {0xe34, 0x10008c1f}, {0xe38, 0x02140102}, + {0xe3c, 0x681604c2}, {0xe40, 0x01007c00}, + {0xe44, 0x01004800}, {0xe48, 0xfb000000}, + {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f}, + {0xe54, 0x10008c1f}, {0xe58, 0x02140102}, + {0xe5c, 0x28160d05}, {0xe60, 0x00000048}, + {0xe68, 0x001b25a4}, {0xe6c, 0x00c00014}, + {0xe70, 0x00c00014}, {0xe74, 0x01000014}, + {0xe78, 0x01000014}, {0xe7c, 0x01000014}, + {0xe80, 0x01000014}, {0xe84, 0x00c00014}, + {0xe88, 0x01000014}, {0xe8c, 0x00c00014}, + {0xed0, 0x00c00014}, {0xed4, 0x00c00014}, + {0xed8, 0x00c00014}, {0xedc, 0x00000014}, + {0xee0, 0x00000014}, {0xee8, 0x21555448}, + {0xeec, 0x01c00014}, {0xf14, 0x00000003}, + {0xf4c, 0x00000000}, {0xf00, 0x00000300}, + {0xffff, 0xffffffff}, +}; + +static const struct rtl8xxxu_reg32val rtl8188e_agc_table[] = { + {0xc78, 0xfb000001}, {0xc78, 0xfb010001}, + {0xc78, 0xfb020001}, {0xc78, 0xfb030001}, + {0xc78, 0xfb040001}, {0xc78, 0xfb050001}, + {0xc78, 0xfa060001}, {0xc78, 0xf9070001}, + {0xc78, 0xf8080001}, {0xc78, 0xf7090001}, + {0xc78, 0xf60a0001}, {0xc78, 0xf50b0001}, + {0xc78, 0xf40c0001}, {0xc78, 0xf30d0001}, + {0xc78, 0xf20e0001}, {0xc78, 0xf10f0001}, + {0xc78, 0xf0100001}, {0xc78, 0xef110001}, + {0xc78, 0xee120001}, {0xc78, 0xed130001}, + {0xc78, 0xec140001}, {0xc78, 0xeb150001}, + {0xc78, 0xea160001}, {0xc78, 0xe9170001}, + {0xc78, 0xe8180001}, {0xc78, 0xe7190001}, + {0xc78, 0xe61a0001}, {0xc78, 0xe51b0001}, + {0xc78, 0xe41c0001}, {0xc78, 0xe31d0001}, + {0xc78, 0xe21e0001}, {0xc78, 0xe11f0001}, + {0xc78, 0x8a200001}, {0xc78, 0x89210001}, + {0xc78, 0x88220001}, {0xc78, 0x87230001}, + {0xc78, 0x86240001}, {0xc78, 0x85250001}, + {0xc78, 0x84260001}, {0xc78, 0x83270001}, + {0xc78, 0x82280001}, {0xc78, 0x6b290001}, + {0xc78, 0x6a2a0001}, {0xc78, 0x692b0001}, + {0xc78, 0x682c0001}, {0xc78, 0x672d0001}, + {0xc78, 0x662e0001}, {0xc78, 0x652f0001}, + {0xc78, 0x64300001}, {0xc78, 0x63310001}, + {0xc78, 0x62320001}, {0xc78, 0x61330001}, + {0xc78, 0x46340001}, {0xc78, 0x45350001}, + {0xc78, 0x44360001}, {0xc78, 0x43370001}, + {0xc78, 0x42380001}, {0xc78, 0x41390001}, + {0xc78, 0x403a0001}, {0xc78, 0x403b0001}, + {0xc78, 0x403c0001}, {0xc78, 0x403d0001}, + {0xc78, 0x403e0001}, {0xc78, 0x403f0001}, + {0xc78, 0xfb400001}, {0xc78, 0xfb410001}, + {0xc78, 0xfb420001}, {0xc78, 0xfb430001}, + {0xc78, 0xfb440001}, {0xc78, 0xfb450001}, + {0xc78, 0xfb460001}, {0xc78, 0xfb470001}, + {0xc78, 0xfb480001}, {0xc78, 0xfa490001}, + {0xc78, 0xf94a0001}, {0xc78, 0xf84b0001}, + {0xc78, 0xf74c0001}, {0xc78, 0xf64d0001}, + {0xc78, 0xf54e0001}, {0xc78, 0xf44f0001}, + {0xc78, 0xf3500001}, {0xc78, 0xf2510001}, + {0xc78, 0xf1520001}, {0xc78, 0xf0530001}, + {0xc78, 0xef540001}, {0xc78, 0xee550001}, + {0xc78, 0xed560001}, {0xc78, 0xec570001}, + {0xc78, 0xeb580001}, {0xc78, 0xea590001}, + {0xc78, 0xe95a0001}, {0xc78, 0xe85b0001}, + {0xc78, 0xe75c0001}, {0xc78, 0xe65d0001}, + {0xc78, 0xe55e0001}, {0xc78, 0xe45f0001}, + {0xc78, 0xe3600001}, {0xc78, 0xe2610001}, + {0xc78, 0xc3620001}, {0xc78, 0xc2630001}, + {0xc78, 0xc1640001}, {0xc78, 0x8b650001}, + {0xc78, 0x8a660001}, {0xc78, 0x89670001}, + {0xc78, 0x88680001}, {0xc78, 0x87690001}, + {0xc78, 0x866a0001}, {0xc78, 0x856b0001}, + {0xc78, 0x846c0001}, {0xc78, 0x676d0001}, + {0xc78, 0x666e0001}, {0xc78, 0x656f0001}, + {0xc78, 0x64700001}, {0xc78, 0x63710001}, + {0xc78, 0x62720001}, {0xc78, 0x61730001}, + {0xc78, 0x60740001}, {0xc78, 0x46750001}, + {0xc78, 0x45760001}, {0xc78, 0x44770001}, + {0xc78, 0x43780001}, {0xc78, 0x42790001}, + {0xc78, 0x417a0001}, {0xc78, 0x407b0001}, + {0xc78, 0x407c0001}, {0xc78, 0x407d0001}, + {0xc78, 0x407e0001}, {0xc78, 0x407f0001}, + {0xc50, 0x69553422}, {0xc50, 0x69553420}, + {0xffff, 0xffffffff} +}; + +static const struct rtl8xxxu_rfregval rtl8188eu_radioa_init_table[] = { + {0x00, 0x00030000}, {0x08, 0x00084000}, + {0x18, 0x00000407}, {0x19, 0x00000012}, + {0x1e, 0x00080009}, {0x1f, 0x00000880}, + {0x2f, 0x0001a060}, {0x3f, 0x00000000}, + {0x42, 0x000060c0}, {0x57, 0x000d0000}, + {0x58, 0x000be180}, {0x67, 0x00001552}, + {0x83, 0x00000000}, {0xb0, 0x000ff8fc}, + {0xb1, 0x00054400}, {0xb2, 0x000ccc19}, + {0xb4, 0x00043003}, {0xb6, 0x0004953e}, + {0xb7, 0x0001c718}, {0xb8, 0x000060ff}, + {0xb9, 0x00080001}, {0xba, 0x00040000}, + {0xbb, 0x00000400}, {0xbf, 0x000c0000}, + {0xc2, 0x00002400}, {0xc3, 0x00000009}, + {0xc4, 0x00040c91}, {0xc5, 0x00099999}, + {0xc6, 0x000000a3}, {0xc7, 0x00088820}, + {0xc8, 0x00076c06}, {0xc9, 0x00000000}, + {0xca, 0x00080000}, {0xdf, 0x00000180}, + {0xef, 0x000001a0}, {0x51, 0x0006b27d}, + {0x52, 0x0007e49d}, /* Set to 0x0007e4dd for SDIO */ + {0x53, 0x00000073}, {0x56, 0x00051ff3}, + {0x35, 0x00000086}, {0x35, 0x00000186}, + {0x35, 0x00000286}, {0x36, 0x00001c25}, + {0x36, 0x00009c25}, {0x36, 0x00011c25}, + {0x36, 0x00019c25}, {0xb6, 0x00048538}, + {0x18, 0x00000c07}, {0x5a, 0x0004bd00}, + {0x19, 0x000739d0}, {0x34, 0x0000adf3}, + {0x34, 0x00009df0}, {0x34, 0x00008ded}, + {0x34, 0x00007dea}, {0x34, 0x00006de7}, + {0x34, 0x000054ee}, {0x34, 0x000044eb}, + {0x34, 0x000034e8}, {0x34, 0x0000246b}, + {0x34, 0x00001468}, {0x34, 0x0000006d}, + {0x00, 0x00030159}, {0x84, 0x00068200}, + {0x86, 0x000000ce}, {0x87, 0x00048a00}, + {0x8e, 0x00065540}, {0x8f, 0x00088000}, + {0xef, 0x000020a0}, {0x3b, 0x000f02b0}, + {0x3b, 0x000ef7b0}, {0x3b, 0x000d4fb0}, + {0x3b, 0x000cf060}, {0x3b, 0x000b0090}, + {0x3b, 0x000a0080}, {0x3b, 0x00090080}, + {0x3b, 0x0008f780}, {0x3b, 0x000722b0}, + {0x3b, 0x0006f7b0}, {0x3b, 0x00054fb0}, + {0x3b, 0x0004f060}, {0x3b, 0x00030090}, + {0x3b, 0x00020080}, {0x3b, 0x00010080}, + {0x3b, 0x0000f780}, {0xef, 0x000000a0}, + {0x00, 0x00010159}, {0x18, 0x0000f407}, + {0xFE, 0x00000000}, {0xFE, 0x00000000}, + {0x1F, 0x00080003}, {0xFE, 0x00000000}, + {0xFE, 0x00000000}, {0x1E, 0x00000001}, + {0x1F, 0x00080000}, {0x00, 0x00033e60}, + {0xff, 0xffffffff} +}; + +#define PERENTRY 23 +#define RETRYSIZE 5 +#define RATESIZE 28 +#define TX_RPT2_ITEM_SIZE 8 + +static const u8 retry_penalty[PERENTRY][RETRYSIZE + 1] = { + {5, 4, 3, 2, 0, 3}, /* 92 , idx=0 */ + {6, 5, 4, 3, 0, 4}, /* 86 , idx=1 */ + {6, 5, 4, 2, 0, 4}, /* 81 , idx=2 */ + {8, 7, 6, 4, 0, 6}, /* 75 , idx=3 */ + {10, 9, 8, 6, 0, 8}, /* 71 , idx=4 */ + {10, 9, 8, 4, 0, 8}, /* 66 , idx=5 */ + {10, 9, 8, 2, 0, 8}, /* 62 , idx=6 */ + {10, 9, 8, 0, 0, 8}, /* 59 , idx=7 */ + {18, 17, 16, 8, 0, 16}, /* 53 , idx=8 */ + {26, 25, 24, 16, 0, 24}, /* 50 , idx=9 */ + {34, 33, 32, 24, 0, 32}, /* 47 , idx=0x0a */ + {34, 31, 28, 20, 0, 32}, /* 43 , idx=0x0b */ + {34, 31, 27, 18, 0, 32}, /* 40 , idx=0x0c */ + {34, 31, 26, 16, 0, 32}, /* 37 , idx=0x0d */ + {34, 30, 22, 16, 0, 32}, /* 32 , idx=0x0e */ + {34, 30, 24, 16, 0, 32}, /* 26 , idx=0x0f */ + {49, 46, 40, 16, 0, 48}, /* 20 , idx=0x10 */ + {49, 45, 32, 0, 0, 48}, /* 17 , idx=0x11 */ + {49, 45, 22, 18, 0, 48}, /* 15 , idx=0x12 */ + {49, 40, 24, 16, 0, 48}, /* 12 , idx=0x13 */ + {49, 32, 18, 12, 0, 48}, /* 9 , idx=0x14 */ + {49, 22, 18, 14, 0, 48}, /* 6 , idx=0x15 */ + {49, 16, 16, 0, 0, 48} /* 3, idx=0x16 */ +}; + +static const u8 pt_penalty[RETRYSIZE + 1] = {34, 31, 30, 24, 0, 32}; + +static const u8 retry_penalty_idx_normal[2][RATESIZE] = { + { /* RSSI>TH */ + 4, 4, 4, 5, + 4, 4, 5, 7, 7, 7, 8, 0x0a, + 4, 4, 4, 4, 6, 0x0a, 0x0b, 0x0d, + 5, 5, 7, 7, 8, 0x0b, 0x0d, 0x0f + }, + { /* RSSITH */ + 4, 4, 4, 5, + 4, 4, 5, 7, 7, 7, 8, 0x0a, + 4, 4, 4, 4, 6, 0x0a, 0x0b, 0x0d, + 5, 5, 7, 7, 8, 0x0b, 0x0d, 0x0f + }, + { /* RSSIudev->dev; + u32 sys_cfg, vendor; + int ret = 0; + + strscpy(priv->chip_name, "8188EU", sizeof(priv->chip_name)); + priv->rtl_chip = RTL8188E; + priv->rf_paths = 1; + priv->rx_paths = 1; + priv->tx_paths = 1; + priv->has_wifi = 1; + + sys_cfg = rtl8xxxu_read32(priv, REG_SYS_CFG); + priv->chip_cut = u32_get_bits(sys_cfg, SYS_CFG_CHIP_VERSION_MASK); + if (sys_cfg & SYS_CFG_TRP_VAUX_EN) { + dev_info(dev, "Unsupported test chip\n"); + return -EOPNOTSUPP; + } + + /* + * TODO: At a glance, I cut requires a different firmware, + * different initialisation tables, and no software rate + * control. The vendor driver is not configured to handle + * I cut chips by default. Are there any in the wild? + */ + if (priv->chip_cut == 8) { + dev_info(dev, "RTL8188EU cut I is not supported. Please complain about it at linux-wireless@vger.kernel.org.\n"); + return -EOPNOTSUPP; + } + + vendor = sys_cfg & SYS_CFG_VENDOR_ID; + rtl8xxxu_identify_vendor_1bit(priv, vendor); + + ret = rtl8xxxu_config_endpoints_no_sie(priv); + + return ret; +} + +static void rtl8188eu_config_channel(struct ieee80211_hw *hw) +{ + struct rtl8xxxu_priv *priv = hw->priv; + u32 val32, rsr; + u8 opmode; + int sec_ch_above, channel; + int i; + + opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE); + rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); + channel = hw->conf.chandef.chan->hw_value; + + switch (hw->conf.chandef.width) { + case NL80211_CHAN_WIDTH_20_NOHT: + case NL80211_CHAN_WIDTH_20: + opmode |= BW_OPMODE_20MHZ; + rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode); + + val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); + val32 &= ~FPGA_RF_MODE; + rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); + + val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); + val32 &= ~FPGA_RF_MODE; + rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); + break; + case NL80211_CHAN_WIDTH_40: + if (hw->conf.chandef.center_freq1 > + hw->conf.chandef.chan->center_freq) { + sec_ch_above = 1; + channel += 2; + } else { + sec_ch_above = 0; + channel -= 2; + } + + opmode &= ~BW_OPMODE_20MHZ; + rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode); + rsr &= ~RSR_RSC_BANDWIDTH_40M; + if (sec_ch_above) + rsr |= RSR_RSC_LOWER_SUB_CHANNEL; + else + rsr |= RSR_RSC_UPPER_SUB_CHANNEL; + rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr); + + val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); + val32 |= FPGA_RF_MODE; + rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); + + val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); + val32 |= FPGA_RF_MODE; + rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); + + /* + * Set Control channel to upper or lower. These settings + * are required only for 40MHz + */ + val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM); + val32 &= ~CCK0_SIDEBAND; + if (!sec_ch_above) + val32 |= CCK0_SIDEBAND; + rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32); + + val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF); + val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */ + if (sec_ch_above) + val32 |= OFDM_LSTF_PRIME_CH_LOW; + else + val32 |= OFDM_LSTF_PRIME_CH_HIGH; + rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); + + val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); + val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL); + if (sec_ch_above) + val32 |= FPGA0_PS_UPPER_CHANNEL; + else + val32 |= FPGA0_PS_LOWER_CHANNEL; + rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); + break; + + default: + break; + } + + for (i = RF_A; i < priv->rf_paths; i++) { + val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); + u32p_replace_bits(&val32, channel, MODE_AG_CHANNEL_MASK); + rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); + } + + for (i = RF_A; i < priv->rf_paths; i++) { + val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); + val32 &= ~MODE_AG_BW_MASK; + if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) + val32 |= MODE_AG_BW_40MHZ_8723B; + else + val32 |= MODE_AG_BW_20MHZ_8723B; + rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); + } +} + +static void rtl8188eu_init_aggregation(struct rtl8xxxu_priv *priv) +{ + u8 agg_ctrl, usb_spec; + + usb_spec = rtl8xxxu_read8(priv, REG_USB_SPECIAL_OPTION); + usb_spec &= ~USB_SPEC_USB_AGG_ENABLE; + rtl8xxxu_write8(priv, REG_USB_SPECIAL_OPTION, usb_spec); + + agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL); + agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN; + rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl); +} + +static int rtl8188eu_parse_efuse(struct rtl8xxxu_priv *priv) +{ + struct rtl8188eu_efuse *efuse = &priv->efuse_wifi.efuse8188eu; + + if (efuse->rtl_id != cpu_to_le16(0x8129)) + return -EINVAL; + + ether_addr_copy(priv->mac_addr, efuse->mac_addr); + + memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base, + sizeof(efuse->tx_power_index_A.cck_base)); + + memcpy(priv->ht40_1s_tx_power_index_A, + efuse->tx_power_index_A.ht40_base, + sizeof(efuse->tx_power_index_A.ht40_base)); + + priv->default_crystal_cap = efuse->xtal_k & 0x3f; + + return 0; +} + +static void rtl8188eu_reset_8051(struct rtl8xxxu_priv *priv) +{ + u16 sys_func; + + sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC); + sys_func &= ~SYS_FUNC_CPU_ENABLE; + rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func); + + sys_func |= SYS_FUNC_CPU_ENABLE; + rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func); +} + +static int rtl8188eu_load_firmware(struct rtl8xxxu_priv *priv) +{ + const char *fw_name; + int ret; + + fw_name = "rtlwifi/rtl8188eufw.bin"; + + ret = rtl8xxxu_load_firmware(priv, fw_name); + + return ret; +} + +static void rtl8188eu_init_phy_bb(struct rtl8xxxu_priv *priv) +{ + u8 val8; + u16 val16; + + val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); + val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB | SYS_FUNC_DIO_RF; + rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); + + /* + * Per vendor driver, run power sequence before init of RF + */ + val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB; + rtl8xxxu_write8(priv, REG_RF_CTRL, val8); + + val8 = SYS_FUNC_USBA | SYS_FUNC_USBD | + SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB; + rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); + + rtl8xxxu_init_phy_regs(priv, rtl8188eu_phy_init_table); + rtl8xxxu_init_phy_regs(priv, rtl8188e_agc_table); +} + +static int rtl8188eu_init_phy_rf(struct rtl8xxxu_priv *priv) +{ + return rtl8xxxu_init_phy_rf(priv, rtl8188eu_radioa_init_table, RF_A); +} + +static int rtl8188eu_iqk_path_a(struct rtl8xxxu_priv *priv) +{ + u32 reg_eac, reg_e94, reg_e9c; + int result = 0; + + /* Path A IQK setting */ + rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1c); + rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x30008c1c); + + rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x8214032a); + rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160000); + + /* LO calibration setting */ + rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911); + + /* One shot, path A LOK & IQK */ + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); + + mdelay(10); + + /* Check failed */ + reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); + reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); + reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); + + if (!(reg_eac & BIT(28)) && + ((reg_e94 & 0x03ff0000) != 0x01420000) && + ((reg_e9c & 0x03ff0000) != 0x00420000)) + result |= 0x01; + + return result; +} + +static int rtl8188eu_rx_iqk_path_a(struct rtl8xxxu_priv *priv) +{ + u32 reg_ea4, reg_eac, reg_e94, reg_e9c, val32; + int result = 0; + + /* Leave IQK mode */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); + u32p_replace_bits(&val32, 0, 0xffffff00); + rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); + + /* Enable path A PA in TX IQK mode */ + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf117b); + + /* Enter IQK mode */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); + u32p_replace_bits(&val32, 0x808000, 0xffffff00); + rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); + + /* TX IQK setting */ + rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); + rtl8xxxu_write32(priv, REG_RX_IQK, 0x81004800); + + /* path-A IQK setting */ + rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1c); + rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x30008c1c); + + rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160804); + rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160000); + + /* LO calibration setting */ + rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911); + + /* One shot, path A LOK & IQK */ + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); + + mdelay(10); + + /* Check failed */ + reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); + reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); + reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); + + if (!(reg_eac & BIT(28)) && + ((reg_e94 & 0x03ff0000) != 0x01420000) && + ((reg_e9c & 0x03ff0000) != 0x00420000)) + result |= 0x01; + else + goto out; + + val32 = 0x80007c00 | + (reg_e94 & 0x03ff0000) | ((reg_e9c >> 16) & 0x03ff); + rtl8xxxu_write32(priv, REG_TX_IQK, val32); + + /* Modify RX IQK mode table */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); + u32p_replace_bits(&val32, 0, 0xffffff00); + rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); + + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7ffa); + + /* Enter IQK mode */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); + u32p_replace_bits(&val32, 0x808000, 0xffffff00); + rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); + + /* IQK setting */ + rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); + + /* Path A IQK setting */ + rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x30008c1c); + rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1c); + + rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160c05); + rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160c05); + + /* LO calibration setting */ + rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911); + + /* One shot, path A LOK & IQK */ + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); + + mdelay(10); + + reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); + reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); + + if (!(reg_eac & BIT(27)) && + ((reg_ea4 & 0x03ff0000) != 0x01320000) && + ((reg_eac & 0x03ff0000) != 0x00360000)) + result |= 0x02; + else + dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n", + __func__); + +out: + return result; +} + +static void rtl8188eu_phy_iqcalibrate(struct rtl8xxxu_priv *priv, + int result[][8], int t) +{ + struct device *dev = &priv->udev->dev; + u32 i, val32; + int path_a_ok; + int retry = 2; + static const u32 adda_regs[RTL8XXXU_ADDA_REGS] = { + REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH, + REG_RX_WAIT_CCA, REG_TX_CCK_RFON, + REG_TX_CCK_BBON, REG_TX_OFDM_RFON, + REG_TX_OFDM_BBON, REG_TX_TO_RX, + REG_TX_TO_TX, REG_RX_CCK, + REG_RX_OFDM, REG_RX_WAIT_RIFS, + REG_RX_TO_RX, REG_STANDBY, + REG_SLEEP, REG_PMPD_ANAEN + }; + static const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = { + REG_TXPAUSE, REG_BEACON_CTRL, + REG_BEACON_CTRL_1, REG_GPIO_MUXCFG + }; + static const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = { + REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR, + REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, + REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE, + REG_FPGA0_XB_RF_INT_OE, REG_CCK0_AFE_SETTING + }; + + /* + * Note: IQ calibration must be performed after loading + * PHY_REG.txt , and radio_a, radio_b.txt + */ + + if (t == 0) { + /* Save ADDA parameters, turn Path A ADDA on */ + rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup, + RTL8XXXU_ADDA_REGS); + rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup); + rtl8xxxu_save_regs(priv, iqk_bb_regs, + priv->bb_backup, RTL8XXXU_BB_REGS); + } + + rtl8xxxu_path_adda_on(priv, adda_regs, true); + + if (t == 0) { + val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1); + priv->pi_enabled = u32_get_bits(val32, FPGA0_HSSI_PARM1_PI); + } + + if (!priv->pi_enabled) { + /* Switch BB to PI mode to do IQ Calibration. */ + rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100); + rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100); + } + + /* MAC settings */ + rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup); + + val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING); + u32p_replace_bits(&val32, 0xf, 0x0f000000); + rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32); + + rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600); + rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4); + rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000); + + if (!priv->no_pape) { + val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL); + val32 |= (FPGA0_RF_PAPE | + (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT)); + rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32); + } + + val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE); + val32 &= ~BIT(10); + rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32); + val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE); + val32 &= ~BIT(10); + rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32); + + /* Page B init */ + rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x0f600000); + + /* IQ calibration setting */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); + u32p_replace_bits(&val32, 0x808000, 0xffffff00); + rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); + rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); + rtl8xxxu_write32(priv, REG_RX_IQK, 0x81004800); + + for (i = 0; i < retry; i++) { + path_a_ok = rtl8188eu_iqk_path_a(priv); + if (path_a_ok == 0x01) { + val32 = rtl8xxxu_read32(priv, + REG_TX_POWER_BEFORE_IQK_A); + result[t][0] = (val32 >> 16) & 0x3ff; + val32 = rtl8xxxu_read32(priv, + REG_TX_POWER_AFTER_IQK_A); + result[t][1] = (val32 >> 16) & 0x3ff; + break; + } + } + + if (!path_a_ok) + dev_dbg(dev, "%s: Path A TX IQK failed!\n", __func__); + + for (i = 0; i < retry; i++) { + path_a_ok = rtl8188eu_rx_iqk_path_a(priv); + if (path_a_ok == 0x03) { + val32 = rtl8xxxu_read32(priv, + REG_RX_POWER_BEFORE_IQK_A_2); + result[t][2] = (val32 >> 16) & 0x3ff; + val32 = rtl8xxxu_read32(priv, + REG_RX_POWER_AFTER_IQK_A_2); + result[t][3] = (val32 >> 16) & 0x3ff; + + break; + } + } + + if (!path_a_ok) + dev_dbg(dev, "%s: Path A RX IQK failed!\n", __func__); + + /* Back to BB mode, load original value */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); + u32p_replace_bits(&val32, 0, 0xffffff00); + rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); + + if (t == 0) + return; + + if (!priv->pi_enabled) { + /* Switch back BB to SI mode after finishing IQ Calibration */ + rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000000); + rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000000); + } + + /* Reload ADDA power saving parameters */ + rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup, + RTL8XXXU_ADDA_REGS); + + /* Reload MAC parameters */ + rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup); + + /* Reload BB parameters */ + rtl8xxxu_restore_regs(priv, iqk_bb_regs, + priv->bb_backup, RTL8XXXU_BB_REGS); + + /* Restore RX initial gain */ + rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3); + + /* Load 0xe30 IQC default value */ + rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00); + rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00); +} + +static void rtl8188eu_phy_iq_calibrate(struct rtl8xxxu_priv *priv) +{ + struct device *dev = &priv->udev->dev; + int result[4][8]; /* last is final result */ + int i, candidate; + bool path_a_ok; + u32 reg_e94, reg_e9c, reg_ea4, reg_eac; + u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc; + bool simu; + + memset(result, 0, sizeof(result)); + result[3][0] = 0x100; + result[3][2] = 0x100; + result[3][4] = 0x100; + result[3][6] = 0x100; + + candidate = -1; + + path_a_ok = false; + + for (i = 0; i < 3; i++) { + rtl8188eu_phy_iqcalibrate(priv, result, i); + + if (i == 1) { + simu = rtl8xxxu_simularity_compare(priv, + result, 0, 1); + if (simu) { + candidate = 0; + break; + } + } + + if (i == 2) { + simu = rtl8xxxu_simularity_compare(priv, + result, 0, 2); + if (simu) { + candidate = 0; + break; + } + + simu = rtl8xxxu_simularity_compare(priv, + result, 1, 2); + if (simu) + candidate = 1; + else + candidate = 3; + } + } + + if (candidate >= 0) { + reg_e94 = result[candidate][0]; + priv->rege94 = reg_e94; + reg_e9c = result[candidate][1]; + priv->rege9c = reg_e9c; + reg_ea4 = result[candidate][2]; + reg_eac = result[candidate][3]; + reg_eb4 = result[candidate][4]; + priv->regeb4 = reg_eb4; + reg_ebc = result[candidate][5]; + priv->regebc = reg_ebc; + reg_ec4 = result[candidate][6]; + reg_ecc = result[candidate][7]; + dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate); + dev_dbg(dev, + "%s: e94=%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x ecc=%x\n", + __func__, reg_e94, reg_e9c, reg_ea4, reg_eac, + reg_eb4, reg_ebc, reg_ec4, reg_ecc); + path_a_ok = true; + } else { + reg_e94 = 0x100; + reg_eb4 = 0x100; + priv->rege94 = 0x100; + priv->regeb4 = 0x100; + reg_e9c = 0x0; + reg_ebc = 0x0; + priv->rege9c = 0x0; + priv->regebc = 0x0; + } + + if (reg_e94 && candidate >= 0) + rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result, + candidate, (reg_ea4 == 0)); + + rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg, + priv->bb_recovery_backup, RTL8XXXU_BB_REGS); +} + +static void rtl8188e_disabled_to_emu(struct rtl8xxxu_priv *priv) +{ + u16 val16; + + val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO); + val16 &= ~(APS_FSMCO_HW_SUSPEND | APS_FSMCO_PCIE); + rtl8xxxu_write16(priv, REG_APS_FSMCO, val16); +} + +static int rtl8188e_emu_to_active(struct rtl8xxxu_priv *priv) +{ + u8 val8; + u32 val32; + u16 val16; + int count, ret = 0; + + /* wait till 0x04[17] = 1 power ready*/ + for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { + val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); + if (val32 & BIT(17)) + break; + + udelay(10); + } + + if (!count) { + ret = -EBUSY; + goto exit; + } + + /* reset baseband */ + val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); + val8 &= ~(SYS_FUNC_BBRSTB | SYS_FUNC_BB_GLB_RSTN); + rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); + + /*0x24[23] = 2b'01 schmit trigger */ + val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL); + val32 |= BIT(23); + rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32); + + /* 0x04[15] = 0 disable HWPDN (control by DRV)*/ + val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO); + val16 &= ~APS_FSMCO_HW_POWERDOWN; + rtl8xxxu_write16(priv, REG_APS_FSMCO, val16); + + /*0x04[12:11] = 2b'00 disable WL suspend*/ + val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO); + val16 &= ~(APS_FSMCO_HW_SUSPEND | APS_FSMCO_PCIE); + rtl8xxxu_write16(priv, REG_APS_FSMCO, val16); + + /* set, then poll until 0 */ + val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); + val32 |= APS_FSMCO_MAC_ENABLE; + rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); + + for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { + val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); + if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) { + ret = 0; + break; + } + udelay(10); + } + + if (!count) { + ret = -EBUSY; + goto exit; + } + + /* LDO normal mode*/ + val8 = rtl8xxxu_read8(priv, REG_LPLDO_CTRL); + val8 &= ~BIT(4); + rtl8xxxu_write8(priv, REG_LPLDO_CTRL, val8); + +exit: + return ret; +} + +static int rtl8188eu_active_to_emu(struct rtl8xxxu_priv *priv) +{ + u8 val8; + + /* Turn off RF */ + val8 = rtl8xxxu_read8(priv, REG_RF_CTRL); + val8 &= ~RF_ENABLE; + rtl8xxxu_write8(priv, REG_RF_CTRL, val8); + + /* LDO Sleep mode */ + val8 = rtl8xxxu_read8(priv, REG_LPLDO_CTRL); + val8 |= BIT(4); + rtl8xxxu_write8(priv, REG_LPLDO_CTRL, val8); + + return 0; +} + +static int rtl8188eu_emu_to_disabled(struct rtl8xxxu_priv *priv) +{ + u32 val32; + u16 val16; + u8 val8; + + val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL); + val32 |= BIT(23); + rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32); + + val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO); + val16 &= ~APS_FSMCO_PCIE; + val16 |= APS_FSMCO_HW_SUSPEND; + rtl8xxxu_write16(priv, REG_APS_FSMCO, val16); + + rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x00); + + val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG + 1); + val8 &= ~BIT(4); + rtl8xxxu_write8(priv, REG_GPIO_MUXCFG + 1, val8); + + /* Set USB suspend enable local register 0xfe10[4]=1 */ + val8 = rtl8xxxu_read8(priv, 0xfe10); + val8 |= BIT(4); + rtl8xxxu_write8(priv, 0xfe10, val8); + + return 0; +} + +static int rtl8188eu_active_to_lps(struct rtl8xxxu_priv *priv) +{ + struct device *dev = &priv->udev->dev; + u8 val8; + u16 val16; + u32 val32; + int retry, retval; + + rtl8xxxu_write8(priv, REG_TXPAUSE, 0x7f); + + retry = 100; + retval = -EBUSY; + /* Poll 32 bit wide REG_SCH_TX_CMD for 0 to ensure no TX is pending. */ + do { + val32 = rtl8xxxu_read32(priv, REG_SCH_TX_CMD); + if (!val32) { + retval = 0; + break; + } + } while (retry--); + + if (!retry) { + dev_warn(dev, "Failed to flush TX queue\n"); + retval = -EBUSY; + goto out; + } + + /* Disable CCK and OFDM, clock gated */ + val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); + val8 &= ~SYS_FUNC_BBRSTB; + rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); + + udelay(2); + + /* Reset MAC TRX */ + val16 = rtl8xxxu_read16(priv, REG_CR); + val16 |= 0xff; + val16 &= ~(CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE | CR_SECURITY_ENABLE); + rtl8xxxu_write16(priv, REG_CR, val16); + + val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST); + val8 |= DUAL_TSF_TX_OK; + rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8); + +out: + return retval; +} + +static int rtl8188eu_power_on(struct rtl8xxxu_priv *priv) +{ + u16 val16; + int ret; + + rtl8188e_disabled_to_emu(priv); + + ret = rtl8188e_emu_to_active(priv); + if (ret) + goto exit; + + /* + * Enable MAC DMA/WMAC/SCHEDULE/SEC block + * Set CR bit10 to enable 32k calibration. + * We do not set CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE here + * due to a hardware bug in the 88E, requiring those to be + * set after REG_TRXFF_BNDY is set. If not the RXFF bundary + * will get set to a larger buffer size than the real buffer + * size. + */ + val16 = (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE | + CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | + CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE | + CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE); + rtl8xxxu_write16(priv, REG_CR, val16); + +exit: + return ret; +} + +static void rtl8188eu_power_off(struct rtl8xxxu_priv *priv) +{ + u8 val8; + u16 val16; + + rtl8xxxu_flush_fifo(priv); + + val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL); + val8 &= ~TX_REPORT_CTRL_TIMER_ENABLE; + rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8); + + /* Turn off RF */ + rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00); + + rtl8188eu_active_to_lps(priv); + + /* Reset Firmware if running in RAM */ + if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL) + rtl8xxxu_firmware_self_reset(priv); + + /* Reset MCU */ + val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); + val16 &= ~SYS_FUNC_CPU_ENABLE; + rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); + + /* Reset MCU ready status */ + rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00); + + /* 32K_CTRL looks to be very 8188e specific */ + val8 = rtl8xxxu_read8(priv, REG_32K_CTRL); + val8 &= ~BIT(0); + rtl8xxxu_write8(priv, REG_32K_CTRL, val8); + + rtl8188eu_active_to_emu(priv); + rtl8188eu_emu_to_disabled(priv); + + /* Reset MCU IO Wrapper */ + val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); + val8 &= ~BIT(3); + rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); + + val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); + val8 |= BIT(3); + rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); + + /* Vendor driver refers to GPIO_IN */ + val8 = rtl8xxxu_read8(priv, REG_GPIO_PIN_CTRL); + /* Vendor driver refers to GPIO_OUT */ + rtl8xxxu_write8(priv, REG_GPIO_PIN_CTRL + 1, val8); + rtl8xxxu_write8(priv, REG_GPIO_PIN_CTRL + 2, 0xff); + + val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL); + rtl8xxxu_write8(priv, REG_GPIO_IO_SEL, val8 << 4); + val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL + 1); + rtl8xxxu_write8(priv, REG_GPIO_IO_SEL + 1, val8 | 0x0f); + + /* + * Set LNA, TRSW, EX_PA Pin to output mode + * Referred to as REG_BB_PAD_CTRL in 8188eu vendor driver + */ + rtl8xxxu_write32(priv, REG_PAD_CTRL1, 0x00080808); + + rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x00); + + rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, 0x00000000); +} + +static void rtl8188e_enable_rf(struct rtl8xxxu_priv *priv) +{ + u32 val32; + + rtl8xxxu_write8(priv, REG_RF_CTRL, RF_ENABLE | RF_RSTB | RF_SDMRSTB); + + val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); + val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK); + val32 |= OFDM_RF_PATH_RX_A | OFDM_RF_PATH_TX_A; + rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); + + rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); +} + +static void rtl8188e_disable_rf(struct rtl8xxxu_priv *priv) +{ + u32 val32; + + val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); + val32 &= ~OFDM_RF_PATH_TX_MASK; + rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); + + /* Power down RF module */ + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0); + + rtl8188eu_active_to_emu(priv); +} + +static void rtl8188e_usb_quirks(struct rtl8xxxu_priv *priv) +{ + u16 val16; + + /* + * Technically this is not a USB quirk, but a chip quirk. + * This has to be done after REG_TRXFF_BNDY is set, see + * rtl8188eu_power_on() for details. + */ + val16 = rtl8xxxu_read16(priv, REG_CR); + val16 |= (CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE); + rtl8xxxu_write16(priv, REG_CR, val16); + + rtl8xxxu_gen2_usb_quirks(priv); + + /* Pre-TX enable WEP/TKIP security */ + rtl8xxxu_write8(priv, REG_EARLY_MODE_CONTROL_8188E + 3, 0x01); +} + +static s8 rtl8188e_cck_rssi(struct rtl8xxxu_priv *priv, struct rtl8723au_phy_stats *phy_stats) +{ + /* only use lna 0/1/2/3/7 */ + static const s8 lna_gain_table_0[8] = {17, -1, -13, -29, -32, -35, -38, -41}; + /* only use lna 3/7 */ + static const s8 lna_gain_table_1[8] = {29, 20, 12, 3, -6, -15, -24, -33}; + + u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a; + s8 rx_pwr_all = 0x00; + u8 vga_idx, lna_idx; + s8 lna_gain = 0; + + lna_idx = u8_get_bits(cck_agc_rpt, CCK_AGC_RPT_LNA_IDX_MASK); + vga_idx = u8_get_bits(cck_agc_rpt, CCK_AGC_RPT_VGA_IDX_MASK); + + if (priv->chip_cut >= 8) /* cut I */ /* SMIC */ + lna_gain = lna_gain_table_0[lna_idx]; + else /* TSMC */ + lna_gain = lna_gain_table_1[lna_idx]; + + rx_pwr_all = lna_gain - (2 * vga_idx); + + return rx_pwr_all; +} + +static int rtl8188eu_led_brightness_set(struct led_classdev *led_cdev, + enum led_brightness brightness) +{ + struct rtl8xxxu_priv *priv = container_of(led_cdev, + struct rtl8xxxu_priv, + led_cdev); + u8 ledcfg = rtl8xxxu_read8(priv, REG_LEDCFG2); + + if (brightness == LED_OFF) { + ledcfg &= ~LEDCFG2_HW_LED_CONTROL; + ledcfg |= LEDCFG2_SW_LED_CONTROL | LEDCFG2_SW_LED_DISABLE; + } else if (brightness == LED_ON) { + ledcfg &= ~(LEDCFG2_HW_LED_CONTROL | LEDCFG2_SW_LED_DISABLE); + ledcfg |= LEDCFG2_SW_LED_CONTROL; + } else if (brightness == RTL8XXXU_HW_LED_CONTROL) { + ledcfg &= ~LEDCFG2_SW_LED_DISABLE; + ledcfg |= LEDCFG2_HW_LED_CONTROL | LEDCFG2_HW_LED_ENABLE; + } + + rtl8xxxu_write8(priv, REG_LEDCFG2, ledcfg); + + return 0; +} + +static void rtl8188e_set_tx_rpt_timing(struct rtl8xxxu_ra_info *ra, u8 timing) +{ + u8 idx; + + for (idx = 0; idx < 5; idx++) + if (dynamic_tx_rpt_timing[idx] == ra->rpt_time) + break; + + if (timing == DEFAULT_TIMING) { + idx = 0; /* 200ms */ + } else if (timing == INCREASE_TIMING) { + if (idx < 5) + idx++; + } else if (timing == DECREASE_TIMING) { + if (idx > 0) + idx--; + } + + ra->rpt_time = dynamic_tx_rpt_timing[idx]; +} + +static void rtl8188e_rate_down(struct rtl8xxxu_ra_info *ra) +{ + u8 rate_id = ra->pre_rate; + u8 lowest_rate = ra->lowest_rate; + u8 highest_rate = ra->highest_rate; + s8 i; + + if (rate_id > highest_rate) { + rate_id = highest_rate; + } else if (ra->rate_sgi) { + ra->rate_sgi = 0; + } else if (rate_id > lowest_rate) { + if (rate_id > 0) { + for (i = rate_id - 1; i >= lowest_rate; i--) { + if (ra->ra_use_rate & BIT(i)) { + rate_id = i; + goto rate_down_finish; + } + } + } + } else if (rate_id <= lowest_rate) { + rate_id = lowest_rate; + } + +rate_down_finish: + if (ra->ra_waiting_counter == 1) { + ra->ra_waiting_counter++; + ra->ra_pending_counter++; + } else if (ra->ra_waiting_counter > 1) { + ra->ra_waiting_counter = 0; + ra->ra_pending_counter = 0; + } + + if (ra->ra_pending_counter >= 4) + ra->ra_pending_counter = 4; + + ra->ra_drop_after_down = 1; + + ra->decision_rate = rate_id; + + rtl8188e_set_tx_rpt_timing(ra, DECREASE_TIMING); +} + +static void rtl8188e_rate_up(struct rtl8xxxu_ra_info *ra) +{ + u8 rate_id = ra->pre_rate; + u8 highest_rate = ra->highest_rate; + u8 i; + + if (ra->ra_waiting_counter == 1) { + ra->ra_waiting_counter = 0; + ra->ra_pending_counter = 0; + } else if (ra->ra_waiting_counter > 1) { + ra->pre_rssi_sta_ra = ra->rssi_sta_ra; + goto rate_up_finish; + } + + rtl8188e_set_tx_rpt_timing(ra, DEFAULT_TIMING); + + if (rate_id < highest_rate) { + for (i = rate_id + 1; i <= highest_rate; i++) { + if (ra->ra_use_rate & BIT(i)) { + rate_id = i; + goto rate_up_finish; + } + } + } else if (rate_id == highest_rate) { + if (ra->sgi_enable && !ra->rate_sgi) + ra->rate_sgi = 1; + else if (!ra->sgi_enable) + ra->rate_sgi = 0; + } else { /* rate_id > ra->highest_rate */ + rate_id = highest_rate; + } + +rate_up_finish: + if (ra->ra_waiting_counter == (4 + pending_for_rate_up_fail[ra->ra_pending_counter])) + ra->ra_waiting_counter = 0; + else + ra->ra_waiting_counter++; + + ra->decision_rate = rate_id; +} + +static void rtl8188e_reset_ra_counter(struct rtl8xxxu_ra_info *ra) +{ + u8 rate_id = ra->decision_rate; + + ra->nsc_up = (n_threshold_high[rate_id] + n_threshold_low[rate_id]) >> 1; + ra->nsc_down = (n_threshold_high[rate_id] + n_threshold_low[rate_id]) >> 1; +} + +static void rtl8188e_rate_decision(struct rtl8xxxu_ra_info *ra) +{ + struct rtl8xxxu_priv *priv = container_of(ra, struct rtl8xxxu_priv, ra_info); + const u8 *retry_penalty_idx_0; + const u8 *retry_penalty_idx_1; + const u8 *retry_penalty_up_idx; + u8 rate_id, penalty_id1, penalty_id2; + int i; + + if (ra->total == 0) + return; + + if (ra->ra_drop_after_down) { + ra->ra_drop_after_down--; + + rtl8188e_reset_ra_counter(ra); + + return; + } + + if (priv->chip_cut == 8) { /* cut I */ + retry_penalty_idx_0 = retry_penalty_idx_cut_i[0]; + retry_penalty_idx_1 = retry_penalty_idx_cut_i[1]; + retry_penalty_up_idx = retry_penalty_up_idx_cut_i; + } else { + retry_penalty_idx_0 = retry_penalty_idx_normal[0]; + retry_penalty_idx_1 = retry_penalty_idx_normal[1]; + retry_penalty_up_idx = retry_penalty_up_idx_normal; + } + + if (ra->rssi_sta_ra < (ra->pre_rssi_sta_ra - 3) || + ra->rssi_sta_ra > (ra->pre_rssi_sta_ra + 3)) { + ra->pre_rssi_sta_ra = ra->rssi_sta_ra; + ra->ra_waiting_counter = 0; + ra->ra_pending_counter = 0; + } + + /* Start RA decision */ + if (ra->pre_rate > ra->highest_rate) + rate_id = ra->highest_rate; + else + rate_id = ra->pre_rate; + + /* rate down */ + if (ra->rssi_sta_ra > rssi_threshold[rate_id]) + penalty_id1 = retry_penalty_idx_0[rate_id]; + else + penalty_id1 = retry_penalty_idx_1[rate_id]; + + for (i = 0; i < 5; i++) + ra->nsc_down += ra->retry[i] * retry_penalty[penalty_id1][i]; + + if (ra->nsc_down > (ra->total * retry_penalty[penalty_id1][5])) + ra->nsc_down -= ra->total * retry_penalty[penalty_id1][5]; + else + ra->nsc_down = 0; + + /* rate up */ + penalty_id2 = retry_penalty_up_idx[rate_id]; + + for (i = 0; i < 5; i++) + ra->nsc_up += ra->retry[i] * retry_penalty[penalty_id2][i]; + + if (ra->nsc_up > (ra->total * retry_penalty[penalty_id2][5])) + ra->nsc_up -= ra->total * retry_penalty[penalty_id2][5]; + else + ra->nsc_up = 0; + + if (ra->nsc_down < n_threshold_low[rate_id] || + ra->drop > dropping_necessary[rate_id]) { + rtl8188e_rate_down(ra); + + rtl8xxxu_update_ra_report(&priv->ra_report, ra->decision_rate, + ra->rate_sgi, priv->ra_report.txrate.bw); + } else if (ra->nsc_up > n_threshold_high[rate_id]) { + rtl8188e_rate_up(ra); + + rtl8xxxu_update_ra_report(&priv->ra_report, ra->decision_rate, + ra->rate_sgi, priv->ra_report.txrate.bw); + } + + if (ra->decision_rate == ra->pre_rate) + ra->dynamic_tx_rpt_timing_counter++; + else + ra->dynamic_tx_rpt_timing_counter = 0; + + if (ra->dynamic_tx_rpt_timing_counter >= 4) { + /* Rate didn't change 4 times, extend RPT timing */ + rtl8188e_set_tx_rpt_timing(ra, INCREASE_TIMING); + ra->dynamic_tx_rpt_timing_counter = 0; + } + + ra->pre_rate = ra->decision_rate; + + rtl8188e_reset_ra_counter(ra); +} + +static void rtl8188e_power_training_try_state(struct rtl8xxxu_ra_info *ra) +{ + ra->pt_try_state = 0; + switch (ra->pt_mode_ss) { + case 3: + if (ra->decision_rate >= DESC_RATE_MCS13) + ra->pt_try_state = 1; + break; + case 2: + if (ra->decision_rate >= DESC_RATE_MCS5) + ra->pt_try_state = 1; + break; + case 1: + if (ra->decision_rate >= DESC_RATE_48M) + ra->pt_try_state = 1; + break; + case 0: + if (ra->decision_rate >= DESC_RATE_11M) + ra->pt_try_state = 1; + break; + default: + break; + } + + if (ra->rssi_sta_ra < 48) { + ra->pt_stage = 0; + } else if (ra->pt_try_state == 1) { + if ((ra->pt_stop_count >= 10) || + (ra->pt_pre_rssi > ra->rssi_sta_ra + 5) || + (ra->pt_pre_rssi < ra->rssi_sta_ra - 5) || + (ra->decision_rate != ra->pt_pre_rate)) { + if (ra->pt_stage == 0) + ra->pt_stage = 1; + else if (ra->pt_stage == 1) + ra->pt_stage = 3; + else + ra->pt_stage = 5; + + ra->pt_pre_rssi = ra->rssi_sta_ra; + ra->pt_stop_count = 0; + } else { + ra->ra_stage = 0; + ra->pt_stop_count++; + } + } else { + ra->pt_stage = 0; + ra->ra_stage = 0; + } + + ra->pt_pre_rate = ra->decision_rate; + + /* TODO: implement the "false alarm" statistics for this */ + /* Disable power training when noisy environment */ + /* if (p_dm_odm->is_disable_power_training) { */ + if (1) { + ra->pt_stage = 0; + ra->ra_stage = 0; + ra->pt_stop_count = 0; + } +} + +static void rtl8188e_power_training_decision(struct rtl8xxxu_ra_info *ra) +{ + u8 temp_stage; + u32 numsc; + u32 num_total; + u8 stage_id; + u8 j; + + numsc = 0; + num_total = ra->total * pt_penalty[5]; + for (j = 0; j <= 4; j++) { + numsc += ra->retry[j] * pt_penalty[j]; + + if (numsc > num_total) + break; + } + + j >>= 1; + temp_stage = (ra->pt_stage + 1) >> 1; + if (temp_stage > j) + stage_id = temp_stage - j; + else + stage_id = 0; + + ra->pt_smooth_factor = (ra->pt_smooth_factor >> 1) + + (ra->pt_smooth_factor >> 2) + + stage_id * 16 + 2; + if (ra->pt_smooth_factor > 192) + ra->pt_smooth_factor = 192; + stage_id = ra->pt_smooth_factor >> 6; + temp_stage = stage_id * 2; + if (temp_stage != 0) + temp_stage--; + if (ra->drop > 3) + temp_stage = 0; + ra->pt_stage = temp_stage; +} + +void rtl8188e_handle_ra_tx_report2(struct rtl8xxxu_priv *priv, struct sk_buff *skb) +{ + u32 *_rx_desc = (u32 *)(skb->data - sizeof(struct rtl8xxxu_rxdesc16)); + struct rtl8xxxu_rxdesc16 *rx_desc = (struct rtl8xxxu_rxdesc16 *)_rx_desc; + struct device *dev = &priv->udev->dev; + struct rtl8xxxu_ra_info *ra = &priv->ra_info; + u32 tx_rpt_len = rx_desc->pktlen & 0x3ff; + u32 items = tx_rpt_len / TX_RPT2_ITEM_SIZE; + u64 macid_valid = ((u64)_rx_desc[5] << 32) | _rx_desc[4]; + u32 macid; + u8 *rpt = skb->data; + bool valid; + u16 min_rpt_time = 0x927c; + + dev_dbg(dev, "%s: len: %d items: %d\n", __func__, tx_rpt_len, items); + + /* We only use macid 0, so only the first item is relevant. + * AP mode will use more of them if it's ever implemented. + */ + if (!priv->vifs[0] || priv->vifs[0]->type == NL80211_IFTYPE_STATION) + items = 1; + + for (macid = 0; macid < items; macid++) { + valid = false; + + if (macid < 64) + valid = macid_valid & BIT(macid); + + if (valid) { + ra->retry[0] = le16_to_cpu(*(__le16 *)rpt); + ra->retry[1] = rpt[2]; + ra->retry[2] = rpt[3]; + ra->retry[3] = rpt[4]; + ra->retry[4] = rpt[5]; + ra->drop = rpt[6]; + ra->total = ra->retry[0] + ra->retry[1] + ra->retry[2] + + ra->retry[3] + ra->retry[4] + ra->drop; + + if (ra->total > 0) { + if (ra->ra_stage < 5) + rtl8188e_rate_decision(ra); + else if (ra->ra_stage == 5) + rtl8188e_power_training_try_state(ra); + else /* ra->ra_stage == 6 */ + rtl8188e_power_training_decision(ra); + + if (ra->ra_stage <= 5) + ra->ra_stage++; + else + ra->ra_stage = 0; + } + } else if (macid == 0) { + dev_warn(dev, "%s: TX report item 0 not valid\n", __func__); + } + + dev_dbg(dev, "%s: valid: %d retry: %d %d %d %d %d drop: %d\n", + __func__, valid, + ra->retry[0], ra->retry[1], ra->retry[2], + ra->retry[3], ra->retry[4], ra->drop); + + if (min_rpt_time > ra->rpt_time) + min_rpt_time = ra->rpt_time; + + rpt += TX_RPT2_ITEM_SIZE; + } + + if (min_rpt_time != ra->pre_min_rpt_time) { + rtl8xxxu_write16(priv, REG_TX_REPORT_TIME, min_rpt_time); + ra->pre_min_rpt_time = min_rpt_time; + } +} + +static void rtl8188e_arfb_refresh(struct rtl8xxxu_ra_info *ra) +{ + s8 i; + + ra->ra_use_rate = ra->rate_mask; + + /* Highest rate */ + if (ra->ra_use_rate) { + for (i = RATESIZE; i >= 0; i--) { + if (ra->ra_use_rate & BIT(i)) { + ra->highest_rate = i; + break; + } + } + } else { + ra->highest_rate = 0; + } + + /* Lowest rate */ + if (ra->ra_use_rate) { + for (i = 0; i < RATESIZE; i++) { + if (ra->ra_use_rate & BIT(i)) { + ra->lowest_rate = i; + break; + } + } + } else { + ra->lowest_rate = 0; + } + + if (ra->highest_rate > DESC_RATE_MCS7) + ra->pt_mode_ss = 3; + else if (ra->highest_rate > DESC_RATE_54M) + ra->pt_mode_ss = 2; + else if (ra->highest_rate > DESC_RATE_11M) + ra->pt_mode_ss = 1; + else + ra->pt_mode_ss = 0; +} + +static void +rtl8188e_update_rate_mask(struct rtl8xxxu_priv *priv, + u32 ramask, u8 rateid, int sgi, int txbw_40mhz, + u8 macid) +{ + struct rtl8xxxu_ra_info *ra = &priv->ra_info; + + ra->rate_id = rateid; + ra->rate_mask = ramask; + ra->sgi_enable = sgi; + + rtl8188e_arfb_refresh(ra); +} + +static void rtl8188e_ra_set_rssi(struct rtl8xxxu_priv *priv, u8 macid, u8 rssi) +{ + priv->ra_info.rssi_sta_ra = rssi; +} + +void rtl8188e_ra_info_init_all(struct rtl8xxxu_ra_info *ra) +{ + ra->decision_rate = DESC_RATE_MCS7; + ra->pre_rate = DESC_RATE_MCS7; + ra->highest_rate = DESC_RATE_MCS7; + ra->lowest_rate = 0; + ra->rate_id = 0; + ra->rate_mask = 0xfffff; + ra->rssi_sta_ra = 0; + ra->pre_rssi_sta_ra = 0; + ra->sgi_enable = 0; + ra->ra_use_rate = 0xfffff; + ra->nsc_down = (n_threshold_high[DESC_RATE_MCS7] + n_threshold_low[DESC_RATE_MCS7]) / 2; + ra->nsc_up = (n_threshold_high[DESC_RATE_MCS7] + n_threshold_low[DESC_RATE_MCS7]) / 2; + ra->rate_sgi = 0; + ra->rpt_time = 0x927c; + ra->drop = 0; + ra->retry[0] = 0; + ra->retry[1] = 0; + ra->retry[2] = 0; + ra->retry[3] = 0; + ra->retry[4] = 0; + ra->total = 0; + ra->ra_waiting_counter = 0; + ra->ra_pending_counter = 0; + ra->ra_drop_after_down = 0; + + ra->pt_try_state = 0; + ra->pt_stage = 5; + ra->pt_smooth_factor = 192; + ra->pt_stop_count = 0; + ra->pt_pre_rate = 0; + ra->pt_pre_rssi = 0; + ra->pt_mode_ss = 0; + ra->ra_stage = 0; +} + +struct rtl8xxxu_fileops rtl8188eu_fops = { + .identify_chip = rtl8188eu_identify_chip, + .parse_efuse = rtl8188eu_parse_efuse, + .load_firmware = rtl8188eu_load_firmware, + .power_on = rtl8188eu_power_on, + .power_off = rtl8188eu_power_off, + .read_efuse = rtl8xxxu_read_efuse, + .reset_8051 = rtl8188eu_reset_8051, + .llt_init = rtl8xxxu_init_llt_table, + .init_phy_bb = rtl8188eu_init_phy_bb, + .init_phy_rf = rtl8188eu_init_phy_rf, + .phy_lc_calibrate = rtl8723a_phy_lc_calibrate, + .phy_iq_calibrate = rtl8188eu_phy_iq_calibrate, + .config_channel = rtl8188eu_config_channel, + .parse_rx_desc = rtl8xxxu_parse_rxdesc16, + .parse_phystats = rtl8723au_rx_parse_phystats, + .init_aggregation = rtl8188eu_init_aggregation, + .enable_rf = rtl8188e_enable_rf, + .disable_rf = rtl8188e_disable_rf, + .usb_quirks = rtl8188e_usb_quirks, + .set_tx_power = rtl8188f_set_tx_power, + .update_rate_mask = rtl8188e_update_rate_mask, + .report_connect = rtl8xxxu_gen2_report_connect, + .report_rssi = rtl8188e_ra_set_rssi, + .fill_txdesc = rtl8xxxu_fill_txdesc_v3, + .set_crystal_cap = rtl8188f_set_crystal_cap, + .cck_rssi = rtl8188e_cck_rssi, + .led_classdev_brightness_set = rtl8188eu_led_brightness_set, + .writeN_block_size = 128, + .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc16), + .tx_desc_size = sizeof(struct rtl8xxxu_txdesc32), + .has_tx_report = 1, + .init_reg_pkt_life_time = 1, + .gen2_thermal_meter = 1, + .max_sec_cam_num = 32, + .adda_1t_init = 0x0b1b25a0, + .adda_1t_path_on = 0x0bdb25a0, + /* + * Use 9K for 8188e normal chip + * Max RX buffer = 10K - max(TxReportSize(64*8), WOLPattern(16*24)) + */ + .trxff_boundary = 0x25ff, + .pbp_rx = PBP_PAGE_SIZE_128, + .pbp_tx = PBP_PAGE_SIZE_128, + .mactable = rtl8188e_mac_init_table, + .total_page_num = TX_TOTAL_PAGE_NUM_8188E, + .page_num_hi = TX_PAGE_NUM_HI_PQ_8188E, + .page_num_lo = TX_PAGE_NUM_LO_PQ_8188E, + .page_num_norm = TX_PAGE_NUM_NORM_PQ_8188E, + .last_llt_entry = 175, +}; diff --git a/drivers/net/wireless/realtek/rtl8xxxu/8188f.c b/drivers/net/wireless/realtek/rtl8xxxu/8188f.c new file mode 100644 index 000000000000..296370414134 --- /dev/null +++ b/drivers/net/wireless/realtek/rtl8xxxu/8188f.c @@ -0,0 +1,1762 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * RTL8XXXU mac80211 USB driver - 8188f specific subdriver + * + * Copyright (c) 2022 Bitterblue Smith + * + * Portions copied from existing rtl8xxxu code: + * Copyright (c) 2014 - 2017 Jes Sorensen + * + * Portions, notably calibration code: + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "rtl8xxxu.h" +#include "regs.h" + +static const struct rtl8xxxu_reg8val rtl8188f_mac_init_table[] = { + {0x024, 0xDF}, {0x025, 0x07}, {0x02B, 0x1C}, {0x283, 0x20}, + {0x421, 0x0F}, {0x428, 0x0A}, {0x429, 0x10}, {0x430, 0x00}, + {0x431, 0x00}, {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, + {0x435, 0x05}, {0x436, 0x07}, {0x437, 0x08}, {0x43C, 0x04}, + {0x43D, 0x05}, {0x43E, 0x07}, {0x43F, 0x08}, {0x440, 0x5D}, + {0x441, 0x01}, {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, + {0x446, 0x00}, {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xF0}, + {0x44A, 0x0F}, {0x44B, 0x3E}, {0x44C, 0x10}, {0x44D, 0x00}, + {0x44E, 0x00}, {0x44F, 0x00}, {0x450, 0x00}, {0x451, 0xF0}, + {0x452, 0x0F}, {0x453, 0x00}, {0x456, 0x5E}, {0x460, 0x44}, + {0x461, 0x44}, {0x4BC, 0xC0}, {0x4C8, 0xFF}, {0x4C9, 0x08}, + {0x4CC, 0xFF}, {0x4CD, 0xFF}, {0x4CE, 0x01}, {0x500, 0x26}, + {0x501, 0xA2}, {0x502, 0x2F}, {0x503, 0x00}, {0x504, 0x28}, + {0x505, 0xA3}, {0x506, 0x5E}, {0x507, 0x00}, {0x508, 0x2B}, + {0x509, 0xA4}, {0x50A, 0x5E}, {0x50B, 0x00}, {0x50C, 0x4F}, + {0x50D, 0xA4}, {0x50E, 0x00}, {0x50F, 0x00}, {0x512, 0x1C}, + {0x514, 0x0A}, {0x516, 0x0A}, {0x525, 0x4F}, {0x550, 0x10}, + {0x551, 0x10}, {0x559, 0x02}, {0x55C, 0x28}, {0x55D, 0xFF}, + {0x605, 0x30}, {0x608, 0x0E}, {0x609, 0x2A}, {0x620, 0xFF}, + {0x621, 0xFF}, {0x622, 0xFF}, {0x623, 0xFF}, {0x624, 0xFF}, + {0x625, 0xFF}, {0x626, 0xFF}, {0x627, 0xFF}, {0x638, 0x28}, + {0x63C, 0x0A}, {0x63D, 0x0A}, {0x63E, 0x0E}, {0x63F, 0x0E}, + {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00}, {0x652, 0xC8}, + {0x66E, 0x05}, {0x700, 0x21}, {0x701, 0x43}, {0x702, 0x65}, + {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43}, {0x70A, 0x65}, + {0x70B, 0x87}, + {0xffff, 0xff}, +}; + +static const struct rtl8xxxu_reg32val rtl8188fu_phy_init_table[] = { + {0x800, 0x80045700}, {0x804, 0x00000001}, + {0x808, 0x0000FC00}, {0x80C, 0x0000000A}, + {0x810, 0x10001331}, {0x814, 0x020C3D10}, + {0x818, 0x00200385}, {0x81C, 0x00000000}, + {0x820, 0x01000100}, {0x824, 0x00390204}, + {0x828, 0x00000000}, {0x82C, 0x00000000}, + {0x830, 0x00000000}, {0x834, 0x00000000}, + {0x838, 0x00000000}, {0x83C, 0x00000000}, + {0x840, 0x00010000}, {0x844, 0x00000000}, + {0x848, 0x00000000}, {0x84C, 0x00000000}, + {0x850, 0x00030000}, {0x854, 0x00000000}, + {0x858, 0x569A569A}, {0x85C, 0x569A569A}, + {0x860, 0x00000130}, {0x864, 0x00000000}, + {0x868, 0x00000000}, {0x86C, 0x27272700}, + {0x870, 0x00000000}, {0x874, 0x25004000}, + {0x878, 0x00000808}, {0x87C, 0x004F0201}, + {0x880, 0xB0000B1E}, {0x884, 0x00000007}, + {0x888, 0x00000000}, {0x88C, 0xCCC000C0}, + {0x890, 0x00000800}, {0x894, 0xFFFFFFFE}, + {0x898, 0x40302010}, {0x89C, 0x00706050}, + {0x900, 0x00000000}, {0x904, 0x00000023}, + {0x908, 0x00000000}, {0x90C, 0x81121111}, + {0x910, 0x00000002}, {0x914, 0x00000201}, + {0x948, 0x99000000}, {0x94C, 0x00000010}, + {0x950, 0x20003000}, {0x954, 0x4A880000}, + {0x958, 0x4BC5D87A}, {0x95C, 0x04EB9B79}, + {0x96C, 0x00000003}, {0xA00, 0x00D047C8}, + {0xA04, 0x80FF800C}, {0xA08, 0x8C898300}, + {0xA0C, 0x2E7F120F}, {0xA10, 0x9500BB78}, + {0xA14, 0x1114D028}, {0xA18, 0x00881117}, + {0xA1C, 0x89140F00}, {0xA20, 0xD1D80000}, + {0xA24, 0x5A7DA0BD}, {0xA28, 0x0000223B}, + {0xA2C, 0x00D30000}, {0xA70, 0x101FBF00}, + {0xA74, 0x00000007}, {0xA78, 0x00000900}, + {0xA7C, 0x225B0606}, {0xA80, 0x218075B1}, + {0xA84, 0x00120000}, {0xA88, 0x040C0000}, + {0xA8C, 0x12345678}, {0xA90, 0xABCDEF00}, + {0xA94, 0x001B1B89}, {0xA98, 0x05100000}, + {0xA9C, 0x3F000000}, {0xAA0, 0x00000000}, + {0xB2C, 0x00000000}, {0xC00, 0x48071D40}, + {0xC04, 0x03A05611}, {0xC08, 0x000000E4}, + {0xC0C, 0x6C6C6C6C}, {0xC10, 0x18800000}, + {0xC14, 0x40000100}, {0xC18, 0x08800000}, + {0xC1C, 0x40000100}, {0xC20, 0x00000000}, + {0xC24, 0x00000000}, {0xC28, 0x00000000}, + {0xC2C, 0x00000000}, {0xC30, 0x69E9CC4A}, + {0xC34, 0x31000040}, {0xC38, 0x21688080}, + {0xC3C, 0x00001714}, {0xC40, 0x1F78403F}, + {0xC44, 0x00010036}, {0xC48, 0xEC020107}, + {0xC4C, 0x007F037F}, {0xC50, 0x69553420}, + {0xC54, 0x43BC0094}, {0xC58, 0x00013169}, + {0xC5C, 0x00250492}, {0xC60, 0x00000000}, + {0xC64, 0x7112848B}, {0xC68, 0x47C07BFF}, + {0xC6C, 0x00000036}, {0xC70, 0x2C7F000D}, + {0xC74, 0x020600DB}, {0xC78, 0x0000001F}, + {0xC7C, 0x00B91612}, {0xC80, 0x390000E4}, + {0xC84, 0x11F60000}, + {0xC88, 0x40000100}, {0xC8C, 0x20200000}, + {0xC90, 0x00091521}, {0xC94, 0x00000000}, + {0xC98, 0x00121820}, {0xC9C, 0x00007F7F}, + {0xCA0, 0x00000000}, {0xCA4, 0x000300A0}, + {0xCA8, 0x00000000}, {0xCAC, 0x00000000}, + {0xCB0, 0x00000000}, {0xCB4, 0x00000000}, + {0xCB8, 0x00000000}, {0xCBC, 0x28000000}, + {0xCC0, 0x00000000}, {0xCC4, 0x00000000}, + {0xCC8, 0x00000000}, {0xCCC, 0x00000000}, + {0xCD0, 0x00000000}, {0xCD4, 0x00000000}, + {0xCD8, 0x64B22427}, {0xCDC, 0x00766932}, + {0xCE0, 0x00222222}, {0xCE4, 0x10000000}, + {0xCE8, 0x37644302}, {0xCEC, 0x2F97D40C}, + {0xD00, 0x04030740}, {0xD04, 0x40020401}, + {0xD08, 0x0000907F}, {0xD0C, 0x20010201}, + {0xD10, 0xA0633333}, {0xD14, 0x3333BC53}, + {0xD18, 0x7A8F5B6F}, {0xD2C, 0xCB979975}, + {0xD30, 0x00000000}, {0xD34, 0x80608000}, + {0xD38, 0x98000000}, {0xD3C, 0x40127353}, + {0xD40, 0x00000000}, {0xD44, 0x00000000}, + {0xD48, 0x00000000}, {0xD4C, 0x00000000}, + {0xD50, 0x6437140A}, {0xD54, 0x00000000}, + {0xD58, 0x00000282}, {0xD5C, 0x30032064}, + {0xD60, 0x4653DE68}, {0xD64, 0x04518A3C}, + {0xD68, 0x00002101}, {0xD6C, 0x2A201C16}, + {0xD70, 0x1812362E}, {0xD74, 0x322C2220}, + {0xD78, 0x000E3C24}, {0xE00, 0x2D2D2D2D}, + {0xE04, 0x2D2D2D2D}, {0xE08, 0x0390272D}, + {0xE10, 0x2D2D2D2D}, {0xE14, 0x2D2D2D2D}, + {0xE18, 0x2D2D2D2D}, {0xE1C, 0x2D2D2D2D}, + {0xE28, 0x00000000}, {0xE30, 0x1000DC1F}, + {0xE34, 0x10008C1F}, {0xE38, 0x02140102}, + {0xE3C, 0x681604C2}, {0xE40, 0x01007C00}, + {0xE44, 0x01004800}, {0xE48, 0xFB000000}, + {0xE4C, 0x000028D1}, {0xE50, 0x1000DC1F}, + {0xE54, 0x10008C1F}, {0xE58, 0x02140102}, + {0xE5C, 0x28160D05}, {0xE60, 0x00000008}, + {0xE60, 0x021400A0}, {0xE64, 0x281600A0}, + {0xE6C, 0x01C00010}, {0xE70, 0x01C00010}, + {0xE74, 0x02000010}, {0xE78, 0x02000010}, + {0xE7C, 0x02000010}, {0xE80, 0x02000010}, + {0xE84, 0x01C00010}, {0xE88, 0x02000010}, + {0xE8C, 0x01C00010}, {0xED0, 0x01C00010}, + {0xED4, 0x01C00010}, {0xED8, 0x01C00010}, + {0xEDC, 0x00000010}, {0xEE0, 0x00000010}, + {0xEEC, 0x03C00010}, {0xF14, 0x00000003}, + {0xF4C, 0x00000000}, {0xF00, 0x00000300}, + {0xffff, 0xffffffff}, +}; + +static const struct rtl8xxxu_reg32val rtl8188f_agc_table[] = { + {0xC78, 0xFC000001}, {0xC78, 0xFB010001}, + {0xC78, 0xFA020001}, {0xC78, 0xF9030001}, + {0xC78, 0xF8040001}, {0xC78, 0xF7050001}, + {0xC78, 0xF6060001}, {0xC78, 0xF5070001}, + {0xC78, 0xF4080001}, {0xC78, 0xF3090001}, + {0xC78, 0xF20A0001}, {0xC78, 0xF10B0001}, + {0xC78, 0xF00C0001}, {0xC78, 0xEF0D0001}, + {0xC78, 0xEE0E0001}, {0xC78, 0xED0F0001}, + {0xC78, 0xEC100001}, {0xC78, 0xEB110001}, + {0xC78, 0xEA120001}, {0xC78, 0xE9130001}, + {0xC78, 0xE8140001}, {0xC78, 0xE7150001}, + {0xC78, 0xE6160001}, {0xC78, 0xE5170001}, + {0xC78, 0xE4180001}, {0xC78, 0xE3190001}, + {0xC78, 0xE21A0001}, {0xC78, 0xE11B0001}, + {0xC78, 0xE01C0001}, {0xC78, 0xC21D0001}, + {0xC78, 0xC11E0001}, {0xC78, 0xC01F0001}, + {0xC78, 0xA5200001}, {0xC78, 0xA4210001}, + {0xC78, 0xA3220001}, {0xC78, 0xA2230001}, + {0xC78, 0xA1240001}, {0xC78, 0xA0250001}, + {0xC78, 0x65260001}, {0xC78, 0x64270001}, + {0xC78, 0x63280001}, {0xC78, 0x62290001}, + {0xC78, 0x612A0001}, {0xC78, 0x442B0001}, + {0xC78, 0x432C0001}, {0xC78, 0x422D0001}, + {0xC78, 0x412E0001}, {0xC78, 0x402F0001}, + {0xC78, 0x21300001}, {0xC78, 0x20310001}, + {0xC78, 0x05320001}, {0xC78, 0x04330001}, + {0xC78, 0x03340001}, {0xC78, 0x02350001}, + {0xC78, 0x01360001}, {0xC78, 0x00370001}, + {0xC78, 0x00380001}, {0xC78, 0x00390001}, + {0xC78, 0x003A0001}, {0xC78, 0x003B0001}, + {0xC78, 0x003C0001}, {0xC78, 0x003D0001}, + {0xC78, 0x003E0001}, {0xC78, 0x003F0001}, + {0xC50, 0x69553422}, {0xC50, 0x69553420}, + {0xffff, 0xffffffff} +}; + +static const struct rtl8xxxu_rfregval rtl8188fu_radioa_init_table[] = { + {0x00, 0x00030000}, {0x08, 0x00008400}, + {0x18, 0x00000407}, {0x19, 0x00000012}, + {0x1B, 0x00001C6C}, + {0x1E, 0x00080009}, {0x1F, 0x00000880}, + {0x2F, 0x0001A060}, {0x3F, 0x00028000}, + {0x42, 0x000060C0}, {0x57, 0x000D0000}, + {0x58, 0x000C0160}, {0x67, 0x00001552}, + {0x83, 0x00000000}, {0xB0, 0x000FF9F0}, + {0xB1, 0x00022218}, {0xB2, 0x00034C00}, + {0xB4, 0x0004484B}, {0xB5, 0x0000112A}, + {0xB6, 0x0000053E}, {0xB7, 0x00010408}, + {0xB8, 0x00010200}, {0xB9, 0x00080001}, + {0xBA, 0x00040001}, {0xBB, 0x00000400}, + {0xBF, 0x000C0000}, {0xC2, 0x00002400}, + {0xC3, 0x00000009}, {0xC4, 0x00040C91}, + {0xC5, 0x00099999}, {0xC6, 0x000000A3}, + {0xC7, 0x0008F820}, {0xC8, 0x00076C06}, + {0xC9, 0x00000000}, {0xCA, 0x00080000}, + {0xDF, 0x00000180}, {0xEF, 0x000001A0}, + {0x51, 0x000E8333}, {0x52, 0x000FAC2C}, + {0x53, 0x00000103}, {0x56, 0x000517F0}, + {0x35, 0x00000099}, {0x35, 0x00000199}, + {0x35, 0x00000299}, {0x36, 0x00000064}, + {0x36, 0x00008064}, {0x36, 0x00010064}, + {0x36, 0x00018064}, {0x18, 0x00000C07}, + {0x5A, 0x00048000}, {0x19, 0x000739D0}, + {0x34, 0x0000ADD6}, {0x34, 0x00009DD3}, + {0x34, 0x00008CF4}, {0x34, 0x00007CF1}, + {0x34, 0x00006CEE}, {0x34, 0x00005CEB}, + {0x34, 0x00004CCE}, {0x34, 0x00003CCB}, + {0x34, 0x00002CC8}, {0x34, 0x00001C4B}, + {0x34, 0x00000C48}, + {0x00, 0x00030159}, {0x84, 0x00048000}, + {0x86, 0x0000002A}, {0x87, 0x00000025}, + {0x8E, 0x00065540}, {0x8F, 0x00088000}, + {0xEF, 0x000020A0}, {0x3B, 0x000F0F00}, + {0x3B, 0x000E0B00}, {0x3B, 0x000D0900}, + {0x3B, 0x000C0700}, {0x3B, 0x000B0600}, + {0x3B, 0x000A0400}, {0x3B, 0x00090200}, + {0x3B, 0x00080000}, {0x3B, 0x0007BF00}, + {0x3B, 0x00060B00}, {0x3B, 0x0005C900}, + {0x3B, 0x00040700}, {0x3B, 0x00030600}, + {0x3B, 0x0002D500}, {0x3B, 0x00010200}, + {0x3B, 0x0000E000}, {0xEF, 0x000000A0}, + {0xEF, 0x00000010}, {0x3B, 0x0000C0A8}, + {0x3B, 0x00010400}, {0xEF, 0x00000000}, + {0xEF, 0x00080000}, {0x30, 0x00010000}, + {0x31, 0x0000000F}, {0x32, 0x00007EFE}, + {0xEF, 0x00000000}, {0x00, 0x00010159}, + {0x18, 0x0000FC07}, {0xFE, 0x00000000}, + {0xFE, 0x00000000}, {0x1F, 0x00080003}, + {0xFE, 0x00000000}, {0xFE, 0x00000000}, + {0x1E, 0x00000001}, {0x1F, 0x00080000}, + {0x00, 0x00033D95}, + {0xff, 0xffffffff} +}; + +static const struct rtl8xxxu_rfregval rtl8188fu_cut_b_radioa_init_table[] = { + {0x00, 0x00030000}, {0x08, 0x00008400}, + {0x18, 0x00000407}, {0x19, 0x00000012}, + {0x1B, 0x00001C6C}, + {0x1E, 0x00080009}, {0x1F, 0x00000880}, + {0x2F, 0x0001A060}, {0x3F, 0x00028000}, + {0x42, 0x000060C0}, {0x57, 0x000D0000}, + {0x58, 0x000C0160}, {0x67, 0x00001552}, + {0x83, 0x00000000}, {0xB0, 0x000FF9F0}, + {0xB1, 0x00022218}, {0xB2, 0x00034C00}, + {0xB4, 0x0004484B}, {0xB5, 0x0000112A}, + {0xB6, 0x0000053E}, {0xB7, 0x00010408}, + {0xB8, 0x00010200}, {0xB9, 0x00080001}, + {0xBA, 0x00040001}, {0xBB, 0x00000400}, + {0xBF, 0x000C0000}, {0xC2, 0x00002400}, + {0xC3, 0x00000009}, {0xC4, 0x00040C91}, + {0xC5, 0x00099999}, {0xC6, 0x000000A3}, + {0xC7, 0x0008F820}, {0xC8, 0x00076C06}, + {0xC9, 0x00000000}, {0xCA, 0x00080000}, + {0xDF, 0x00000180}, {0xEF, 0x000001A0}, + {0x51, 0x000E8231}, {0x52, 0x000FAC2C}, + {0x53, 0x00000141}, {0x56, 0x000517F0}, + {0x35, 0x00000090}, {0x35, 0x00000190}, + {0x35, 0x00000290}, {0x36, 0x00001064}, + {0x36, 0x00009064}, {0x36, 0x00011064}, + {0x36, 0x00019064}, {0x18, 0x00000C07}, + {0x5A, 0x00048000}, {0x19, 0x000739D0}, + {0x34, 0x0000ADD2}, {0x34, 0x00009DD0}, + {0x34, 0x00008CF3}, {0x34, 0x00007CF0}, + {0x34, 0x00006CED}, {0x34, 0x00005CD2}, + {0x34, 0x00004CCF}, {0x34, 0x00003CCC}, + {0x34, 0x00002CC9}, {0x34, 0x00001C4C}, + {0x34, 0x00000C49}, + {0x00, 0x00030159}, {0x84, 0x00048000}, + {0x86, 0x0000002A}, {0x87, 0x00000025}, + {0x8E, 0x00065540}, {0x8F, 0x00088000}, + {0xEF, 0x000020A0}, {0x3B, 0x000F0F00}, + {0x3B, 0x000E0B00}, {0x3B, 0x000D0900}, + {0x3B, 0x000C0700}, {0x3B, 0x000B0600}, + {0x3B, 0x000A0400}, {0x3B, 0x00090200}, + {0x3B, 0x00080000}, {0x3B, 0x0007BF00}, + {0x3B, 0x00060B00}, {0x3B, 0x0005C900}, + {0x3B, 0x00040700}, {0x3B, 0x00030600}, + {0x3B, 0x0002D500}, {0x3B, 0x00010200}, + {0x3B, 0x0000E000}, {0xEF, 0x000000A0}, + {0xEF, 0x00000010}, {0x3B, 0x0000C0A8}, + {0x3B, 0x00010400}, {0xEF, 0x00000000}, + {0xEF, 0x00080000}, {0x30, 0x00010000}, + {0x31, 0x0000000F}, {0x32, 0x00007EFE}, + {0xEF, 0x00000000}, {0x00, 0x00010159}, + {0x18, 0x0000FC07}, {0xFE, 0x00000000}, + {0xFE, 0x00000000}, {0x1F, 0x00080003}, + {0xFE, 0x00000000}, {0xFE, 0x00000000}, + {0x1E, 0x00000001}, {0x1F, 0x00080000}, + {0x00, 0x00033D95}, + {0xff, 0xffffffff} +}; + +static int rtl8188fu_identify_chip(struct rtl8xxxu_priv *priv) +{ + struct device *dev = &priv->udev->dev; + u32 sys_cfg, vendor; + int ret = 0; + + strscpy(priv->chip_name, "8188FU", sizeof(priv->chip_name)); + priv->rtl_chip = RTL8188F; + priv->rf_paths = 1; + priv->rx_paths = 1; + priv->tx_paths = 1; + priv->has_wifi = 1; + + sys_cfg = rtl8xxxu_read32(priv, REG_SYS_CFG); + priv->chip_cut = u32_get_bits(sys_cfg, SYS_CFG_CHIP_VERSION_MASK); + if (sys_cfg & SYS_CFG_TRP_VAUX_EN) { + dev_info(dev, "Unsupported test chip\n"); + ret = -ENOTSUPP; + goto out; + } + + vendor = sys_cfg & SYS_CFG_VENDOR_EXT_MASK; + rtl8xxxu_identify_vendor_2bits(priv, vendor); + + ret = rtl8xxxu_config_endpoints_no_sie(priv); + +out: + return ret; +} + +void rtl8188f_channel_to_group(int channel, int *group, int *cck_group) +{ + if (channel < 3) + *group = 0; + else if (channel < 6) + *group = 1; + else if (channel < 9) + *group = 2; + else if (channel < 12) + *group = 3; + else + *group = 4; + + if (channel == 14) + *cck_group = 5; + else + *cck_group = *group; +} + +void +rtl8188f_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40) +{ + u32 val32, ofdm, mcs; + u8 cck, ofdmbase, mcsbase; + int group, cck_group; + + rtl8188f_channel_to_group(channel, &group, &cck_group); + + cck = priv->cck_tx_power_index_A[cck_group]; + + val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32); + val32 &= 0xffff00ff; + val32 |= (cck << 8); + rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); + + val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); + val32 &= 0xff; + val32 |= ((cck << 8) | (cck << 16) | (cck << 24)); + rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); + + ofdmbase = priv->ht40_1s_tx_power_index_A[group]; + ofdmbase += priv->ofdm_tx_power_diff[0].a; + ofdm = ofdmbase | ofdmbase << 8 | ofdmbase << 16 | ofdmbase << 24; + + rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm); + rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm); + + mcsbase = priv->ht40_1s_tx_power_index_A[group]; + if (ht40) + /* This diff is always 0 - not used in 8188FU. */ + mcsbase += priv->ht40_tx_power_diff[0].a; + else + mcsbase += priv->ht20_tx_power_diff[0].a; + mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24; + + rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs); + rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs); + rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs); + rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs); +} + +/* A workaround to eliminate the 2400MHz, 2440MHz, 2480MHz spur of 8188F. */ +static void rtl8188f_spur_calibration(struct rtl8xxxu_priv *priv, u8 channel) +{ + static const u32 frequencies[14 + 1] = { + [5] = 0xFCCD, + [6] = 0xFC4D, + [7] = 0xFFCD, + [8] = 0xFF4D, + [11] = 0xFDCD, + [13] = 0xFCCD, + [14] = 0xFF9A + }; + + static const u32 reg_d40[14 + 1] = { + [5] = 0x06000000, + [6] = 0x00000600, + [13] = 0x06000000 + }; + + static const u32 reg_d44[14 + 1] = { + [11] = 0x04000000 + }; + + static const u32 reg_d4c[14 + 1] = { + [7] = 0x06000000, + [8] = 0x00000380, + [14] = 0x00180000 + }; + + const u8 threshold = 0x16; + bool do_notch, hw_ctrl, sw_ctrl, hw_ctrl_s1 = 0, sw_ctrl_s1 = 0; + u32 val32, initial_gain, reg948; + + val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_D_SYNC_PATH); + val32 |= GENMASK(28, 24); + rtl8xxxu_write32(priv, REG_OFDM0_RX_D_SYNC_PATH, val32); + + /* enable notch filter */ + val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_D_SYNC_PATH); + val32 |= BIT(9); + rtl8xxxu_write32(priv, REG_OFDM0_RX_D_SYNC_PATH, val32); + + if (channel <= 14 && frequencies[channel] > 0) { + reg948 = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); + hw_ctrl = reg948 & BIT(6); + sw_ctrl = !hw_ctrl; + + if (hw_ctrl) { + val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE); + val32 &= GENMASK(5, 3); + hw_ctrl_s1 = val32 == BIT(3); + } else if (sw_ctrl) { + sw_ctrl_s1 = !(reg948 & BIT(9)); + } + + if (hw_ctrl_s1 || sw_ctrl_s1) { + initial_gain = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); + + /* Disable CCK block */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); + val32 &= ~FPGA_RF_MODE_CCK; + rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); + + val32 = initial_gain & ~OFDM0_X_AGC_CORE1_IGI_MASK; + val32 |= 0x30; + rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32); + + /* disable 3-wire */ + rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xccf000c0); + + /* Setup PSD */ + rtl8xxxu_write32(priv, REG_FPGA0_PSD_FUNC, frequencies[channel]); + + /* Start PSD */ + rtl8xxxu_write32(priv, REG_FPGA0_PSD_FUNC, 0x400000 | frequencies[channel]); + + msleep(30); + + do_notch = rtl8xxxu_read32(priv, REG_FPGA0_PSD_REPORT) >= threshold; + + /* turn off PSD */ + rtl8xxxu_write32(priv, REG_FPGA0_PSD_FUNC, frequencies[channel]); + + /* enable 3-wire */ + rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xccc000c0); + + /* Enable CCK block */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); + val32 |= FPGA_RF_MODE_CCK; + rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); + + rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, initial_gain); + + if (do_notch) { + rtl8xxxu_write32(priv, REG_OFDM1_CSI_FIX_MASK1, reg_d40[channel]); + rtl8xxxu_write32(priv, REG_OFDM1_CSI_FIX_MASK2, reg_d44[channel]); + rtl8xxxu_write32(priv, 0xd48, 0x0); + rtl8xxxu_write32(priv, 0xd4c, reg_d4c[channel]); + + /* enable CSI mask */ + val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING); + val32 |= BIT(28); + rtl8xxxu_write32(priv, REG_OFDM1_CFO_TRACKING, val32); + + return; + } + } + } + + /* disable CSI mask function */ + val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING); + val32 &= ~BIT(28); + rtl8xxxu_write32(priv, REG_OFDM1_CFO_TRACKING, val32); +} + +static void rtl8188fu_config_channel(struct ieee80211_hw *hw) +{ + struct rtl8xxxu_priv *priv = hw->priv; + u32 val32; + u8 channel, subchannel; + bool sec_ch_above; + + channel = (u8)hw->conf.chandef.chan->hw_value; + + /* Set channel */ + val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG); + val32 &= ~MODE_AG_CHANNEL_MASK; + val32 |= channel; + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32); + + /* Spur calibration */ + rtl8188f_spur_calibration(priv, channel); + + /* Set bandwidth mode */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); + val32 &= ~FPGA_RF_MODE; + val32 |= hw->conf.chandef.width == NL80211_CHAN_WIDTH_40; + rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); + + val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); + val32 &= ~FPGA_RF_MODE; + val32 |= hw->conf.chandef.width == NL80211_CHAN_WIDTH_40; + rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); + + /* RXADC CLK */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); + val32 |= GENMASK(10, 8); + rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); + + /* TXDAC CLK */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); + val32 |= BIT(14) | BIT(12); + val32 &= ~BIT(13); + rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); + + /* small BW */ + val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT); + val32 &= ~GENMASK(31, 30); + rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32); + + /* adc buffer clk */ + val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT); + val32 &= ~BIT(29); + val32 |= BIT(28); + rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32); + + /* adc buffer clk */ + val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_AFE); + val32 &= ~BIT(29); + val32 |= BIT(28); + rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_AFE, val32); + + val32 = rtl8xxxu_read32(priv, REG_OFDM_RX_DFIR); + val32 &= ~BIT(19); + rtl8xxxu_write32(priv, REG_OFDM_RX_DFIR, val32); + + val32 = rtl8xxxu_read32(priv, REG_OFDM_RX_DFIR); + val32 &= ~GENMASK(23, 20); + val32 |= BIT(21); + if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_20 || + hw->conf.chandef.width == NL80211_CHAN_WIDTH_20_NOHT) + val32 |= BIT(20); + else if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) + val32 |= BIT(22); + rtl8xxxu_write32(priv, REG_OFDM_RX_DFIR, val32); + + if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) { + if (hw->conf.chandef.center_freq1 > + hw->conf.chandef.chan->center_freq) { + sec_ch_above = 1; + channel += 2; + } else { + sec_ch_above = 0; + channel -= 2; + } + + /* Set Control channel to upper or lower. */ + val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM); + val32 &= ~CCK0_SIDEBAND; + if (!sec_ch_above) + val32 |= CCK0_SIDEBAND; + rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32); + + val32 = rtl8xxxu_read32(priv, REG_DATA_SUBCHANNEL); + val32 &= ~GENMASK(3, 0); + if (sec_ch_above) + subchannel = 2; + else + subchannel = 1; + val32 |= subchannel; + rtl8xxxu_write32(priv, REG_DATA_SUBCHANNEL, val32); + + val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); + val32 &= ~RSR_RSC_BANDWIDTH_40M; + rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); + } + + /* RF TRX_BW */ + val32 = channel; + if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_20 || + hw->conf.chandef.width == NL80211_CHAN_WIDTH_20_NOHT) + val32 |= MODE_AG_BW_20MHZ_8723B; + else if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) + val32 |= MODE_AG_BW_40MHZ_8723B; + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32); + + /* FILTER BW&RC Corner (ACPR) */ + if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_20 || + hw->conf.chandef.width == NL80211_CHAN_WIDTH_20_NOHT) + val32 = 0x00065; + else if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) + val32 = 0x00025; + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RXG_MIX_SWBW, val32); + + if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_20 || + hw->conf.chandef.width == NL80211_CHAN_WIDTH_20_NOHT) + val32 = 0x0; + else if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) + val32 = 0x01000; + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RX_BB2, val32); + + /* RC Corner */ + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x00140); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RX_G2, 0x01c6c); +} + +static void rtl8188fu_init_aggregation(struct rtl8xxxu_priv *priv) +{ + u8 agg_ctrl, rxdma_mode, usb_tx_agg_desc_num = 6; + u32 agg_rx, val32; + + /* TX aggregation */ + val32 = rtl8xxxu_read32(priv, REG_DWBCN0_CTRL_8188F); + val32 &= ~(0xf << 4); + val32 |= usb_tx_agg_desc_num << 4; + rtl8xxxu_write32(priv, REG_DWBCN0_CTRL_8188F, val32); + rtl8xxxu_write8(priv, REG_DWBCN1_CTRL_8723B, usb_tx_agg_desc_num << 1); + + /* RX aggregation */ + agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL); + agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN; + + agg_rx = rtl8xxxu_read32(priv, REG_RXDMA_AGG_PG_TH); + agg_rx &= ~RXDMA_USB_AGG_ENABLE; + agg_rx &= ~0xFF0F; /* reset agg size and timeout */ + + rxdma_mode = rtl8xxxu_read8(priv, REG_RXDMA_PRO_8723B); + rxdma_mode &= ~BIT(1); + + rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl); + rtl8xxxu_write32(priv, REG_RXDMA_AGG_PG_TH, agg_rx); + rtl8xxxu_write8(priv, REG_RXDMA_PRO_8723B, rxdma_mode); +} + +static void rtl8188fu_init_statistics(struct rtl8xxxu_priv *priv) +{ + u32 val32; + + /* Time duration for NHM unit: 4us, 0xc350=200ms */ + rtl8xxxu_write16(priv, REG_NHM_TIMER_8723B + 2, 0xc350); + rtl8xxxu_write16(priv, REG_NHM_TH9_TH10_8723B + 2, 0xffff); + rtl8xxxu_write32(priv, REG_NHM_TH3_TO_TH0_8723B, 0xffffff50); + rtl8xxxu_write32(priv, REG_NHM_TH7_TO_TH4_8723B, 0xffffffff); + + /* TH8 */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); + val32 |= 0xff; + rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); + + /* Enable CCK */ + val32 = rtl8xxxu_read32(priv, REG_NHM_TH9_TH10_8723B); + val32 &= ~(BIT(8) | BIT(9) | BIT(10)); + val32 |= BIT(8); + rtl8xxxu_write32(priv, REG_NHM_TH9_TH10_8723B, val32); + + /* Max power amongst all RX antennas */ + val32 = rtl8xxxu_read32(priv, REG_OFDM0_FA_RSTC); + val32 |= BIT(7); + rtl8xxxu_write32(priv, REG_OFDM0_FA_RSTC, val32); +} + +static int rtl8188fu_parse_efuse(struct rtl8xxxu_priv *priv) +{ + struct rtl8188fu_efuse *efuse = &priv->efuse_wifi.efuse8188fu; + + if (efuse->rtl_id != cpu_to_le16(0x8129)) + return -EINVAL; + + ether_addr_copy(priv->mac_addr, efuse->mac_addr); + + memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base, + sizeof(efuse->tx_power_index_A.cck_base)); + + memcpy(priv->ht40_1s_tx_power_index_A, + efuse->tx_power_index_A.ht40_base, + sizeof(efuse->tx_power_index_A.ht40_base)); + + priv->ofdm_tx_power_diff[0].a = efuse->tx_power_index_A.ht20_ofdm_1s_diff.a; + priv->ht20_tx_power_diff[0].a = efuse->tx_power_index_A.ht20_ofdm_1s_diff.b; + + priv->default_crystal_cap = efuse->xtal_k & 0x3f; + + return 0; +} + +static int rtl8188fu_load_firmware(struct rtl8xxxu_priv *priv) +{ + const char *fw_name; + int ret; + + fw_name = "rtlwifi/rtl8188fufw.bin"; + + ret = rtl8xxxu_load_firmware(priv, fw_name); + + return ret; +} + +static void rtl8188fu_init_phy_bb(struct rtl8xxxu_priv *priv) +{ + u8 val8; + u16 val16; + + /* Enable BB and RF */ + val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); + val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB | SYS_FUNC_DIO_RF; + rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); + + /* + * Per vendor driver, run power sequence before init of RF + */ + val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB; + rtl8xxxu_write8(priv, REG_RF_CTRL, val8); + + usleep_range(10, 20); + + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_IQADJ_G1, 0x780); + + val8 = SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB | SYS_FUNC_USBA | SYS_FUNC_USBD; + rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); + + rtl8xxxu_init_phy_regs(priv, rtl8188fu_phy_init_table); + rtl8xxxu_init_phy_regs(priv, rtl8188f_agc_table); +} + +static int rtl8188fu_init_phy_rf(struct rtl8xxxu_priv *priv) +{ + int ret; + + if (priv->chip_cut == 1) + ret = rtl8xxxu_init_phy_rf(priv, rtl8188fu_cut_b_radioa_init_table, RF_A); + else + ret = rtl8xxxu_init_phy_rf(priv, rtl8188fu_radioa_init_table, RF_A); + + return ret; +} + +void rtl8188f_phy_lc_calibrate(struct rtl8xxxu_priv *priv) +{ + u32 val32; + u32 rf_amode, lstf; + int i; + + /* Check continuous TX and Packet TX */ + lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF); + + if (lstf & OFDM_LSTF_MASK) { + /* Disable all continuous TX */ + val32 = lstf & ~OFDM_LSTF_MASK; + rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); + } else { + /* Deal with Packet TX case */ + /* block all queues */ + rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); + } + + /* Read original RF mode Path A */ + rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG); + + /* Start LC calibration */ + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, rf_amode | 0x08000); + + for (i = 0; i < 100; i++) { + if ((rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG) & 0x08000) == 0) + break; + msleep(10); + } + + if (i == 100) + dev_warn(&priv->udev->dev, "LC calibration timed out.\n"); + + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, rf_amode); + + /* Restore original parameters */ + if (lstf & OFDM_LSTF_MASK) + rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf); + else /* Deal with Packet TX case */ + rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); +} + +static int rtl8188fu_iqk_path_a(struct rtl8xxxu_priv *priv, u32 *lok_result) +{ + u32 reg_eac, reg_e94, reg_e9c, val32; + int result = 0; + + /* + * Leave IQK mode + */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); + val32 &= 0x000000ff; + rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); + + /* + * Enable path A PA in TX IQK mode + */ + val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); + val32 |= 0x80000; + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x20000); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0x07ff7); + + /* PA,PAD gain adjust */ + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x980); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_PAD_TXG, 0x5102a); + + /* enter IQK mode */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); + val32 &= 0x000000ff; + val32 |= 0x80800000; + rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); + + /* path-A IQK setting */ + rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); + rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); + + rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821403ff); + rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160000); + + /* LO calibration setting */ + rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911); + + /* One shot, path A LOK & IQK */ + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); + + mdelay(25); + + /* + * Leave IQK mode + */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); + val32 &= 0x000000ff; + rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); + + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x180); + + /* save LOK result */ + *lok_result = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_TXM_IDAC); + + /* Check failed */ + reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); + reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); + reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); + + if (!(reg_eac & BIT(28)) && + ((reg_e94 & 0x03ff0000) != 0x01420000) && + ((reg_e9c & 0x03ff0000) != 0x00420000)) + result |= 0x01; + + return result; +} + +static int rtl8188fu_rx_iqk_path_a(struct rtl8xxxu_priv *priv, u32 lok_result) +{ + u32 reg_ea4, reg_eac, reg_e94, reg_e9c, val32; + int result = 0; + + /* + * Leave IQK mode + */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); + val32 &= 0x000000ff; + rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); + + /* + * Enable path A PA in TX IQK mode + */ + val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); + val32 |= 0x80000; + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf1173); + + /* PA,PAD gain adjust */ + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x980); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_PAD_TXG, 0x5102a); + + /* + * Enter IQK mode + */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); + val32 &= 0x000000ff; + val32 |= 0x80800000; + rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); + + /* + * Tx IQK setting + */ + rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); + rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); + + /* path-A IQK setting */ + rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1c); + rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x30008c1c); + + rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160fff); + rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160000); + + /* LO calibration setting */ + rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911); + + /* One shot, path A LOK & IQK */ + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); + + mdelay(25); + + /* + * Leave IQK mode + */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); + val32 &= 0x000000ff; + rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); + + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x180); + + /* Check failed */ + reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); + reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); + reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); + + if (!(reg_eac & BIT(28)) && + ((reg_e94 & 0x03ff0000) != 0x01420000) && + ((reg_e9c & 0x03ff0000) != 0x00420000)) + result |= 0x01; + else /* If TX not OK, ignore RX */ + goto out; + + val32 = 0x80007c00 | (reg_e94 & 0x3ff0000) | + ((reg_e9c & 0x3ff0000) >> 16); + rtl8xxxu_write32(priv, REG_TX_IQK, val32); + + /* + * Modify RX IQK mode table + */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); + val32 &= 0x000000ff; + rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); + + val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); + val32 |= 0x80000; + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7ff2); + + /* + * PA, PAD setting + */ + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x980); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_PAD_TXG, 0x51000); + + /* + * Enter IQK mode + */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); + val32 &= 0x000000ff; + val32 |= 0x80800000; + rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); + + /* + * RX IQK setting + */ + rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); + + /* path-A IQK setting */ + rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x30008c1c); + rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1c); + + rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160000); + rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x281613ff); + + /* LO calibration setting */ + rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911); + + /* One shot, path A LOK & IQK */ + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); + + mdelay(25); + + /* + * Leave IQK mode + */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); + val32 &= 0x000000ff; + rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); + + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x180); + + /* reload LOK value */ + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXM_IDAC, lok_result); + + /* Check failed */ + reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); + reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); + + if (!(reg_eac & BIT(27)) && + ((reg_ea4 & 0x03ff0000) != 0x01320000) && + ((reg_eac & 0x03ff0000) != 0x00360000)) + result |= 0x02; + +out: + return result; +} + +static void rtl8188fu_phy_iqcalibrate(struct rtl8xxxu_priv *priv, + int result[][8], int t) +{ + struct device *dev = &priv->udev->dev; + u32 i, val32, rx_initial_gain, lok_result; + u32 path_sel_bb, path_sel_rf; + int path_a_ok; + int retry = 2; + static const u32 adda_regs[RTL8XXXU_ADDA_REGS] = { + REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH, + REG_RX_WAIT_CCA, REG_TX_CCK_RFON, + REG_TX_CCK_BBON, REG_TX_OFDM_RFON, + REG_TX_OFDM_BBON, REG_TX_TO_RX, + REG_TX_TO_TX, REG_RX_CCK, + REG_RX_OFDM, REG_RX_WAIT_RIFS, + REG_RX_TO_RX, REG_STANDBY, + REG_SLEEP, REG_PMPD_ANAEN + }; + static const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = { + REG_TXPAUSE, REG_BEACON_CTRL, + REG_BEACON_CTRL_1, REG_GPIO_MUXCFG + }; + static const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = { + REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR, + REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, + REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE, + REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE + }; + + /* + * Note: IQ calibration must be performed after loading + * PHY_REG.txt , and radio_a, radio_b.txt + */ + + rx_initial_gain = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); + + if (t == 0) { + /* Save ADDA parameters, turn Path A ADDA on */ + rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup, + RTL8XXXU_ADDA_REGS); + rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup); + rtl8xxxu_save_regs(priv, iqk_bb_regs, + priv->bb_backup, RTL8XXXU_BB_REGS); + } + + rtl8xxxu_path_adda_on(priv, adda_regs, true); + + if (t == 0) { + val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1); + priv->pi_enabled = u32_get_bits(val32, FPGA0_HSSI_PARM1_PI); + } + + /* save RF path */ + path_sel_bb = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); + path_sel_rf = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_S0S1); + + /* BB setting */ + rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600); + rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4); + rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x25204000); + + /* MAC settings */ + val32 = rtl8xxxu_read32(priv, REG_TX_PTCL_CTRL); + val32 |= 0x00ff0000; + rtl8xxxu_write32(priv, REG_TX_PTCL_CTRL, val32); + + /* IQ calibration setting */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); + val32 &= 0xff; + val32 |= 0x80800000; + rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); + rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); + rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); + + for (i = 0; i < retry; i++) { + path_a_ok = rtl8188fu_iqk_path_a(priv, &lok_result); + if (path_a_ok == 0x01) { + val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); + val32 &= 0xff; + rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); + + val32 = rtl8xxxu_read32(priv, + REG_TX_POWER_BEFORE_IQK_A); + result[t][0] = (val32 >> 16) & 0x3ff; + + val32 = rtl8xxxu_read32(priv, + REG_TX_POWER_AFTER_IQK_A); + result[t][1] = (val32 >> 16) & 0x3ff; + break; + } + } + + for (i = 0; i < retry; i++) { + path_a_ok = rtl8188fu_rx_iqk_path_a(priv, lok_result); + if (path_a_ok == 0x03) { + val32 = rtl8xxxu_read32(priv, + REG_RX_POWER_BEFORE_IQK_A_2); + result[t][2] = (val32 >> 16) & 0x3ff; + + val32 = rtl8xxxu_read32(priv, + REG_RX_POWER_AFTER_IQK_A_2); + result[t][3] = (val32 >> 16) & 0x3ff; + break; + } + } + + if (!path_a_ok) + dev_dbg(dev, "%s: Path A IQK failed!\n", __func__); + + /* Back to BB mode, load original value */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); + val32 &= 0xff; + rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); + + if (t == 0) + return; + + if (!priv->pi_enabled) { + /* + * Switch back BB to SI mode after finishing + * IQ Calibration + */ + val32 = 0x01000000; + rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32); + rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32); + } + + /* Reload ADDA power saving parameters */ + rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup, + RTL8XXXU_ADDA_REGS); + + /* Reload MAC parameters */ + rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup); + + /* Reload BB parameters */ + rtl8xxxu_restore_regs(priv, iqk_bb_regs, + priv->bb_backup, RTL8XXXU_BB_REGS); + + /* Reload RF path */ + rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel_bb); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, path_sel_rf); + + /* Restore RX initial gain */ + val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); + val32 &= 0xffffff00; + val32 |= 0x50; + rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32); + val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); + val32 &= 0xffffff00; + val32 |= rx_initial_gain & 0xff; + rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32); + + /* Load 0xe30 IQC default value */ + rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00); + rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00); +} + +static void rtl8188fu_phy_iq_calibrate(struct rtl8xxxu_priv *priv) +{ + struct device *dev = &priv->udev->dev; + int result[4][8]; /* last is final result */ + int i, candidate; + bool path_a_ok; + u32 reg_e94, reg_e9c, reg_ea4, reg_eac; + u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc; + s32 reg_tmp = 0; + bool simu; + u32 path_sel_bb, path_sel_rf; + + /* Save RF path */ + path_sel_bb = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); + path_sel_rf = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_S0S1); + + memset(result, 0, sizeof(result)); + candidate = -1; + + path_a_ok = false; + + for (i = 0; i < 3; i++) { + rtl8188fu_phy_iqcalibrate(priv, result, i); + + if (i == 1) { + simu = rtl8xxxu_gen2_simularity_compare(priv, result, 0, 1); + if (simu) { + candidate = 0; + break; + } + } + + if (i == 2) { + simu = rtl8xxxu_gen2_simularity_compare(priv, result, 0, 2); + if (simu) { + candidate = 0; + break; + } + + simu = rtl8xxxu_gen2_simularity_compare(priv, result, 1, 2); + if (simu) { + candidate = 1; + } else { + for (i = 0; i < 8; i++) + reg_tmp += result[3][i]; + + if (reg_tmp) + candidate = 3; + else + candidate = -1; + } + } + } + + for (i = 0; i < 4; i++) { + reg_e94 = result[i][0]; + reg_e9c = result[i][1]; + reg_ea4 = result[i][2]; + reg_eac = result[i][3]; + reg_eb4 = result[i][4]; + reg_ebc = result[i][5]; + reg_ec4 = result[i][6]; + reg_ecc = result[i][7]; + } + + if (candidate >= 0) { + reg_e94 = result[candidate][0]; + priv->rege94 = reg_e94; + reg_e9c = result[candidate][1]; + priv->rege9c = reg_e9c; + reg_ea4 = result[candidate][2]; + reg_eac = result[candidate][3]; + reg_eb4 = result[candidate][4]; + priv->regeb4 = reg_eb4; + reg_ebc = result[candidate][5]; + priv->regebc = reg_ebc; + reg_ec4 = result[candidate][6]; + reg_ecc = result[candidate][7]; + dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate); + dev_dbg(dev, + "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x ecc=%x\n", + __func__, reg_e94, reg_e9c, + reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc); + path_a_ok = true; + } else { + reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100; + reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0; + } + + if (reg_e94 && candidate >= 0) + rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result, + candidate, (reg_ea4 == 0)); + + rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg, + priv->bb_recovery_backup, RTL8XXXU_BB_REGS); + + rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel_bb); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, path_sel_rf); +} + +static void rtl8188f_disabled_to_emu(struct rtl8xxxu_priv *priv) +{ + u16 val8; + + /* 0x04[12:11] = 2b'01enable WL suspend */ + val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); + val8 &= ~((APS_FSMCO_PCIE | APS_FSMCO_HW_SUSPEND) >> 8); + rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); + + /* 0xC4[4] <= 1, turn off USB APHY LDO under suspend mode */ + val8 = rtl8xxxu_read8(priv, 0xc4); + val8 &= ~BIT(4); + rtl8xxxu_write8(priv, 0xc4, val8); +} + +static int rtl8188f_emu_to_active(struct rtl8xxxu_priv *priv) +{ + u8 val8; + u32 val32; + int count, ret = 0; + + /* Disable SW LPS */ + val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); + val8 &= ~(APS_FSMCO_SW_LPS >> 8); + rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); + + /* wait till 0x04[17] = 1 power ready */ + for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { + val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); + if (val32 & BIT(17)) + break; + + udelay(10); + } + + if (!count) { + ret = -EBUSY; + goto exit; + } + + /* Disable HWPDN */ + val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); + val8 &= ~(APS_FSMCO_HW_POWERDOWN >> 8); + rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); + + /* Disable WL suspend */ + val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); + val8 &= ~(APS_FSMCO_HW_SUSPEND >> 8); + rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); + + /* set, then poll until 0 */ + val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); + val8 |= APS_FSMCO_MAC_ENABLE >> 8; + rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); + + for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { + val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); + if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) { + ret = 0; + break; + } + udelay(10); + } + + if (!count) { + ret = -EBUSY; + goto exit; + } + + /* 0x27<=35 to reduce RF noise */ + val8 = rtl8xxxu_write8(priv, 0x27, 0x35); +exit: + return ret; +} + +static int rtl8188fu_active_to_emu(struct rtl8xxxu_priv *priv) +{ + u8 val8; + u32 val32; + int count, ret = 0; + + /* Turn off RF */ + rtl8xxxu_write8(priv, REG_RF_CTRL, 0); + + /* 0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */ + val8 = rtl8xxxu_read8(priv, 0x4e); + val8 &= ~BIT(7); + rtl8xxxu_write8(priv, 0x4e, val8); + + /* 0x27 <= 34, xtal_qsel = 0 to xtal bring up */ + rtl8xxxu_write8(priv, 0x27, 0x34); + + /* 0x04[9] = 1 turn off MAC by HW state machine */ + val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); + val8 |= APS_FSMCO_MAC_OFF >> 8; + rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); + + for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { + val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); + if ((val32 & APS_FSMCO_MAC_OFF) == 0) { + ret = 0; + break; + } + udelay(10); + } + + if (!count) { + ret = -EBUSY; + goto exit; + } + +exit: + return ret; +} + +static int rtl8188fu_emu_to_disabled(struct rtl8xxxu_priv *priv) +{ + u8 val8; + + /* 0x04[12:11] = 2b'01 enable WL suspend */ + val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); + val8 &= ~((APS_FSMCO_PCIE | APS_FSMCO_HW_SUSPEND) >> 8); + val8 |= APS_FSMCO_HW_SUSPEND >> 8; + rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); + + /* 0xC4[4] <= 1, turn off USB APHY LDO under suspend mode */ + val8 = rtl8xxxu_read8(priv, 0xc4); + val8 |= BIT(4); + rtl8xxxu_write8(priv, 0xc4, val8); + + return 0; +} + +static int rtl8188fu_active_to_lps(struct rtl8xxxu_priv *priv) +{ + struct device *dev = &priv->udev->dev; + u8 val8; + u16 val16; + u32 val32; + int retry, retval; + + /* set RPWM IMR */ + val8 = rtl8xxxu_read8(priv, REG_FTIMR + 1); + val8 |= IMR0_CPWM >> 8; + rtl8xxxu_write8(priv, REG_FTIMR + 1, val8); + + /* Tx Pause */ + rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); + + retry = 100; + retval = -EBUSY; + + /* + * Poll 32 bit wide REG_SCH_TX_CMD for 0x00000000 to ensure no TX is pending. + */ + do { + val32 = rtl8xxxu_read32(priv, REG_SCH_TX_CMD); + if (!val32) { + retval = 0; + break; + } + } while (retry--); + + if (!retry) { + dev_warn(dev, "Failed to flush TX queue\n"); + retval = -EBUSY; + goto out; + } + + /* Disable CCK and OFDM, clock gated */ + val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); + val8 &= ~SYS_FUNC_BBRSTB; + rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); + + udelay(2); + + /* Whole BB is reset */ + val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); + val8 &= ~SYS_FUNC_BB_GLB_RSTN; + rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); + + /* Reset MAC TRX */ + val16 = rtl8xxxu_read16(priv, REG_CR); + val16 |= 0x3f; + val16 &= ~(CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE | CR_SECURITY_ENABLE); + rtl8xxxu_write16(priv, REG_CR, val16); + + /* Respond TxOK to scheduler */ + val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST); + val8 |= DUAL_TSF_TX_OK; + rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8); + +out: + return retval; +} + +static int rtl8188fu_power_on(struct rtl8xxxu_priv *priv) +{ + u16 val16; + int ret; + + rtl8188f_disabled_to_emu(priv); + + ret = rtl8188f_emu_to_active(priv); + if (ret) + goto exit; + + rtl8xxxu_write8(priv, REG_CR, 0); + + val16 = rtl8xxxu_read16(priv, REG_CR); + + val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE | + CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | + CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE | + CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE); + rtl8xxxu_write16(priv, REG_CR, val16); + +exit: + return ret; +} + +static void rtl8188fu_power_off(struct rtl8xxxu_priv *priv) +{ + u8 val8; + u16 val16; + + rtl8xxxu_flush_fifo(priv); + + val16 = rtl8xxxu_read16(priv, REG_GPIO_MUXCFG); + val16 &= ~BIT(12); + rtl8xxxu_write16(priv, REG_GPIO_MUXCFG, val16); + + rtl8xxxu_write32(priv, REG_HISR0, 0xFFFFFFFF); + rtl8xxxu_write32(priv, REG_HISR1, 0xFFFFFFFF); + + /* Stop Tx Report Timer. 0x4EC[Bit1]=b'0 */ + val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL); + val8 &= ~TX_REPORT_CTRL_TIMER_ENABLE; + rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8); + + /* Turn off RF */ + rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00); + + /* Reset Firmware if running in RAM */ + if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL) + rtl8xxxu_firmware_self_reset(priv); + + rtl8188fu_active_to_lps(priv); + + /* Reset MCU */ + val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); + val16 &= ~SYS_FUNC_CPU_ENABLE; + rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); + + /* Reset MCU ready status */ + rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00); + + rtl8188fu_active_to_emu(priv); + rtl8188fu_emu_to_disabled(priv); +} + +#define PPG_BB_GAIN_2G_TXA_OFFSET_8188F 0xee +#define PPG_BB_GAIN_2G_TX_OFFSET_MASK 0x0f + +static void rtl8188f_enable_rf(struct rtl8xxxu_priv *priv) +{ + u32 val32; + u8 pg_pwrtrim = 0xff, val8; + s8 bb_gain; + + /* Somehow this is not found in the efuse we read earlier. */ + rtl8xxxu_read_efuse8(priv, PPG_BB_GAIN_2G_TXA_OFFSET_8188F, &pg_pwrtrim); + + if (pg_pwrtrim != 0xff) { + bb_gain = pg_pwrtrim & PPG_BB_GAIN_2G_TX_OFFSET_MASK; + + if (bb_gain == PPG_BB_GAIN_2G_TX_OFFSET_MASK) + bb_gain = 0; + else if (bb_gain & 1) + bb_gain = bb_gain >> 1; + else + bb_gain = -(bb_gain >> 1); + + val8 = abs(bb_gain); + if (bb_gain > 0) + val8 |= BIT(5); + + val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_55); + val32 &= ~0xfc000; + val32 |= val8 << 14; + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_55, val32); + } + + rtl8xxxu_write8(priv, REG_RF_CTRL, RF_ENABLE | RF_RSTB | RF_SDMRSTB); + + val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); + val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK); + val32 |= OFDM_RF_PATH_RX_A | OFDM_RF_PATH_TX_A; + rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); + + rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); +} + +static void rtl8188f_disable_rf(struct rtl8xxxu_priv *priv) +{ + u32 val32; + + val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); + val32 &= ~OFDM_RF_PATH_TX_MASK; + rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); + + /* Power down RF module */ + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0); +} + +static void rtl8188f_usb_quirks(struct rtl8xxxu_priv *priv) +{ + u16 val16; + u32 val32; + + val16 = rtl8xxxu_read16(priv, REG_CR); + val16 |= (CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE); + rtl8xxxu_write16(priv, REG_CR, val16); + + val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK); + val32 |= TXDMA_OFFSET_DROP_DATA_EN; + rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32); +} + +#define XTAL1 GENMASK(22, 17) +#define XTAL0 GENMASK(16, 11) + +void rtl8188f_set_crystal_cap(struct rtl8xxxu_priv *priv, u8 crystal_cap) +{ + struct rtl8xxxu_cfo_tracking *cfo = &priv->cfo_tracking; + u32 val32; + + if (crystal_cap == cfo->crystal_cap) + return; + + val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL); + + dev_dbg(&priv->udev->dev, + "%s: Adjusting crystal cap from 0x%x (actually 0x%lx 0x%lx) to 0x%x\n", + __func__, + cfo->crystal_cap, + FIELD_GET(XTAL1, val32), + FIELD_GET(XTAL0, val32), + crystal_cap); + + val32 &= ~(XTAL1 | XTAL0); + val32 |= FIELD_PREP(XTAL1, crystal_cap) | + FIELD_PREP(XTAL0, crystal_cap); + rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32); + + cfo->crystal_cap = crystal_cap; +} + +static s8 rtl8188f_cck_rssi(struct rtl8xxxu_priv *priv, struct rtl8723au_phy_stats *phy_stats) +{ + u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a; + s8 rx_pwr_all = 0x00; + u8 vga_idx, lna_idx; + + lna_idx = u8_get_bits(cck_agc_rpt, CCK_AGC_RPT_LNA_IDX_MASK); + vga_idx = u8_get_bits(cck_agc_rpt, CCK_AGC_RPT_VGA_IDX_MASK); + + switch (lna_idx) { + case 7: + if (vga_idx <= 27) + rx_pwr_all = -100 + 2 * (27 - vga_idx); + else + rx_pwr_all = -100; + break; + case 5: + rx_pwr_all = -74 + 2 * (21 - vga_idx); + break; + case 3: + rx_pwr_all = -60 + 2 * (20 - vga_idx); + break; + case 1: + rx_pwr_all = -44 + 2 * (19 - vga_idx); + break; + default: + break; + } + + return rx_pwr_all; +} + +struct rtl8xxxu_fileops rtl8188fu_fops = { + .identify_chip = rtl8188fu_identify_chip, + .parse_efuse = rtl8188fu_parse_efuse, + .load_firmware = rtl8188fu_load_firmware, + .power_on = rtl8188fu_power_on, + .power_off = rtl8188fu_power_off, + .read_efuse = rtl8xxxu_read_efuse, + .reset_8051 = rtl8xxxu_reset_8051, + .llt_init = rtl8xxxu_auto_llt_table, + .init_phy_bb = rtl8188fu_init_phy_bb, + .init_phy_rf = rtl8188fu_init_phy_rf, + .phy_init_antenna_selection = rtl8723bu_phy_init_antenna_selection, + .phy_lc_calibrate = rtl8188f_phy_lc_calibrate, + .phy_iq_calibrate = rtl8188fu_phy_iq_calibrate, + .config_channel = rtl8188fu_config_channel, + .parse_rx_desc = rtl8xxxu_parse_rxdesc24, + .parse_phystats = rtl8723au_rx_parse_phystats, + .init_aggregation = rtl8188fu_init_aggregation, + .init_statistics = rtl8188fu_init_statistics, + .init_burst = rtl8xxxu_init_burst, + .enable_rf = rtl8188f_enable_rf, + .disable_rf = rtl8188f_disable_rf, + .usb_quirks = rtl8188f_usb_quirks, + .set_tx_power = rtl8188f_set_tx_power, + .update_rate_mask = rtl8xxxu_gen2_update_rate_mask, + .report_connect = rtl8xxxu_gen2_report_connect, + .report_rssi = rtl8xxxu_gen2_report_rssi, + .fill_txdesc = rtl8xxxu_fill_txdesc_v2, + .set_crystal_cap = rtl8188f_set_crystal_cap, + .cck_rssi = rtl8188f_cck_rssi, + .writeN_block_size = 128, + .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc24), + .tx_desc_size = sizeof(struct rtl8xxxu_txdesc40), + .has_s0s1 = 1, + .has_tx_report = 1, + .gen2_thermal_meter = 1, + .needs_full_init = 1, + .init_reg_rxfltmap = 1, + .init_reg_pkt_life_time = 1, + .init_reg_hmtfr = 1, + .ampdu_max_time = 0x70, + .ustime_tsf_edca = 0x28, + .max_aggr_num = 0x0c14, + .supports_ap = 1, + .max_macid_num = 16, + .max_sec_cam_num = 16, + .supports_concurrent = 1, + .adda_1t_init = 0x03c00014, + .adda_1t_path_on = 0x03c00014, + .trxff_boundary = 0x3f7f, + .pbp_rx = PBP_PAGE_SIZE_256, + .pbp_tx = PBP_PAGE_SIZE_256, + .mactable = rtl8188f_mac_init_table, + .total_page_num = TX_TOTAL_PAGE_NUM_8188F, + .page_num_hi = TX_PAGE_NUM_HI_PQ_8188F, + .page_num_lo = TX_PAGE_NUM_LO_PQ_8188F, + .page_num_norm = TX_PAGE_NUM_NORM_PQ_8188F, +}; diff --git a/drivers/net/wireless/realtek/rtl8xxxu/8192c.c b/drivers/net/wireless/realtek/rtl8xxxu/8192c.c new file mode 100644 index 000000000000..b1c5a9971617 --- /dev/null +++ b/drivers/net/wireless/realtek/rtl8xxxu/8192c.c @@ -0,0 +1,673 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * RTL8XXXU mac80211 USB driver - 8188c/8188r/8192c specific subdriver + * + * Copyright (c) 2014 - 2017 Jes Sorensen + * + * Portions, notably calibration code: + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This driver was written as a replacement for the vendor provided + * rtl8723au driver. As the Realtek 8xxx chips are very similar in + * their programming interface, I have started adding support for + * additional 8xxx chips like the 8192cu, 8188cus, etc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "rtl8xxxu.h" +#include "regs.h" + +#ifdef CONFIG_RTL8XXXU_UNTESTED +static struct rtl8xxxu_power_base rtl8192c_power_base = { + .reg_0e00 = 0x07090c0c, + .reg_0e04 = 0x01020405, + .reg_0e08 = 0x00000000, + .reg_086c = 0x00000000, + + .reg_0e10 = 0x0b0c0c0e, + .reg_0e14 = 0x01030506, + .reg_0e18 = 0x0b0c0d0e, + .reg_0e1c = 0x01030509, + + .reg_0830 = 0x07090c0c, + .reg_0834 = 0x01020405, + .reg_0838 = 0x00000000, + .reg_086c_2 = 0x00000000, + + .reg_083c = 0x0b0c0d0e, + .reg_0848 = 0x01030509, + .reg_084c = 0x0b0c0d0e, + .reg_0868 = 0x01030509, +}; + +static struct rtl8xxxu_power_base rtl8188r_power_base = { + .reg_0e00 = 0x06080808, + .reg_0e04 = 0x00040406, + .reg_0e08 = 0x00000000, + .reg_086c = 0x00000000, + + .reg_0e10 = 0x04060608, + .reg_0e14 = 0x00020204, + .reg_0e18 = 0x04060608, + .reg_0e1c = 0x00020204, + + .reg_0830 = 0x06080808, + .reg_0834 = 0x00040406, + .reg_0838 = 0x00000000, + .reg_086c_2 = 0x00000000, + + .reg_083c = 0x04060608, + .reg_0848 = 0x00020204, + .reg_084c = 0x04060608, + .reg_0868 = 0x00020204, +}; + +static const struct rtl8xxxu_reg8val rtl8192cu_mac_init_table[] = { + {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00}, + {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05}, + {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00}, + {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05}, + {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01}, + {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f}, + {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72}, + {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08}, + {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff}, + {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2}, + {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3}, + {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4}, + {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4}, + {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a}, + {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16}, + {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00}, + {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02}, + {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a}, + {0x652, 0x20}, {0x652, 0x20}, {0x63c, 0x08}, {0x63d, 0x08}, + {0x63e, 0x0c}, {0x63f, 0x0c}, {0x66e, 0x05}, {0x700, 0x21}, + {0x701, 0x43}, {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, + {0x709, 0x43}, {0x70a, 0x65}, {0x70b, 0x87}, + {0xffff, 0xff}, +}; + +static const struct rtl8xxxu_rfregval rtl8192cu_radioa_2t_init_table[] = { + {0x00, 0x00030159}, {0x01, 0x00031284}, + {0x02, 0x00098000}, {0x03, 0x00018c63}, + {0x04, 0x000210e7}, {0x09, 0x0002044f}, + {0x0a, 0x0001adb1}, {0x0b, 0x00054867}, + {0x0c, 0x0008992e}, {0x0d, 0x0000e52c}, + {0x0e, 0x00039ce7}, {0x0f, 0x00000451}, + {0x19, 0x00000000}, {0x1a, 0x00010255}, + {0x1b, 0x00060a00}, {0x1c, 0x000fc378}, + {0x1d, 0x000a1250}, {0x1e, 0x0004445f}, + {0x1f, 0x00080001}, {0x20, 0x0000b614}, + {0x21, 0x0006c000}, {0x22, 0x00000000}, + {0x23, 0x00001558}, {0x24, 0x00000060}, + {0x25, 0x00000483}, {0x26, 0x0004f000}, + {0x27, 0x000ec7d9}, {0x28, 0x000577c0}, + {0x29, 0x00004783}, {0x2a, 0x00000001}, + {0x2b, 0x00021334}, {0x2a, 0x00000000}, + {0x2b, 0x00000054}, {0x2a, 0x00000001}, + {0x2b, 0x00000808}, {0x2b, 0x00053333}, + {0x2c, 0x0000000c}, {0x2a, 0x00000002}, + {0x2b, 0x00000808}, {0x2b, 0x0005b333}, + {0x2c, 0x0000000d}, {0x2a, 0x00000003}, + {0x2b, 0x00000808}, {0x2b, 0x00063333}, + {0x2c, 0x0000000d}, {0x2a, 0x00000004}, + {0x2b, 0x00000808}, {0x2b, 0x0006b333}, + {0x2c, 0x0000000d}, {0x2a, 0x00000005}, + {0x2b, 0x00000808}, {0x2b, 0x00073333}, + {0x2c, 0x0000000d}, {0x2a, 0x00000006}, + {0x2b, 0x00000709}, {0x2b, 0x0005b333}, + {0x2c, 0x0000000d}, {0x2a, 0x00000007}, + {0x2b, 0x00000709}, {0x2b, 0x00063333}, + {0x2c, 0x0000000d}, {0x2a, 0x00000008}, + {0x2b, 0x0000060a}, {0x2b, 0x0004b333}, + {0x2c, 0x0000000d}, {0x2a, 0x00000009}, + {0x2b, 0x0000060a}, {0x2b, 0x00053333}, + {0x2c, 0x0000000d}, {0x2a, 0x0000000a}, + {0x2b, 0x0000060a}, {0x2b, 0x0005b333}, + {0x2c, 0x0000000d}, {0x2a, 0x0000000b}, + {0x2b, 0x0000060a}, {0x2b, 0x00063333}, + {0x2c, 0x0000000d}, {0x2a, 0x0000000c}, + {0x2b, 0x0000060a}, {0x2b, 0x0006b333}, + {0x2c, 0x0000000d}, {0x2a, 0x0000000d}, + {0x2b, 0x0000060a}, {0x2b, 0x00073333}, + {0x2c, 0x0000000d}, {0x2a, 0x0000000e}, + {0x2b, 0x0000050b}, {0x2b, 0x00066666}, + {0x2c, 0x0000001a}, {0x2a, 0x000e0000}, + {0x10, 0x0004000f}, {0x11, 0x000e31fc}, + {0x10, 0x0006000f}, {0x11, 0x000ff9f8}, + {0x10, 0x0002000f}, {0x11, 0x000203f9}, + {0x10, 0x0003000f}, {0x11, 0x000ff500}, + {0x10, 0x00000000}, {0x11, 0x00000000}, + {0x10, 0x0008000f}, {0x11, 0x0003f100}, + {0x10, 0x0009000f}, {0x11, 0x00023100}, + {0x12, 0x00032000}, {0x12, 0x00071000}, + {0x12, 0x000b0000}, {0x12, 0x000fc000}, + {0x13, 0x000287b3}, {0x13, 0x000244b7}, + {0x13, 0x000204ab}, {0x13, 0x0001c49f}, + {0x13, 0x00018493}, {0x13, 0x0001429b}, + {0x13, 0x00010299}, {0x13, 0x0000c29c}, + {0x13, 0x000081a0}, {0x13, 0x000040ac}, + {0x13, 0x00000020}, {0x14, 0x0001944c}, + {0x14, 0x00059444}, {0x14, 0x0009944c}, + {0x14, 0x000d9444}, {0x15, 0x0000f424}, + {0x15, 0x0004f424}, {0x15, 0x0008f424}, + {0x15, 0x000cf424}, {0x16, 0x000e0330}, + {0x16, 0x000a0330}, {0x16, 0x00060330}, + {0x16, 0x00020330}, {0x00, 0x00010159}, + {0x18, 0x0000f401}, {0xfe, 0x00000000}, + {0xfe, 0x00000000}, {0x1f, 0x00080003}, + {0xfe, 0x00000000}, {0xfe, 0x00000000}, + {0x1e, 0x00044457}, {0x1f, 0x00080000}, + {0x00, 0x00030159}, + {0xff, 0xffffffff} +}; + +static const struct rtl8xxxu_rfregval rtl8192cu_radiob_2t_init_table[] = { + {0x00, 0x00030159}, {0x01, 0x00031284}, + {0x02, 0x00098000}, {0x03, 0x00018c63}, + {0x04, 0x000210e7}, {0x09, 0x0002044f}, + {0x0a, 0x0001adb1}, {0x0b, 0x00054867}, + {0x0c, 0x0008992e}, {0x0d, 0x0000e52c}, + {0x0e, 0x00039ce7}, {0x0f, 0x00000451}, + {0x12, 0x00032000}, {0x12, 0x00071000}, + {0x12, 0x000b0000}, {0x12, 0x000fc000}, + {0x13, 0x000287af}, {0x13, 0x000244b7}, + {0x13, 0x000204ab}, {0x13, 0x0001c49f}, + {0x13, 0x00018493}, {0x13, 0x00014297}, + {0x13, 0x00010295}, {0x13, 0x0000c298}, + {0x13, 0x0000819c}, {0x13, 0x000040a8}, + {0x13, 0x0000001c}, {0x14, 0x0001944c}, + {0x14, 0x00059444}, {0x14, 0x0009944c}, + {0x14, 0x000d9444}, {0x15, 0x0000f424}, + {0x15, 0x0004f424}, {0x15, 0x0008f424}, + {0x15, 0x000cf424}, {0x16, 0x000e0330}, + {0x16, 0x000a0330}, {0x16, 0x00060330}, + {0x16, 0x00020330}, + {0xff, 0xffffffff} +}; + +static const struct rtl8xxxu_rfregval rtl8192cu_radioa_1t_init_table[] = { + {0x00, 0x00030159}, {0x01, 0x00031284}, + {0x02, 0x00098000}, {0x03, 0x00018c63}, + {0x04, 0x000210e7}, {0x09, 0x0002044f}, + {0x0a, 0x0001adb1}, {0x0b, 0x00054867}, + {0x0c, 0x0008992e}, {0x0d, 0x0000e52c}, + {0x0e, 0x00039ce7}, {0x0f, 0x00000451}, + {0x19, 0x00000000}, {0x1a, 0x00010255}, + {0x1b, 0x00060a00}, {0x1c, 0x000fc378}, + {0x1d, 0x000a1250}, {0x1e, 0x0004445f}, + {0x1f, 0x00080001}, {0x20, 0x0000b614}, + {0x21, 0x0006c000}, {0x22, 0x00000000}, + {0x23, 0x00001558}, {0x24, 0x00000060}, + {0x25, 0x00000483}, {0x26, 0x0004f000}, + {0x27, 0x000ec7d9}, {0x28, 0x000577c0}, + {0x29, 0x00004783}, {0x2a, 0x00000001}, + {0x2b, 0x00021334}, {0x2a, 0x00000000}, + {0x2b, 0x00000054}, {0x2a, 0x00000001}, + {0x2b, 0x00000808}, {0x2b, 0x00053333}, + {0x2c, 0x0000000c}, {0x2a, 0x00000002}, + {0x2b, 0x00000808}, {0x2b, 0x0005b333}, + {0x2c, 0x0000000d}, {0x2a, 0x00000003}, + {0x2b, 0x00000808}, {0x2b, 0x00063333}, + {0x2c, 0x0000000d}, {0x2a, 0x00000004}, + {0x2b, 0x00000808}, {0x2b, 0x0006b333}, + {0x2c, 0x0000000d}, {0x2a, 0x00000005}, + {0x2b, 0x00000808}, {0x2b, 0x00073333}, + {0x2c, 0x0000000d}, {0x2a, 0x00000006}, + {0x2b, 0x00000709}, {0x2b, 0x0005b333}, + {0x2c, 0x0000000d}, {0x2a, 0x00000007}, + {0x2b, 0x00000709}, {0x2b, 0x00063333}, + {0x2c, 0x0000000d}, {0x2a, 0x00000008}, + {0x2b, 0x0000060a}, {0x2b, 0x0004b333}, + {0x2c, 0x0000000d}, {0x2a, 0x00000009}, + {0x2b, 0x0000060a}, {0x2b, 0x00053333}, + {0x2c, 0x0000000d}, {0x2a, 0x0000000a}, + {0x2b, 0x0000060a}, {0x2b, 0x0005b333}, + {0x2c, 0x0000000d}, {0x2a, 0x0000000b}, + {0x2b, 0x0000060a}, {0x2b, 0x00063333}, + {0x2c, 0x0000000d}, {0x2a, 0x0000000c}, + {0x2b, 0x0000060a}, {0x2b, 0x0006b333}, + {0x2c, 0x0000000d}, {0x2a, 0x0000000d}, + {0x2b, 0x0000060a}, {0x2b, 0x00073333}, + {0x2c, 0x0000000d}, {0x2a, 0x0000000e}, + {0x2b, 0x0000050b}, {0x2b, 0x00066666}, + {0x2c, 0x0000001a}, {0x2a, 0x000e0000}, + {0x10, 0x0004000f}, {0x11, 0x000e31fc}, + {0x10, 0x0006000f}, {0x11, 0x000ff9f8}, + {0x10, 0x0002000f}, {0x11, 0x000203f9}, + {0x10, 0x0003000f}, {0x11, 0x000ff500}, + {0x10, 0x00000000}, {0x11, 0x00000000}, + {0x10, 0x0008000f}, {0x11, 0x0003f100}, + {0x10, 0x0009000f}, {0x11, 0x00023100}, + {0x12, 0x00032000}, {0x12, 0x00071000}, + {0x12, 0x000b0000}, {0x12, 0x000fc000}, + {0x13, 0x000287b3}, {0x13, 0x000244b7}, + {0x13, 0x000204ab}, {0x13, 0x0001c49f}, + {0x13, 0x00018493}, {0x13, 0x0001429b}, + {0x13, 0x00010299}, {0x13, 0x0000c29c}, + {0x13, 0x000081a0}, {0x13, 0x000040ac}, + {0x13, 0x00000020}, {0x14, 0x0001944c}, + {0x14, 0x00059444}, {0x14, 0x0009944c}, + {0x14, 0x000d9444}, {0x15, 0x0000f405}, + {0x15, 0x0004f405}, {0x15, 0x0008f405}, + {0x15, 0x000cf405}, {0x16, 0x000e0330}, + {0x16, 0x000a0330}, {0x16, 0x00060330}, + {0x16, 0x00020330}, {0x00, 0x00010159}, + {0x18, 0x0000f401}, {0xfe, 0x00000000}, + {0xfe, 0x00000000}, {0x1f, 0x00080003}, + {0xfe, 0x00000000}, {0xfe, 0x00000000}, + {0x1e, 0x00044457}, {0x1f, 0x00080000}, + {0x00, 0x00030159}, + {0xff, 0xffffffff} +}; + +static const struct rtl8xxxu_rfregval rtl8188ru_radioa_1t_highpa_table[] = { + {0x00, 0x00030159}, {0x01, 0x00031284}, + {0x02, 0x00098000}, {0x03, 0x00018c63}, + {0x04, 0x000210e7}, {0x09, 0x0002044f}, + {0x0a, 0x0001adb0}, {0x0b, 0x00054867}, + {0x0c, 0x0008992e}, {0x0d, 0x0000e529}, + {0x0e, 0x00039ce7}, {0x0f, 0x00000451}, + {0x19, 0x00000000}, {0x1a, 0x00000255}, + {0x1b, 0x00060a00}, {0x1c, 0x000fc378}, + {0x1d, 0x000a1250}, {0x1e, 0x0004445f}, + {0x1f, 0x00080001}, {0x20, 0x0000b614}, + {0x21, 0x0006c000}, {0x22, 0x0000083c}, + {0x23, 0x00001558}, {0x24, 0x00000060}, + {0x25, 0x00000483}, {0x26, 0x0004f000}, + {0x27, 0x000ec7d9}, {0x28, 0x000977c0}, + {0x29, 0x00004783}, {0x2a, 0x00000001}, + {0x2b, 0x00021334}, {0x2a, 0x00000000}, + {0x2b, 0x00000054}, {0x2a, 0x00000001}, + {0x2b, 0x00000808}, {0x2b, 0x00053333}, + {0x2c, 0x0000000c}, {0x2a, 0x00000002}, + {0x2b, 0x00000808}, {0x2b, 0x0005b333}, + {0x2c, 0x0000000d}, {0x2a, 0x00000003}, + {0x2b, 0x00000808}, {0x2b, 0x00063333}, + {0x2c, 0x0000000d}, {0x2a, 0x00000004}, + {0x2b, 0x00000808}, {0x2b, 0x0006b333}, + {0x2c, 0x0000000d}, {0x2a, 0x00000005}, + {0x2b, 0x00000808}, {0x2b, 0x00073333}, + {0x2c, 0x0000000d}, {0x2a, 0x00000006}, + {0x2b, 0x00000709}, {0x2b, 0x0005b333}, + {0x2c, 0x0000000d}, {0x2a, 0x00000007}, + {0x2b, 0x00000709}, {0x2b, 0x00063333}, + {0x2c, 0x0000000d}, {0x2a, 0x00000008}, + {0x2b, 0x0000060a}, {0x2b, 0x0004b333}, + {0x2c, 0x0000000d}, {0x2a, 0x00000009}, + {0x2b, 0x0000060a}, {0x2b, 0x00053333}, + {0x2c, 0x0000000d}, {0x2a, 0x0000000a}, + {0x2b, 0x0000060a}, {0x2b, 0x0005b333}, + {0x2c, 0x0000000d}, {0x2a, 0x0000000b}, + {0x2b, 0x0000060a}, {0x2b, 0x00063333}, + {0x2c, 0x0000000d}, {0x2a, 0x0000000c}, + {0x2b, 0x0000060a}, {0x2b, 0x0006b333}, + {0x2c, 0x0000000d}, {0x2a, 0x0000000d}, + {0x2b, 0x0000060a}, {0x2b, 0x00073333}, + {0x2c, 0x0000000d}, {0x2a, 0x0000000e}, + {0x2b, 0x0000050b}, {0x2b, 0x00066666}, + {0x2c, 0x0000001a}, {0x2a, 0x000e0000}, + {0x10, 0x0004000f}, {0x11, 0x000e31fc}, + {0x10, 0x0006000f}, {0x11, 0x000ff9f8}, + {0x10, 0x0002000f}, {0x11, 0x000203f9}, + {0x10, 0x0003000f}, {0x11, 0x000ff500}, + {0x10, 0x00000000}, {0x11, 0x00000000}, + {0x10, 0x0008000f}, {0x11, 0x0003f100}, + {0x10, 0x0009000f}, {0x11, 0x00023100}, + {0x12, 0x000d8000}, {0x12, 0x00090000}, + {0x12, 0x00051000}, {0x12, 0x00012000}, + {0x13, 0x00028fb4}, {0x13, 0x00024fa8}, + {0x13, 0x000207a4}, {0x13, 0x0001c3b0}, + {0x13, 0x000183a4}, {0x13, 0x00014398}, + {0x13, 0x000101a4}, {0x13, 0x0000c198}, + {0x13, 0x000080a4}, {0x13, 0x00004098}, + {0x13, 0x00000000}, {0x14, 0x0001944c}, + {0x14, 0x00059444}, {0x14, 0x0009944c}, + {0x14, 0x000d9444}, {0x15, 0x0000f405}, + {0x15, 0x0004f405}, {0x15, 0x0008f405}, + {0x15, 0x000cf405}, {0x16, 0x000e0330}, + {0x16, 0x000a0330}, {0x16, 0x00060330}, + {0x16, 0x00020330}, {0x00, 0x00010159}, + {0x18, 0x0000f401}, {0xfe, 0x00000000}, + {0xfe, 0x00000000}, {0x1f, 0x00080003}, + {0xfe, 0x00000000}, {0xfe, 0x00000000}, + {0x1e, 0x00044457}, {0x1f, 0x00080000}, + {0x00, 0x00030159}, + {0xff, 0xffffffff} +}; + +static int rtl8192cu_identify_chip(struct rtl8xxxu_priv *priv) +{ + struct device *dev = &priv->udev->dev; + u32 val32, bonding, sys_cfg, vendor; + int ret = 0; + + sys_cfg = rtl8xxxu_read32(priv, REG_SYS_CFG); + priv->chip_cut = u32_get_bits(sys_cfg, SYS_CFG_CHIP_VERSION_MASK); + if (sys_cfg & SYS_CFG_TRP_VAUX_EN) { + dev_info(dev, "Unsupported test chip\n"); + ret = -ENOTSUPP; + goto out; + } + + if (sys_cfg & SYS_CFG_TYPE_ID) { + bonding = rtl8xxxu_read32(priv, REG_HPON_FSM); + bonding &= HPON_FSM_BONDING_MASK; + if (bonding == HPON_FSM_BONDING_1T2R) { + strscpy(priv->chip_name, "8191CU", sizeof(priv->chip_name)); + priv->tx_paths = 1; + priv->usb_interrupts = 1; + priv->rtl_chip = RTL8191C; + } else { + strscpy(priv->chip_name, "8192CU", sizeof(priv->chip_name)); + priv->tx_paths = 2; + priv->usb_interrupts = 0; + priv->rtl_chip = RTL8192C; + } + priv->rf_paths = 2; + priv->rx_paths = 2; + } else { + strscpy(priv->chip_name, "8188CU", sizeof(priv->chip_name)); + priv->rf_paths = 1; + priv->rx_paths = 1; + priv->tx_paths = 1; + priv->rtl_chip = RTL8188C; + priv->usb_interrupts = 0; + } + priv->has_wifi = 1; + + vendor = sys_cfg & SYS_CFG_VENDOR_ID; + rtl8xxxu_identify_vendor_1bit(priv, vendor); + + val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS); + priv->rom_rev = u32_get_bits(val32, GPIO_RF_RL_ID); + + rtl8xxxu_config_endpoints_sie(priv); + + /* + * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX + */ + if (!priv->ep_tx_count) + ret = rtl8xxxu_config_endpoints_no_sie(priv); + +out: + return ret; +} + +static int rtl8192cu_load_firmware(struct rtl8xxxu_priv *priv) +{ + const char *fw_name; + int ret; + + if (!priv->vendor_umc) + fw_name = "rtlwifi/rtl8192cufw_TMSC.bin"; + else if (priv->chip_cut || priv->rtl_chip == RTL8192C) + fw_name = "rtlwifi/rtl8192cufw_B.bin"; + else + fw_name = "rtlwifi/rtl8192cufw_A.bin"; + + ret = rtl8xxxu_load_firmware(priv, fw_name); + + return ret; +} + +static int rtl8192cu_parse_efuse(struct rtl8xxxu_priv *priv) +{ + struct rtl8192cu_efuse *efuse = &priv->efuse_wifi.efuse8192; + + if (efuse->rtl_id != cpu_to_le16(0x8129)) + return -EINVAL; + + ether_addr_copy(priv->mac_addr, efuse->mac_addr); + + memcpy(priv->cck_tx_power_index_A, + efuse->cck_tx_power_index_A, + sizeof(efuse->cck_tx_power_index_A)); + memcpy(priv->cck_tx_power_index_B, + efuse->cck_tx_power_index_B, + sizeof(efuse->cck_tx_power_index_B)); + + memcpy(priv->ht40_1s_tx_power_index_A, + efuse->ht40_1s_tx_power_index_A, + sizeof(efuse->ht40_1s_tx_power_index_A)); + memcpy(priv->ht40_1s_tx_power_index_B, + efuse->ht40_1s_tx_power_index_B, + sizeof(efuse->ht40_1s_tx_power_index_B)); + memcpy(priv->ht40_2s_tx_power_index_diff, + efuse->ht40_2s_tx_power_index_diff, + sizeof(efuse->ht40_2s_tx_power_index_diff)); + + memcpy(priv->ht20_tx_power_index_diff, + efuse->ht20_tx_power_index_diff, + sizeof(efuse->ht20_tx_power_index_diff)); + memcpy(priv->ofdm_tx_power_index_diff, + efuse->ofdm_tx_power_index_diff, + sizeof(efuse->ofdm_tx_power_index_diff)); + + memcpy(priv->ht40_max_power_offset, + efuse->ht40_max_power_offset, + sizeof(efuse->ht40_max_power_offset)); + memcpy(priv->ht20_max_power_offset, + efuse->ht20_max_power_offset, + sizeof(efuse->ht20_max_power_offset)); + + priv->power_base = &rtl8192c_power_base; + + if (efuse->rf_regulatory & 0x20) { + strscpy(priv->chip_name, "8188RU", sizeof(priv->chip_name)); + priv->rtl_chip = RTL8188R; + priv->hi_pa = 1; + priv->no_pape = 1; + priv->power_base = &rtl8188r_power_base; + } + + return 0; +} + +static int rtl8192cu_init_phy_rf(struct rtl8xxxu_priv *priv) +{ + const struct rtl8xxxu_rfregval *rftable; + int ret; + + if (priv->rtl_chip == RTL8188R) { + rftable = rtl8188ru_radioa_1t_highpa_table; + ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A); + } else if (priv->rf_paths == 1) { + rftable = rtl8192cu_radioa_1t_init_table; + ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A); + } else { + rftable = rtl8192cu_radioa_2t_init_table; + ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A); + if (ret) + goto exit; + rftable = rtl8192cu_radiob_2t_init_table; + ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_B); + } + +exit: + return ret; +} + +static int rtl8192cu_power_on(struct rtl8xxxu_priv *priv) +{ + u8 val8; + u16 val16; + u32 val32; + int i; + + for (i = 100; i; i--) { + val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO); + if (val8 & APS_FSMCO_PFM_ALDN) + break; + } + + if (!i) { + pr_info("%s: Poll failed\n", __func__); + return -ENODEV; + } + + /* + * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register + */ + rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0); + rtl8xxxu_write8(priv, REG_SPS0_CTRL, 0x2b); + udelay(100); + + val8 = rtl8xxxu_read8(priv, REG_LDOV12D_CTRL); + if (!(val8 & LDOV12D_ENABLE)) { + pr_info("%s: Enabling LDOV12D (%02x)\n", __func__, val8); + val8 |= LDOV12D_ENABLE; + rtl8xxxu_write8(priv, REG_LDOV12D_CTRL, val8); + + udelay(100); + + val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL); + val8 &= ~SYS_ISO_MD2PP; + rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8); + } + + /* + * Auto enable WLAN + */ + val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO); + val16 |= APS_FSMCO_MAC_ENABLE; + rtl8xxxu_write16(priv, REG_APS_FSMCO, val16); + + for (i = 1000; i; i--) { + val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO); + if (!(val16 & APS_FSMCO_MAC_ENABLE)) + break; + } + if (!i) { + pr_info("%s: FSMCO_MAC_ENABLE poll failed\n", __func__); + return -EBUSY; + } + + /* + * Enable radio, GPIO, LED + */ + val16 = APS_FSMCO_HW_SUSPEND | APS_FSMCO_ENABLE_POWERDOWN | + APS_FSMCO_PFM_ALDN; + rtl8xxxu_write16(priv, REG_APS_FSMCO, val16); + + /* + * Release RF digital isolation + */ + val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL); + val16 &= ~SYS_ISO_DIOR; + rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16); + + val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL); + val8 &= ~APSD_CTRL_OFF; + rtl8xxxu_write8(priv, REG_APSD_CTRL, val8); + for (i = 200; i; i--) { + val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL); + if (!(val8 & APSD_CTRL_OFF_STATUS)) + break; + } + + if (!i) { + pr_info("%s: APSD_CTRL poll failed\n", __func__); + return -EBUSY; + } + + /* + * Enable MAC DMA/WMAC/SCHEDULE/SEC block + */ + val16 = rtl8xxxu_read16(priv, REG_CR); + val16 |= CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE | + CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | CR_PROTOCOL_ENABLE | + CR_SCHEDULE_ENABLE | CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE; + rtl8xxxu_write16(priv, REG_CR, val16); + + rtl8xxxu_write8(priv, 0xfe10, 0x19); + + /* + * Workaround for 8188RU LNA power leakage problem. + */ + if (priv->rtl_chip == RTL8188R) { + val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM); + val32 &= ~BIT(1); + rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32); + } + return 0; +} + +static int rtl8192cu_led_brightness_set(struct led_classdev *led_cdev, + enum led_brightness brightness) +{ + struct rtl8xxxu_priv *priv = container_of(led_cdev, + struct rtl8xxxu_priv, + led_cdev); + u8 ledcfg = rtl8xxxu_read8(priv, REG_LEDCFG0); + + if (brightness == LED_OFF) + ledcfg = LEDCFG2_SW_LED_CONTROL | LEDCFG2_SW_LED_DISABLE; + else if (brightness == LED_ON) + ledcfg = LEDCFG2_SW_LED_CONTROL; + else if (brightness == RTL8XXXU_HW_LED_CONTROL) + ledcfg = LEDCFG2_HW_LED_CONTROL | LEDCFG2_HW_LED_ENABLE; + + rtl8xxxu_write8(priv, REG_LEDCFG0, ledcfg); + + return 0; +} + +struct rtl8xxxu_fileops rtl8192cu_fops = { + .identify_chip = rtl8192cu_identify_chip, + .parse_efuse = rtl8192cu_parse_efuse, + .load_firmware = rtl8192cu_load_firmware, + .power_on = rtl8192cu_power_on, + .power_off = rtl8xxxu_power_off, + .read_efuse = rtl8xxxu_read_efuse, + .reset_8051 = rtl8xxxu_reset_8051, + .llt_init = rtl8xxxu_init_llt_table, + .init_phy_bb = rtl8xxxu_gen1_init_phy_bb, + .init_phy_rf = rtl8192cu_init_phy_rf, + .phy_lc_calibrate = rtl8723a_phy_lc_calibrate, + .phy_iq_calibrate = rtl8xxxu_gen1_phy_iq_calibrate, + .config_channel = rtl8xxxu_gen1_config_channel, + .parse_rx_desc = rtl8xxxu_parse_rxdesc16, + .parse_phystats = rtl8723au_rx_parse_phystats, + .init_aggregation = rtl8xxxu_gen1_init_aggregation, + .enable_rf = rtl8xxxu_gen1_enable_rf, + .disable_rf = rtl8xxxu_gen1_disable_rf, + .usb_quirks = rtl8xxxu_gen1_usb_quirks, + .set_tx_power = rtl8xxxu_gen1_set_tx_power, + .update_rate_mask = rtl8xxxu_update_rate_mask, + .report_connect = rtl8xxxu_gen1_report_connect, + .report_rssi = rtl8xxxu_gen1_report_rssi, + .fill_txdesc = rtl8xxxu_fill_txdesc_v1, + .cck_rssi = rtl8723a_cck_rssi, + .led_classdev_brightness_set = rtl8192cu_led_brightness_set, + .writeN_block_size = 128, + .rx_agg_buf_size = 16000, + .tx_desc_size = sizeof(struct rtl8xxxu_txdesc32), + .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc16), + .max_sec_cam_num = 32, + .adda_1t_init = 0x0b1b25a0, + .adda_1t_path_on = 0x0bdb25a0, + .adda_2t_path_on_a = 0x04db25a4, + .adda_2t_path_on_b = 0x0b1b25a4, + .trxff_boundary = 0x27ff, + .pbp_rx = PBP_PAGE_SIZE_128, + .pbp_tx = PBP_PAGE_SIZE_128, + .mactable = rtl8192cu_mac_init_table, + .total_page_num = TX_TOTAL_PAGE_NUM, + .page_num_hi = TX_PAGE_NUM_HI_PQ, + .page_num_lo = TX_PAGE_NUM_LO_PQ, + .page_num_norm = TX_PAGE_NUM_NORM_PQ, +}; +#endif diff --git a/drivers/net/wireless/realtek/rtl8xxxu/8192e.c b/drivers/net/wireless/realtek/rtl8xxxu/8192e.c new file mode 100644 index 000000000000..562173176c60 --- /dev/null +++ b/drivers/net/wireless/realtek/rtl8xxxu/8192e.c @@ -0,0 +1,1779 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * RTL8XXXU mac80211 USB driver - 8192e specific subdriver + * + * Copyright (c) 2014 - 2017 Jes Sorensen + * + * Portions, notably calibration code: + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This driver was written as a replacement for the vendor provided + * rtl8723au driver. As the Realtek 8xxx chips are very similar in + * their programming interface, I have started adding support for + * additional 8xxx chips like the 8192cu, 8188cus, etc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "rtl8xxxu.h" +#include "regs.h" + +static const struct rtl8xxxu_reg8val rtl8192e_mac_init_table[] = { + {0x011, 0xeb}, {0x012, 0x07}, {0x014, 0x75}, {0x303, 0xa7}, + {0x428, 0x0a}, {0x429, 0x10}, {0x430, 0x00}, {0x431, 0x00}, + {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05}, + {0x436, 0x07}, {0x437, 0x08}, {0x43c, 0x04}, {0x43d, 0x05}, + {0x43e, 0x07}, {0x43f, 0x08}, {0x440, 0x5d}, {0x441, 0x01}, + {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, {0x446, 0x00}, + {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xf0}, {0x44a, 0x0f}, + {0x44b, 0x3e}, {0x44c, 0x10}, {0x44d, 0x00}, {0x44e, 0x00}, + {0x44f, 0x00}, {0x450, 0x00}, {0x451, 0xf0}, {0x452, 0x0f}, + {0x453, 0x00}, {0x456, 0x5e}, {0x460, 0x66}, {0x461, 0x66}, + {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff}, {0x4cd, 0xff}, + {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2}, {0x502, 0x2f}, + {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3}, {0x506, 0x5e}, + {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4}, {0x50a, 0x5e}, + {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4}, {0x50e, 0x00}, + {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a}, {0x516, 0x0a}, + {0x525, 0x4f}, {0x540, 0x12}, {0x541, 0x64}, {0x550, 0x10}, + {0x551, 0x10}, {0x559, 0x02}, {0x55c, 0x50}, {0x55d, 0xff}, + {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a}, {0x620, 0xff}, + {0x621, 0xff}, {0x622, 0xff}, {0x623, 0xff}, {0x624, 0xff}, + {0x625, 0xff}, {0x626, 0xff}, {0x627, 0xff}, {0x638, 0x50}, + {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e}, {0x63f, 0x0e}, + {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00}, {0x652, 0xc8}, + {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43}, {0x702, 0x65}, + {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43}, {0x70a, 0x65}, + {0x70b, 0x87}, + {0xffff, 0xff}, +}; + +static const struct rtl8xxxu_reg32val rtl8192eu_phy_init_table[] = { + {0x800, 0x80040000}, {0x804, 0x00000003}, + {0x808, 0x0000fc00}, {0x80c, 0x0000000a}, + {0x810, 0x10001331}, {0x814, 0x020c3d10}, + {0x818, 0x02220385}, {0x81c, 0x00000000}, + {0x820, 0x01000100}, {0x824, 0x00390204}, + {0x828, 0x01000100}, {0x82c, 0x00390204}, + {0x830, 0x32323232}, {0x834, 0x30303030}, + {0x838, 0x30303030}, {0x83c, 0x30303030}, + {0x840, 0x00010000}, {0x844, 0x00010000}, + {0x848, 0x28282828}, {0x84c, 0x28282828}, + {0x850, 0x00000000}, {0x854, 0x00000000}, + {0x858, 0x009a009a}, {0x85c, 0x01000014}, + {0x860, 0x66f60000}, {0x864, 0x061f0000}, + {0x868, 0x30303030}, {0x86c, 0x30303030}, + {0x870, 0x00000000}, {0x874, 0x55004200}, + {0x878, 0x08080808}, {0x87c, 0x00000000}, + {0x880, 0xb0000c1c}, {0x884, 0x00000001}, + {0x888, 0x00000000}, {0x88c, 0xcc0000c0}, + {0x890, 0x00000800}, {0x894, 0xfffffffe}, + {0x898, 0x40302010}, {0x900, 0x00000000}, + {0x904, 0x00000023}, {0x908, 0x00000000}, + {0x90c, 0x81121313}, {0x910, 0x806c0001}, + {0x914, 0x00000001}, {0x918, 0x00000000}, + {0x91c, 0x00010000}, {0x924, 0x00000001}, + {0x928, 0x00000000}, {0x92c, 0x00000000}, + {0x930, 0x00000000}, {0x934, 0x00000000}, + {0x938, 0x00000000}, {0x93c, 0x00000000}, + {0x940, 0x00000000}, {0x944, 0x00000000}, + {0x94c, 0x00000008}, {0xa00, 0x00d0c7c8}, + {0xa04, 0x81ff000c}, {0xa08, 0x8c838300}, + {0xa0c, 0x2e68120f}, {0xa10, 0x95009b78}, + {0xa14, 0x1114d028}, {0xa18, 0x00881117}, + {0xa1c, 0x89140f00}, {0xa20, 0x1a1b0000}, + {0xa24, 0x090e1317}, {0xa28, 0x00000204}, + {0xa2c, 0x00d30000}, {0xa70, 0x101fff00}, + {0xa74, 0x00000007}, {0xa78, 0x00000900}, + {0xa7c, 0x225b0606}, {0xa80, 0x218075b1}, + {0xb38, 0x00000000}, {0xc00, 0x48071d40}, + {0xc04, 0x03a05633}, {0xc08, 0x000000e4}, + {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000}, + {0xc14, 0x40000100}, {0xc18, 0x08800000}, + {0xc1c, 0x40000100}, {0xc20, 0x00000000}, + {0xc24, 0x00000000}, {0xc28, 0x00000000}, + {0xc2c, 0x00000000}, {0xc30, 0x69e9ac47}, + {0xc34, 0x469652af}, {0xc38, 0x49795994}, + {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f}, + {0xc44, 0x000100b7}, {0xc48, 0xec020107}, + {0xc4c, 0x007f037f}, +#ifdef EXT_PA_8192EU + /* External PA or external LNA */ + {0xc50, 0x00340220}, +#else + {0xc50, 0x00340020}, +#endif + {0xc54, 0x0080801f}, +#ifdef EXT_PA_8192EU + /* External PA or external LNA */ + {0xc58, 0x00000220}, +#else + {0xc58, 0x00000020}, +#endif + {0xc5c, 0x00248492}, {0xc60, 0x00000000}, + {0xc64, 0x7112848b}, {0xc68, 0x47c00bff}, + {0xc6c, 0x00000036}, {0xc70, 0x00000600}, + {0xc74, 0x02013169}, {0xc78, 0x0000001f}, + {0xc7c, 0x00b91612}, +#ifdef EXT_PA_8192EU + /* External PA or external LNA */ + {0xc80, 0x2d4000b5}, +#else + {0xc80, 0x40000100}, +#endif + {0xc84, 0x21f60000}, +#ifdef EXT_PA_8192EU + /* External PA or external LNA */ + {0xc88, 0x2d4000b5}, +#else + {0xc88, 0x40000100}, +#endif + {0xc8c, 0xa0e40000}, {0xc90, 0x00121820}, + {0xc94, 0x00000000}, {0xc98, 0x00121820}, + {0xc9c, 0x00007f7f}, {0xca0, 0x00000000}, + {0xca4, 0x000300a0}, {0xca8, 0x00000000}, + {0xcac, 0x00000000}, {0xcb0, 0x00000000}, + {0xcb4, 0x00000000}, {0xcb8, 0x00000000}, + {0xcbc, 0x28000000}, {0xcc0, 0x00000000}, + {0xcc4, 0x00000000}, {0xcc8, 0x00000000}, + {0xccc, 0x00000000}, {0xcd0, 0x00000000}, + {0xcd4, 0x00000000}, {0xcd8, 0x64b22427}, + {0xcdc, 0x00766932}, {0xce0, 0x00222222}, + {0xce4, 0x00040000}, {0xce8, 0x77644302}, + {0xcec, 0x2f97d40c}, {0xd00, 0x00080740}, + {0xd04, 0x00020403}, {0xd08, 0x0000907f}, + {0xd0c, 0x20010201}, {0xd10, 0xa0633333}, + {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b}, + {0xd1c, 0x0000007f}, {0xd2c, 0xcc979975}, + {0xd30, 0x00000000}, {0xd34, 0x80608000}, + {0xd38, 0x00000000}, {0xd3c, 0x00127353}, + {0xd40, 0x00000000}, {0xd44, 0x00000000}, + {0xd48, 0x00000000}, {0xd4c, 0x00000000}, + {0xd50, 0x6437140a}, {0xd54, 0x00000000}, + {0xd58, 0x00000282}, {0xd5c, 0x30032064}, + {0xd60, 0x4653de68}, {0xd64, 0x04518a3c}, + {0xd68, 0x00002101}, {0xd6c, 0x2a201c16}, + {0xd70, 0x1812362e}, {0xd74, 0x322c2220}, + {0xd78, 0x000e3c24}, {0xd80, 0x01081008}, + {0xd84, 0x00000800}, {0xd88, 0xf0b50000}, + {0xe00, 0x30303030}, {0xe04, 0x30303030}, + {0xe08, 0x03903030}, {0xe10, 0x30303030}, + {0xe14, 0x30303030}, {0xe18, 0x30303030}, + {0xe1c, 0x30303030}, {0xe28, 0x00000000}, + {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f}, + {0xe38, 0x02140102}, {0xe3c, 0x681604c2}, + {0xe40, 0x01007c00}, {0xe44, 0x01004800}, + {0xe48, 0xfb000000}, {0xe4c, 0x000028d1}, + {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f}, + {0xe58, 0x02140102}, {0xe5c, 0x28160d05}, + {0xe60, 0x00000008}, {0xe68, 0x0fc05656}, + {0xe6c, 0x03c09696}, {0xe70, 0x03c09696}, + {0xe74, 0x0c005656}, {0xe78, 0x0c005656}, + {0xe7c, 0x0c005656}, {0xe80, 0x0c005656}, + {0xe84, 0x03c09696}, {0xe88, 0x0c005656}, + {0xe8c, 0x03c09696}, {0xed0, 0x03c09696}, + {0xed4, 0x03c09696}, {0xed8, 0x03c09696}, + {0xedc, 0x0000d6d6}, {0xee0, 0x0000d6d6}, + {0xeec, 0x0fc01616}, {0xee4, 0xb0000c1c}, + {0xee8, 0x00000001}, {0xf14, 0x00000003}, + {0xf4c, 0x00000000}, {0xf00, 0x00000300}, + {0xffff, 0xffffffff}, +}; + +static const struct rtl8xxxu_reg32val rtl8xxx_agc_8192eu_std_table[] = { + {0xc78, 0xfb000001}, {0xc78, 0xfb010001}, + {0xc78, 0xfb020001}, {0xc78, 0xfb030001}, + {0xc78, 0xfb040001}, {0xc78, 0xfb050001}, + {0xc78, 0xfa060001}, {0xc78, 0xf9070001}, + {0xc78, 0xf8080001}, {0xc78, 0xf7090001}, + {0xc78, 0xf60a0001}, {0xc78, 0xf50b0001}, + {0xc78, 0xf40c0001}, {0xc78, 0xf30d0001}, + {0xc78, 0xf20e0001}, {0xc78, 0xf10f0001}, + {0xc78, 0xf0100001}, {0xc78, 0xef110001}, + {0xc78, 0xee120001}, {0xc78, 0xed130001}, + {0xc78, 0xec140001}, {0xc78, 0xeb150001}, + {0xc78, 0xea160001}, {0xc78, 0xe9170001}, + {0xc78, 0xe8180001}, {0xc78, 0xe7190001}, + {0xc78, 0xc81a0001}, {0xc78, 0xc71b0001}, + {0xc78, 0xc61c0001}, {0xc78, 0x071d0001}, + {0xc78, 0x061e0001}, {0xc78, 0x051f0001}, + {0xc78, 0x04200001}, {0xc78, 0x03210001}, + {0xc78, 0xaa220001}, {0xc78, 0xa9230001}, + {0xc78, 0xa8240001}, {0xc78, 0xa7250001}, + {0xc78, 0xa6260001}, {0xc78, 0x85270001}, + {0xc78, 0x84280001}, {0xc78, 0x83290001}, + {0xc78, 0x252a0001}, {0xc78, 0x242b0001}, + {0xc78, 0x232c0001}, {0xc78, 0x222d0001}, + {0xc78, 0x672e0001}, {0xc78, 0x662f0001}, + {0xc78, 0x65300001}, {0xc78, 0x64310001}, + {0xc78, 0x63320001}, {0xc78, 0x62330001}, + {0xc78, 0x61340001}, {0xc78, 0x45350001}, + {0xc78, 0x44360001}, {0xc78, 0x43370001}, + {0xc78, 0x42380001}, {0xc78, 0x41390001}, + {0xc78, 0x403a0001}, {0xc78, 0x403b0001}, + {0xc78, 0x403c0001}, {0xc78, 0x403d0001}, + {0xc78, 0x403e0001}, {0xc78, 0x403f0001}, + {0xc78, 0xfb400001}, {0xc78, 0xfb410001}, + {0xc78, 0xfb420001}, {0xc78, 0xfb430001}, + {0xc78, 0xfb440001}, {0xc78, 0xfb450001}, + {0xc78, 0xfa460001}, {0xc78, 0xf9470001}, + {0xc78, 0xf8480001}, {0xc78, 0xf7490001}, + {0xc78, 0xf64a0001}, {0xc78, 0xf54b0001}, + {0xc78, 0xf44c0001}, {0xc78, 0xf34d0001}, + {0xc78, 0xf24e0001}, {0xc78, 0xf14f0001}, + {0xc78, 0xf0500001}, {0xc78, 0xef510001}, + {0xc78, 0xee520001}, {0xc78, 0xed530001}, + {0xc78, 0xec540001}, {0xc78, 0xeb550001}, + {0xc78, 0xea560001}, {0xc78, 0xe9570001}, + {0xc78, 0xe8580001}, {0xc78, 0xe7590001}, + {0xc78, 0xe65a0001}, {0xc78, 0xe55b0001}, + {0xc78, 0xe45c0001}, {0xc78, 0xe35d0001}, + {0xc78, 0xe25e0001}, {0xc78, 0xe15f0001}, + {0xc78, 0x8a600001}, {0xc78, 0x89610001}, + {0xc78, 0x88620001}, {0xc78, 0x87630001}, + {0xc78, 0x86640001}, {0xc78, 0x85650001}, + {0xc78, 0x84660001}, {0xc78, 0x83670001}, + {0xc78, 0x82680001}, {0xc78, 0x6b690001}, + {0xc78, 0x6a6a0001}, {0xc78, 0x696b0001}, + {0xc78, 0x686c0001}, {0xc78, 0x676d0001}, + {0xc78, 0x666e0001}, {0xc78, 0x656f0001}, + {0xc78, 0x64700001}, {0xc78, 0x63710001}, + {0xc78, 0x62720001}, {0xc78, 0x61730001}, + {0xc78, 0x49740001}, {0xc78, 0x48750001}, + {0xc78, 0x47760001}, {0xc78, 0x46770001}, + {0xc78, 0x45780001}, {0xc78, 0x44790001}, + {0xc78, 0x437a0001}, {0xc78, 0x427b0001}, + {0xc78, 0x417c0001}, {0xc78, 0x407d0001}, + {0xc78, 0x407e0001}, {0xc78, 0x407f0001}, + {0xc50, 0x00040022}, {0xc50, 0x00040020}, + {0xffff, 0xffffffff} +}; + +static const struct rtl8xxxu_reg32val rtl8xxx_agc_8192eu_highpa_table[] = { + {0xc78, 0xfa000001}, {0xc78, 0xf9010001}, + {0xc78, 0xf8020001}, {0xc78, 0xf7030001}, + {0xc78, 0xf6040001}, {0xc78, 0xf5050001}, + {0xc78, 0xf4060001}, {0xc78, 0xf3070001}, + {0xc78, 0xf2080001}, {0xc78, 0xf1090001}, + {0xc78, 0xf00a0001}, {0xc78, 0xef0b0001}, + {0xc78, 0xee0c0001}, {0xc78, 0xed0d0001}, + {0xc78, 0xec0e0001}, {0xc78, 0xeb0f0001}, + {0xc78, 0xea100001}, {0xc78, 0xe9110001}, + {0xc78, 0xe8120001}, {0xc78, 0xe7130001}, + {0xc78, 0xe6140001}, {0xc78, 0xe5150001}, + {0xc78, 0xe4160001}, {0xc78, 0xe3170001}, + {0xc78, 0xe2180001}, {0xc78, 0xe1190001}, + {0xc78, 0x8a1a0001}, {0xc78, 0x891b0001}, + {0xc78, 0x881c0001}, {0xc78, 0x871d0001}, + {0xc78, 0x861e0001}, {0xc78, 0x851f0001}, + {0xc78, 0x84200001}, {0xc78, 0x83210001}, + {0xc78, 0x82220001}, {0xc78, 0x6a230001}, + {0xc78, 0x69240001}, {0xc78, 0x68250001}, + {0xc78, 0x67260001}, {0xc78, 0x66270001}, + {0xc78, 0x65280001}, {0xc78, 0x64290001}, + {0xc78, 0x632a0001}, {0xc78, 0x622b0001}, + {0xc78, 0x612c0001}, {0xc78, 0x602d0001}, + {0xc78, 0x472e0001}, {0xc78, 0x462f0001}, + {0xc78, 0x45300001}, {0xc78, 0x44310001}, + {0xc78, 0x43320001}, {0xc78, 0x42330001}, + {0xc78, 0x41340001}, {0xc78, 0x40350001}, + {0xc78, 0x40360001}, {0xc78, 0x40370001}, + {0xc78, 0x40380001}, {0xc78, 0x40390001}, + {0xc78, 0x403a0001}, {0xc78, 0x403b0001}, + {0xc78, 0x403c0001}, {0xc78, 0x403d0001}, + {0xc78, 0x403e0001}, {0xc78, 0x403f0001}, + {0xc78, 0xfa400001}, {0xc78, 0xf9410001}, + {0xc78, 0xf8420001}, {0xc78, 0xf7430001}, + {0xc78, 0xf6440001}, {0xc78, 0xf5450001}, + {0xc78, 0xf4460001}, {0xc78, 0xf3470001}, + {0xc78, 0xf2480001}, {0xc78, 0xf1490001}, + {0xc78, 0xf04a0001}, {0xc78, 0xef4b0001}, + {0xc78, 0xee4c0001}, {0xc78, 0xed4d0001}, + {0xc78, 0xec4e0001}, {0xc78, 0xeb4f0001}, + {0xc78, 0xea500001}, {0xc78, 0xe9510001}, + {0xc78, 0xe8520001}, {0xc78, 0xe7530001}, + {0xc78, 0xe6540001}, {0xc78, 0xe5550001}, + {0xc78, 0xe4560001}, {0xc78, 0xe3570001}, + {0xc78, 0xe2580001}, {0xc78, 0xe1590001}, + {0xc78, 0x8a5a0001}, {0xc78, 0x895b0001}, + {0xc78, 0x885c0001}, {0xc78, 0x875d0001}, + {0xc78, 0x865e0001}, {0xc78, 0x855f0001}, + {0xc78, 0x84600001}, {0xc78, 0x83610001}, + {0xc78, 0x82620001}, {0xc78, 0x6a630001}, + {0xc78, 0x69640001}, {0xc78, 0x68650001}, + {0xc78, 0x67660001}, {0xc78, 0x66670001}, + {0xc78, 0x65680001}, {0xc78, 0x64690001}, + {0xc78, 0x636a0001}, {0xc78, 0x626b0001}, + {0xc78, 0x616c0001}, {0xc78, 0x606d0001}, + {0xc78, 0x476e0001}, {0xc78, 0x466f0001}, + {0xc78, 0x45700001}, {0xc78, 0x44710001}, + {0xc78, 0x43720001}, {0xc78, 0x42730001}, + {0xc78, 0x41740001}, {0xc78, 0x40750001}, + {0xc78, 0x40760001}, {0xc78, 0x40770001}, + {0xc78, 0x40780001}, {0xc78, 0x40790001}, + {0xc78, 0x407a0001}, {0xc78, 0x407b0001}, + {0xc78, 0x407c0001}, {0xc78, 0x407d0001}, + {0xc78, 0x407e0001}, {0xc78, 0x407f0001}, + {0xc50, 0x00040222}, {0xc50, 0x00040220}, + {0xffff, 0xffffffff} +}; + +static const struct rtl8xxxu_rfregval rtl8192eu_radioa_init_table[] = { + {0x7f, 0x00000082}, {0x81, 0x0003fc00}, + {0x00, 0x00030000}, {0x08, 0x00008400}, + {0x18, 0x00000407}, {0x19, 0x00000012}, + {0x1b, 0x00000064}, {0x1e, 0x00080009}, + {0x1f, 0x00000880}, {0x2f, 0x0001a060}, + {0x3f, 0x00000000}, {0x42, 0x000060c0}, + {0x57, 0x000d0000}, {0x58, 0x000be180}, + {0x67, 0x00001552}, {0x83, 0x00000000}, + {0xb0, 0x000ff9f1}, {0xb1, 0x00055418}, + {0xb2, 0x0008cc00}, {0xb4, 0x00043083}, + {0xb5, 0x00008166}, {0xb6, 0x0000803e}, + {0xb7, 0x0001c69f}, {0xb8, 0x0000407f}, + {0xb9, 0x00080001}, {0xba, 0x00040001}, + {0xbb, 0x00000400}, {0xbf, 0x000c0000}, + {0xc2, 0x00002400}, {0xc3, 0x00000009}, + {0xc4, 0x00040c91}, {0xc5, 0x00099999}, + {0xc6, 0x000000a3}, {0xc7, 0x00088820}, + {0xc8, 0x00076c06}, {0xc9, 0x00000000}, + {0xca, 0x00080000}, {0xdf, 0x00000180}, + {0xef, 0x000001a0}, {0x51, 0x00069545}, + {0x52, 0x0007e45e}, {0x53, 0x00000071}, + {0x56, 0x00051ff3}, {0x35, 0x000000a8}, + {0x35, 0x000001e2}, {0x35, 0x000002a8}, + {0x36, 0x00001c24}, {0x36, 0x00009c24}, + {0x36, 0x00011c24}, {0x36, 0x00019c24}, + {0x18, 0x00000c07}, {0x5a, 0x00048000}, + {0x19, 0x000739d0}, +#ifdef EXT_PA_8192EU + /* External PA or external LNA */ + {0x34, 0x0000a093}, {0x34, 0x0000908f}, + {0x34, 0x0000808c}, {0x34, 0x0000704d}, + {0x34, 0x0000604a}, {0x34, 0x00005047}, + {0x34, 0x0000400a}, {0x34, 0x00003007}, + {0x34, 0x00002004}, {0x34, 0x00001001}, + {0x34, 0x00000000}, +#else + /* Regular */ + {0x34, 0x0000add7}, {0x34, 0x00009dd4}, + {0x34, 0x00008dd1}, {0x34, 0x00007dce}, + {0x34, 0x00006dcb}, {0x34, 0x00005dc8}, + {0x34, 0x00004dc5}, {0x34, 0x000034cc}, + {0x34, 0x0000244f}, {0x34, 0x0000144c}, + {0x34, 0x00000014}, +#endif + {0x00, 0x00030159}, + {0x84, 0x00068180}, + {0x86, 0x0000014e}, + {0x87, 0x00048e00}, + {0x8e, 0x00065540}, + {0x8f, 0x00088000}, + {0xef, 0x000020a0}, +#ifdef EXT_PA_8192EU + /* External PA or external LNA */ + {0x3b, 0x000f07b0}, +#else + {0x3b, 0x000f02b0}, +#endif + {0x3b, 0x000ef7b0}, {0x3b, 0x000d4fb0}, + {0x3b, 0x000cf060}, {0x3b, 0x000b0090}, + {0x3b, 0x000a0080}, {0x3b, 0x00090080}, + {0x3b, 0x0008f780}, +#ifdef EXT_PA_8192EU + /* External PA or external LNA */ + {0x3b, 0x000787b0}, +#else + {0x3b, 0x00078730}, +#endif + {0x3b, 0x00060fb0}, {0x3b, 0x0005ffa0}, + {0x3b, 0x00040620}, {0x3b, 0x00037090}, + {0x3b, 0x00020080}, {0x3b, 0x0001f060}, + {0x3b, 0x0000ffb0}, {0xef, 0x000000a0}, + {0xfe, 0x00000000}, {0x18, 0x0000fc07}, + {0xfe, 0x00000000}, {0xfe, 0x00000000}, + {0xfe, 0x00000000}, {0xfe, 0x00000000}, + {0x1e, 0x00000001}, {0x1f, 0x00080000}, + {0x00, 0x00033e70}, + {0xff, 0xffffffff} +}; + +static const struct rtl8xxxu_rfregval rtl8192eu_radiob_init_table[] = { + {0x7f, 0x00000082}, {0x81, 0x0003fc00}, + {0x00, 0x00030000}, {0x08, 0x00008400}, + {0x18, 0x00000407}, {0x19, 0x00000012}, + {0x1b, 0x00000064}, {0x1e, 0x00080009}, + {0x1f, 0x00000880}, {0x2f, 0x0001a060}, + {0x3f, 0x00000000}, {0x42, 0x000060c0}, + {0x57, 0x000d0000}, {0x58, 0x000be180}, + {0x67, 0x00001552}, {0x7f, 0x00000082}, + {0x81, 0x0003f000}, {0x83, 0x00000000}, + {0xdf, 0x00000180}, {0xef, 0x000001a0}, + {0x51, 0x00069545}, {0x52, 0x0007e42e}, + {0x53, 0x00000071}, {0x56, 0x00051ff3}, + {0x35, 0x000000a8}, {0x35, 0x000001e0}, + {0x35, 0x000002a8}, {0x36, 0x00001ca8}, + {0x36, 0x00009c24}, {0x36, 0x00011c24}, + {0x36, 0x00019c24}, {0x18, 0x00000c07}, + {0x5a, 0x00048000}, {0x19, 0x000739d0}, +#ifdef EXT_PA_8192EU + /* External PA or external LNA */ + {0x34, 0x0000a093}, {0x34, 0x0000908f}, + {0x34, 0x0000808c}, {0x34, 0x0000704d}, + {0x34, 0x0000604a}, {0x34, 0x00005047}, + {0x34, 0x0000400a}, {0x34, 0x00003007}, + {0x34, 0x00002004}, {0x34, 0x00001001}, + {0x34, 0x00000000}, +#else + {0x34, 0x0000add7}, {0x34, 0x00009dd4}, + {0x34, 0x00008dd1}, {0x34, 0x00007dce}, + {0x34, 0x00006dcb}, {0x34, 0x00005dc8}, + {0x34, 0x00004dc5}, {0x34, 0x000034cc}, + {0x34, 0x0000244f}, {0x34, 0x0000144c}, + {0x34, 0x00000014}, +#endif + {0x00, 0x00030159}, {0x84, 0x00068180}, + {0x86, 0x000000ce}, {0x87, 0x00048a00}, + {0x8e, 0x00065540}, {0x8f, 0x00088000}, + {0xef, 0x000020a0}, +#ifdef EXT_PA_8192EU + /* External PA or external LNA */ + {0x3b, 0x000f07b0}, +#else + {0x3b, 0x000f02b0}, +#endif + + {0x3b, 0x000ef7b0}, {0x3b, 0x000d4fb0}, + {0x3b, 0x000cf060}, {0x3b, 0x000b0090}, + {0x3b, 0x000a0080}, {0x3b, 0x00090080}, + {0x3b, 0x0008f780}, +#ifdef EXT_PA_8192EU + /* External PA or external LNA */ + {0x3b, 0x000787b0}, +#else + {0x3b, 0x00078730}, +#endif + {0x3b, 0x00060fb0}, {0x3b, 0x0005ffa0}, + {0x3b, 0x00040620}, {0x3b, 0x00037090}, + {0x3b, 0x00020080}, {0x3b, 0x0001f060}, + {0x3b, 0x0000ffb0}, {0xef, 0x000000a0}, + {0x00, 0x00010159}, {0xfe, 0x00000000}, + {0xfe, 0x00000000}, {0xfe, 0x00000000}, + {0xfe, 0x00000000}, {0x1e, 0x00000001}, + {0x1f, 0x00080000}, {0x00, 0x00033e70}, + {0xff, 0xffffffff} +}; + +static int rtl8192eu_identify_chip(struct rtl8xxxu_priv *priv) +{ + struct device *dev = &priv->udev->dev; + u32 val32, bonding, sys_cfg, vendor; + int ret = 0; + + sys_cfg = rtl8xxxu_read32(priv, REG_SYS_CFG); + priv->chip_cut = u32_get_bits(sys_cfg, SYS_CFG_CHIP_VERSION_MASK); + if (sys_cfg & SYS_CFG_TRP_VAUX_EN) { + dev_info(dev, "Unsupported test chip\n"); + ret = -ENOTSUPP; + goto out; + } + + bonding = rtl8xxxu_read32(priv, REG_HPON_FSM); + bonding &= HPON_FSM_BONDING_MASK; + if (bonding == HPON_FSM_BONDING_1T2R) { + strscpy(priv->chip_name, "8191EU", sizeof(priv->chip_name)); + priv->tx_paths = 1; + priv->rtl_chip = RTL8191E; + } else { + strscpy(priv->chip_name, "8192EU", sizeof(priv->chip_name)); + priv->tx_paths = 2; + priv->rtl_chip = RTL8192E; + } + priv->rf_paths = 2; + priv->rx_paths = 2; + priv->has_wifi = 1; + + vendor = sys_cfg & SYS_CFG_VENDOR_EXT_MASK; + rtl8xxxu_identify_vendor_2bits(priv, vendor); + + val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS); + priv->rom_rev = u32_get_bits(val32, GPIO_RF_RL_ID); + + rtl8xxxu_config_endpoints_sie(priv); + + /* + * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX + */ + if (!priv->ep_tx_count) + ret = rtl8xxxu_config_endpoints_no_sie(priv); + +out: + return ret; +} + +static void +rtl8192e_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40) +{ + u32 val32, ofdm, mcs; + u8 cck, ofdmbase, mcsbase; + int group, tx_idx; + + tx_idx = 0; + group = rtl8xxxu_gen2_channel_to_group(channel); + + cck = priv->cck_tx_power_index_A[group]; + + val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32); + val32 &= 0xffff00ff; + val32 |= (cck << 8); + rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); + + val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); + val32 &= 0xff; + val32 |= ((cck << 8) | (cck << 16) | (cck << 24)); + rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); + + ofdmbase = priv->ht40_1s_tx_power_index_A[group]; + ofdmbase += priv->ofdm_tx_power_diff[tx_idx].a; + ofdm = ofdmbase | ofdmbase << 8 | ofdmbase << 16 | ofdmbase << 24; + + rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm); + rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm); + + mcsbase = priv->ht40_1s_tx_power_index_A[group]; + if (ht40) + mcsbase += priv->ht40_tx_power_diff[tx_idx++].a; + else + mcsbase += priv->ht20_tx_power_diff[tx_idx++].a; + mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24; + + rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs); + rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs); + rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs); + rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs); + + if (priv->tx_paths > 1) { + cck = priv->cck_tx_power_index_B[group]; + + val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32); + val32 &= 0xff; + val32 |= ((cck << 8) | (cck << 16) | (cck << 24)); + rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32); + + val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); + val32 &= 0xffffff00; + val32 |= cck; + rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); + + ofdmbase = priv->ht40_1s_tx_power_index_B[group]; + ofdmbase += priv->ofdm_tx_power_diff[tx_idx].b; + ofdm = ofdmbase | ofdmbase << 8 | + ofdmbase << 16 | ofdmbase << 24; + + rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, ofdm); + rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, ofdm); + + mcsbase = priv->ht40_1s_tx_power_index_B[group]; + if (ht40) + mcsbase += priv->ht40_tx_power_diff[tx_idx++].b; + else + mcsbase += priv->ht20_tx_power_diff[tx_idx++].b; + mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24; + + rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, mcs); + rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, mcs); + rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, mcs); + rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, mcs); + } +} + +static int rtl8192eu_parse_efuse(struct rtl8xxxu_priv *priv) +{ + struct rtl8192eu_efuse *efuse = &priv->efuse_wifi.efuse8192eu; + int i; + + if (efuse->rtl_id != cpu_to_le16(0x8129)) + return -EINVAL; + + ether_addr_copy(priv->mac_addr, efuse->mac_addr); + + memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base, + sizeof(efuse->tx_power_index_A.cck_base)); + memcpy(priv->cck_tx_power_index_B, efuse->tx_power_index_B.cck_base, + sizeof(efuse->tx_power_index_B.cck_base)); + + memcpy(priv->ht40_1s_tx_power_index_A, + efuse->tx_power_index_A.ht40_base, + sizeof(efuse->tx_power_index_A.ht40_base)); + memcpy(priv->ht40_1s_tx_power_index_B, + efuse->tx_power_index_B.ht40_base, + sizeof(efuse->tx_power_index_B.ht40_base)); + + priv->ht20_tx_power_diff[0].a = + efuse->tx_power_index_A.ht20_ofdm_1s_diff.b; + priv->ht20_tx_power_diff[0].b = + efuse->tx_power_index_B.ht20_ofdm_1s_diff.b; + + priv->ht40_tx_power_diff[0].a = 0; + priv->ht40_tx_power_diff[0].b = 0; + + for (i = 1; i < RTL8723B_TX_COUNT; i++) { + priv->ofdm_tx_power_diff[i].a = + efuse->tx_power_index_A.pwr_diff[i - 1].ofdm; + priv->ofdm_tx_power_diff[i].b = + efuse->tx_power_index_B.pwr_diff[i - 1].ofdm; + + priv->ht20_tx_power_diff[i].a = + efuse->tx_power_index_A.pwr_diff[i - 1].ht20; + priv->ht20_tx_power_diff[i].b = + efuse->tx_power_index_B.pwr_diff[i - 1].ht20; + + priv->ht40_tx_power_diff[i].a = + efuse->tx_power_index_A.pwr_diff[i - 1].ht40; + priv->ht40_tx_power_diff[i].b = + efuse->tx_power_index_B.pwr_diff[i - 1].ht40; + } + + priv->default_crystal_cap = priv->efuse_wifi.efuse8192eu.xtal_k & 0x3f; + + return 0; +} + +static int rtl8192eu_load_firmware(struct rtl8xxxu_priv *priv) +{ + const char *fw_name; + int ret; + + fw_name = "rtlwifi/rtl8192eu_nic.bin"; + + ret = rtl8xxxu_load_firmware(priv, fw_name); + + return ret; +} + +static void rtl8192eu_init_phy_bb(struct rtl8xxxu_priv *priv) +{ + u8 val8; + u16 val16; + + val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); + val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB | SYS_FUNC_DIO_RF; + rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); + + /* 6. 0x1f[7:0] = 0x07 */ + val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB; + rtl8xxxu_write8(priv, REG_RF_CTRL, val8); + + val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); + val16 |= (SYS_FUNC_USBA | SYS_FUNC_USBD | SYS_FUNC_DIO_RF | + SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB); + rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); + val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB; + rtl8xxxu_write8(priv, REG_RF_CTRL, val8); + rtl8xxxu_init_phy_regs(priv, rtl8192eu_phy_init_table); + + if (priv->hi_pa) + rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8192eu_highpa_table); + else + rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8192eu_std_table); +} + +static int rtl8192eu_init_phy_rf(struct rtl8xxxu_priv *priv) +{ + int ret; + + ret = rtl8xxxu_init_phy_rf(priv, rtl8192eu_radioa_init_table, RF_A); + if (ret) + goto exit; + + ret = rtl8xxxu_init_phy_rf(priv, rtl8192eu_radiob_init_table, RF_B); + +exit: + return ret; +} + +static int rtl8192eu_iqk_path_a(struct rtl8xxxu_priv *priv) +{ + u32 reg_eac, reg_e94, reg_e9c; + int result = 0; + + /* + * TX IQK + * PA/PAD controlled by 0x0 + */ + rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x00180); + + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x20000); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0x07f77); + + rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); + + /* Path A IQK setting */ + rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); + rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); + rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); + rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); + + rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140303); + rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x68160000); + + /* LO calibration setting */ + rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911); + + /* One shot, path A LOK & IQK */ + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); + + mdelay(10); + + /* Check failed */ + reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); + reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); + reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); + + if (!(reg_eac & BIT(28)) && + ((reg_e94 & 0x03ff0000) != 0x01420000) && + ((reg_e9c & 0x03ff0000) != 0x00420000)) + result |= 0x01; + + return result; +} + +static int rtl8192eu_rx_iqk_path_a(struct rtl8xxxu_priv *priv) +{ + u32 reg_ea4, reg_eac, reg_e94, reg_e9c, val32; + int result = 0; + + /* Leave IQK mode */ + rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00); + + /* Enable path A PA in TX IQK mode */ + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf1173); + + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0); + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000); + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f); + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf1173); + + /* PA/PAD control by 0x56, and set = 0x0 */ + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x00980); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_PAD_TXG, 0x511e0); + + /* Enter IQK mode */ + rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); + + /* TX IQK setting */ + rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); + rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); + + /* path-A IQK setting */ + rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); + rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); + rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); + rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); + + rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x8216031f); + rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x6816031f); + + /* LO calibration setting */ + rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911); + + /* One shot, path A LOK & IQK */ + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); + + mdelay(10); + + /* Check failed */ + reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); + reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); + reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); + + if (!(reg_eac & BIT(28)) && + ((reg_e94 & 0x03ff0000) != 0x01420000) && + ((reg_e9c & 0x03ff0000) != 0x00420000)) { + result |= 0x01; + } else { + /* PA/PAD controlled by 0x0 */ + rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x180); + goto out; + } + + val32 = 0x80007c00 | + (reg_e94 & 0x03ff0000) | ((reg_e9c >> 16) & 0x03ff); + rtl8xxxu_write32(priv, REG_TX_IQK, val32); + + /* Modify RX IQK mode table */ + rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); + + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7ff2); + + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0); + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000); + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f); + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf7ff2); + + /* PA/PAD control by 0x56, and set = 0x0 */ + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x00980); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_PAD_TXG, 0x510e0); + + /* Enter IQK mode */ + rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); + + /* IQK setting */ + rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); + + /* Path A IQK setting */ + rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); + rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c); + rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); + rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); + + rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821608ff); + rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x281608ff); + + /* LO calibration setting */ + rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a891); + + /* One shot, path A LOK & IQK */ + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); + + mdelay(10); + + reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); + reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); + + rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x180); + + if (!(reg_eac & BIT(27)) && + ((reg_ea4 & 0x03ff0000) != 0x01320000) && + ((reg_eac & 0x03ff0000) != 0x00360000)) + result |= 0x02; + else + dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n", + __func__); + +out: + return result; +} + +static int rtl8192eu_iqk_path_b(struct rtl8xxxu_priv *priv) +{ + u32 reg_eac, reg_eb4, reg_ebc; + int result = 0; + + rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_CCA, 0x00180); + + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0); + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x20000); + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f); + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0x07f77); + + rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); + + /* Path B IQK setting */ + rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); + rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); + rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x18008c1c); + rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); + + rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140303); + rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x68160000); + + /* LO calibration setting */ + rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911); + + /* One shot, path A LOK & IQK */ + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000); + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); + + mdelay(1); + + /* Check failed */ + reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); + reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); + reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); + + if (!(reg_eac & BIT(31)) && + ((reg_eb4 & 0x03ff0000) != 0x01420000) && + ((reg_ebc & 0x03ff0000) != 0x00420000)) + result |= 0x01; + else + dev_warn(&priv->udev->dev, "%s: Path B IQK failed!\n", + __func__); + + return result; +} + +static int rtl8192eu_rx_iqk_path_b(struct rtl8xxxu_priv *priv) +{ + u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc, val32; + int result = 0; + + /* Leave IQK mode */ + rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); + + /* Enable path A PA in TX IQK mode */ + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0); + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000); + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f); + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf1173); + + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf1173); + + /* PA/PAD control by 0x56, and set = 0x0 */ + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_CCA, 0x00980); + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_PAD_TXG, 0x511e0); + + /* Enter IQK mode */ + rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); + + /* TX IQK setting */ + rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); + rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); + + /* path-A IQK setting */ + rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); + rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); + rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x18008c1c); + rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); + + rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x8216031f); + rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x6816031f); + + /* LO calibration setting */ + rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911); + + /* One shot, path A LOK & IQK */ + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000); + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); + + mdelay(10); + + /* Check failed */ + reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); + reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); + reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); + + if (!(reg_eac & BIT(31)) && + ((reg_eb4 & 0x03ff0000) != 0x01420000) && + ((reg_ebc & 0x03ff0000) != 0x00420000)) { + result |= 0x01; + } else { + /* + * PA/PAD controlled by 0x0 + * Vendor driver restores RF_A here which I believe is a bug + */ + rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_CCA, 0x180); + goto out; + } + + val32 = 0x80007c00 | + (reg_eb4 & 0x03ff0000) | ((reg_ebc >> 16) & 0x03ff); + rtl8xxxu_write32(priv, REG_TX_IQK, val32); + + /* Modify RX IQK mode table */ + rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); + + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0); + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000); + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f); + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf7ff2); + + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7ff2); + + /* PA/PAD control by 0x56, and set = 0x0 */ + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_CCA, 0x00980); + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_PAD_TXG, 0x510e0); + + /* Enter IQK mode */ + rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); + + /* IQK setting */ + rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); + + /* Path A IQK setting */ + rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); + rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); + rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); + rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x18008c1c); + + rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821608ff); + rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x281608ff); + + /* LO calibration setting */ + rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a891); + + /* One shot, path A LOK & IQK */ + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000); + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); + + mdelay(10); + + reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); + reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2); + reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2); + + rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_CCA, 0x180); + + if (!(reg_eac & BIT(30)) && + ((reg_ec4 & 0x03ff0000) != 0x01320000) && + ((reg_ecc & 0x03ff0000) != 0x00360000)) + result |= 0x02; + else + dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n", + __func__); + +out: + return result; +} + +static void rtl8192eu_phy_iqcalibrate(struct rtl8xxxu_priv *priv, + int result[][8], int t) +{ + struct device *dev = &priv->udev->dev; + u32 i, val32; + int path_a_ok, path_b_ok; + int retry = 2; + static const u32 adda_regs[RTL8XXXU_ADDA_REGS] = { + REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH, + REG_RX_WAIT_CCA, REG_TX_CCK_RFON, + REG_TX_CCK_BBON, REG_TX_OFDM_RFON, + REG_TX_OFDM_BBON, REG_TX_TO_RX, + REG_TX_TO_TX, REG_RX_CCK, + REG_RX_OFDM, REG_RX_WAIT_RIFS, + REG_RX_TO_RX, REG_STANDBY, + REG_SLEEP, REG_PMPD_ANAEN + }; + static const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = { + REG_TXPAUSE, REG_BEACON_CTRL, + REG_BEACON_CTRL_1, REG_GPIO_MUXCFG + }; + static const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = { + REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR, + REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, + REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE, + REG_FPGA0_XB_RF_INT_OE, REG_CCK0_AFE_SETTING + }; + u8 xa_agc = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1) & 0xff; + u8 xb_agc = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1) & 0xff; + + /* + * Note: IQ calibration must be performed after loading + * PHY_REG.txt , and radio_a, radio_b.txt + */ + + if (t == 0) { + /* Save ADDA parameters, turn Path A ADDA on */ + rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup, + RTL8XXXU_ADDA_REGS); + rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup); + rtl8xxxu_save_regs(priv, iqk_bb_regs, + priv->bb_backup, RTL8XXXU_BB_REGS); + } + + rtl8xxxu_path_adda_on(priv, adda_regs, true); + + /* MAC settings */ + rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup); + + val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING); + val32 |= 0x0f000000; + rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32); + + rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600); + rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4); + rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22208200); + + val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL); + val32 |= (FPGA0_RF_PAPE | (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT)); + rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32); + + val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE); + val32 |= BIT(10); + rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32); + val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE); + val32 |= BIT(10); + rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32); + + rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); + rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); + rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); + + for (i = 0; i < retry; i++) { + path_a_ok = rtl8192eu_iqk_path_a(priv); + if (path_a_ok == 0x01) { + val32 = rtl8xxxu_read32(priv, + REG_TX_POWER_BEFORE_IQK_A); + result[t][0] = (val32 >> 16) & 0x3ff; + val32 = rtl8xxxu_read32(priv, + REG_TX_POWER_AFTER_IQK_A); + result[t][1] = (val32 >> 16) & 0x3ff; + + break; + } + } + + if (!path_a_ok) + dev_dbg(dev, "%s: Path A TX IQK failed!\n", __func__); + + for (i = 0; i < retry; i++) { + path_a_ok = rtl8192eu_rx_iqk_path_a(priv); + if (path_a_ok == 0x03) { + val32 = rtl8xxxu_read32(priv, + REG_RX_POWER_BEFORE_IQK_A_2); + result[t][2] = (val32 >> 16) & 0x3ff; + val32 = rtl8xxxu_read32(priv, + REG_RX_POWER_AFTER_IQK_A_2); + result[t][3] = (val32 >> 16) & 0x3ff; + + break; + } + } + + if (!path_a_ok) + dev_dbg(dev, "%s: Path A RX IQK failed!\n", __func__); + + if (priv->rf_paths > 1) { + /* Path A into standby */ + rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x10000); + rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); + + /* Turn Path B ADDA on */ + rtl8xxxu_path_adda_on(priv, adda_regs, false); + + rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); + rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); + rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); + + for (i = 0; i < retry; i++) { + path_b_ok = rtl8192eu_iqk_path_b(priv); + if (path_b_ok == 0x01) { + val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); + result[t][4] = (val32 >> 16) & 0x3ff; + val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); + result[t][5] = (val32 >> 16) & 0x3ff; + break; + } + } + + if (!path_b_ok) + dev_dbg(dev, "%s: Path B IQK failed!\n", __func__); + + for (i = 0; i < retry; i++) { + path_b_ok = rtl8192eu_rx_iqk_path_b(priv); + if (path_b_ok == 0x03) { + val32 = rtl8xxxu_read32(priv, + REG_RX_POWER_BEFORE_IQK_B_2); + result[t][6] = (val32 >> 16) & 0x3ff; + val32 = rtl8xxxu_read32(priv, + REG_RX_POWER_AFTER_IQK_B_2); + result[t][7] = (val32 >> 16) & 0x3ff; + break; + } + } + + if (!path_b_ok) + dev_dbg(dev, "%s: Path B RX IQK failed!\n", __func__); + } + + /* Back to BB mode, load original value */ + rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); + + if (t) { + /* Reload ADDA power saving parameters */ + rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup, + RTL8XXXU_ADDA_REGS); + + /* Reload MAC parameters */ + rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup); + + /* Reload BB parameters */ + rtl8xxxu_restore_regs(priv, iqk_bb_regs, + priv->bb_backup, RTL8XXXU_BB_REGS); + + /* Restore RX initial gain */ + val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); + val32 &= 0xffffff00; + rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | 0x50); + rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | xa_agc); + + if (priv->rf_paths > 1) { + val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1); + val32 &= 0xffffff00; + rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1, + val32 | 0x50); + rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1, + val32 | xb_agc); + } + + /* Load 0xe30 IQC default value */ + rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00); + rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00); + } +} + +static void rtl8192eu_phy_iq_calibrate(struct rtl8xxxu_priv *priv) +{ + struct device *dev = &priv->udev->dev; + int result[4][8]; /* last is final result */ + int i, candidate; + bool path_a_ok, path_b_ok; + u32 reg_e94, reg_e9c, reg_ea4, reg_eac; + u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc; + bool simu; + + memset(result, 0, sizeof(result)); + candidate = -1; + + path_a_ok = false; + path_b_ok = false; + + for (i = 0; i < 3; i++) { + rtl8192eu_phy_iqcalibrate(priv, result, i); + + if (i == 1) { + simu = rtl8xxxu_gen2_simularity_compare(priv, + result, 0, 1); + if (simu) { + candidate = 0; + break; + } + } + + if (i == 2) { + simu = rtl8xxxu_gen2_simularity_compare(priv, + result, 0, 2); + if (simu) { + candidate = 0; + break; + } + + simu = rtl8xxxu_gen2_simularity_compare(priv, + result, 1, 2); + if (simu) + candidate = 1; + else + candidate = 3; + } + } + + for (i = 0; i < 4; i++) { + reg_e94 = result[i][0]; + reg_e9c = result[i][1]; + reg_ea4 = result[i][2]; + reg_eb4 = result[i][4]; + reg_ebc = result[i][5]; + reg_ec4 = result[i][6]; + } + + if (candidate >= 0) { + reg_e94 = result[candidate][0]; + priv->rege94 = reg_e94; + reg_e9c = result[candidate][1]; + priv->rege9c = reg_e9c; + reg_ea4 = result[candidate][2]; + reg_eac = result[candidate][3]; + reg_eb4 = result[candidate][4]; + priv->regeb4 = reg_eb4; + reg_ebc = result[candidate][5]; + priv->regebc = reg_ebc; + reg_ec4 = result[candidate][6]; + reg_ecc = result[candidate][7]; + dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate); + dev_dbg(dev, + "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x ecc=%x\n", + __func__, reg_e94, reg_e9c, + reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc); + path_a_ok = true; + path_b_ok = true; + } else { + reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100; + reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0; + } + + if (reg_e94 && candidate >= 0) + rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result, + candidate, (reg_ea4 == 0)); + + if (priv->rf_paths > 1) + rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result, + candidate, (reg_ec4 == 0)); + + rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg, + priv->bb_recovery_backup, RTL8XXXU_BB_REGS); +} + +/* + * This is needed for 8723bu as well, presumable + */ +static void rtl8192e_crystal_afe_adjust(struct rtl8xxxu_priv *priv) +{ + u8 val8; + u32 val32; + + /* + * 40Mhz crystal source, MAC 0x28[2]=0 + */ + val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL); + val8 &= 0xfb; + rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8); + + val32 = rtl8xxxu_read32(priv, REG_AFE_CTRL4); + val32 &= 0xfffffc7f; + rtl8xxxu_write32(priv, REG_AFE_CTRL4, val32); + + /* + * 92e AFE parameter + * AFE PLL KVCO selection, MAC 0x28[6]=1 + */ + val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL); + val8 &= 0xbf; + rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8); + + /* + * AFE PLL KVCO selection, MAC 0x78[21]=0 + */ + val32 = rtl8xxxu_read32(priv, REG_AFE_CTRL4); + val32 &= 0xffdfffff; + rtl8xxxu_write32(priv, REG_AFE_CTRL4, val32); +} + +static void rtl8192e_disabled_to_emu(struct rtl8xxxu_priv *priv) +{ + u8 val8; + + /* Clear suspend enable and power down enable*/ + val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); + val8 &= ~(BIT(3) | BIT(4)); + rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); +} + +static int rtl8192e_emu_to_active(struct rtl8xxxu_priv *priv) +{ + u8 val8; + u32 val32; + int count, ret = 0; + + /* disable HWPDN 0x04[15]=0*/ + val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); + val8 &= ~BIT(7); + rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); + + /* disable SW LPS 0x04[10]= 0 */ + val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); + val8 &= ~BIT(2); + rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); + + /* disable WL suspend*/ + val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); + val8 &= ~(BIT(3) | BIT(4)); + rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); + + /* wait till 0x04[17] = 1 power ready*/ + for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { + val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); + if (val32 & BIT(17)) + break; + + udelay(10); + } + + if (!count) { + ret = -EBUSY; + goto exit; + } + + /* We should be able to optimize the following three entries into one */ + + /* release WLON reset 0x04[16]= 1*/ + val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2); + val8 |= BIT(0); + rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8); + + /* set, then poll until 0 */ + val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); + val32 |= APS_FSMCO_MAC_ENABLE; + rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); + + for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { + val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); + if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) { + ret = 0; + break; + } + udelay(10); + } + + if (!count) { + ret = -EBUSY; + goto exit; + } + +exit: + return ret; +} + +static int rtl8192eu_active_to_lps(struct rtl8xxxu_priv *priv) +{ + struct device *dev = &priv->udev->dev; + u8 val8; + u16 val16; + u32 val32; + int retry, retval; + + rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); + + retry = 100; + retval = -EBUSY; + /* + * Poll 32 bit wide 0x05f8 for 0x00000000 to ensure no TX is pending. + */ + do { + val32 = rtl8xxxu_read32(priv, REG_SCH_TX_CMD); + if (!val32) { + retval = 0; + break; + } + } while (retry--); + + if (!retry) { + dev_warn(dev, "Failed to flush TX queue\n"); + retval = -EBUSY; + goto out; + } + + /* Disable CCK and OFDM, clock gated */ + val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); + val8 &= ~SYS_FUNC_BBRSTB; + rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); + + udelay(2); + + /* Reset whole BB */ + val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); + val8 &= ~SYS_FUNC_BB_GLB_RSTN; + rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); + + /* Reset MAC TRX */ + val16 = rtl8xxxu_read16(priv, REG_CR); + val16 &= 0xff00; + val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE); + rtl8xxxu_write16(priv, REG_CR, val16); + + val16 = rtl8xxxu_read16(priv, REG_CR); + val16 &= ~CR_SECURITY_ENABLE; + rtl8xxxu_write16(priv, REG_CR, val16); + + val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST); + val8 |= DUAL_TSF_TX_OK; + rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8); + +out: + return retval; +} + +static int rtl8192eu_active_to_emu(struct rtl8xxxu_priv *priv) +{ + u8 val8; + int count, ret = 0; + + /* Turn off RF */ + val8 = rtl8xxxu_read8(priv, REG_RF_CTRL); + val8 &= ~RF_ENABLE; + rtl8xxxu_write8(priv, REG_RF_CTRL, val8); + + /* Switch DPDT_SEL_P output from register 0x65[2] */ + val8 = rtl8xxxu_read8(priv, REG_LEDCFG2); + val8 &= ~LEDCFG2_DPDT_SELECT; + rtl8xxxu_write8(priv, REG_LEDCFG2, val8); + + /* 0x0005[1] = 1 turn off MAC by HW state machine*/ + val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); + val8 |= BIT(1); + rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); + + for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { + val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); + if ((val8 & BIT(1)) == 0) + break; + udelay(10); + } + + if (!count) { + dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n", + __func__); + ret = -EBUSY; + goto exit; + } + +exit: + return ret; +} + +static int rtl8192eu_emu_to_disabled(struct rtl8xxxu_priv *priv) +{ + u8 val8; + + /* 0x04[12:11] = 01 enable WL suspend */ + val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); + val8 &= ~(BIT(3) | BIT(4)); + val8 |= BIT(3); + rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); + + return 0; +} + +static int rtl8192eu_power_on(struct rtl8xxxu_priv *priv) +{ + u16 val16; + u32 val32; + int ret; + + val32 = rtl8xxxu_read32(priv, REG_SYS_CFG); + if (val32 & SYS_CFG_SPS_LDO_SEL) { + rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0xc3); + } else { + /* + * Raise 1.2V voltage + */ + val32 = rtl8xxxu_read32(priv, REG_8192E_LDOV12_CTRL); + val32 &= 0xff0fffff; + val32 |= 0x00500000; + rtl8xxxu_write32(priv, REG_8192E_LDOV12_CTRL, val32); + rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0x83); + } + + /* + * Adjust AFE before enabling PLL + */ + rtl8192e_crystal_afe_adjust(priv); + rtl8192e_disabled_to_emu(priv); + + ret = rtl8192e_emu_to_active(priv); + if (ret) + goto exit; + + rtl8xxxu_write16(priv, REG_CR, 0x0000); + + /* + * Enable MAC DMA/WMAC/SCHEDULE/SEC block + * Set CR bit10 to enable 32k calibration. + */ + val16 = rtl8xxxu_read16(priv, REG_CR); + val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE | + CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | + CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE | + CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE | + CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE); + rtl8xxxu_write16(priv, REG_CR, val16); + +exit: + return ret; +} + +static void rtl8192eu_power_off(struct rtl8xxxu_priv *priv) +{ + u8 val8; + u16 val16; + + rtl8xxxu_flush_fifo(priv); + + val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL); + val8 &= ~TX_REPORT_CTRL_TIMER_ENABLE; + rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8); + + /* Turn off RF */ + rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00); + + rtl8192eu_active_to_lps(priv); + + /* Reset Firmware if running in RAM */ + if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL) + rtl8xxxu_firmware_self_reset(priv); + + /* Reset MCU */ + val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); + val16 &= ~SYS_FUNC_CPU_ENABLE; + rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); + + /* Reset MCU ready status */ + rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00); + + rtl8xxxu_reset_8051(priv); + + rtl8192eu_active_to_emu(priv); + rtl8192eu_emu_to_disabled(priv); +} + +static void rtl8192e_enable_rf(struct rtl8xxxu_priv *priv) +{ + u32 val32; + u8 val8; + + val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA); + val32 |= (BIT(22) | BIT(23)); + rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32); + + val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG); + val8 |= BIT(5); + rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8); + + /* + * WLAN action by PTA + */ + rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04); + + val32 = rtl8xxxu_read32(priv, REG_PWR_DATA); + val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN; + rtl8xxxu_write32(priv, REG_PWR_DATA, val32); + + val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER); + val32 |= (BIT(0) | BIT(1)); + rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32); + + rtl8xxxu_write8(priv, REG_RFE_CTRL_ANTA_SRC, 0x77); + + val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); + val32 &= ~BIT(24); + val32 |= BIT(23); + rtl8xxxu_write32(priv, REG_LEDCFG0, val32); + + /* + * Fix external switch Main->S1, Aux->S0 + */ + val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1); + val8 &= ~BIT(0); + rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8); + + /* + * Fix transmission failure of rtl8192e. + */ + rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); +} + +static s8 rtl8192e_cck_rssi(struct rtl8xxxu_priv *priv, struct rtl8723au_phy_stats *phy_stats) +{ + static const s8 lna_gain_table_0[8] = {15, 9, -10, -21, -23, -27, -43, -44}; + static const s8 lna_gain_table_1[8] = {24, 18, 13, -4, -11, -18, -31, -36}; + + u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a; + s8 rx_pwr_all = 0x00; + u8 vga_idx, lna_idx; + s8 lna_gain = 0; + + lna_idx = u8_get_bits(cck_agc_rpt, CCK_AGC_RPT_LNA_IDX_MASK); + vga_idx = u8_get_bits(cck_agc_rpt, CCK_AGC_RPT_VGA_IDX_MASK); + + if (priv->cck_agc_report_type == 0) + lna_gain = lna_gain_table_0[lna_idx]; + else + lna_gain = lna_gain_table_1[lna_idx]; + + rx_pwr_all = lna_gain - (2 * vga_idx); + + return rx_pwr_all; +} + +static int rtl8192eu_led_brightness_set(struct led_classdev *led_cdev, + enum led_brightness brightness) +{ + struct rtl8xxxu_priv *priv = container_of(led_cdev, + struct rtl8xxxu_priv, + led_cdev); + u8 ledcfg = rtl8xxxu_read8(priv, REG_LEDCFG1); + + if (brightness == LED_OFF) { + ledcfg &= ~LEDCFG1_HW_LED_CONTROL; + ledcfg |= LEDCFG1_LED_DISABLE; + } else if (brightness == LED_ON) { + ledcfg &= ~(LEDCFG1_HW_LED_CONTROL | LEDCFG1_LED_DISABLE); + } else if (brightness == RTL8XXXU_HW_LED_CONTROL) { + ledcfg &= ~LEDCFG1_LED_DISABLE; + ledcfg |= LEDCFG1_HW_LED_CONTROL; + } + + rtl8xxxu_write8(priv, REG_LEDCFG1, ledcfg); + + return 0; +} + +struct rtl8xxxu_fileops rtl8192eu_fops = { + .identify_chip = rtl8192eu_identify_chip, + .parse_efuse = rtl8192eu_parse_efuse, + .load_firmware = rtl8192eu_load_firmware, + .power_on = rtl8192eu_power_on, + .power_off = rtl8192eu_power_off, + .read_efuse = rtl8xxxu_read_efuse, + .reset_8051 = rtl8xxxu_reset_8051, + .llt_init = rtl8xxxu_auto_llt_table, + .init_phy_bb = rtl8192eu_init_phy_bb, + .init_phy_rf = rtl8192eu_init_phy_rf, + .phy_lc_calibrate = rtl8723a_phy_lc_calibrate, + .phy_iq_calibrate = rtl8192eu_phy_iq_calibrate, + .config_channel = rtl8xxxu_gen2_config_channel, + .parse_rx_desc = rtl8xxxu_parse_rxdesc24, + .parse_phystats = rtl8723au_rx_parse_phystats, + .enable_rf = rtl8192e_enable_rf, + .disable_rf = rtl8xxxu_gen2_disable_rf, + .usb_quirks = rtl8xxxu_gen2_usb_quirks, + .set_tx_power = rtl8192e_set_tx_power, + .update_rate_mask = rtl8xxxu_gen2_update_rate_mask, + .report_connect = rtl8xxxu_gen2_report_connect, + .report_rssi = rtl8xxxu_gen2_report_rssi, + .fill_txdesc = rtl8xxxu_fill_txdesc_v2, + .set_crystal_cap = rtl8723a_set_crystal_cap, + .cck_rssi = rtl8192e_cck_rssi, + .led_classdev_brightness_set = rtl8192eu_led_brightness_set, + .writeN_block_size = 128, + .tx_desc_size = sizeof(struct rtl8xxxu_txdesc40), + .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc24), + .has_s0s1 = 0, + .gen2_thermal_meter = 1, + .needs_full_init = 1, + .supports_ap = 1, + .max_macid_num = 128, + .max_sec_cam_num = 64, + .adda_1t_init = 0x0fc01616, + .adda_1t_path_on = 0x0fc01616, + .adda_2t_path_on_a = 0x0fc01616, + .adda_2t_path_on_b = 0x0fc01616, + .trxff_boundary = 0x3cff, + .mactable = rtl8192e_mac_init_table, + .total_page_num = TX_TOTAL_PAGE_NUM_8192E, + .page_num_hi = TX_PAGE_NUM_HI_PQ_8192E, + .page_num_lo = TX_PAGE_NUM_LO_PQ_8192E, + .page_num_norm = TX_PAGE_NUM_NORM_PQ_8192E, +}; diff --git a/drivers/net/wireless/realtek/rtl8xxxu/8192f.c b/drivers/net/wireless/realtek/rtl8xxxu/8192f.c new file mode 100644 index 000000000000..843ff0269b39 --- /dev/null +++ b/drivers/net/wireless/realtek/rtl8xxxu/8192f.c @@ -0,0 +1,2103 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * RTL8XXXU mac80211 USB driver - 8192fu specific subdriver + * + * Copyright (c) 2023 Bitterblue Smith + * + * Portions copied from existing rtl8xxxu code: + * Copyright (c) 2014 - 2017 Jes Sorensen + * + * Portions, notably calibration code: + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "rtl8xxxu.h" +#include "regs.h" + +static const struct rtl8xxxu_reg8val rtl8192f_mac_init_table[] = { + {0x420, 0x00}, {0x422, 0x78}, {0x428, 0x0a}, {0x429, 0x10}, + {0x430, 0x00}, {0x431, 0x00}, {0x432, 0x00}, {0x433, 0x01}, + {0x434, 0x04}, {0x435, 0x05}, {0x436, 0x07}, {0x437, 0x08}, + {0x43c, 0x04}, {0x43d, 0x05}, {0x43e, 0x07}, {0x43f, 0x08}, + {0x440, 0x5d}, {0x441, 0x01}, {0x442, 0x00}, {0x444, 0x10}, + {0x445, 0xf0}, {0x446, 0x0e}, {0x447, 0x1f}, {0x448, 0x00}, + {0x449, 0x00}, {0x44a, 0x00}, {0x44b, 0x00}, {0x44c, 0x10}, + {0x44d, 0xf0}, {0x44e, 0x0e}, {0x44f, 0x00}, {0x450, 0x00}, + {0x451, 0x00}, {0x452, 0x00}, {0x453, 0x00}, {0x480, 0x20}, + {0x49c, 0x30}, {0x49d, 0xf0}, {0x49e, 0x03}, {0x49f, 0x3e}, + {0x4a0, 0x00}, {0x4a1, 0x00}, {0x4a2, 0x00}, {0x4a3, 0x00}, + {0x4a4, 0x15}, {0x4a5, 0xf0}, {0x4a6, 0x01}, {0x4a7, 0x0e}, + {0x4a8, 0xe0}, {0x4a9, 0x00}, {0x4aa, 0x00}, {0x4ab, 0x00}, + {0x2448, 0x06}, {0x244a, 0x06}, {0x244c, 0x06}, {0x244e, 0x06}, + {0x4c7, 0x80}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4ca, 0x3c}, + {0x4cb, 0x3c}, {0x4cc, 0xff}, {0x4cd, 0xff}, {0x4ce, 0x01}, + {0x500, 0x26}, {0x501, 0xa2}, {0x502, 0x2f}, {0x503, 0x00}, + {0x504, 0x28}, {0x505, 0xa3}, {0x506, 0x5e}, {0x507, 0x00}, + {0x508, 0x2b}, {0x509, 0xa4}, {0x50a, 0x5e}, {0x50b, 0x00}, + {0x50c, 0x4f}, {0x50d, 0xa4}, {0x50e, 0x00}, {0x50f, 0x00}, + {0x512, 0x1c}, {0x514, 0x0a}, {0x516, 0x0a}, {0x521, 0x2f}, + {0x525, 0x0f}, {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, + {0x55c, 0x50}, {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, + {0x609, 0x2a}, {0x60c, 0x18}, {0x620, 0xff}, {0x621, 0xff}, + {0x622, 0xff}, {0x623, 0xff}, {0x624, 0xff}, {0x625, 0xff}, + {0x626, 0xff}, {0x627, 0xff}, {0x638, 0x50}, {0x63c, 0x0a}, + {0x63d, 0x0a}, {0x63e, 0x0e}, {0x63f, 0x0e}, {0x640, 0x40}, + {0x642, 0x40}, {0x643, 0x00}, {0x652, 0xc8}, {0x66e, 0x05}, + {0x6a0, 0xff}, {0x6a1, 0xff}, {0x6a2, 0xff}, {0x6a3, 0xff}, + {0x6a4, 0xff}, {0x6a5, 0xff}, {0x6de, 0x84}, {0x700, 0x21}, + {0x701, 0x43}, {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, + {0x709, 0x43}, {0x70a, 0x65}, {0x70b, 0x87}, {0x718, 0x40}, + {0x7c0, 0x38}, {0x7c2, 0x0f}, {0x7c3, 0xc0}, {0x073, 0x04}, + {0x7c4, 0x77}, {0x024, 0xc7}, {0x7ec, 0xff}, {0x7ed, 0xff}, + {0x7ee, 0xff}, {0x7ef, 0xff}, + {0xffff, 0xff}, +}; + +/* If updating the phy init table, also update rtl8192f_revise_cck_tx_psf(). */ +static const struct rtl8xxxu_reg32val rtl8192fu_phy_init_table[] = { + {0x800, 0x80006C00}, {0x804, 0x00004001}, + {0x808, 0x0000FC00}, {0x80C, 0x00000000}, + {0x810, 0x20200322}, {0x814, 0x020C3910}, + {0x818, 0x00000385}, {0x81C, 0x07000000}, + {0x820, 0x01000100}, {0x824, 0x00390204}, + {0x828, 0x01000100}, {0x82C, 0x00390204}, + {0x830, 0x25252525}, {0x834, 0x25252525}, + {0x838, 0x25252525}, {0x83C, 0x25252525}, + {0x840, 0x00010000}, {0x844, 0x00010000}, + {0x848, 0x25252525}, {0x84C, 0x25252525}, + {0x850, 0x00031FE0}, {0x854, 0x00000000}, + {0x858, 0x569A569A}, {0x85C, 0x00400040}, + {0x860, 0x66F60000}, {0x864, 0x061F0000}, + {0x868, 0x25252525}, {0x86C, 0x25252525}, + {0x870, 0x00000300}, {0x874, 0x04003400}, + {0x878, 0x08080808}, {0x87C, 0x004F0201}, + {0x880, 0xD8001402}, {0x884, 0xC0000120}, + {0x888, 0x00000000}, {0x88C, 0xCC0000C0}, + {0x890, 0x00000000}, {0x894, 0xFFFFFFFE}, + {0x898, 0x40302010}, {0x89C, 0x00706050}, + {0x900, 0x00000000}, {0x904, 0x00000023}, + {0x908, 0x00000F00}, {0x90C, 0x81121313}, + {0x910, 0x024C0000}, {0x914, 0x00000000}, + {0x918, 0x00000000}, {0x91C, 0x00000000}, + {0x920, 0x00000000}, {0x924, 0x00000000}, + {0x928, 0x00000000}, {0x92C, 0x00000000}, + {0x930, 0x88000000}, {0x934, 0x00000245}, + {0x938, 0x00024588}, {0x93C, 0x00000000}, + {0x940, 0x000007FF}, {0x944, 0x3F3F0000}, + {0x948, 0x000001A3}, {0x94C, 0x20200008}, + {0x950, 0x00338A98}, {0x954, 0x00000000}, + {0x958, 0xCBCAD87A}, {0x95C, 0x06EB5735}, + {0x960, 0x00000000}, {0x964, 0x00000000}, + {0x968, 0x00000000}, {0x96C, 0x00000003}, + {0x970, 0x00000000}, {0x974, 0x00000000}, + {0x978, 0x00000000}, {0x97C, 0x10030000}, + {0x980, 0x00000000}, {0x984, 0x02800280}, + {0x988, 0x020A5704}, {0x98C, 0x1461C826}, + {0x990, 0x0001469E}, {0x994, 0x008858D1}, + {0x998, 0x400086C9}, {0x99C, 0x44444242}, + {0x9A0, 0x00000000}, {0x9A4, 0x00000000}, + {0x9A8, 0x00000000}, {0x9AC, 0xC0000000}, + {0xA00, 0x00D047C8}, {0xA04, 0xC1FF0008}, + {0xA08, 0x88838300}, {0xA0C, 0x2E20100F}, + {0xA10, 0x9500BB78}, {0xA14, 0x11144028}, + {0xA18, 0x00881117}, {0xA1C, 0x89140F00}, + {0xA20, 0xE82C0001}, {0xA24, 0x64B80C1C}, + {0xA28, 0x00158810}, {0xA2C, 0x10BB8000}, + {0xA70, 0x00008000}, {0xA74, 0x80800100}, + {0xA78, 0x000089F0}, {0xA7C, 0x225B0606}, + {0xA80, 0x20803210}, {0xA84, 0x00200200}, + {0xA88, 0x00000000}, {0xA8C, 0x00000000}, + {0xA90, 0x00000000}, {0xA94, 0x00000000}, + {0xA98, 0x00000000}, {0xA9C, 0x00460000}, + {0xAA0, 0x00000000}, {0xAA4, 0x00020014}, + {0xAA8, 0xBA0A0008}, {0xAAC, 0x01235667}, + {0xAB0, 0x00000000}, {0xAB4, 0x00201402}, + {0xAB8, 0x0000001C}, {0xABC, 0x0000F7FF}, + {0xAC0, 0xD4C0A742}, {0xAC4, 0x00000000}, + {0xAC8, 0x00000F08}, {0xACC, 0x00000F07}, + {0xAD0, 0xA1052A10}, {0xAD4, 0x0D9D8452}, + {0xAD8, 0x9E024024}, {0xADC, 0x0023C001}, + {0xAE0, 0x00000391}, {0xB2C, 0x00000000}, + {0xC00, 0x00000080}, {0xC04, 0x6F005433}, + {0xC08, 0x000004E4}, {0xC0C, 0x6C6C6C6C}, + {0xC10, 0x22000000}, {0xC14, 0x40000100}, + {0xC18, 0x22000000}, {0xC1C, 0x40000100}, + {0xC20, 0x00000000}, {0xC24, 0x40000100}, + {0xC28, 0x00000000}, {0xC2C, 0x40000100}, + {0xC30, 0x0401E809}, {0xC34, 0x30000020}, + {0xC38, 0x23808080}, {0xC3C, 0x00002F44}, + {0xC40, 0x1CF8403F}, {0xC44, 0x000100C7}, + {0xC48, 0xEC060106}, {0xC4C, 0x007F037F}, + {0xC50, 0x00E48020}, {0xC54, 0x04008017}, + {0xC58, 0x00000020}, {0xC5C, 0x00708492}, + {0xC60, 0x09280200}, {0xC64, 0x5014838B}, + {0xC68, 0x47C006C7}, {0xC6C, 0x00000035}, + {0xC70, 0x00001007}, {0xC74, 0x02815269}, + {0xC78, 0x0FE07F1F}, {0xC7C, 0x00B91612}, + {0xC80, 0x40000100}, {0xC84, 0x32000000}, + {0xC88, 0x40000100}, {0xC8C, 0xA0240000}, + {0xC90, 0x400E161E}, {0xC94, 0x00000F00}, + {0xC98, 0x400E161E}, {0xC9C, 0x0000BDC8}, + {0xCA0, 0x00000000}, {0xCA4, 0x098300A0}, + {0xCA8, 0x00006B00}, {0xCAC, 0x87F45B1A}, + {0xCB0, 0x0000002D}, {0xCB4, 0x00000000}, + {0xCB8, 0x00000000}, {0xCBC, 0x28100200}, + {0xCC0, 0x0010A3D0}, {0xCC4, 0x00000F7D}, + {0xCC8, 0x00000000}, {0xCCC, 0x00000000}, + {0xCD0, 0x593659AD}, {0xCD4, 0xB7545121}, + {0xCD8, 0x64B22427}, {0xCDC, 0x00766932}, + {0xCE0, 0x40201000}, {0xCE4, 0x00000000}, + {0xCE8, 0x40E04407}, {0xCEC, 0x2E572000}, + {0xD00, 0x000D8780}, {0xD04, 0x40020403}, + {0xD08, 0x0002907F}, {0xD0C, 0x20010201}, + {0xD10, 0x06288888}, {0xD14, 0x8888367B}, + {0xD18, 0x7D806DB3}, {0xD1C, 0x0000007F}, + {0xD20, 0x567600B8}, {0xD24, 0x0000018B}, + {0xD28, 0xD513FF7D}, {0xD2C, 0xCC979975}, + {0xD30, 0x04928000}, {0xD34, 0x40608000}, + {0xD38, 0x88DDA000}, {0xD3C, 0x00026EE2}, + {0xD50, 0x67270001}, {0xD54, 0x20500000}, + {0xD58, 0x16161616}, {0xD5C, 0x71F20064}, + {0xD60, 0x4653DA60}, {0xD64, 0x3E718A3C}, + {0xD68, 0x00000183}, {0xD7C, 0x00000000}, + {0xD80, 0x50000000}, {0xD84, 0x31310400}, + {0xD88, 0xF5B50000}, {0xD8C, 0x00000000}, + {0xD90, 0x00000000}, {0xD94, 0x44BBBB44}, + {0xD98, 0x44BB44FF}, {0xD9C, 0x06033688}, + {0xE00, 0x25252525}, {0xE04, 0x25252525}, + {0xE08, 0x25252525}, {0xE10, 0x25252525}, + {0xE14, 0x25252525}, {0xE18, 0x25252525}, + {0xE1C, 0x25252525}, {0xE20, 0x00000000}, + {0xE24, 0x00200000}, {0xE28, 0x00000000}, + {0xE2C, 0x00000000}, {0xE30, 0x01007C00}, + {0xE34, 0x01004800}, {0xE38, 0x10008C0F}, + {0xE3C, 0x3C008C0F}, {0xE40, 0x01007C00}, + {0xE44, 0x00000000}, {0xE48, 0x00000000}, + {0xE4C, 0x00000000}, {0xE50, 0x01007C00}, + {0xE54, 0x01004800}, {0xE58, 0x10008C0F}, + {0xE5C, 0x3C008C0F}, {0xE60, 0x02100000}, + {0xE64, 0xBBBBBBBB}, {0xE68, 0x40404040}, + {0xE6C, 0x80408040}, {0xE70, 0x80408040}, + {0xE74, 0x40404040}, {0xE78, 0x00400040}, + {0xE7C, 0x40404040}, {0xE80, 0x00FF0000}, + {0xE84, 0x80408040}, {0xE88, 0x40404040}, + {0xE8C, 0x80408040}, {0xED0, 0x80408040}, + {0xED4, 0x80408040}, {0xED8, 0x80408040}, + {0xEDC, 0xC040C040}, {0xEE0, 0xC040C040}, + {0xEE4, 0x00400040}, {0xEE8, 0xD8001402}, + {0xEEC, 0xC0000120}, {0xEF0, 0x02000B09}, + {0xEF4, 0x00000001}, {0xEF8, 0x00000000}, + {0xF00, 0x00000300}, {0xF04, 0x00000002}, + {0xF08, 0x00007D0C}, {0xF0C, 0x0000A907}, + {0xF10, 0x00005807}, {0xF14, 0x00000003}, + {0xF18, 0x07D003E8}, {0xF1C, 0x8000001F}, + {0xF20, 0x00000000}, {0xF24, 0x00000000}, + {0xF28, 0x00000000}, {0xF2C, 0x00000000}, + {0xF30, 0x00000000}, {0xF34, 0x00000000}, + {0xF38, 0x00030055}, {0xF3C, 0x0000003A}, + {0xF40, 0x00000002}, {0xF44, 0x00000000}, + {0xF48, 0x00000000}, {0xF4C, 0x0B000000}, + {0xF50, 0x00000000}, + {0xffff, 0xffffffff}, +}; + +static const struct rtl8xxxu_reg32val rtl8192f_agc_table[] = { + {0xC78, 0x0FA0001F}, {0xC78, 0x0FA0011F}, + {0xC78, 0x0FA0021F}, {0xC78, 0x0FA0031F}, + {0xC78, 0x0FA0041F}, {0xC78, 0x0FA0051F}, + {0xC78, 0x0F90061F}, {0xC78, 0x0F80071F}, + {0xC78, 0x0F70081F}, {0xC78, 0x0F60091F}, + {0xC78, 0x0F500A1F}, {0xC78, 0x0F400B1F}, + {0xC78, 0x0F300C1F}, {0xC78, 0x0F200D1F}, + {0xC78, 0x0F100E1F}, {0xC78, 0x0F000F1F}, + {0xC78, 0x0EF0101F}, {0xC78, 0x0EE0111F}, + {0xC78, 0x0ED0121F}, {0xC78, 0x0EC0131F}, + {0xC78, 0x0EB0141F}, {0xC78, 0x0EA0151F}, + {0xC78, 0x0E90161F}, {0xC78, 0x0E80171F}, + {0xC78, 0x0E70181F}, {0xC78, 0x0E60191F}, + {0xC78, 0x0E501A1F}, {0xC78, 0x0E401B1F}, + {0xC78, 0x0E301C1F}, {0xC78, 0x0C701D1F}, + {0xC78, 0x0C601E1F}, {0xC78, 0x0C501F1F}, + {0xC78, 0x0C40201F}, {0xC78, 0x0C30211F}, + {0xC78, 0x0A60221F}, {0xC78, 0x0A50231F}, + {0xC78, 0x0A40241F}, {0xC78, 0x0A30251F}, + {0xC78, 0x0860261F}, {0xC78, 0x0850271F}, + {0xC78, 0x0840281F}, {0xC78, 0x0830291F}, + {0xC78, 0x06702A1F}, {0xC78, 0x06602B1F}, + {0xC78, 0x06502C1F}, {0xC78, 0x06402D1F}, + {0xC78, 0x06302E1F}, {0xC78, 0x04602F1F}, + {0xC78, 0x0450301F}, {0xC78, 0x0440311F}, + {0xC78, 0x0430321F}, {0xC78, 0x0260331F}, + {0xC78, 0x0250341F}, {0xC78, 0x0240351F}, + {0xC78, 0x0230361F}, {0xC78, 0x0050371F}, + {0xC78, 0x0040381F}, {0xC78, 0x0030391F}, + {0xC78, 0x00203A1F}, {0xC78, 0x00103B1F}, + {0xC78, 0x00003C1F}, {0xC78, 0x00003D1F}, + {0xC78, 0x00003E1F}, {0xC78, 0x00003F1F}, + + {0xC78, 0x0FA0401F}, {0xC78, 0x0FA0411F}, + {0xC78, 0x0FA0421F}, {0xC78, 0x0FA0431F}, + {0xC78, 0x0F90441F}, {0xC78, 0x0F80451F}, + {0xC78, 0x0F70461F}, {0xC78, 0x0F60471F}, + {0xC78, 0x0F50481F}, {0xC78, 0x0F40491F}, + {0xC78, 0x0F304A1F}, {0xC78, 0x0F204B1F}, + {0xC78, 0x0F104C1F}, {0xC78, 0x0F004D1F}, + {0xC78, 0x0EF04E1F}, {0xC78, 0x0EE04F1F}, + {0xC78, 0x0ED0501F}, {0xC78, 0x0EC0511F}, + {0xC78, 0x0EB0521F}, {0xC78, 0x0EA0531F}, + {0xC78, 0x0E90541F}, {0xC78, 0x0E80551F}, + {0xC78, 0x0E70561F}, {0xC78, 0x0E60571F}, + {0xC78, 0x0E50581F}, {0xC78, 0x0E40591F}, + {0xC78, 0x0E305A1F}, {0xC78, 0x0E205B1F}, + {0xC78, 0x0E105C1F}, {0xC78, 0x0C505D1F}, + {0xC78, 0x0C405E1F}, {0xC78, 0x0C305F1F}, + {0xC78, 0x0C20601F}, {0xC78, 0x0C10611F}, + {0xC78, 0x0A40621F}, {0xC78, 0x0A30631F}, + {0xC78, 0x0A20641F}, {0xC78, 0x0A10651F}, + {0xC78, 0x0840661F}, {0xC78, 0x0830671F}, + {0xC78, 0x0820681F}, {0xC78, 0x0810691F}, + {0xC78, 0x06506A1F}, {0xC78, 0x06406B1F}, + {0xC78, 0x06306C1F}, {0xC78, 0x06206D1F}, + {0xC78, 0x06106E1F}, {0xC78, 0x04406F1F}, + {0xC78, 0x0430701F}, {0xC78, 0x0420711F}, + {0xC78, 0x0410721F}, {0xC78, 0x0240731F}, + {0xC78, 0x0230741F}, {0xC78, 0x0220751F}, + {0xC78, 0x0210761F}, {0xC78, 0x0030771F}, + {0xC78, 0x0020781F}, {0xC78, 0x0010791F}, + {0xC78, 0x00007A1F}, {0xC78, 0x00007B1F}, + {0xC78, 0x00007C1F}, {0xC78, 0x00007D1F}, + {0xC78, 0x00007E1F}, {0xC78, 0x00007F1F}, + + {0xC78, 0x0FA0801F}, {0xC78, 0x0FA0811F}, + {0xC78, 0x0FA0821F}, {0xC78, 0x0FA0831F}, + {0xC78, 0x0FA0841F}, {0xC78, 0x0FA0851F}, + {0xC78, 0x0F90861F}, {0xC78, 0x0F80871F}, + {0xC78, 0x0F70881F}, {0xC78, 0x0F60891F}, + {0xC78, 0x0F508A1F}, {0xC78, 0x0F408B1F}, + {0xC78, 0x0F308C1F}, {0xC78, 0x0F208D1F}, + {0xC78, 0x0F108E1F}, {0xC78, 0x0B908F1F}, + {0xC78, 0x0B80901F}, {0xC78, 0x0B70911F}, + {0xC78, 0x0B60921F}, {0xC78, 0x0B50931F}, + {0xC78, 0x0B40941F}, {0xC78, 0x0B30951F}, + {0xC78, 0x0B20961F}, {0xC78, 0x0B10971F}, + {0xC78, 0x0B00981F}, {0xC78, 0x0AF0991F}, + {0xC78, 0x0AE09A1F}, {0xC78, 0x0AD09B1F}, + {0xC78, 0x0AC09C1F}, {0xC78, 0x0AB09D1F}, + {0xC78, 0x0AA09E1F}, {0xC78, 0x0A909F1F}, + {0xC78, 0x0A80A01F}, {0xC78, 0x0A70A11F}, + {0xC78, 0x0A60A21F}, {0xC78, 0x0A50A31F}, + {0xC78, 0x0A40A41F}, {0xC78, 0x0A30A51F}, + {0xC78, 0x0A20A61F}, {0xC78, 0x0A10A71F}, + {0xC78, 0x0A00A81F}, {0xC78, 0x0830A91F}, + {0xC78, 0x0820AA1F}, {0xC78, 0x0810AB1F}, + {0xC78, 0x0800AC1F}, {0xC78, 0x0640AD1F}, + {0xC78, 0x0630AE1F}, {0xC78, 0x0620AF1F}, + {0xC78, 0x0610B01F}, {0xC78, 0x0600B11F}, + {0xC78, 0x0430B21F}, {0xC78, 0x0420B31F}, + {0xC78, 0x0410B41F}, {0xC78, 0x0400B51F}, + {0xC78, 0x0230B61F}, {0xC78, 0x0220B71F}, + {0xC78, 0x0210B81F}, {0xC78, 0x0200B91F}, + {0xC78, 0x0000BA1F}, {0xC78, 0x0000BB1F}, + {0xC78, 0x0000BC1F}, {0xC78, 0x0000BD1F}, + {0xC78, 0x0000BE1F}, {0xC78, 0x0000BF1F}, + {0xC50, 0x00E48024}, {0xC50, 0x00E48020}, + {0xffff, 0xffffffff} +}; + +static const struct rtl8xxxu_rfregval rtl8192fu_radioa_init_table[] = { + {0x00, 0x30000}, {0x18, 0x0FC07}, {0x81, 0x0FC00}, {0x82, 0x003C0}, + {0x84, 0x00005}, {0x86, 0xA33A5}, {0x87, 0x00000}, {0x88, 0x58010}, + {0x8E, 0x64540}, {0x8F, 0x282D8}, {0x51, 0x02C06}, {0x52, 0x7A007}, + {0x53, 0x10061}, {0x54, 0x60018}, {0x55, 0x82020}, {0x56, 0x08CC6}, + {0x57, 0x2CC00}, {0x58, 0x00000}, {0x5A, 0x50000}, {0x5B, 0x00006}, + {0x5C, 0x00015}, {0x65, 0x20000}, {0x6E, 0x38319}, {0xF5, 0x43180}, + {0xEF, 0x00002}, {0x33, 0x00301}, {0x33, 0x1032A}, {0x33, 0x2032A}, + {0xEF, 0x00000}, {0xDF, 0x00002}, {0x35, 0x00000}, {0xF0, 0x08008}, + {0xEF, 0x00800}, {0x33, 0x0040E}, {0x33, 0x04845}, {0x33, 0x08848}, + {0x33, 0x0C84B}, {0x33, 0x1088A}, {0x33, 0x14C50}, {0x33, 0x18C8E}, + {0x33, 0x1CCCD}, {0x33, 0x20CD0}, {0x33, 0x24CD3}, {0x33, 0x28CD6}, + {0x33, 0x4002B}, {0x33, 0x4402E}, {0x33, 0x48846}, {0x33, 0x4C849}, + {0x33, 0x50888}, {0x33, 0x54CC6}, {0x33, 0x58CC9}, {0x33, 0x5CCCC}, + {0x33, 0x60CCF}, {0x33, 0x64CD2}, {0x33, 0x68CD5}, {0xEF, 0x00000}, + {0xEF, 0x00400}, {0x33, 0x01C23}, {0x33, 0x05C23}, {0x33, 0x09D23}, + {0x33, 0x0DD23}, {0x33, 0x11FA3}, {0x33, 0x15FA3}, {0x33, 0x19FAB}, + {0x33, 0x1DFAB}, {0xEF, 0x00000}, {0xEF, 0x00200}, {0x33, 0x00030}, + {0x33, 0x04030}, {0x33, 0x08030}, {0x33, 0x0C030}, {0x33, 0x10030}, + {0x33, 0x14030}, {0x33, 0x18030}, {0x33, 0x1C030}, {0x33, 0x20030}, + {0x33, 0x24030}, {0x33, 0x28030}, {0x33, 0x2C030}, {0x33, 0x30030}, + {0x33, 0x34030}, {0x33, 0x38030}, {0x33, 0x3C030}, {0xEF, 0x00000}, + {0xEF, 0x00100}, {0x33, 0x44001}, {0x33, 0x48001}, {0x33, 0x4C001}, + {0x33, 0x50001}, {0x33, 0x54001}, {0x33, 0x58001}, {0x33, 0x5C001}, + {0x33, 0x60001}, {0x33, 0x64001}, {0x33, 0x68001}, {0x33, 0x6C001}, + {0x33, 0x70001}, {0x33, 0x74001}, {0x33, 0x78001}, {0x33, 0x04000}, + {0x33, 0x08000}, {0x33, 0x0C000}, {0x33, 0x10000}, {0x33, 0x14000}, + {0x33, 0x18001}, {0x33, 0x1C002}, {0x33, 0x20002}, {0x33, 0x24002}, + {0x33, 0x28002}, {0x33, 0x2C002}, {0x33, 0x30002}, {0x33, 0x34002}, + {0x33, 0x38002}, {0xEF, 0x00000}, {0x84, 0x00000}, {0xEF, 0x80010}, + {0x30, 0x20000}, {0x31, 0x0006F}, {0x32, 0x01FF7}, {0xEF, 0x00000}, + {0x84, 0x00000}, {0xEF, 0x80000}, {0x30, 0x30000}, {0x31, 0x0006F}, + {0x32, 0xF1DF3}, {0xEF, 0x00000}, {0x84, 0x00000}, {0xEF, 0x80000}, + {0x30, 0x38000}, {0x31, 0x0006F}, {0x32, 0xF1FF2}, {0xEF, 0x00000}, + {0x1B, 0x746CE}, {0xEF, 0x20000}, {0x33, 0x30000}, {0x33, 0x38000}, + {0x33, 0x70000}, {0x33, 0x78000}, {0xEF, 0x00000}, {0xDF, 0x08000}, + {0xB0, 0xFFBCB}, {0xB3, 0x06000}, {0xB7, 0x18DF0}, {0xB8, 0x38FF0}, + {0xC9, 0x00600}, {0xDF, 0x00000}, {0xB1, 0x33B8F}, {0xB2, 0x33762}, + {0xB4, 0x141F0}, {0xB5, 0x14080}, {0xB6, 0x12425}, {0xB9, 0xC0008}, + {0xBA, 0x40005}, {0xC2, 0x02C01}, {0xC3, 0x0000B}, {0xC4, 0x81E2F}, + {0xC5, 0x5C28F}, {0xC6, 0x000A0}, {0xCA, 0x02000}, {0xFE, 0x00000}, + {0x18, 0x08C07}, {0xFE, 0x00000}, {0xFE, 0x00000}, {0xFE, 0x00000}, + {0x00, 0x31DD5}, + {0xff, 0xffffffff} +}; + +static const struct rtl8xxxu_rfregval rtl8192fu_radiob_init_table[] = { + {0x00, 0x30000}, {0x81, 0x0FC00}, {0x82, 0x003C0}, {0x84, 0x00005}, + {0x86, 0xA33A5}, {0x87, 0x00000}, {0x88, 0x58010}, {0x8E, 0x64540}, + {0x8F, 0x282D8}, {0x51, 0x02C06}, {0x52, 0x7A007}, {0x53, 0x10061}, + {0x54, 0x60018}, {0x55, 0x82020}, {0x56, 0x08CC6}, {0x57, 0x2CC00}, + {0x58, 0x00000}, {0x5A, 0x50000}, {0x5B, 0x00006}, {0x5C, 0x00015}, + {0x65, 0x20000}, {0x6E, 0x38319}, {0xF5, 0x43180}, {0xEF, 0x00002}, + {0x33, 0x00301}, {0x33, 0x1032A}, {0x33, 0x2032A}, {0xEF, 0x00000}, + {0xDF, 0x00002}, {0x35, 0x00000}, {0xF0, 0x08008}, {0xEF, 0x00800}, + {0x33, 0x0040E}, {0x33, 0x04845}, {0x33, 0x08848}, {0x33, 0x0C84B}, + {0x33, 0x1088A}, {0x33, 0x14CC8}, {0x33, 0x18CCB}, {0x33, 0x1CCCE}, + {0x33, 0x20CD1}, {0x33, 0x24CD4}, {0x33, 0x28CD7}, {0x33, 0x4002B}, + {0x33, 0x4402E}, {0x33, 0x48846}, {0x33, 0x4C849}, {0x33, 0x50888}, + {0x33, 0x54CC6}, {0x33, 0x58CC9}, {0x33, 0x5CCCC}, {0x33, 0x60CCF}, + {0x33, 0x64CD2}, {0x33, 0x68CD5}, {0xEF, 0x00000}, {0xEF, 0x00400}, + {0x33, 0x01D23}, {0x33, 0x05D23}, {0x33, 0x09FA3}, {0x33, 0x0DFA3}, + {0x33, 0x11D2B}, {0x33, 0x15D2B}, {0x33, 0x19FAB}, {0x33, 0x1DFAB}, + {0xEF, 0x00000}, {0xEF, 0x00200}, {0x33, 0x00030}, {0x33, 0x04030}, + {0x33, 0x08030}, {0x33, 0x0C030}, {0x33, 0x10030}, {0x33, 0x14030}, + {0x33, 0x18030}, {0x33, 0x1C030}, {0x33, 0x20030}, {0x33, 0x24030}, + {0x33, 0x28030}, {0x33, 0x2C030}, {0x33, 0x30030}, {0x33, 0x34030}, + {0x33, 0x38030}, {0x33, 0x3C030}, {0xEF, 0x00000}, {0xEF, 0x00100}, + {0x33, 0x44000}, {0x33, 0x48000}, {0x33, 0x4C000}, {0x33, 0x50000}, + {0x33, 0x54000}, {0x33, 0x58000}, {0x33, 0x5C000}, {0x33, 0x60000}, + {0x33, 0x64000}, {0x33, 0x68000}, {0x33, 0x6C000}, {0x33, 0x70000}, + {0x33, 0x74000}, {0x33, 0x78000}, {0x33, 0x04000}, {0x33, 0x08000}, + {0x33, 0x0C000}, {0x33, 0x10000}, {0x33, 0x14000}, {0x33, 0x18000}, + {0x33, 0x1C001}, {0x33, 0x20001}, {0x33, 0x24001}, {0x33, 0x28001}, + {0x33, 0x2C001}, {0x33, 0x30001}, {0x33, 0x34001}, {0x33, 0x38001}, + {0xEF, 0x00000}, {0x84, 0x00000}, {0xEF, 0x80010}, {0x30, 0x20000}, + {0x31, 0x0006F}, {0x32, 0x01FF7}, {0xEF, 0x00000}, {0x84, 0x00000}, + {0xEF, 0x80000}, {0x30, 0x30000}, {0x31, 0x0006F}, {0x32, 0xF1DF3}, + {0xEF, 0x00000}, {0x84, 0x00000}, {0xEF, 0x80000}, {0x30, 0x38000}, + {0x31, 0x0006F}, {0x32, 0xF1FF2}, {0xEF, 0x00000}, {0x1B, 0x746CE}, + {0xEF, 0x20000}, {0x33, 0x30000}, {0x33, 0x38000}, {0x33, 0x70000}, + {0x33, 0x78000}, {0xEF, 0x00000}, {0x00, 0x31DD5}, + {0xff, 0xffffffff} +}; + +static int rtl8192fu_identify_chip(struct rtl8xxxu_priv *priv) +{ + struct device *dev = &priv->udev->dev; + u32 sys_cfg, vendor, val32; + + strscpy(priv->chip_name, "8192FU", sizeof(priv->chip_name)); + priv->rtl_chip = RTL8192F; + priv->rf_paths = 2; + priv->rx_paths = 2; + priv->tx_paths = 2; + + sys_cfg = rtl8xxxu_read32(priv, REG_SYS_CFG); + priv->chip_cut = u32_get_bits(sys_cfg, SYS_CFG_CHIP_VERSION_MASK); + if (sys_cfg & SYS_CFG_TRP_VAUX_EN) { + dev_info(dev, "Unsupported test chip\n"); + return -EOPNOTSUPP; + } + + val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL); + priv->has_wifi = u32_get_bits(val32, MULTI_WIFI_FUNC_EN); + priv->has_bluetooth = u32_get_bits(val32, MULTI_BT_FUNC_EN); + priv->has_gps = u32_get_bits(val32, MULTI_GPS_FUNC_EN); + priv->is_multi_func = 1; + + vendor = sys_cfg & SYS_CFG_VENDOR_ID; + rtl8xxxu_identify_vendor_1bit(priv, vendor); + + val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS); + priv->rom_rev = u32_get_bits(val32, GPIO_RF_RL_ID); + + return rtl8xxxu_config_endpoints_no_sie(priv); +} + +static void +rtl8192f_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40) +{ + u8 cck, ofdmbase, mcsbase; + u32 val32, ofdm, mcs; + int group, cck_group; + + rtl8188f_channel_to_group(channel, &group, &cck_group); + + cck = priv->cck_tx_power_index_A[cck_group]; + + rtl8xxxu_write32_mask(priv, REG_TX_AGC_A_CCK1_MCS32, 0x00007f00, cck); + + val32 = (cck << 16) | (cck << 8) | cck; + rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, + 0x7f7f7f00, val32); + + ofdmbase = priv->ht40_1s_tx_power_index_A[group]; + ofdmbase += priv->ofdm_tx_power_diff[RF_A].a; + ofdm = ofdmbase | ofdmbase << 8 | ofdmbase << 16 | ofdmbase << 24; + + rtl8xxxu_write32_mask(priv, REG_TX_AGC_A_RATE18_06, 0x7f7f7f7f, ofdm); + rtl8xxxu_write32_mask(priv, REG_TX_AGC_A_RATE54_24, 0x7f7f7f7f, ofdm); + + mcsbase = priv->ht40_1s_tx_power_index_A[group]; + if (ht40) + mcsbase += priv->ht40_tx_power_diff[RF_A].a; + else + mcsbase += priv->ht20_tx_power_diff[RF_A].a; + mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24; + + rtl8xxxu_write32_mask(priv, REG_TX_AGC_A_MCS03_MCS00, 0x7f7f7f7f, mcs); + rtl8xxxu_write32_mask(priv, REG_TX_AGC_A_MCS07_MCS04, 0x7f7f7f7f, mcs); + rtl8xxxu_write32_mask(priv, REG_TX_AGC_A_MCS11_MCS08, 0x7f7f7f7f, mcs); + rtl8xxxu_write32_mask(priv, REG_TX_AGC_A_MCS15_MCS12, 0x7f7f7f7f, mcs); + + if (priv->tx_paths == 1) + return; + + cck = priv->cck_tx_power_index_B[cck_group]; + + val32 = (cck << 16) | (cck << 8) | cck; + rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_CCK1_55_MCS32, + 0x7f7f7f00, val32); + + rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, + 0x0000007f, cck); + + ofdmbase = priv->ht40_1s_tx_power_index_B[group]; + ofdmbase += priv->ofdm_tx_power_diff[RF_B].b; + ofdm = ofdmbase | ofdmbase << 8 | ofdmbase << 16 | ofdmbase << 24; + + rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_RATE18_06, 0x7f7f7f7f, ofdm); + rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_RATE54_24, 0x7f7f7f7f, ofdm); + + mcsbase = priv->ht40_1s_tx_power_index_B[group]; + if (ht40) + mcsbase += priv->ht40_tx_power_diff[RF_B].b; + else + mcsbase += priv->ht20_tx_power_diff[RF_B].b; + mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24; + + rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_MCS03_MCS00, 0x7f7f7f7f, mcs); + rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_MCS07_MCS04, 0x7f7f7f7f, mcs); + rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_MCS11_MCS08, 0x7f7f7f7f, mcs); + rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_MCS15_MCS12, 0x7f7f7f7f, mcs); +} + +static void rtl8192f_revise_cck_tx_psf(struct rtl8xxxu_priv *priv, u8 channel) +{ + if (channel == 13) { + /* Special value for channel 13 */ + rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER1, 0xf8fe0001); + /* Normal values */ + rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER2, 0x64B80C1C); + rtl8xxxu_write16(priv, REG_CCK0_DEBUG_PORT, 0x8810); + rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER3, 0x01235667); + } else if (channel == 14) { + /* Normal value */ + rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER1, 0xE82C0001); + /* Special values for channel 14 */ + rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER2, 0x0000B81C); + rtl8xxxu_write16(priv, REG_CCK0_DEBUG_PORT, 0x0000); + rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER3, 0x00003667); + } else { + /* Restore normal values from the phy init table */ + rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER1, 0xE82C0001); + rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER2, 0x64B80C1C); + rtl8xxxu_write16(priv, REG_CCK0_DEBUG_PORT, 0x8810); + rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER3, 0x01235667); + } +} + +static void rtl8192fu_config_kfree(struct rtl8xxxu_priv *priv, u8 channel) +{ + u8 bb_gain[3] = { EFUSE_UNDEFINED, EFUSE_UNDEFINED, EFUSE_UNDEFINED }; + u8 bb_gain_path_mask[2] = { 0x0f, 0xf0 }; + enum rtl8xxxu_rfpath rfpath; + u8 bb_gain_for_path; + u8 channel_idx = 0; + + if (channel >= 1 && channel <= 3) + channel_idx = 0; + if (channel >= 4 && channel <= 9) + channel_idx = 1; + if (channel >= 10 && channel <= 14) + channel_idx = 2; + + rtl8xxxu_read_efuse8(priv, 0x1ee, &bb_gain[1]); + rtl8xxxu_read_efuse8(priv, 0x1ec, &bb_gain[0]); + rtl8xxxu_read_efuse8(priv, 0x1ea, &bb_gain[2]); + + if (bb_gain[1] == EFUSE_UNDEFINED) + return; + + if (bb_gain[0] == EFUSE_UNDEFINED) + bb_gain[0] = bb_gain[1]; + + if (bb_gain[2] == EFUSE_UNDEFINED) + bb_gain[2] = bb_gain[1]; + + for (rfpath = RF_A; rfpath < priv->rf_paths; rfpath++) { + /* power_trim based on 55[19:14] */ + rtl8xxxu_write_rfreg_mask(priv, rfpath, RF6052_REG_UNKNOWN_55, + BIT(5), 1); + + /* enable 55[14] for 0.5db step */ + rtl8xxxu_write_rfreg_mask(priv, rfpath, RF6052_REG_GAIN_CTRL, + BIT(18), 1); + + /* enter power_trim debug mode */ + rtl8xxxu_write_rfreg_mask(priv, rfpath, RF6052_REG_GAIN_CCA, + BIT(7), 1); + + /* write enable */ + rtl8xxxu_write_rfreg_mask(priv, rfpath, RF6052_REG_WE_LUT, BIT(7), 1); + + bb_gain_for_path = (bb_gain[channel_idx] & bb_gain_path_mask[rfpath]); + bb_gain_for_path >>= __ffs(bb_gain_path_mask[rfpath]); + + rtl8xxxu_write_rfreg_mask(priv, rfpath, RF6052_REG_TXPA_G3, + 0x70000, channel_idx * 2); + rtl8xxxu_write_rfreg_mask(priv, rfpath, RF6052_REG_TXPA_G3, + 0x3f, bb_gain_for_path); + + rtl8xxxu_write_rfreg_mask(priv, rfpath, RF6052_REG_TXPA_G3, + 0x70000, channel_idx * 2 + 1); + rtl8xxxu_write_rfreg_mask(priv, rfpath, RF6052_REG_TXPA_G3, + 0x3f, bb_gain_for_path); + + /* leave power_trim debug mode */ + rtl8xxxu_write_rfreg_mask(priv, rfpath, RF6052_REG_GAIN_CCA, + BIT(7), 0); + + /* write disable */ + rtl8xxxu_write_rfreg_mask(priv, rfpath, RF6052_REG_WE_LUT, BIT(7), 0); + } +} + +static void rtl8192fu_config_channel(struct ieee80211_hw *hw) +{ + struct rtl8xxxu_priv *priv = hw->priv; + bool ht40 = conf_is_ht40(&hw->conf); + u8 channel, subchannel = 0; + bool sec_ch_above = 0; + u32 val32; + + channel = (u8)hw->conf.chandef.chan->hw_value; + + if (conf_is_ht40_plus(&hw->conf)) { + sec_ch_above = 1; + channel += 2; + subchannel = 2; + } else if (conf_is_ht40_minus(&hw->conf)) { + sec_ch_above = 0; + channel -= 2; + subchannel = 1; + } + + val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG); + + rtl8192f_revise_cck_tx_psf(priv, channel); + + /* Set channel */ + val32 &= ~(BIT(18) | BIT(17)); /* select the 2.4G band(?) */ + u32p_replace_bits(&val32, channel, 0xff); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32); + if (priv->rf_paths > 1) + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_MODE_AG, val32); + + rtl8192fu_config_kfree(priv, channel); + + rtl8xxxu_write8(priv, REG_DATA_SUBCHANNEL, subchannel); + + /* small BW */ + rtl8xxxu_write32_clear(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, GENMASK(31, 30)); + + rtl8xxxu_write32_mask(priv, REG_FPGA0_RF_MODE, FPGA_RF_MODE, ht40); + rtl8xxxu_write32_mask(priv, REG_FPGA1_RF_MODE, FPGA_RF_MODE, ht40); + + /* ADC clock = 160M */ + rtl8xxxu_write32_mask(priv, REG_FPGA0_RF_MODE, GENMASK(10, 8), 4); + + /* DAC clock = 80M */ + rtl8xxxu_write32_mask(priv, REG_FPGA0_RF_MODE, BIT(13) | BIT(12), 2); + + /* ADC buffer clk */ + rtl8xxxu_write32_mask(priv, REG_ANTDIV_PARA1, BIT(27) | BIT(26), 2); + + if (ht40) + /* Set Control channel to upper or lower. */ + rtl8xxxu_write32_mask(priv, REG_CCK0_SYSTEM, + CCK0_SIDEBAND, !sec_ch_above); + + /* Enable CCK */ + rtl8xxxu_write32_set(priv, REG_FPGA0_RF_MODE, FPGA_RF_MODE_CCK); + + /* RF TRX_BW */ + val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG); + val32 &= ~MODE_AG_BW_MASK; + if (ht40) + val32 |= MODE_AG_BW_40MHZ_8723B; + else + val32 |= MODE_AG_BW_20MHZ_8723B; + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32); + if (priv->rf_paths > 1) + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_MODE_AG, val32); + + /* Modify RX DFIR parameters */ + rtl8xxxu_write32_mask(priv, REG_TAP_UPD_97F, BIT(21) | BIT(20), 2); + + rtl8xxxu_write32_mask(priv, REG_DOWNSAM_FACTOR, BIT(29) | BIT(28), 2); + + if (ht40) + val32 = 0x3; + else + val32 = 0x1a3; + rtl8xxxu_write32_mask(priv, REG_RX_DFIR_MOD_97F, 0x1ff, val32); +} + +static void rtl8192fu_init_aggregation(struct rtl8xxxu_priv *priv) +{ + u32 agg_rx; + u8 agg_ctrl; + + /* RX aggregation */ + agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL); + agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN; + + agg_rx = rtl8xxxu_read32(priv, REG_RXDMA_AGG_PG_TH); + agg_rx &= ~RXDMA_USB_AGG_ENABLE; + agg_rx &= ~0xFF0F; /* reset agg size and timeout */ + + rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl); + rtl8xxxu_write32(priv, REG_RXDMA_AGG_PG_TH, agg_rx); +} + +static int rtl8192fu_parse_efuse(struct rtl8xxxu_priv *priv) +{ + struct rtl8192fu_efuse *efuse = &priv->efuse_wifi.efuse8192fu; + int i; + + if (efuse->rtl_id != cpu_to_le16(0x8129)) + return -EINVAL; + + ether_addr_copy(priv->mac_addr, efuse->mac_addr); + + memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base, + sizeof(efuse->tx_power_index_A.cck_base)); + memcpy(priv->cck_tx_power_index_B, efuse->tx_power_index_B.cck_base, + sizeof(efuse->tx_power_index_B.cck_base)); + + memcpy(priv->ht40_1s_tx_power_index_A, + efuse->tx_power_index_A.ht40_base, + sizeof(efuse->tx_power_index_A.ht40_base)); + memcpy(priv->ht40_1s_tx_power_index_B, + efuse->tx_power_index_B.ht40_base, + sizeof(efuse->tx_power_index_B.ht40_base)); + + priv->ht20_tx_power_diff[0].a = + efuse->tx_power_index_A.ht20_ofdm_1s_diff.b; + priv->ht20_tx_power_diff[0].b = + efuse->tx_power_index_B.ht20_ofdm_1s_diff.b; + + priv->ht40_tx_power_diff[0].a = 0; + priv->ht40_tx_power_diff[0].b = 0; + + for (i = 1; i < RTL8723B_TX_COUNT; i++) { + priv->ofdm_tx_power_diff[i].a = + efuse->tx_power_index_A.pwr_diff[i - 1].ofdm; + priv->ofdm_tx_power_diff[i].b = + efuse->tx_power_index_B.pwr_diff[i - 1].ofdm; + + priv->ht20_tx_power_diff[i].a = + efuse->tx_power_index_A.pwr_diff[i - 1].ht20; + priv->ht20_tx_power_diff[i].b = + efuse->tx_power_index_B.pwr_diff[i - 1].ht20; + + priv->ht40_tx_power_diff[i].a = + efuse->tx_power_index_A.pwr_diff[i - 1].ht40; + priv->ht40_tx_power_diff[i].b = + efuse->tx_power_index_B.pwr_diff[i - 1].ht40; + } + + priv->default_crystal_cap = efuse->xtal_k & 0x3f; + + priv->rfe_type = efuse->rfe_option & 0x1f; + + if (priv->rfe_type != 5 && priv->rfe_type != 1) + dev_warn(&priv->udev->dev, + "%s: RFE type %d was not tested. Please send an email to linux-wireless@vger.kernel.org about this.\n", + __func__, priv->rfe_type); + + return 0; +} + +static int rtl8192fu_load_firmware(struct rtl8xxxu_priv *priv) +{ + return rtl8xxxu_load_firmware(priv, "rtlwifi/rtl8192fufw.bin"); +} + +static void rtl8192fu_init_phy_bb(struct rtl8xxxu_priv *priv) +{ + /* Enable BB and RF */ + rtl8xxxu_write16_set(priv, REG_SYS_FUNC, + SYS_FUNC_BBRSTB | SYS_FUNC_BB_GLB_RSTN); + + rtl8xxxu_write8(priv, REG_RF_CTRL, RF_ENABLE | RF_RSTB | RF_SDMRSTB); + + /* To Fix MAC loopback mode fail. */ + rtl8xxxu_write8(priv, REG_LDOHCI12_CTRL, 0xf); + rtl8xxxu_write8(priv, REG_SYS_SWR_CTRL2 + 1, 0xe9); + + rtl8xxxu_init_phy_regs(priv, rtl8192fu_phy_init_table); + + rtl8xxxu_init_phy_regs(priv, rtl8192f_agc_table); +} + +static int rtl8192fu_init_phy_rf(struct rtl8xxxu_priv *priv) +{ + int ret; + + ret = rtl8xxxu_init_phy_rf(priv, rtl8192fu_radioa_init_table, RF_A); + if (ret) + return ret; + + return rtl8xxxu_init_phy_rf(priv, rtl8192fu_radiob_init_table, RF_B); +} + +static void rtl8192f_phy_lc_calibrate(struct rtl8xxxu_priv *priv) +{ + u32 backup_mask = BIT(31) | BIT(30); + u32 backup; + u32 val32; + + /* Aries's NarrowBand */ + val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT); + backup = u32_get_bits(val32, backup_mask); + + u32p_replace_bits(&val32, 0, backup_mask); + rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32); + + rtl8188f_phy_lc_calibrate(priv); + + /* Aries's NarrowBand */ + val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT); + u32p_replace_bits(&val32, backup, backup_mask); + rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32); + + /* reset OFDM state */ + rtl8xxxu_write32_clear(priv, REG_FPGA0_RF_MODE, FPGA_RF_MODE_OFDM); + rtl8xxxu_write32_set(priv, REG_FPGA0_RF_MODE, FPGA_RF_MODE_OFDM); +} + +static int rtl8192fu_iqk_path_a(struct rtl8xxxu_priv *priv) +{ + u32 reg_eac, reg_e94, reg_e9c, val32; + u32 rf_0x58_i, rf_0x58_q; + u8 rfe = priv->rfe_type; + int result = 0; + int ktime, i; + + /* Leave IQK mode */ + rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); + + rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xccf000c0); + rtl8xxxu_write32(priv, REG_ANAPWR1, 0x44ffbb44); + rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00400040); + rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x6f005403); + rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000804e4); + rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x04203400); + rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100); + + rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_GAIN_CCA, BIT(4), 1); + rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_GAIN_CCA, BIT(11), 1); + if (rfe == 7 || rfe == 8 || rfe == 9 || rfe == 12) + val32 = 0x30; + else + val32 = 0xe9; + rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_PAD_TXG, 0x003ff, val32); + + rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000); + + /* path-A IQK setting */ + rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); + rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); + rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); + rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); + + rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x8214000f); + rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28140000); + + rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); + rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); + + /* LO calibration setting */ + rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00e62911); + + /* One shot, path A LOK & IQK */ + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa005800); + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8005800); + + mdelay(15); + + ktime = 0; + while (rtl8xxxu_read32(priv, REG_IQK_RPT_TXA) == 0 && ktime < 21) { + mdelay(5); + ktime += 5; + } + + /* Check failed */ + reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); + reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); + reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); + + /* reload 0xdf and CCK_IND off */ + rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); + + rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_WE_LUT, BIT(4), 1); + + val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_TXMOD); + rf_0x58_i = u32_get_bits(val32, 0xfc000); + rf_0x58_q = u32_get_bits(val32, 0x003f0); + + for (i = 0; i < 8; i++) { + rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_TXPA_G3, + 0x1c000, i); + rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_TXPA_G3, + 0x00fc0, rf_0x58_i); + rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_TXPA_G3, + 0x0003f, rf_0x58_q); + } + + rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_AC, BIT(14), 0); + rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_WE_LUT, BIT(4), 0); + rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_GAIN_CCA, 0x00810, 0); + + if (!(reg_eac & BIT(28)) && + ((reg_e94 & 0x03ff0000) != 0x01420000) && + ((reg_e9c & 0x03ff0000) != 0x00420000)) + result |= 0x01; + + return result; +} + +static int rtl8192fu_rx_iqk_path_a(struct rtl8xxxu_priv *priv) +{ + u32 reg_ea4, reg_eac, reg_e94, reg_e9c, val32; + int result = 0; + int ktime; + + /* Leave IQK mode */ + rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); + + /* PA/PAD control by 0x56, and set = 0x0 */ + rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_GAIN_CCA, BIT(1), 1); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_P1, 0); + rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_GAIN_CCA, BIT(11), 1); + rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_PAD_TXG, 0x003ff, 0x27); + + /* Enter IQK mode */ + rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000); + + /* path-A IQK setting */ + rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); + rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); + rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); + rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); + + rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160027); + rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160000); + + /* Tx IQK setting */ + rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); + rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); + + /* LO calibration setting */ + rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0086a911); + + /* One shot, path A LOK & IQK */ + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa005800); + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8005800); + + mdelay(15); + + ktime = 0; + while (rtl8xxxu_read32(priv, REG_IQK_RPT_TXA) == 0 && ktime < 21) { + mdelay(5); + ktime += 5; + } + + /* Check failed */ + reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); + reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); + reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); + + if (!(reg_eac & BIT(28)) && + ((reg_e94 & 0x03ff0000) != 0x01420000) && + ((reg_e9c & 0x03ff0000) != 0x00420000)) { + result |= 0x01; + } else { /* If TX not OK, ignore RX */ + /* PA/PAD controlled by 0x0 */ + rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); + + rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_GAIN_CCA, + BIT(11), 0); + + return result; + } + + val32 = 0x80007c00 | (reg_e94 & 0x3ff0000) | ((reg_e9c & 0x3ff0000) >> 16); + rtl8xxxu_write32(priv, REG_TX_IQK, val32); + + /* Modify RX IQK mode table */ + rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); + + /* PA/PAD control by 0x56, and set = 0x0 */ + rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_GAIN_CCA, BIT(1), 1); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_P1, 0); + rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_GAIN_CCA, BIT(11), 1); + rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_PAD_TXG, 0x003ff, 0x1e0); + + rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xccf000c0); + rtl8xxxu_write32(priv, REG_ANAPWR1, 0x44ffbb44); + rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00400040); + rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x6f005403); + rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000804e4); + rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x04203400); + rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100); + + /* Enter IQK mode */ + rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000); + + /* path-A IQK setting */ + rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); + rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c); + rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); + rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); + + rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82170000); + rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28170000); + + /* RX IQK setting */ + rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); + + /* LO calibration setting */ + rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a8d1); + + /* One shot, path A LOK & IQK */ + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa005800); + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8005800); + + mdelay(15); + + ktime = 0; + while (rtl8xxxu_read32(priv, REG_IQK_RPT_RXA) == 0 && ktime < 21) { + mdelay(5); + ktime += 5; + } + + /* Check failed */ + reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); + reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); + + /* Leave IQK mode */ + rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); + + rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_GAIN_CCA, BIT(11), 0); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_P1, 0x02000); + + if (!(reg_eac & BIT(27)) && + ((reg_ea4 & 0x03ff0000) != 0x01320000) && + ((reg_eac & 0x03ff0000) != 0x00360000)) + result |= 0x02; + + return result; +} + +static int rtl8192fu_iqk_path_b(struct rtl8xxxu_priv *priv) +{ + u32 reg_eac, reg_eb4, reg_ebc, val32; + u32 rf_0x58_i, rf_0x58_q; + u8 rfe = priv->rfe_type; + int result = 0; + int ktime, i; + + /* PA/PAD controlled by 0x0 */ + rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); + + rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xccf000c0); + rtl8xxxu_write32(priv, REG_ANAPWR1, 0x44ffbb44); + rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00400040); + rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x6f005403); + rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000804e4); + rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x04203400); + rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000000); + + rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_GAIN_CCA, BIT(4), 1); + rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_GAIN_CCA, BIT(11), 1); + if (rfe == 7 || rfe == 8 || rfe == 9 || rfe == 12) + rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_PAD_TXG, + 0x003ff, 0x30); + else + rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_PAD_TXG, + 0x00fff, 0xe9); + + rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000); + + /* Path B IQK setting */ + rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); + rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); + rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x18008c1c); + rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); + + rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x8214000F); + rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28140000); + + rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); + rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); + + /* LO calibration setting */ + rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00e62911); + + /* One shot, path B LOK & IQK */ + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa005800); + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8005800); + + mdelay(15); + + ktime = 0; + while (rtl8xxxu_read32(priv, REG_IQK_RPT_TXB) == 0 && ktime < 21) { + mdelay(5); + ktime += 5; + } + + /* Check failed */ + reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); + reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); + reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); + + /* reload 0xdf and CCK_IND off */ + rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); + + rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_WE_LUT, BIT(4), 1); + + val32 = rtl8xxxu_read_rfreg(priv, RF_B, RF6052_REG_TXMOD); + rf_0x58_i = u32_get_bits(val32, 0xfc000); + rf_0x58_q = u32_get_bits(val32, 0x003f0); + + for (i = 0; i < 8; i++) { + rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_TXPA_G3, + 0x1c000, i); + rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_TXPA_G3, + 0x00fc0, rf_0x58_i); + rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_TXPA_G3, + 0x0003f, rf_0x58_q); + } + + rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_AC, BIT(14), 0); + rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_WE_LUT, BIT(4), 0); + rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_GAIN_CCA, 0x00810, 0); + + if (!(reg_eac & BIT(31)) && + ((reg_eb4 & 0x03ff0000) != 0x01420000) && + ((reg_ebc & 0x03ff0000) != 0x00420000)) + result |= 0x01; + else + dev_warn(&priv->udev->dev, "%s: Path B IQK failed!\n", + __func__); + + return result; +} + +static int rtl8192fu_rx_iqk_path_b(struct rtl8xxxu_priv *priv) +{ + u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc, val32; + int result = 0; + int ktime; + + /* Leave IQK mode */ + rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); + + rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_GAIN_CCA, BIT(1), 1); + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_P1, 0); + rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_GAIN_CCA, BIT(11), 1); + rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_PAD_TXG, 0x003ff, 0x67); + + rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xccf000c0); + rtl8xxxu_write32(priv, REG_ANAPWR1, 0x44ffbb44); + rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00400040); + rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x6f005403); + rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000804e4); + rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x04203400); + rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000000); + + rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000); + + /* path-B IQK setting */ + rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); + rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); + rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x18008c1c); + rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); + + rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82160027); + rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160000); + + /* LO calibration setting */ + rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0086a911); + + /* One shot, path A LOK & IQK */ + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa005800); + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8005800); + + mdelay(15); + + ktime = 0; + while (rtl8xxxu_read32(priv, REG_IQK_RPT_TXB) == 0 && ktime < 21) { + mdelay(5); + ktime += 5; + } + + /* Check failed */ + reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); + reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); + reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); + + if (!(reg_eac & BIT(31)) && + ((reg_eb4 & 0x03ff0000) != 0x01420000) && + ((reg_ebc & 0x03ff0000) != 0x00420000)) { + result |= 0x01; + } else { + /* PA/PAD controlled by 0x0 */ + rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); + + rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_GAIN_CCA, + BIT(11), 0); + + return result; + } + + val32 = 0x80007c00 | (reg_eb4 & 0x03ff0000) | ((reg_ebc >> 16) & 0x03ff); + rtl8xxxu_write32(priv, REG_TX_IQK, val32); + + /* Modify RX IQK mode table */ + rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); + + rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_GAIN_CCA, BIT(1), 1); + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_P1, 0); + rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_GAIN_CCA, BIT(11), 1); + rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_PAD_TXG, 0x003ff, 0x1e0); + + rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xccf000c0); + rtl8xxxu_write32(priv, REG_ANAPWR1, 0x44ffbb44); + rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00400040); + rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x6f005403); + rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000804e4); + rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x04203400); + rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000000); + + rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000); + + /* Path B IQK setting */ + rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); + rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); + rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); + rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x18008c1c); + + rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82170000); + rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28170000); + + /* IQK setting */ + rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); + + /* LO calibration setting */ + rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911); + + /* One shot, path A LOK & IQK */ + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa005800); + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8005800); + + mdelay(15); + + ktime = 0; + while (rtl8xxxu_read32(priv, REG_IQK_RPT_RXB) == 0 && ktime < 21) { + mdelay(5); + ktime += 5; + } + + reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); + reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2); + reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2); + + rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); + rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100); + + rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_GAIN_CCA, BIT(11), 0); + rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_GAIN_CCA, BIT(1), 0); + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_P1, 0x02000); + + if (!(reg_eac & BIT(30)) && + ((reg_ec4 & 0x03ff0000) != 0x01320000) && + ((reg_ecc & 0x03ff0000) != 0x00360000)) + result |= 0x02; + else + dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n", + __func__); + + return result; +} + +static void rtl8192fu_phy_iqcalibrate(struct rtl8xxxu_priv *priv, + int result[][8], int t) +{ + static const u32 adda_regs[2] = { + REG_ANAPWR1, REG_RX_WAIT_CCA + }; + static const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = { + REG_TXPAUSE, REG_BEACON_CTRL, + REG_BEACON_CTRL_1, REG_GPIO_MUXCFG + }; + static const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = { + REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR, + REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, + REG_DPDT_CTRL, REG_RFE_CTRL_ANTA_SRC, + REG_RFE_CTRL_ANT_SRC2, REG_CCK0_AFE_SETTING + }; + u32 rx_initial_gain_a, rx_initial_gain_b; + struct device *dev = &priv->udev->dev; + int path_a_ok, path_b_ok; + u8 rfe = priv->rfe_type; + int retry = 2; + u32 i, val32; + + /* + * Note: IQ calibration must be performed after loading + * PHY_REG.txt , and radio_a, radio_b.txt + */ + + rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); + + rx_initial_gain_a = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); + rx_initial_gain_b = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1); + + if (t == 0) { + /* Save ADDA parameters, turn Path A ADDA on */ + rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup, + ARRAY_SIZE(adda_regs)); + rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup); + rtl8xxxu_save_regs(priv, iqk_bb_regs, + priv->bb_backup, RTL8XXXU_BB_REGS); + } + + /* Instead of rtl8xxxu_path_adda_on */ + rtl8xxxu_write32_set(priv, REG_FPGA0_XCD_RF_PARM, BIT(31)); + + /* MAC settings */ + rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); + rtl8xxxu_write8_clear(priv, REG_GPIO_MUXCFG, GPIO_MUXCFG_IO_SEL_ENBT); + + if (rfe == 7 || rfe == 8 || rfe == 9 || rfe == 12) { + /* in ePA IQK, rfe_func_config & SW both pull down */ + /* path A */ + rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANTA_SRC, 0xF, 0x7); + rtl8xxxu_write32_mask(priv, REG_DPDT_CTRL, 0x1, 0x0); + + rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANTA_SRC, 0xF00, 0x7); + rtl8xxxu_write32_mask(priv, REG_DPDT_CTRL, 0x4, 0x0); + + rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANTA_SRC, 0xF000, 0x7); + rtl8xxxu_write32_mask(priv, REG_DPDT_CTRL, 0x8, 0x0); + + /* path B */ + rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC2, 0xF0, 0x7); + rtl8xxxu_write32_mask(priv, REG_DPDT_CTRL, 0x20000, 0x0); + + rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC2, 0xF0000, 0x7); + rtl8xxxu_write32_mask(priv, REG_DPDT_CTRL, 0x100000, 0x0); + + rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC3, 0xF000, 0x7); + rtl8xxxu_write32_mask(priv, REG_DPDT_CTRL, 0x8000000, 0x0); + } + + if (priv->rf_paths > 1) { + /* path B standby */ + rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x000000); + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x10000); + rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000); + } + + for (i = 0; i < retry; i++) { + path_a_ok = rtl8192fu_iqk_path_a(priv); + + if (path_a_ok == 0x01) { + val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); + result[t][0] = (val32 >> 16) & 0x3ff; + + val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); + result[t][1] = (val32 >> 16) & 0x3ff; + break; + } else { + result[t][0] = 0x100; + result[t][1] = 0x0; + } + } + + for (i = 0; i < retry; i++) { + path_a_ok = rtl8192fu_rx_iqk_path_a(priv); + + if (path_a_ok == 0x03) { + val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); + result[t][2] = (val32 >> 16) & 0x3ff; + + val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); + result[t][3] = (val32 >> 16) & 0x3ff; + break; + } else { + result[t][2] = 0x100; + result[t][3] = 0x0; + } + } + + if (!path_a_ok) + dev_warn(dev, "%s: Path A IQK failed!\n", __func__); + + if (priv->rf_paths > 1) { + for (i = 0; i < retry; i++) { + path_b_ok = rtl8192fu_iqk_path_b(priv); + + if (path_b_ok == 0x01) { + val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); + result[t][4] = (val32 >> 16) & 0x3ff; + + val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); + result[t][5] = (val32 >> 16) & 0x3ff; + break; + } else { + result[t][4] = 0x100; + result[t][5] = 0x0; + } + } + + for (i = 0; i < retry; i++) { + path_b_ok = rtl8192fu_rx_iqk_path_b(priv); + + if (path_b_ok == 0x03) { + val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2); + result[t][6] = (val32 >> 16) & 0x3ff; + + val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2); + result[t][7] = (val32 >> 16) & 0x3ff; + break; + } else { + result[t][6] = 0x100; + result[t][7] = 0x0; + } + } + + if (!path_b_ok) + dev_warn(dev, "%s: Path B IQK failed!\n", __func__); + } + + /* Back to BB mode, load original value */ + rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); + + rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xcc0000c0); + + rtl8xxxu_write32(priv, REG_ANAPWR1, 0x44bbbb44); + rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x80408040); + rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x6f005433); + rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000004e4); + rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x04003400); + rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100); + + /* Reload ADDA power saving parameters */ + rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup, + ARRAY_SIZE(adda_regs)); + + /* Reload MAC parameters */ + rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup); + + /* Reload BB parameters */ + rtl8xxxu_restore_regs(priv, iqk_bb_regs, priv->bb_backup, RTL8XXXU_BB_REGS); + + rtl8xxxu_write32_clear(priv, REG_FPGA0_XCD_RF_PARM, BIT(31)); + + /* Restore RX initial gain */ + rtl8xxxu_write32_mask(priv, REG_OFDM0_XA_AGC_CORE1, 0xff, 0x50); + rtl8xxxu_write32_mask(priv, REG_OFDM0_XA_AGC_CORE1, 0xff, + rx_initial_gain_a & 0xff); + if (priv->rf_paths > 1) { + rtl8xxxu_write32_mask(priv, REG_OFDM0_XB_AGC_CORE1, 0xff, 0x50); + rtl8xxxu_write32_mask(priv, REG_OFDM0_XB_AGC_CORE1, 0xff, + rx_initial_gain_b & 0xff); + } +} + +static void rtl8192fu_phy_iq_calibrate(struct rtl8xxxu_priv *priv) +{ + s32 reg_e94, reg_e9c, reg_ea4, reg_eac; + s32 reg_eb4, reg_ebc, reg_ec4, reg_ecc; + struct device *dev = &priv->udev->dev; + u32 path_a_0xdf, path_a_0x35; + u32 path_b_0xdf, path_b_0x35; + bool path_a_ok, path_b_ok; + u8 rfe = priv->rfe_type; + u32 rfe_path_select; + int result[4][8]; /* last is final result */ + int i, candidate; + s32 reg_tmp = 0; + bool simu; + u32 val32; + + rfe_path_select = rtl8xxxu_read32(priv, REG_RFE_PATH_SELECT); + + path_a_0xdf = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA); + path_a_0x35 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_GAIN_P1); + path_b_0xdf = rtl8xxxu_read_rfreg(priv, RF_B, RF6052_REG_GAIN_CCA); + path_b_0x35 = rtl8xxxu_read_rfreg(priv, RF_B, RF6052_REG_GAIN_P1); + + memset(result, 0, sizeof(result)); + candidate = -1; + + path_a_ok = false; + path_b_ok = false; + + for (i = 0; i < 3; i++) { + rtl8192fu_phy_iqcalibrate(priv, result, i); + + if (i == 1) { + simu = rtl8xxxu_gen2_simularity_compare(priv, result, 0, 1); + if (simu) { + candidate = 0; + break; + } + } + + if (i == 2) { + simu = rtl8xxxu_gen2_simularity_compare(priv, result, 0, 2); + if (simu) { + candidate = 0; + break; + } + + simu = rtl8xxxu_gen2_simularity_compare(priv, result, 1, 2); + if (simu) { + candidate = 1; + } else { + for (i = 0; i < 8; i++) + reg_tmp += result[3][i]; + + if (reg_tmp) + candidate = 3; + else + candidate = -1; + } + } + } + + if (candidate >= 0) { + reg_e94 = result[candidate][0]; + reg_e9c = result[candidate][1]; + reg_ea4 = result[candidate][2]; + reg_eac = result[candidate][3]; + reg_eb4 = result[candidate][4]; + reg_ebc = result[candidate][5]; + reg_ec4 = result[candidate][6]; + reg_ecc = result[candidate][7]; + + dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate); + dev_dbg(dev, "%s: e94=%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x ecc=%c\n", + __func__, reg_e94, reg_e9c, reg_ea4, reg_eac, + reg_eb4, reg_ebc, reg_ec4, reg_ecc); + + path_a_ok = true; + path_b_ok = true; + } + + rtl8xxxu_write32_mask(priv, REG_TX_IQK_TONE_A, 0x3ff00000, 0x100); + rtl8xxxu_write32_mask(priv, REG_NP_ANTA, 0x3ff, 0); + rtl8xxxu_write32_mask(priv, REG_TX_IQK_TONE_B, 0x3ff00000, 0x100); + rtl8xxxu_write32_mask(priv, REG_TAP_UPD_97F, 0x3ff, 0); + + if (candidate >= 0) { + if (reg_e94) + rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result, + candidate, (reg_ea4 == 0)); + + if (reg_eb4) + rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result, + candidate, (reg_ec4 == 0)); + } + + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, path_a_0xdf); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_P1, path_a_0x35); + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_CCA, path_b_0xdf); + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_P1, path_b_0x35); + + if (rfe == 7 || rfe == 8 || rfe == 9 || rfe == 12) { + rtl8xxxu_write32_set(priv, REG_SW_GPIO_SHARE_CTRL_1, 0x70000); + rtl8xxxu_write32_clear(priv, REG_LEDCFG0, 0x6c00000); + rtl8xxxu_write32_set(priv, REG_PAD_CTRL1, BIT(29) | BIT(28)); + rtl8xxxu_write32_clear(priv, REG_SW_GPIO_SHARE_CTRL_0, + 0x600000 | BIT(4)); + + /* + * Originally: + * odm_set_bb_reg(dm, R_0x944, BIT(11) | 0x1F, 0x3F); + * + * It clears bit 11 and sets bits 0..4. The mask doesn't cover + * bit 5 so it's not modified. Is that what it's supposed to + * accomplish? + */ + val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER); + val32 &= ~BIT(11); + val32 |= 0x1f; + rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32); + + if (rfe == 7) { + rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANTA_SRC, + 0xfffff, 0x23200); + rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC2, + 0xfffff, 0x23200); + rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC1, + 0xf000, 0x3); + rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC3, + 0xf000, 0x3); + } else { + rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANTA_SRC, + 0xfffff, 0x22200); + rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC2, + 0xfffff, 0x22200); + rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC1, + 0xf000, 0x2); + rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC3, + 0xf000, 0x2); + } + + rtl8xxxu_write32_clear(priv, REG_RFE_OPT62, BIT(2)); + + if (rfe == 7) + rtl8xxxu_write32(priv, REG_RFE_OPT, 0x03000003); + + rtl8xxxu_write32(priv, REG_RFE_PATH_SELECT, rfe_path_select); + } +} + +static void rtl8192fu_disabled_to_emu(struct rtl8xxxu_priv *priv) +{ + rtl8xxxu_write16_clear(priv, REG_APS_FSMCO, + APS_FSMCO_HW_POWERDOWN | APS_FSMCO_HW_SUSPEND); + + rtl8xxxu_write32_clear(priv, REG_GPIO_INTM, BIT(16)); + + rtl8xxxu_write16_clear(priv, REG_APS_FSMCO, + APS_FSMCO_PCIE | APS_FSMCO_HW_SUSPEND); +} + +static int rtl8192fu_emu_to_active(struct rtl8xxxu_priv *priv) +{ + u32 val32; + u16 val16; + int count; + + /* enable LDOA12 MACRO block for all interface */ + rtl8xxxu_write8_set(priv, REG_LDOA15_CTRL, LDOA15_ENABLE); + + /* disable BT_GPS_SEL pins */ + rtl8xxxu_write32_clear(priv, REG_PAD_CTRL1, BIT(28)); + + mdelay(1); + + /* release analog Ips to digital */ + rtl8xxxu_write8_clear(priv, REG_SYS_ISO_CTRL, SYS_ISO_ANALOG_IPS); + + val16 = APS_FSMCO_PCIE | APS_FSMCO_HW_SUSPEND | APS_FSMCO_SW_LPS; + rtl8xxxu_write16_clear(priv, REG_APS_FSMCO, val16); + + /* wait till 0x04[17] = 1 power ready */ + for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { + val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); + if (val32 & BIT(17)) + break; + + udelay(10); + } + + if (!count) + return -EBUSY; + + rtl8xxxu_write32_set(priv, REG_APS_FSMCO, APS_FSMCO_WLON_RESET); + + for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { + val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); + if ((val32 & (APS_FSMCO_MAC_ENABLE | APS_FSMCO_MAC_OFF)) == 0) + break; + + udelay(10); + } + + if (!count) + return -EBUSY; + + /* SWR OCP enable */ + rtl8xxxu_write32_set(priv, REG_AFE_MISC, BIT(18)); + + rtl8xxxu_write16_clear(priv, REG_APS_FSMCO, APS_FSMCO_HW_POWERDOWN); + + rtl8xxxu_write16_clear(priv, REG_APS_FSMCO, + APS_FSMCO_PCIE | APS_FSMCO_HW_SUSPEND); + + /* 0x7c[31]=1, LDO has max output capability */ + rtl8xxxu_write32_set(priv, REG_LDO_SW_CTRL, BIT(31)); + + rtl8xxxu_write16_set(priv, REG_APS_FSMCO, APS_FSMCO_MAC_ENABLE); + + for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { + val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); + if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) + break; + + udelay(10); + } + + if (!count) + return -EBUSY; + + /* Enable WL control XTAL setting */ + rtl8xxxu_write8_set(priv, REG_AFE_MISC, AFE_MISC_WL_XTAL_CTRL); + + /* Enable falling edge triggering interrupt */ + rtl8xxxu_write16_set(priv, REG_GPIO_INTM, GPIO_INTM_EDGE_TRIG_IRQ); + + /* Enable GPIO9 data mode */ + rtl8xxxu_write16_clear(priv, REG_GPIO_IO_SEL_2, GPIO_IO_SEL_2_GPIO09_IRQ); + + /* Enable GPIO9 input mode */ + rtl8xxxu_write16_clear(priv, REG_GPIO_IO_SEL_2, GPIO_IO_SEL_2_GPIO09_INPUT); + + /* Enable HSISR GPIO[C:0] interrupt */ + rtl8xxxu_write8_set(priv, REG_HSIMR, BIT(0)); + + /* RF HW ON/OFF Enable */ + rtl8xxxu_write8_clear(priv, REG_MULTI_FUNC_CTRL, MULTI_WIFI_HW_ROF_EN); + + /* Register Lock Disable */ + rtl8xxxu_write8_set(priv, REG_RSV_CTRL, BIT(7)); + + /* For GPIO9 internal pull high setting */ + rtl8xxxu_write16_set(priv, REG_MULTI_FUNC_CTRL, BIT(14)); + + /* reset RF path S1 */ + rtl8xxxu_write8(priv, REG_RF_CTRL, 0); + + /* reset RF path S0 */ + rtl8xxxu_write8(priv, REG_AFE_CTRL4 + 3, 0); + + /* enable RF path S1 */ + rtl8xxxu_write8(priv, REG_RF_CTRL, RF_SDMRSTB | RF_RSTB | RF_ENABLE); + + /* enable RF path S0 */ + rtl8xxxu_write8(priv, REG_AFE_CTRL4 + 3, RF_SDMRSTB | RF_RSTB | RF_ENABLE); + + /* AFE_Ctrl */ + rtl8xxxu_write8_set(priv, REG_RSVD_1, BIT(5)); + + /* AFE_Ctrl */ + rtl8xxxu_write8(priv, REG_RSVD_4, 0xcc); + + /* AFE_Ctrl 0x24[4:3]=00 for xtal gmn */ + rtl8xxxu_write8_clear(priv, REG_AFE_XTAL_CTRL, BIT(4) | BIT(3)); + + /* GPIO_A[31:0] Pull down software register */ + rtl8xxxu_write32(priv, REG_GPIO_A0, 0xffffffff); + + /* GPIO_B[7:0] Pull down software register */ + rtl8xxxu_write8(priv, REG_GPIO_B0, 0xff); + + /* Register Lock Enable */ + rtl8xxxu_write8_clear(priv, REG_RSV_CTRL, BIT(7)); + + return 0; +} + +static int rtl8192fu_active_to_emu(struct rtl8xxxu_priv *priv) +{ + u32 val32; + int count; + + /* Reset BB, RF enter Power Down mode */ + rtl8xxxu_write8_clear(priv, REG_SYS_FUNC, SYS_FUNC_BBRSTB); + + /* Enable rising edge triggering interrupt */ + rtl8xxxu_write16_clear(priv, REG_GPIO_INTM, GPIO_INTM_EDGE_TRIG_IRQ); + + /* release WLON reset */ + rtl8xxxu_write32_set(priv, REG_APS_FSMCO, APS_FSMCO_WLON_RESET); + + /* turn off MAC by HW state machine */ + rtl8xxxu_write16_set(priv, REG_APS_FSMCO, APS_FSMCO_MAC_OFF); + + for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { + val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); + if ((val32 & APS_FSMCO_MAC_OFF) == 0) + break; + + udelay(10); + } + + if (!count) + return -EBUSY; + + /* analog Ips to digital, 1:isolation */ + rtl8xxxu_write8_set(priv, REG_SYS_ISO_CTRL, SYS_ISO_ANALOG_IPS); + + /* disable LDOA12 MACRO block */ + rtl8xxxu_write8_clear(priv, REG_LDOA15_CTRL, LDOA15_ENABLE); + + return 0; +} + +static int rtl8192fu_emu_to_disabled(struct rtl8xxxu_priv *priv) +{ + u16 val16; + + /* SOP option to disable BG/MB */ + rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20); + + /* 0x04[12:11] = 2b'01 enable WL suspend */ + val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO); + val16 &= ~APS_FSMCO_PCIE; + val16 |= APS_FSMCO_HW_SUSPEND; + rtl8xxxu_write16(priv, REG_APS_FSMCO, val16); + + /* enable GPIO9 as EXT WAKEUP */ + rtl8xxxu_write32_set(priv, REG_GPIO_INTM, BIT(16)); + + return 0; +} + +static int rtl8192fu_active_to_lps(struct rtl8xxxu_priv *priv) +{ + struct device *dev = &priv->udev->dev; + u16 val16; + u32 val32; + int retry; + + /* Tx Pause */ + rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); + + retry = 100; + + /* Poll 32 bit wide REG_SCH_TX_CMD for 0 to ensure no TX is pending. */ + do { + val32 = rtl8xxxu_read32(priv, REG_SCH_TX_CMD); + if (!val32) + break; + + udelay(10); + } while (retry--); + + if (!retry) { + dev_warn(dev, "%s: Failed to flush TX queue\n", __func__); + return -EBUSY; + } + + /* Disable CCK and OFDM, clock gated */ + rtl8xxxu_write8_clear(priv, REG_SYS_FUNC, SYS_FUNC_BBRSTB); + + udelay(2); + + /* Whole BB is reset */ + rtl8xxxu_write8_clear(priv, REG_SYS_FUNC, SYS_FUNC_BB_GLB_RSTN); + + /* Reset MAC TRX */ + val16 = rtl8xxxu_read16(priv, REG_CR); + val16 &= 0xff00; + val16 |= CR_HCI_RXDMA_ENABLE | CR_HCI_TXDMA_ENABLE; + val16 &= ~CR_SECURITY_ENABLE; + rtl8xxxu_write16(priv, REG_CR, val16); + + /* Respond TxOK to scheduler */ + rtl8xxxu_write8_set(priv, REG_DUAL_TSF_RST, DUAL_TSF_TX_OK); + + return 0; +} + +static int rtl8192fu_power_on(struct rtl8xxxu_priv *priv) +{ + u16 val16; + int ret; + + rtl8xxxu_write8(priv, REG_USB_ACCESS_TIMEOUT, 0x80); + + rtl8192fu_disabled_to_emu(priv); + + ret = rtl8192fu_emu_to_active(priv); + if (ret) + return ret; + + rtl8xxxu_write16(priv, REG_CR, 0); + + val16 = rtl8xxxu_read16(priv, REG_CR); + + val16 |= CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE | + CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | + CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE | + CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE; + rtl8xxxu_write16(priv, REG_CR, val16); + + return 0; +} + +static void rtl8192fu_power_off(struct rtl8xxxu_priv *priv) +{ + rtl8xxxu_flush_fifo(priv); + + /* Stop Tx Report Timer. 0x4EC[Bit1]=b'0 */ + rtl8xxxu_write8_clear(priv, REG_TX_REPORT_CTRL, + TX_REPORT_CTRL_TIMER_ENABLE); + + /* stop rx */ + rtl8xxxu_write8(priv, REG_CR, 0x00); + + rtl8192fu_active_to_lps(priv); + + /* Reset Firmware if running in RAM */ + if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL) + rtl8xxxu_firmware_self_reset(priv); + + /* Reset MCU */ + rtl8xxxu_write16_clear(priv, REG_SYS_FUNC, SYS_FUNC_CPU_ENABLE); + + /* Reset MCU ready status */ + rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00); + + rtl8192fu_active_to_emu(priv); + rtl8192fu_emu_to_disabled(priv); +} + +static void rtl8192f_reset_8051(struct rtl8xxxu_priv *priv) +{ + rtl8xxxu_write8_clear(priv, REG_RSV_CTRL, BIT(1)); + + rtl8xxxu_write8_clear(priv, REG_RSV_CTRL + 1, BIT(0)); + + rtl8xxxu_write16_clear(priv, REG_SYS_FUNC, SYS_FUNC_CPU_ENABLE); + + rtl8xxxu_write8_clear(priv, REG_RSV_CTRL, BIT(1)); + + rtl8xxxu_write8_set(priv, REG_RSV_CTRL + 1, BIT(0)); + + rtl8xxxu_write16_set(priv, REG_SYS_FUNC, SYS_FUNC_CPU_ENABLE); +} + +static void rtl8192f_enable_rf(struct rtl8xxxu_priv *priv) +{ + u32 val32; + + rtl8xxxu_write8(priv, REG_RF_CTRL, RF_ENABLE | RF_RSTB | RF_SDMRSTB); + + val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); + val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK); + val32 |= OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B | + OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B; + rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); + + rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); +} + +static void rtl8192f_disable_rf(struct rtl8xxxu_priv *priv) +{ + u32 val32; + + val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); + val32 &= ~OFDM_RF_PATH_TX_MASK; + rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); + + /* Power down RF module */ + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0); +} + +static void rtl8192f_usb_quirks(struct rtl8xxxu_priv *priv) +{ + u16 val16; + + rtl8xxxu_gen2_usb_quirks(priv); + + val16 = rtl8xxxu_read16(priv, REG_CR); + val16 |= (CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE); + rtl8xxxu_write16(priv, REG_CR, val16); +} + +#define XTAL1 GENMASK(6, 1) +#define XTAL0 GENMASK(30, 25) + +static void rtl8192f_set_crystal_cap(struct rtl8xxxu_priv *priv, u8 crystal_cap) +{ + struct rtl8xxxu_cfo_tracking *cfo = &priv->cfo_tracking; + u32 xtal1, xtal0; + + if (crystal_cap == cfo->crystal_cap) + return; + + xtal1 = rtl8xxxu_read32(priv, REG_AFE_PLL_CTRL); + xtal0 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL); + + dev_dbg(&priv->udev->dev, + "%s: Adjusting crystal cap from 0x%x (actually 0x%x 0x%x) to 0x%x\n", + __func__, + cfo->crystal_cap, + u32_get_bits(xtal1, XTAL1), + u32_get_bits(xtal0, XTAL0), + crystal_cap); + + u32p_replace_bits(&xtal1, crystal_cap, XTAL1); + u32p_replace_bits(&xtal0, crystal_cap, XTAL0); + rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, xtal1); + rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, xtal0); + + cfo->crystal_cap = crystal_cap; +} + +static s8 rtl8192f_cck_rssi(struct rtl8xxxu_priv *priv, struct rtl8723au_phy_stats *phy_stats) +{ + struct jaguar2_phy_stats_type0 *phy_stats0 = (struct jaguar2_phy_stats_type0 *)phy_stats; + u8 lna_idx = (phy_stats0->lna_h << 3) | phy_stats0->lna_l; + u8 vga_idx = phy_stats0->vga; + s8 rx_pwr_all; + + switch (lna_idx) { + case 7: + rx_pwr_all = -44 - (2 * vga_idx); + break; + case 5: + rx_pwr_all = -28 - (2 * vga_idx); + break; + case 3: + rx_pwr_all = -10 - (2 * vga_idx); + break; + case 0: + rx_pwr_all = 14 - (2 * vga_idx); + break; + default: + rx_pwr_all = 0; + break; + } + + return rx_pwr_all; +} + +static int rtl8192fu_led_brightness_set(struct led_classdev *led_cdev, + enum led_brightness brightness) +{ + struct rtl8xxxu_priv *priv = container_of(led_cdev, + struct rtl8xxxu_priv, + led_cdev); + u32 ledcfg; + + /* Values obtained by observing the USB traffic from the Windows driver. */ + rtl8xxxu_write32(priv, REG_SW_GPIO_SHARE_CTRL_0, 0x20080); + rtl8xxxu_write32(priv, REG_SW_GPIO_SHARE_CTRL_1, 0x1b0000); + + ledcfg = rtl8xxxu_read32(priv, REG_LEDCFG0); + + /* Comfast CF-826F uses LED1. Asus USB-N13 C1 uses LED0. Set both. */ + + u32p_replace_bits(&ledcfg, LED_GPIO_ENABLE, LEDCFG0_LED2EN); + u32p_replace_bits(&ledcfg, LED_IO_MODE_OUTPUT, LEDCFG0_LED0_IO_MODE); + u32p_replace_bits(&ledcfg, LED_IO_MODE_OUTPUT, LEDCFG0_LED1_IO_MODE); + + if (brightness == LED_OFF) { + u32p_replace_bits(&ledcfg, LED_MODE_SW_CTRL, LEDCFG0_LED0CM); + u32p_replace_bits(&ledcfg, LED_SW_OFF, LEDCFG0_LED0SV); + u32p_replace_bits(&ledcfg, LED_MODE_SW_CTRL, LEDCFG0_LED1CM); + u32p_replace_bits(&ledcfg, LED_SW_OFF, LEDCFG0_LED1SV); + } else if (brightness == LED_ON) { + u32p_replace_bits(&ledcfg, LED_MODE_SW_CTRL, LEDCFG0_LED0CM); + u32p_replace_bits(&ledcfg, LED_SW_ON, LEDCFG0_LED0SV); + u32p_replace_bits(&ledcfg, LED_MODE_SW_CTRL, LEDCFG0_LED1CM); + u32p_replace_bits(&ledcfg, LED_SW_ON, LEDCFG0_LED1SV); + } else if (brightness == RTL8XXXU_HW_LED_CONTROL) { + u32p_replace_bits(&ledcfg, LED_MODE_TX_OR_RX_EVENTS, + LEDCFG0_LED0CM); + u32p_replace_bits(&ledcfg, LED_SW_OFF, LEDCFG0_LED0SV); + u32p_replace_bits(&ledcfg, LED_MODE_TX_OR_RX_EVENTS, + LEDCFG0_LED1CM); + u32p_replace_bits(&ledcfg, LED_SW_OFF, LEDCFG0_LED1SV); + } + + rtl8xxxu_write32(priv, REG_LEDCFG0, ledcfg); + + return 0; +} + +struct rtl8xxxu_fileops rtl8192fu_fops = { + .identify_chip = rtl8192fu_identify_chip, + .parse_efuse = rtl8192fu_parse_efuse, + .load_firmware = rtl8192fu_load_firmware, + .power_on = rtl8192fu_power_on, + .power_off = rtl8192fu_power_off, + .read_efuse = rtl8xxxu_read_efuse, + .reset_8051 = rtl8192f_reset_8051, + .llt_init = rtl8xxxu_auto_llt_table, + .init_phy_bb = rtl8192fu_init_phy_bb, + .init_phy_rf = rtl8192fu_init_phy_rf, + .phy_lc_calibrate = rtl8192f_phy_lc_calibrate, + .phy_iq_calibrate = rtl8192fu_phy_iq_calibrate, + .config_channel = rtl8192fu_config_channel, + .parse_rx_desc = rtl8xxxu_parse_rxdesc24, + .parse_phystats = jaguar2_rx_parse_phystats, + .init_aggregation = rtl8192fu_init_aggregation, + .init_burst = rtl8xxxu_init_burst, + .enable_rf = rtl8192f_enable_rf, + .disable_rf = rtl8192f_disable_rf, + .usb_quirks = rtl8192f_usb_quirks, + .set_tx_power = rtl8192f_set_tx_power, + .update_rate_mask = rtl8xxxu_gen2_update_rate_mask, + .report_connect = rtl8xxxu_gen2_report_connect, + .report_rssi = rtl8xxxu_gen2_report_rssi, + .fill_txdesc = rtl8xxxu_fill_txdesc_v2, + .set_crystal_cap = rtl8192f_set_crystal_cap, + .cck_rssi = rtl8192f_cck_rssi, + .led_classdev_brightness_set = rtl8192fu_led_brightness_set, + .writeN_block_size = 254, + .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc24), + .tx_desc_size = sizeof(struct rtl8xxxu_txdesc40), + .has_tx_report = 1, + .gen2_thermal_meter = 1, + .needs_full_init = 1, + .init_reg_rxfltmap = 1, + .init_reg_pkt_life_time = 1, + .init_reg_hmtfr = 1, + .ampdu_max_time = 0x5e, + .ustime_tsf_edca = 0x50, + .max_aggr_num = 0x1f1f, + .supports_ap = 1, + .max_macid_num = 128, + .max_sec_cam_num = 64, + .trxff_boundary = 0x3f3f, + .pbp_rx = PBP_PAGE_SIZE_256, + .pbp_tx = PBP_PAGE_SIZE_256, + .mactable = rtl8192f_mac_init_table, + .total_page_num = TX_TOTAL_PAGE_NUM_8192F, + .page_num_hi = TX_PAGE_NUM_HI_PQ_8192F, + .page_num_lo = TX_PAGE_NUM_LO_PQ_8192F, + .page_num_norm = TX_PAGE_NUM_NORM_PQ_8192F, +}; diff --git a/drivers/net/wireless/realtek/rtl8xxxu/8710b.c b/drivers/net/wireless/realtek/rtl8xxxu/8710b.c new file mode 100644 index 000000000000..ea1cb0d8554e --- /dev/null +++ b/drivers/net/wireless/realtek/rtl8xxxu/8710b.c @@ -0,0 +1,1887 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * RTL8XXXU mac80211 USB driver - 8710bu aka 8188gu specific subdriver + * + * Copyright (c) 2023 Bitterblue Smith + * + * Portions copied from existing rtl8xxxu code: + * Copyright (c) 2014 - 2017 Jes Sorensen + * + * Portions, notably calibration code: + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "rtl8xxxu.h" +#include "regs.h" + +static const struct rtl8xxxu_reg8val rtl8710b_mac_init_table[] = { + {0x421, 0x0F}, {0x428, 0x0A}, {0x429, 0x10}, {0x430, 0x00}, + {0x431, 0x00}, {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, + {0x435, 0x05}, {0x436, 0x07}, {0x437, 0x08}, {0x43C, 0x04}, + {0x43D, 0x05}, {0x43E, 0x07}, {0x43F, 0x08}, {0x440, 0x5D}, + {0x441, 0x01}, {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, + {0x446, 0x00}, {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xF0}, + {0x44A, 0x0F}, {0x44B, 0x3E}, {0x44C, 0x10}, {0x44D, 0x00}, + {0x44E, 0x00}, {0x44F, 0x00}, {0x450, 0x00}, {0x451, 0xF0}, + {0x452, 0x0F}, {0x453, 0x00}, {0x456, 0x5E}, {0x460, 0x66}, + {0x461, 0x66}, {0x4C8, 0xFF}, {0x4C9, 0x08}, {0x4CC, 0xFF}, + {0x4CD, 0xFF}, {0x4CE, 0x01}, {0x500, 0x26}, {0x501, 0xA2}, + {0x502, 0x2F}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xA3}, + {0x506, 0x5E}, {0x507, 0x00}, {0x508, 0x2B}, {0x509, 0xA4}, + {0x50A, 0x5E}, {0x50B, 0x00}, {0x50C, 0x4F}, {0x50D, 0xA4}, + {0x50E, 0x00}, {0x50F, 0x00}, {0x512, 0x1C}, {0x514, 0x0A}, + {0x516, 0x0A}, {0x525, 0x4F}, {0x550, 0x10}, {0x551, 0x10}, + {0x559, 0x02}, {0x55C, 0x28}, {0x55D, 0xFF}, {0x605, 0x30}, + {0x608, 0x0E}, {0x609, 0x2A}, {0x620, 0xFF}, {0x621, 0xFF}, + {0x622, 0xFF}, {0x623, 0xFF}, {0x624, 0xFF}, {0x625, 0xFF}, + {0x626, 0xFF}, {0x627, 0xFF}, {0x638, 0x28}, {0x63C, 0x0A}, + {0x63D, 0x0A}, {0x63E, 0x0C}, {0x63F, 0x0C}, {0x640, 0x40}, + {0x642, 0x40}, {0x643, 0x00}, {0x652, 0xC8}, {0x66A, 0xB0}, + {0x66E, 0x05}, {0x700, 0x21}, {0x701, 0x43}, {0x702, 0x65}, + {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43}, {0x70A, 0x65}, + {0x70B, 0x87}, + {0xffff, 0xff}, +}; + +/* If updating the phy init tables, also update rtl8710b_revise_cck_tx_psf(). */ +static const struct rtl8xxxu_reg32val rtl8710bu_qfn48m_u_phy_init_table[] = { + {0x800, 0x80045700}, {0x804, 0x00000001}, + {0x808, 0x00FC8000}, {0x80C, 0x0000000A}, + {0x810, 0x10001331}, {0x814, 0x020C3D10}, + {0x818, 0x00200385}, {0x81C, 0x00000000}, + {0x820, 0x01000100}, {0x824, 0x00390204}, + {0x828, 0x00000000}, {0x82C, 0x00000000}, + {0x830, 0x00000000}, {0x834, 0x00000000}, + {0x838, 0x00000000}, {0x83C, 0x00000000}, + {0x840, 0x00010000}, {0x844, 0x00000000}, + {0x848, 0x00000000}, {0x84C, 0x00000000}, + {0x850, 0x00030000}, {0x854, 0x00000000}, + {0x858, 0x7E1A569A}, {0x85C, 0x569A569A}, + {0x860, 0x00000130}, {0x864, 0x20000000}, + {0x868, 0x00000000}, {0x86C, 0x27272700}, + {0x870, 0x00050000}, {0x874, 0x25005000}, + {0x878, 0x00000808}, {0x87C, 0x004F0201}, + {0x880, 0xB0000B1E}, {0x884, 0x00000007}, + {0x888, 0x00000000}, {0x88C, 0xCCC400C0}, + {0x890, 0x00000800}, {0x894, 0xFFFFFFFE}, + {0x898, 0x40302010}, {0x89C, 0x00706050}, + {0x900, 0x00000000}, {0x904, 0x00000023}, + {0x908, 0x00000000}, {0x90C, 0x81121111}, + {0x910, 0x00000402}, {0x914, 0x00000201}, + {0x920, 0x18C6318C}, {0x924, 0x0000018C}, + {0x948, 0x99000000}, {0x94C, 0x00000010}, + {0x950, 0x00003000}, {0x954, 0x5A880000}, + {0x958, 0x4BC6D87A}, {0x95C, 0x04EB9B79}, + {0x96C, 0x00000003}, {0x970, 0x00000000}, + {0x974, 0x00000000}, {0x978, 0x00000000}, + {0x97C, 0x13000000}, {0x980, 0x00000000}, + {0xA00, 0x00D046C8}, {0xA04, 0x80FF800C}, + {0xA08, 0x84838300}, {0xA0C, 0x2E20100F}, + {0xA10, 0x9500BB78}, {0xA14, 0x1114D028}, + {0xA18, 0x00881117}, {0xA1C, 0x89140F00}, + {0xA20, 0xE82C0001}, {0xA24, 0x64B80C1C}, + {0xA28, 0x00008810}, {0xA2C, 0x00D30000}, + {0xA70, 0x101FBF00}, {0xA74, 0x00000007}, + {0xA78, 0x00000900}, {0xA7C, 0x225B0606}, + {0xA80, 0x218075B1}, {0xA84, 0x00200000}, + {0xA88, 0x040C0000}, {0xA8C, 0x12345678}, + {0xA90, 0xABCDEF00}, {0xA94, 0x001B1B89}, + {0xA98, 0x00000000}, {0xA9C, 0x80020000}, + {0xAA0, 0x00000000}, {0xAA4, 0x0000000C}, + {0xAA8, 0xCA110058}, {0xAAC, 0x01235667}, + {0xAB0, 0x00000000}, {0xAB4, 0x20201402}, + {0xB2C, 0x00000000}, {0xC00, 0x48071D40}, + {0xC04, 0x03A05611}, {0xC08, 0x000000E4}, + {0xC0C, 0x6C6C6C6C}, {0xC10, 0x18800000}, + {0xC14, 0x40000100}, {0xC18, 0x08800000}, + {0xC1C, 0x40000100}, {0xC20, 0x00000000}, + {0xC24, 0x00000000}, {0xC28, 0x00000000}, + {0xC2C, 0x00000000}, {0xC30, 0x69E9AC4A}, + {0xC34, 0x31000040}, {0xC38, 0x21688080}, + {0xC3C, 0x0000170C}, {0xC40, 0x1F78403F}, + {0xC44, 0x00010036}, {0xC48, 0xEC020107}, + {0xC4C, 0x007F037F}, {0xC50, 0x69553420}, + {0xC54, 0x43BC0094}, {0xC58, 0x00013169}, + {0xC5C, 0x00250492}, {0xC60, 0x00280A00}, + {0xC64, 0x7112848B}, {0xC68, 0x47C074FF}, + {0xC6C, 0x00000036}, {0xC70, 0x2C7F000D}, + {0xC74, 0x020600DB}, {0xC78, 0x0000001F}, + {0xC7C, 0x00B91612}, {0xC80, 0x390000E4}, + {0xC84, 0x11F60000}, {0xC88, 0x1051B75F}, + {0xC8C, 0x20200109}, {0xC90, 0x00091521}, + {0xC94, 0x00000000}, {0xC98, 0x00121820}, + {0xC9C, 0x00007F7F}, {0xCA0, 0x00011000}, + {0xCA4, 0x800000A0}, {0xCA8, 0x84E6C606}, + {0xCAC, 0x00000060}, {0xCB0, 0x00000000}, + {0xCB4, 0x00000000}, {0xCB8, 0x00000000}, + {0xCBC, 0x28000000}, {0xCC0, 0x1051B75F}, + {0xCC4, 0x00000109}, {0xCC8, 0x000442D6}, + {0xCCC, 0x00000000}, {0xCD0, 0x000001C8}, + {0xCD4, 0x001C8000}, {0xCD8, 0x00000100}, + {0xCDC, 0x40100000}, {0xCE0, 0x00222220}, + {0xCE4, 0x10000000}, {0xCE8, 0x37644302}, + {0xCEC, 0x2F97D40C}, {0xD00, 0x04030740}, + {0xD04, 0x40020401}, {0xD08, 0x0000907F}, + {0xD0C, 0x20010201}, {0xD10, 0xA0633333}, + {0xD14, 0x3333BC53}, {0xD18, 0x7A8F5B6F}, + {0xD2C, 0xCB979975}, {0xD30, 0x00000000}, + {0xD34, 0x40608000}, {0xD38, 0x88000000}, + {0xD3C, 0xC0127353}, {0xD40, 0x00000000}, + {0xD44, 0x00000000}, {0xD48, 0x00000000}, + {0xD4C, 0x00000000}, {0xD50, 0x00006528}, + {0xD54, 0x00000000}, {0xD58, 0x00000282}, + {0xD5C, 0x30032064}, {0xD60, 0x4653DE68}, + {0xD64, 0x04518A3C}, {0xD68, 0x00002101}, + {0xE00, 0x2D2D2D2D}, {0xE04, 0x2D2D2D2D}, + {0xE08, 0x0390272D}, {0xE10, 0x2D2D2D2D}, + {0xE14, 0x2D2D2D2D}, {0xE18, 0x2D2D2D2D}, + {0xE1C, 0x2D2D2D2D}, {0xE28, 0x00000000}, + {0xE30, 0x1000DC1F}, {0xE34, 0x10008C1F}, + {0xE38, 0x02140102}, {0xE3C, 0x681604C2}, + {0xE40, 0x01007C00}, {0xE44, 0x01004800}, + {0xE48, 0xFB000000}, {0xE4C, 0x000028D1}, + {0xE50, 0x1000DC1F}, {0xE54, 0x10008C1F}, + {0xE58, 0x02140102}, {0xE5C, 0x28160D05}, + {0xE60, 0x0000C008}, {0xE68, 0x001B25A4}, + {0xE64, 0x281600A0}, {0xE6C, 0x01C00010}, + {0xE70, 0x01C00010}, {0xE74, 0x02000010}, + {0xE78, 0x02000010}, {0xE7C, 0x02000010}, + {0xE80, 0x02000010}, {0xE84, 0x01C00010}, + {0xE88, 0x02000010}, {0xE8C, 0x01C00010}, + {0xED0, 0x01C00010}, {0xED4, 0x01C00010}, + {0xED8, 0x01C00010}, {0xEDC, 0x00000010}, + {0xEE0, 0x00000010}, {0xEEC, 0x03C00010}, + {0xF14, 0x00000003}, {0xF00, 0x00100300}, + {0xF08, 0x0000800B}, {0xF0C, 0x0000F007}, + {0xF10, 0x0000A487}, {0xF1C, 0x80000064}, + {0xF38, 0x00030155}, {0xF3C, 0x0000003A}, + {0xF4C, 0x13000000}, {0xF50, 0x00000000}, + {0xF18, 0x00000000}, + {0xffff, 0xffffffff}, +}; + +/* If updating the phy init tables, also update rtl8710b_revise_cck_tx_psf(). */ +static const struct rtl8xxxu_reg32val rtl8710bu_qfn48m_s_phy_init_table[] = { + {0x800, 0x80045700}, {0x804, 0x00000001}, + {0x808, 0x00FC8000}, {0x80C, 0x0000000A}, + {0x810, 0x10001331}, {0x814, 0x020C3D10}, + {0x818, 0x00200385}, {0x81C, 0x00000000}, + {0x820, 0x01000100}, {0x824, 0x00390204}, + {0x828, 0x00000000}, {0x82C, 0x00000000}, + {0x830, 0x00000000}, {0x834, 0x00000000}, + {0x838, 0x00000000}, {0x83C, 0x00000000}, + {0x840, 0x00010000}, {0x844, 0x00000000}, + {0x848, 0x00000000}, {0x84C, 0x00000000}, + {0x850, 0x00030000}, {0x854, 0x00000000}, + {0x858, 0x7E1A569A}, {0x85C, 0x569A569A}, + {0x860, 0x00000130}, {0x864, 0x20000000}, + {0x868, 0x00000000}, {0x86C, 0x27272700}, + {0x870, 0x00050000}, {0x874, 0x25005000}, + {0x878, 0x00000808}, {0x87C, 0x004F0201}, + {0x880, 0xB0000B1E}, {0x884, 0x00000007}, + {0x888, 0x00000000}, {0x88C, 0xCCC400C0}, + {0x890, 0x00000800}, {0x894, 0xFFFFFFFE}, + {0x898, 0x40302010}, {0x89C, 0x00706050}, + {0x900, 0x00000000}, {0x904, 0x00000023}, + {0x908, 0x00000000}, {0x90C, 0x81121111}, + {0x910, 0x00000402}, {0x914, 0x00000201}, + {0x920, 0x18C6318C}, {0x924, 0x0000018C}, + {0x948, 0x99000000}, {0x94C, 0x00000010}, + {0x950, 0x00003000}, {0x954, 0x5A880000}, + {0x958, 0x4BC6D87A}, {0x95C, 0x04EB9B79}, + {0x96C, 0x00000003}, {0x970, 0x00000000}, + {0x974, 0x00000000}, {0x978, 0x00000000}, + {0x97C, 0x13000000}, {0x980, 0x00000000}, + {0xA00, 0x00D046C8}, {0xA04, 0x80FF800C}, + {0xA08, 0x84838300}, {0xA0C, 0x2A20100F}, + {0xA10, 0x9500BB78}, {0xA14, 0x1114D028}, + {0xA18, 0x00881117}, {0xA1C, 0x89140F00}, + {0xA20, 0xE82C0001}, {0xA24, 0x64B80C1C}, + {0xA28, 0x00008810}, {0xA2C, 0x00D30000}, + {0xA70, 0x101FBF00}, {0xA74, 0x00000007}, + {0xA78, 0x00000900}, {0xA7C, 0x225B0606}, + {0xA80, 0x218075B1}, {0xA84, 0x00200000}, + {0xA88, 0x040C0000}, {0xA8C, 0x12345678}, + {0xA90, 0xABCDEF00}, {0xA94, 0x001B1B89}, + {0xA98, 0x00000000}, {0xA9C, 0x80020000}, + {0xAA0, 0x00000000}, {0xAA4, 0x0000000C}, + {0xAA8, 0xCA110058}, {0xAAC, 0x01235667}, + {0xAB0, 0x00000000}, {0xAB4, 0x20201402}, + {0xB2C, 0x00000000}, {0xC00, 0x48071D40}, + {0xC04, 0x03A05611}, {0xC08, 0x000000E4}, + {0xC0C, 0x6C6C6C6C}, {0xC10, 0x18800000}, + {0xC14, 0x40000100}, {0xC18, 0x08800000}, + {0xC1C, 0x40000100}, {0xC20, 0x00000000}, + {0xC24, 0x00000000}, {0xC28, 0x00000000}, + {0xC2C, 0x00000000}, {0xC30, 0x69E9AC4A}, + {0xC34, 0x31000040}, {0xC38, 0x21688080}, + {0xC3C, 0x0000170C}, {0xC40, 0x1F78403F}, + {0xC44, 0x00010036}, {0xC48, 0xEC020107}, + {0xC4C, 0x007F037F}, {0xC50, 0x69553420}, + {0xC54, 0x43BC0094}, {0xC58, 0x00013169}, + {0xC5C, 0x00250492}, {0xC60, 0x00280A00}, + {0xC64, 0x7112848B}, {0xC68, 0x47C074FF}, + {0xC6C, 0x00000036}, {0xC70, 0x2C7F000D}, + {0xC74, 0x020600DB}, {0xC78, 0x0000001F}, + {0xC7C, 0x00B91612}, {0xC80, 0x390000E4}, + {0xC84, 0x11F60000}, {0xC88, 0x1051B75F}, + {0xC8C, 0x20200109}, {0xC90, 0x00091521}, + {0xC94, 0x00000000}, {0xC98, 0x00121820}, + {0xC9C, 0x00007F7F}, {0xCA0, 0x00011000}, + {0xCA4, 0x800000A0}, {0xCA8, 0x84E6C606}, + {0xCAC, 0x00000060}, {0xCB0, 0x00000000}, + {0xCB4, 0x00000000}, {0xCB8, 0x00000000}, + {0xCBC, 0x28000000}, {0xCC0, 0x1051B75F}, + {0xCC4, 0x00000109}, {0xCC8, 0x000442D6}, + {0xCCC, 0x00000000}, {0xCD0, 0x000001C8}, + {0xCD4, 0x001C8000}, {0xCD8, 0x00000100}, + {0xCDC, 0x40100000}, {0xCE0, 0x00222220}, + {0xCE4, 0x10000000}, {0xCE8, 0x37644302}, + {0xCEC, 0x2F97D40C}, {0xD00, 0x04030740}, + {0xD04, 0x40020401}, {0xD08, 0x0000907F}, + {0xD0C, 0x20010201}, {0xD10, 0xA0633333}, + {0xD14, 0x3333BC53}, {0xD18, 0x7A8F5B6F}, + {0xD2C, 0xCB979975}, {0xD30, 0x00000000}, + {0xD34, 0x40608000}, {0xD38, 0x88000000}, + {0xD3C, 0xC0127353}, {0xD40, 0x00000000}, + {0xD44, 0x00000000}, {0xD48, 0x00000000}, + {0xD4C, 0x00000000}, {0xD50, 0x00006528}, + {0xD54, 0x00000000}, {0xD58, 0x00000282}, + {0xD5C, 0x30032064}, {0xD60, 0x4653DE68}, + {0xD64, 0x04518A3C}, {0xD68, 0x00002101}, + {0xE00, 0x2D2D2D2D}, {0xE04, 0x2D2D2D2D}, + {0xE08, 0x0390272D}, {0xE10, 0x2D2D2D2D}, + {0xE14, 0x2D2D2D2D}, {0xE18, 0x2D2D2D2D}, + {0xE1C, 0x2D2D2D2D}, {0xE28, 0x00000000}, + {0xE30, 0x1000DC1F}, {0xE34, 0x10008C1F}, + {0xE38, 0x02140102}, {0xE3C, 0x681604C2}, + {0xE40, 0x01007C00}, {0xE44, 0x01004800}, + {0xE48, 0xFB000000}, {0xE4C, 0x000028D1}, + {0xE50, 0x1000DC1F}, {0xE54, 0x10008C1F}, + {0xE58, 0x02140102}, {0xE5C, 0x28160D05}, + {0xE60, 0x0000C008}, {0xE68, 0x001B25A4}, + {0xE64, 0x281600A0}, {0xE6C, 0x01C00010}, + {0xE70, 0x01C00010}, {0xE74, 0x02000010}, + {0xE78, 0x02000010}, {0xE7C, 0x02000010}, + {0xE80, 0x02000010}, {0xE84, 0x01C00010}, + {0xE88, 0x02000010}, {0xE8C, 0x01C00010}, + {0xED0, 0x01C00010}, {0xED4, 0x01C00010}, + {0xED8, 0x01C00010}, {0xEDC, 0x00000010}, + {0xEE0, 0x00000010}, {0xEEC, 0x03C00010}, + {0xF14, 0x00000003}, {0xF00, 0x00100300}, + {0xF08, 0x0000800B}, {0xF0C, 0x0000F007}, + {0xF10, 0x0000A487}, {0xF1C, 0x80000064}, + {0xF38, 0x00030155}, {0xF3C, 0x0000003A}, + {0xF4C, 0x13000000}, {0xF50, 0x00000000}, + {0xF18, 0x00000000}, + {0xffff, 0xffffffff}, +}; + +static const struct rtl8xxxu_reg32val rtl8710b_agc_table[] = { + {0xC78, 0xFC000001}, {0xC78, 0xFB010001}, + {0xC78, 0xFA020001}, {0xC78, 0xF9030001}, + {0xC78, 0xF8040001}, {0xC78, 0xF7050001}, + {0xC78, 0xF6060001}, {0xC78, 0xF5070001}, + {0xC78, 0xF4080001}, {0xC78, 0xF3090001}, + {0xC78, 0xF20A0001}, {0xC78, 0xF10B0001}, + {0xC78, 0xF00C0001}, {0xC78, 0xEF0D0001}, + {0xC78, 0xEE0E0001}, {0xC78, 0xED0F0001}, + {0xC78, 0xEC100001}, {0xC78, 0xEB110001}, + {0xC78, 0xEA120001}, {0xC78, 0xE9130001}, + {0xC78, 0xE8140001}, {0xC78, 0xE7150001}, + {0xC78, 0xE6160001}, {0xC78, 0xE5170001}, + {0xC78, 0xE4180001}, {0xC78, 0xE3190001}, + {0xC78, 0xE21A0001}, {0xC78, 0xE11B0001}, + {0xC78, 0xE01C0001}, {0xC78, 0xC31D0001}, + {0xC78, 0xC21E0001}, {0xC78, 0xC11F0001}, + {0xC78, 0xC0200001}, {0xC78, 0xA3210001}, + {0xC78, 0xA2220001}, {0xC78, 0xA1230001}, + {0xC78, 0xA0240001}, {0xC78, 0x86250001}, + {0xC78, 0x85260001}, {0xC78, 0x84270001}, + {0xC78, 0x83280001}, {0xC78, 0x82290001}, + {0xC78, 0x812A0001}, {0xC78, 0x802B0001}, + {0xC78, 0x632C0001}, {0xC78, 0x622D0001}, + {0xC78, 0x612E0001}, {0xC78, 0x602F0001}, + {0xC78, 0x42300001}, {0xC78, 0x41310001}, + {0xC78, 0x40320001}, {0xC78, 0x23330001}, + {0xC78, 0x22340001}, {0xC78, 0x21350001}, + {0xC78, 0x20360001}, {0xC78, 0x02370001}, + {0xC78, 0x01380001}, {0xC78, 0x00390001}, + {0xC78, 0x003A0001}, {0xC78, 0x003B0001}, + {0xC78, 0x003C0001}, {0xC78, 0x003D0001}, + {0xC78, 0x003E0001}, {0xC78, 0x003F0001}, + {0xC78, 0xF7400001}, {0xC78, 0xF7410001}, + {0xC78, 0xF7420001}, {0xC78, 0xF7430001}, + {0xC78, 0xF7440001}, {0xC78, 0xF7450001}, + {0xC78, 0xF7460001}, {0xC78, 0xF7470001}, + {0xC78, 0xF7480001}, {0xC78, 0xF6490001}, + {0xC78, 0xF34A0001}, {0xC78, 0xF24B0001}, + {0xC78, 0xF14C0001}, {0xC78, 0xF04D0001}, + {0xC78, 0xD14E0001}, {0xC78, 0xD04F0001}, + {0xC78, 0xB5500001}, {0xC78, 0xB4510001}, + {0xC78, 0xB3520001}, {0xC78, 0xB2530001}, + {0xC78, 0xB1540001}, {0xC78, 0xB0550001}, + {0xC78, 0xAF560001}, {0xC78, 0xAE570001}, + {0xC78, 0xAD580001}, {0xC78, 0xAC590001}, + {0xC78, 0xAB5A0001}, {0xC78, 0xAA5B0001}, + {0xC78, 0xA95C0001}, {0xC78, 0xA85D0001}, + {0xC78, 0xA75E0001}, {0xC78, 0xA65F0001}, + {0xC78, 0xA5600001}, {0xC78, 0xA4610001}, + {0xC78, 0xA3620001}, {0xC78, 0xA2630001}, + {0xC78, 0xA1640001}, {0xC78, 0xA0650001}, + {0xC78, 0x87660001}, {0xC78, 0x86670001}, + {0xC78, 0x85680001}, {0xC78, 0x84690001}, + {0xC78, 0x836A0001}, {0xC78, 0x826B0001}, + {0xC78, 0x816C0001}, {0xC78, 0x806D0001}, + {0xC78, 0x636E0001}, {0xC78, 0x626F0001}, + {0xC78, 0x61700001}, {0xC78, 0x60710001}, + {0xC78, 0x42720001}, {0xC78, 0x41730001}, + {0xC78, 0x40740001}, {0xC78, 0x23750001}, + {0xC78, 0x22760001}, {0xC78, 0x21770001}, + {0xC78, 0x20780001}, {0xC78, 0x03790001}, + {0xC78, 0x027A0001}, {0xC78, 0x017B0001}, + {0xC78, 0x007C0001}, {0xC78, 0x007D0001}, + {0xC78, 0x007E0001}, {0xC78, 0x007F0001}, + {0xC50, 0x69553422}, {0xC50, 0x69553420}, + {0xffff, 0xffffffff} +}; + +static const struct rtl8xxxu_rfregval rtl8710bu_qfn48m_u_radioa_init_table[] = { + {0x00, 0x00030000}, {0x08, 0x00008400}, + {0x17, 0x00000000}, {0x18, 0x00000C01}, + {0x19, 0x000739D2}, {0x1C, 0x00000C4C}, + {0x1B, 0x00000C6C}, {0x1E, 0x00080009}, + {0x1F, 0x00000880}, {0x2F, 0x0001A060}, + {0x3F, 0x00015000}, {0x42, 0x000060C0}, + {0x57, 0x000D0000}, {0x58, 0x000C0160}, + {0x67, 0x00001552}, {0x83, 0x00000000}, + {0xB0, 0x000FF9F0}, {0xB1, 0x00010018}, + {0xB2, 0x00054C00}, {0xB4, 0x0004486B}, + {0xB5, 0x0000112A}, {0xB6, 0x0000053E}, + {0xB7, 0x00014408}, {0xB8, 0x00010200}, + {0xB9, 0x00080801}, {0xBA, 0x00040001}, + {0xBB, 0x00000400}, {0xBF, 0x000C0000}, + {0xC2, 0x00002400}, {0xC3, 0x00000009}, + {0xC4, 0x00040C91}, {0xC5, 0x00099999}, + {0xC6, 0x000000A3}, {0xC7, 0x00088820}, + {0xC8, 0x00076C06}, {0xC9, 0x00000000}, + {0xCA, 0x00080000}, {0xDF, 0x00000180}, + {0xEF, 0x000001A8}, {0x3D, 0x00000003}, + {0x3D, 0x00080003}, {0x51, 0x000F1E69}, + {0x52, 0x000FBF6C}, {0x53, 0x0000032F}, + {0x54, 0x00055007}, {0x56, 0x000517F0}, + {0x35, 0x000000F4}, {0x35, 0x00000179}, + {0x35, 0x000002F4}, {0x36, 0x00000BF8}, + {0x36, 0x00008BF8}, {0x36, 0x00010BF8}, + {0x36, 0x00018BF8}, {0x18, 0x00000C01}, + {0x5A, 0x00048000}, {0x5A, 0x00048000}, + {0x34, 0x0000ADF5}, {0x34, 0x00009DF2}, + {0x34, 0x00008DEF}, {0x34, 0x00007DEC}, + {0x34, 0x00006DE9}, {0x34, 0x00005CEC}, + {0x34, 0x00004CE9}, {0x34, 0x00003C6C}, + {0x34, 0x00002C69}, {0x34, 0x0000106E}, + {0x34, 0x0000006B}, {0x84, 0x00048000}, + {0x87, 0x00000065}, {0x8E, 0x00065540}, + {0xDF, 0x00000110}, {0x86, 0x0000002A}, + {0x8F, 0x00088000}, {0x81, 0x0003FD80}, + {0xEF, 0x00082000}, {0x3B, 0x000F0F00}, + {0x3B, 0x000E0E00}, {0x3B, 0x000DFE00}, + {0x3B, 0x000C0D00}, {0x3B, 0x000B0C00}, + {0x3B, 0x000A0500}, {0x3B, 0x00090400}, + {0x3B, 0x00080000}, {0x3B, 0x00070F00}, + {0x3B, 0x00060E00}, {0x3B, 0x00050A00}, + {0x3B, 0x00040D00}, {0x3B, 0x00030C00}, + {0x3B, 0x00020500}, {0x3B, 0x00010400}, + {0x3B, 0x00000000}, {0xEF, 0x00080000}, + {0xEF, 0x00088000}, {0x3B, 0x00000170}, + {0x3B, 0x000C0030}, {0xEF, 0x00080000}, + {0xEF, 0x00080000}, {0x30, 0x00010000}, + {0x31, 0x0000000F}, {0x32, 0x00047EFE}, + {0xEF, 0x00000000}, {0x00, 0x00010159}, + {0x18, 0x0000FC01}, {0xFE, 0x00000000}, + {0x00, 0x00033D95}, + {0xff, 0xffffffff} +}; + +static const struct rtl8xxxu_rfregval rtl8710bu_qfn48m_s_radioa_init_table[] = { + {0x00, 0x00030000}, {0x08, 0x00008400}, + {0x17, 0x00000000}, {0x18, 0x00000C01}, + {0x19, 0x000739D2}, {0x1C, 0x00000C4C}, + {0x1B, 0x00000C6C}, {0x1E, 0x00080009}, + {0x1F, 0x00000880}, {0x2F, 0x0001A060}, + {0x3F, 0x00015000}, {0x42, 0x000060C0}, + {0x57, 0x000D0000}, {0x58, 0x000C0160}, + {0x67, 0x00001552}, {0x83, 0x00000000}, + {0xB0, 0x000FF9F0}, {0xB1, 0x00010018}, + {0xB2, 0x00054C00}, {0xB4, 0x0004486B}, + {0xB5, 0x0000112A}, {0xB6, 0x0000053E}, + {0xB7, 0x00014408}, {0xB8, 0x00010200}, + {0xB9, 0x00080801}, {0xBA, 0x00040001}, + {0xBB, 0x00000400}, {0xBF, 0x000C0000}, + {0xC2, 0x00002400}, {0xC3, 0x00000009}, + {0xC4, 0x00040C91}, {0xC5, 0x00099999}, + {0xC6, 0x000000A3}, {0xC7, 0x00088820}, + {0xC8, 0x00076C06}, {0xC9, 0x00000000}, + {0xCA, 0x00080000}, {0xDF, 0x00000180}, + {0xEF, 0x000001A8}, {0x3D, 0x00000003}, + {0x3D, 0x00080003}, {0x51, 0x000F1E69}, + {0x52, 0x000FBF6C}, {0x53, 0x0000032F}, + {0x54, 0x00055007}, {0x56, 0x000517F0}, + {0x35, 0x000000F4}, {0x35, 0x00000179}, + {0x35, 0x000002F4}, {0x36, 0x00000BF8}, + {0x36, 0x00008BF8}, {0x36, 0x00010BF8}, + {0x36, 0x00018BF8}, {0x18, 0x00000C01}, + {0x5A, 0x00048000}, {0x5A, 0x00048000}, + {0x34, 0x0000ADF5}, {0x34, 0x00009DF2}, + {0x34, 0x00008DEF}, {0x34, 0x00007DEC}, + {0x34, 0x00006DE9}, {0x34, 0x00005CEC}, + {0x34, 0x00004CE9}, {0x34, 0x00003C6C}, + {0x34, 0x00002C69}, {0x34, 0x0000106E}, + {0x34, 0x0000006B}, {0x84, 0x00048000}, + {0x87, 0x00000065}, {0x8E, 0x00065540}, + {0xDF, 0x00000110}, {0x86, 0x0000002A}, + {0x8F, 0x00088000}, {0x81, 0x0003FD80}, + {0xEF, 0x00082000}, {0x3B, 0x000F0F00}, + {0x3B, 0x000E0E00}, {0x3B, 0x000DFE00}, + {0x3B, 0x000C0D00}, {0x3B, 0x000B0C00}, + {0x3B, 0x000A0500}, {0x3B, 0x00090400}, + {0x3B, 0x00080000}, {0x3B, 0x00070F00}, + {0x3B, 0x00060E00}, {0x3B, 0x00050A00}, + {0x3B, 0x00040D00}, {0x3B, 0x00030C00}, + {0x3B, 0x00020500}, {0x3B, 0x00010400}, + {0x3B, 0x00000000}, {0xEF, 0x00080000}, + {0xEF, 0x00088000}, {0x3B, 0x000000B0}, + {0x3B, 0x000C0030}, {0xEF, 0x00080000}, + {0xEF, 0x00080000}, {0x30, 0x00010000}, + {0x31, 0x0000000F}, {0x32, 0x00047EFE}, + {0xEF, 0x00000000}, {0x00, 0x00010159}, + {0x18, 0x0000FC01}, {0xFE, 0x00000000}, + {0x00, 0x00033D95}, + {0xff, 0xffffffff} +}; + +static u32 rtl8710b_indirect_read32(struct rtl8xxxu_priv *priv, u32 addr) +{ + struct device *dev = &priv->udev->dev; + u32 val32, value = 0xffffffff; + u8 polling_count = 0xff; + + if (!IS_ALIGNED(addr, 4)) { + dev_warn(dev, "%s: Aborting because 0x%x is not a multiple of 4.\n", + __func__, addr); + return value; + } + + mutex_lock(&priv->syson_indirect_access_mutex); + + rtl8xxxu_write32(priv, REG_USB_HOST_INDIRECT_ADDR_8710B, addr); + rtl8xxxu_write32(priv, REG_EFUSE_INDIRECT_CTRL_8710B, NORMAL_REG_READ_OFFSET); + + do + val32 = rtl8xxxu_read32(priv, REG_EFUSE_INDIRECT_CTRL_8710B); + while ((val32 & BIT(31)) && (--polling_count > 0)); + + if (polling_count == 0) + dev_warn(dev, "%s: Failed to read from 0x%x, 0x806c = 0x%x\n", + __func__, addr, val32); + else + value = rtl8xxxu_read32(priv, REG_USB_HOST_INDIRECT_DATA_8710B); + + mutex_unlock(&priv->syson_indirect_access_mutex); + + if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ) + dev_info(dev, "%s(%04x) = 0x%08x\n", __func__, addr, value); + + return value; +} + +static void rtl8710b_indirect_write32(struct rtl8xxxu_priv *priv, u32 addr, u32 val) +{ + struct device *dev = &priv->udev->dev; + u8 polling_count = 0xff; + u32 val32; + + if (!IS_ALIGNED(addr, 4)) { + dev_warn(dev, "%s: Aborting because 0x%x is not a multiple of 4.\n", + __func__, addr); + return; + } + + mutex_lock(&priv->syson_indirect_access_mutex); + + rtl8xxxu_write32(priv, REG_USB_HOST_INDIRECT_ADDR_8710B, addr); + rtl8xxxu_write32(priv, REG_USB_HOST_INDIRECT_DATA_8710B, val); + rtl8xxxu_write32(priv, REG_EFUSE_INDIRECT_CTRL_8710B, NORMAL_REG_WRITE_OFFSET); + + do + val32 = rtl8xxxu_read32(priv, REG_EFUSE_INDIRECT_CTRL_8710B); + while ((val32 & BIT(31)) && (--polling_count > 0)); + + if (polling_count == 0) + dev_warn(dev, "%s: Failed to write 0x%x to 0x%x, 0x806c = 0x%x\n", + __func__, val, addr, val32); + + mutex_unlock(&priv->syson_indirect_access_mutex); + + if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE) + dev_info(dev, "%s(%04x) = 0x%08x\n", __func__, addr, val); +} + +static u32 rtl8710b_read_syson_reg(struct rtl8xxxu_priv *priv, u32 addr) +{ + return rtl8710b_indirect_read32(priv, addr | SYSON_REG_BASE_ADDR_8710B); +} + +static void rtl8710b_write_syson_reg(struct rtl8xxxu_priv *priv, u32 addr, u32 val) +{ + rtl8710b_indirect_write32(priv, addr | SYSON_REG_BASE_ADDR_8710B, val); +} + +static int rtl8710b_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data) +{ + u32 val32; + int i; + + /* Write Address */ + rtl8xxxu_write32(priv, REG_USB_HOST_INDIRECT_ADDR_8710B, offset); + + rtl8xxxu_write32(priv, REG_EFUSE_INDIRECT_CTRL_8710B, EFUSE_READ_OFFSET); + + /* Poll for data read */ + val32 = rtl8xxxu_read32(priv, REG_EFUSE_INDIRECT_CTRL_8710B); + for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) { + val32 = rtl8xxxu_read32(priv, REG_EFUSE_INDIRECT_CTRL_8710B); + if (!(val32 & BIT(31))) + break; + } + + if (i == RTL8XXXU_MAX_REG_POLL) + return -EIO; + + val32 = rtl8xxxu_read32(priv, REG_USB_HOST_INDIRECT_DATA_8710B); + + *data = val32 & 0xff; + return 0; +} + +#define EEPROM_PACKAGE_TYPE_8710B 0xF8 +#define PACKAGE_QFN48M_U 0xee +#define PACKAGE_QFN48M_S 0xfe + +static int rtl8710bu_identify_chip(struct rtl8xxxu_priv *priv) +{ + struct device *dev = &priv->udev->dev; + u32 cfg0, cfg2, vendor; + u8 package_type = 0x7; /* a nonsense value */ + + sprintf(priv->chip_name, "8710BU"); + priv->rtl_chip = RTL8710B; + priv->rf_paths = 1; + priv->rx_paths = 1; + priv->tx_paths = 1; + priv->has_wifi = 1; + + cfg0 = rtl8710b_read_syson_reg(priv, REG_SYS_SYSTEM_CFG0_8710B); + priv->chip_cut = cfg0 & 0xf; + + if (cfg0 & BIT(16)) { + dev_info(dev, "%s: Unsupported test chip\n", __func__); + return -EOPNOTSUPP; + } + + vendor = u32_get_bits(cfg0, 0xc0); + + /* SMIC and TSMC are swapped compared to rtl8xxxu_identify_vendor_2bits */ + switch (vendor) { + case 0: + sprintf(priv->chip_vendor, "SMIC"); + priv->vendor_smic = 1; + break; + case 1: + sprintf(priv->chip_vendor, "TSMC"); + break; + case 2: + sprintf(priv->chip_vendor, "UMC"); + priv->vendor_umc = 1; + break; + default: + sprintf(priv->chip_vendor, "unknown"); + break; + } + + rtl8710b_read_efuse8(priv, EEPROM_PACKAGE_TYPE_8710B, &package_type); + + if (package_type == 0xff) { + dev_warn(dev, "Package type is undefined. Assuming it based on the vendor.\n"); + + if (priv->vendor_umc) { + package_type = PACKAGE_QFN48M_U; + } else if (priv->vendor_smic) { + package_type = PACKAGE_QFN48M_S; + } else { + dev_warn(dev, "The vendor is neither UMC nor SMIC. Assuming the package type is QFN48M_U.\n"); + + /* + * In this case the vendor driver doesn't set + * the package type to anything, which is the + * same as setting it to PACKAGE_DEFAULT (0). + */ + package_type = PACKAGE_QFN48M_U; + } + } else if (package_type != PACKAGE_QFN48M_S && + package_type != PACKAGE_QFN48M_U) { + dev_warn(dev, "Failed to read the package type. Assuming it's the default QFN48M_U.\n"); + + /* + * In this case the vendor driver actually sets it to + * PACKAGE_DEFAULT, but that selects the same values + * from the init tables as PACKAGE_QFN48M_U. + */ + package_type = PACKAGE_QFN48M_U; + } + + priv->package_type = package_type; + + dev_dbg(dev, "Package type: 0x%x\n", package_type); + + cfg2 = rtl8710b_read_syson_reg(priv, REG_SYS_SYSTEM_CFG2_8710B); + priv->rom_rev = cfg2 & 0xf; + + return rtl8xxxu_config_endpoints_no_sie(priv); +} + +static void rtl8710b_revise_cck_tx_psf(struct rtl8xxxu_priv *priv, u8 channel) +{ + if (channel == 13) { + /* Normal values */ + rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER2, 0x64B80C1C); + rtl8xxxu_write32(priv, REG_CCK0_DEBUG_PORT, 0x00008810); + rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER3, 0x01235667); + /* Special value for channel 13 */ + rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER1, 0xd1d80001); + } else if (channel == 14) { + /* Special values for channel 14 */ + rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER2, 0x0000B81C); + rtl8xxxu_write32(priv, REG_CCK0_DEBUG_PORT, 0x00000000); + rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER3, 0x00003667); + /* Normal value */ + rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER1, 0xE82C0001); + } else { + /* Restore normal values from the phy init table */ + rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER2, 0x64B80C1C); + rtl8xxxu_write32(priv, REG_CCK0_DEBUG_PORT, 0x00008810); + rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER3, 0x01235667); + rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER1, 0xE82C0001); + } +} + +static void rtl8710bu_config_channel(struct ieee80211_hw *hw) +{ + struct rtl8xxxu_priv *priv = hw->priv; + bool ht40 = conf_is_ht40(&hw->conf); + u8 channel, subchannel = 0; + bool sec_ch_above = 0; + u32 val32; + u16 val16; + + channel = (u8)hw->conf.chandef.chan->hw_value; + + if (conf_is_ht40_plus(&hw->conf)) { + sec_ch_above = 1; + channel += 2; + subchannel = 2; + } else if (conf_is_ht40_minus(&hw->conf)) { + sec_ch_above = 0; + channel -= 2; + subchannel = 1; + } + + /* Set channel */ + val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG); + u32p_replace_bits(&val32, channel, MODE_AG_CHANNEL_MASK); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32); + + rtl8710b_revise_cck_tx_psf(priv, channel); + + /* Set bandwidth mode */ + val16 = rtl8xxxu_read16(priv, REG_WMAC_TRXPTCL_CTL); + val16 &= ~WMAC_TRXPTCL_CTL_BW_MASK; + if (ht40) + val16 |= WMAC_TRXPTCL_CTL_BW_40; + rtl8xxxu_write16(priv, REG_WMAC_TRXPTCL_CTL, val16); + + rtl8xxxu_write8(priv, REG_DATA_SUBCHANNEL, subchannel); + + val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); + u32p_replace_bits(&val32, ht40, FPGA_RF_MODE); + rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); + + val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); + u32p_replace_bits(&val32, ht40, FPGA_RF_MODE); + rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); + + if (ht40) { + /* Set Control channel to upper or lower. */ + val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM); + u32p_replace_bits(&val32, !sec_ch_above, CCK0_SIDEBAND); + rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32); + } + + /* RXADC CLK */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); + val32 |= GENMASK(10, 8); + rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); + + /* TXDAC CLK */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); + val32 |= BIT(14) | BIT(12); + val32 &= ~BIT(13); + rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); + + /* small BW */ + val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT); + val32 &= ~GENMASK(31, 30); + rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32); + + /* adc buffer clk */ + val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT); + val32 &= ~BIT(29); + val32 |= BIT(28); + rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32); + + /* adc buffer clk */ + val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_AFE); + val32 &= ~BIT(29); + val32 |= BIT(28); + rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_AFE, val32); + + val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE); + val32 &= ~BIT(30); + val32 |= BIT(29); + rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32); + + if (ht40) { + val32 = rtl8xxxu_read32(priv, REG_OFDM_RX_DFIR); + val32 &= ~BIT(19); + rtl8xxxu_write32(priv, REG_OFDM_RX_DFIR, val32); + + val32 = rtl8xxxu_read32(priv, REG_OFDM_RX_DFIR); + val32 &= ~GENMASK(23, 20); + rtl8xxxu_write32(priv, REG_OFDM_RX_DFIR, val32); + + val32 = rtl8xxxu_read32(priv, REG_OFDM_RX_DFIR); + val32 &= ~GENMASK(27, 24); + rtl8xxxu_write32(priv, REG_OFDM_RX_DFIR, val32); + + /* RF TRX_BW */ + val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG); + val32 &= ~MODE_AG_BW_MASK; + val32 |= MODE_AG_BW_40MHZ_8723B; + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32); + } else { + val32 = rtl8xxxu_read32(priv, REG_OFDM_RX_DFIR); + val32 |= BIT(19); + rtl8xxxu_write32(priv, REG_OFDM_RX_DFIR, val32); + + val32 = rtl8xxxu_read32(priv, REG_OFDM_RX_DFIR); + val32 &= ~GENMASK(23, 20); + val32 |= BIT(23); + rtl8xxxu_write32(priv, REG_OFDM_RX_DFIR, val32); + + val32 = rtl8xxxu_read32(priv, REG_OFDM_RX_DFIR); + val32 &= ~GENMASK(27, 24); + val32 |= BIT(27) | BIT(25); + rtl8xxxu_write32(priv, REG_OFDM_RX_DFIR, val32); + + /* RF TRX_BW */ + val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG); + val32 &= ~MODE_AG_BW_MASK; + val32 |= MODE_AG_BW_20MHZ_8723B; + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32); + } +} + +static void rtl8710bu_init_aggregation(struct rtl8xxxu_priv *priv) +{ + u32 agg_rx; + u8 agg_ctrl; + + /* RX aggregation */ + agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL); + agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN; + + agg_rx = rtl8xxxu_read32(priv, REG_RXDMA_AGG_PG_TH); + agg_rx &= ~RXDMA_USB_AGG_ENABLE; + agg_rx &= ~0xFF0F; /* reset agg size and timeout */ + + rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl); + rtl8xxxu_write32(priv, REG_RXDMA_AGG_PG_TH, agg_rx); +} + +static void rtl8710bu_init_statistics(struct rtl8xxxu_priv *priv) +{ + u32 val32; + + /* Time duration for NHM unit: 4us, 0xc350=200ms */ + rtl8xxxu_write16(priv, REG_NHM_TIMER_8723B + 2, 0xc350); + rtl8xxxu_write16(priv, REG_NHM_TH9_TH10_8723B + 2, 0xffff); + rtl8xxxu_write32(priv, REG_NHM_TH3_TO_TH0_8723B, 0xffffff50); + rtl8xxxu_write32(priv, REG_NHM_TH7_TO_TH4_8723B, 0xffffffff); + + /* TH8 */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); + val32 |= 0xff; + rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); + + /* Enable CCK */ + val32 = rtl8xxxu_read32(priv, REG_NHM_TH9_TH10_8723B); + val32 &= ~(BIT(8) | BIT(9) | BIT(10)); + val32 |= BIT(8); + rtl8xxxu_write32(priv, REG_NHM_TH9_TH10_8723B, val32); + + /* Max power amongst all RX antennas */ + val32 = rtl8xxxu_read32(priv, REG_OFDM0_FA_RSTC); + val32 |= BIT(7); + rtl8xxxu_write32(priv, REG_OFDM0_FA_RSTC, val32); +} + +static int rtl8710b_read_efuse(struct rtl8xxxu_priv *priv) +{ + struct device *dev = &priv->udev->dev; + u8 val8, word_mask, header, extheader; + u16 efuse_addr, offset; + int i, ret = 0; + u32 val32; + + val32 = rtl8710b_read_syson_reg(priv, REG_SYS_EEPROM_CTRL0_8710B); + priv->boot_eeprom = u32_get_bits(val32, EEPROM_BOOT); + priv->has_eeprom = u32_get_bits(val32, EEPROM_ENABLE); + + /* Default value is 0xff */ + memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN); + + efuse_addr = 0; + while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) { + u16 map_addr; + + ret = rtl8710b_read_efuse8(priv, efuse_addr++, &header); + if (ret || header == 0xff) + goto exit; + + if ((header & 0x1f) == 0x0f) { /* extended header */ + offset = (header & 0xe0) >> 5; + + ret = rtl8710b_read_efuse8(priv, efuse_addr++, &extheader); + if (ret) + goto exit; + + /* All words disabled */ + if ((extheader & 0x0f) == 0x0f) + continue; + + offset |= ((extheader & 0xf0) >> 1); + word_mask = extheader & 0x0f; + } else { + offset = (header >> 4) & 0x0f; + word_mask = header & 0x0f; + } + + /* Get word enable value from PG header */ + + /* We have 8 bits to indicate validity */ + map_addr = offset * 8; + for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) { + /* Check word enable condition in the section */ + if (word_mask & BIT(i)) { + map_addr += 2; + continue; + } + + ret = rtl8710b_read_efuse8(priv, efuse_addr++, &val8); + if (ret) + goto exit; + if (map_addr >= EFUSE_MAP_LEN - 1) { + dev_warn(dev, "%s: Illegal map_addr (%04x), efuse corrupt!\n", + __func__, map_addr); + ret = -EINVAL; + goto exit; + } + priv->efuse_wifi.raw[map_addr++] = val8; + + ret = rtl8710b_read_efuse8(priv, efuse_addr++, &val8); + if (ret) + goto exit; + priv->efuse_wifi.raw[map_addr++] = val8; + } + } + +exit: + + return ret; +} + +static int rtl8710bu_parse_efuse(struct rtl8xxxu_priv *priv) +{ + struct rtl8710bu_efuse *efuse = &priv->efuse_wifi.efuse8710bu; + + if (efuse->rtl_id != cpu_to_le16(0x8195)) + return -EINVAL; + + ether_addr_copy(priv->mac_addr, efuse->mac_addr); + + memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base, + sizeof(efuse->tx_power_index_A.cck_base)); + + memcpy(priv->ht40_1s_tx_power_index_A, + efuse->tx_power_index_A.ht40_base, + sizeof(efuse->tx_power_index_A.ht40_base)); + + priv->ofdm_tx_power_diff[0].a = efuse->tx_power_index_A.ht20_ofdm_1s_diff.a; + priv->ht20_tx_power_diff[0].a = efuse->tx_power_index_A.ht20_ofdm_1s_diff.b; + + priv->default_crystal_cap = efuse->xtal_k & 0x3f; + + return 0; +} + +static int rtl8710bu_load_firmware(struct rtl8xxxu_priv *priv) +{ + if (priv->vendor_smic) { + return rtl8xxxu_load_firmware(priv, "rtlwifi/rtl8710bufw_SMIC.bin"); + } else if (priv->vendor_umc) { + return rtl8xxxu_load_firmware(priv, "rtlwifi/rtl8710bufw_UMC.bin"); + } else { + dev_err(&priv->udev->dev, "We have no suitable firmware for this chip.\n"); + return -1; + } +} + +static void rtl8710bu_init_phy_bb(struct rtl8xxxu_priv *priv) +{ + const struct rtl8xxxu_reg32val *phy_init_table; + u32 val32; + + /* Enable BB and RF */ + val32 = rtl8xxxu_read32(priv, REG_SYS_FUNC_8710B); + val32 |= GENMASK(17, 16) | GENMASK(26, 24); + rtl8xxxu_write32(priv, REG_SYS_FUNC_8710B, val32); + + if (priv->package_type == PACKAGE_QFN48M_U) + phy_init_table = rtl8710bu_qfn48m_u_phy_init_table; + else + phy_init_table = rtl8710bu_qfn48m_s_phy_init_table; + + rtl8xxxu_init_phy_regs(priv, phy_init_table); + + rtl8xxxu_init_phy_regs(priv, rtl8710b_agc_table); +} + +static int rtl8710bu_init_phy_rf(struct rtl8xxxu_priv *priv) +{ + const struct rtl8xxxu_rfregval *radioa_init_table; + + if (priv->package_type == PACKAGE_QFN48M_U) + radioa_init_table = rtl8710bu_qfn48m_u_radioa_init_table; + else + radioa_init_table = rtl8710bu_qfn48m_s_radioa_init_table; + + return rtl8xxxu_init_phy_rf(priv, radioa_init_table, RF_A); +} + +static int rtl8710bu_iqk_path_a(struct rtl8xxxu_priv *priv, u32 *lok_result) +{ + u32 reg_eac, reg_e94, reg_e9c, val32, path_sel_bb; + int result = 0; + + path_sel_bb = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); + + rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x99000000); + + /* + * Leave IQK mode + */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); + u32p_replace_bits(&val32, 0, 0xffffff00); + rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); + + /* + * Enable path A PA in TX IQK mode + */ + val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); + val32 |= 0x80000; + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x20000); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0x07ff7); + + /* PA,PAD gain adjust */ + val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA); + val32 |= BIT(11); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, val32); + val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_PAD_TXG); + u32p_replace_bits(&val32, 0x1ed, 0x00fff); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_PAD_TXG, val32); + + /* enter IQK mode */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); + u32p_replace_bits(&val32, 0x808000, 0xffffff00); + rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); + + /* path-A IQK setting */ + rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); + rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); + + rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821403ff); + rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160c06); + + /* LO calibration setting */ + rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x02002911); + + /* One shot, path A LOK & IQK */ + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000); + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); + + mdelay(10); + + rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel_bb); + + /* + * Leave IQK mode + */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); + u32p_replace_bits(&val32, 0, 0xffffff00); + rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); + + val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA); + val32 &= ~BIT(11); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, val32); + + /* save LOK result */ + *lok_result = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_TXM_IDAC); + + /* Check failed */ + reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); + reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); + reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); + + if (!(reg_eac & BIT(28)) && + ((reg_e94 & 0x03ff0000) != 0x01420000) && + ((reg_e9c & 0x03ff0000) != 0x00420000)) + result |= 0x01; + + return result; +} + +static int rtl8710bu_rx_iqk_path_a(struct rtl8xxxu_priv *priv, u32 lok_result) +{ + u32 reg_ea4, reg_eac, reg_e94, reg_e9c, val32, path_sel_bb, tmp; + int result = 0; + + path_sel_bb = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); + + rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x99000000); + + /* + * Leave IQK mode + */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); + u32p_replace_bits(&val32, 0, 0xffffff00); + rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); + + /* modify RXIQK mode table */ + val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); + val32 |= 0x80000; + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf1173); + + /* PA,PAD gain adjust */ + val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA); + val32 |= BIT(11); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, val32); + val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_PAD_TXG); + u32p_replace_bits(&val32, 0xf, 0x003e0); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_PAD_TXG, val32); + + /* + * Enter IQK mode + */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); + u32p_replace_bits(&val32, 0x808000, 0xffffff00); + rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); + + /* path-A IQK setting */ + rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); + rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); + + rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x8216129f); + rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160c00); + + /* + * Tx IQK setting + */ + rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); + rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); + + /* LO calibration setting */ + rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911); + + /* One shot, path A LOK & IQK */ + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); + + mdelay(10); + + /* Check failed */ + reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); + reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); + reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); + + if (!(reg_eac & BIT(28)) && + ((reg_e94 & 0x03ff0000) != 0x01420000) && + ((reg_e9c & 0x03ff0000) != 0x00420000)) { + result |= 0x01; + } else { /* If TX not OK, ignore RX */ + + /* reload RF path */ + rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel_bb); + + /* + * Leave IQK mode + */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); + u32p_replace_bits(&val32, 0, 0xffffff00); + rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); + + val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA); + val32 &= ~BIT(11); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, val32); + + return result; + } + + val32 = 0x80007c00 | (reg_e94 & 0x3ff0000) | ((reg_e9c & 0x3ff0000) >> 16); + rtl8xxxu_write32(priv, REG_TX_IQK, val32); + + /* + * Modify RX IQK mode table + */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); + u32p_replace_bits(&val32, 0, 0xffffff00); + rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); + + val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); + val32 |= 0x80000; + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7ff2); + + /* + * PA, PAD setting + */ + val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA); + val32 |= BIT(11); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, val32); + val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_PAD_TXG); + u32p_replace_bits(&val32, 0x2a, 0x00fff); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_PAD_TXG, val32); + + /* + * Enter IQK mode + */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); + u32p_replace_bits(&val32, 0x808000, 0xffffff00); + rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); + + /* + * RX IQK setting + */ + rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); + + /* path-A IQK setting */ + rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); + rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c); + + rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x2816169f); + + /* LO calibration setting */ + rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911); + + /* One shot, path A LOK & IQK */ + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); + + mdelay(10); + + /* reload RF path */ + rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel_bb); + + /* + * Leave IQK mode + */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); + u32p_replace_bits(&val32, 0, 0xffffff00); + rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); + + val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA); + val32 &= ~BIT(11); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, val32); + + /* reload LOK value */ + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXM_IDAC, lok_result); + + /* Check failed */ + reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); + reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); + + tmp = (reg_eac & 0x03ff0000) >> 16; + if ((tmp & 0x200) > 0) + tmp = 0x400 - tmp; + + if (!(reg_eac & BIT(27)) && + ((reg_ea4 & 0x03ff0000) != 0x01320000) && + ((reg_eac & 0x03ff0000) != 0x00360000) && + (((reg_ea4 & 0x03ff0000) >> 16) < 0x11a) && + (((reg_ea4 & 0x03ff0000) >> 16) > 0xe6) && + (tmp < 0x1a)) + result |= 0x02; + + return result; +} + +static void rtl8710bu_phy_iqcalibrate(struct rtl8xxxu_priv *priv, + int result[][8], int t) +{ + struct device *dev = &priv->udev->dev; + u32 i, val32, rx_initial_gain, lok_result; + u32 path_sel_bb, path_sel_rf; + int path_a_ok; + int retry = 2; + static const u32 adda_regs[RTL8XXXU_ADDA_REGS] = { + REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH, + REG_RX_WAIT_CCA, REG_TX_CCK_RFON, + REG_TX_CCK_BBON, REG_TX_OFDM_RFON, + REG_TX_OFDM_BBON, REG_TX_TO_RX, + REG_TX_TO_TX, REG_RX_CCK, + REG_RX_OFDM, REG_RX_WAIT_RIFS, + REG_RX_TO_RX, REG_STANDBY, + REG_SLEEP, REG_PMPD_ANAEN + }; + static const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = { + REG_TXPAUSE, REG_BEACON_CTRL, + REG_BEACON_CTRL_1, REG_GPIO_MUXCFG + }; + static const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = { + REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR, + REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, + REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE, + REG_FPGA0_XB_RF_INT_OE, REG_CCK0_AFE_SETTING + }; + + /* + * Note: IQ calibration must be performed after loading + * PHY_REG.txt , and radio_a, radio_b.txt + */ + + rx_initial_gain = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); + + if (t == 0) { + /* Save ADDA parameters, turn Path A ADDA on */ + rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup, + RTL8XXXU_ADDA_REGS); + rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup); + rtl8xxxu_save_regs(priv, iqk_bb_regs, + priv->bb_backup, RTL8XXXU_BB_REGS); + } + + rtl8xxxu_path_adda_on(priv, adda_regs, true); + + if (t == 0) { + val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1); + priv->pi_enabled = u32_get_bits(val32, FPGA0_HSSI_PARM1_PI); + } + + if (!priv->pi_enabled) { + /* Switch BB to PI mode to do IQ Calibration */ + rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100); + rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100); + } + + /* MAC settings */ + val32 = rtl8xxxu_read32(priv, REG_TX_PTCL_CTRL); + val32 |= 0x00ff0000; + rtl8xxxu_write32(priv, REG_TX_PTCL_CTRL, val32); + + /* save RF path */ + path_sel_bb = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); + path_sel_rf = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_S0S1); + + /* BB setting */ + val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING); + val32 |= 0x0f000000; + rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32); + rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x03c00010); + rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05601); + rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4); + rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x25204000); + + /* IQ calibration setting */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); + u32p_replace_bits(&val32, 0x808000, 0xffffff00); + rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); + rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); + rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); + + for (i = 0; i < retry; i++) { + path_a_ok = rtl8710bu_iqk_path_a(priv, &lok_result); + + if (path_a_ok == 0x01) { + val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); + result[t][0] = (val32 >> 16) & 0x3ff; + + val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); + result[t][1] = (val32 >> 16) & 0x3ff; + break; + } else { + result[t][0] = 0x100; + result[t][1] = 0x0; + } + } + + for (i = 0; i < retry; i++) { + path_a_ok = rtl8710bu_rx_iqk_path_a(priv, lok_result); + + if (path_a_ok == 0x03) { + val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); + result[t][2] = (val32 >> 16) & 0x3ff; + + val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); + result[t][3] = (val32 >> 16) & 0x3ff; + break; + } else { + result[t][2] = 0x100; + result[t][3] = 0x0; + } + } + + if (!path_a_ok) + dev_warn(dev, "%s: Path A IQK failed!\n", __func__); + + /* Back to BB mode, load original value */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); + u32p_replace_bits(&val32, 0, 0xffffff00); + rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); + + if (t == 0) + return; + + /* Reload ADDA power saving parameters */ + rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup, RTL8XXXU_ADDA_REGS); + + /* Reload MAC parameters */ + rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup); + + /* Reload BB parameters */ + rtl8xxxu_restore_regs(priv, iqk_bb_regs, priv->bb_backup, RTL8XXXU_BB_REGS); + + /* Reload RF path */ + rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel_bb); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, path_sel_rf); + + /* Restore RX initial gain */ + val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); + u32p_replace_bits(&val32, 0x50, 0x000000ff); + rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32); + val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); + u32p_replace_bits(&val32, rx_initial_gain & 0xff, 0x000000ff); + rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32); + + /* Load 0xe30 IQC default value */ + rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00); + rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00); +} + +static void rtl8710bu_phy_iq_calibrate(struct rtl8xxxu_priv *priv) +{ + struct device *dev = &priv->udev->dev; + int result[4][8]; /* last is final result */ + int i, candidate; + bool path_a_ok; + s32 reg_e94, reg_e9c, reg_ea4, reg_eac; + s32 reg_tmp = 0; + bool simu; + u32 path_sel_bb; + + /* Save RF path */ + path_sel_bb = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); + + memset(result, 0, sizeof(result)); + candidate = -1; + + path_a_ok = false; + + for (i = 0; i < 3; i++) { + rtl8710bu_phy_iqcalibrate(priv, result, i); + + if (i == 1) { + simu = rtl8xxxu_gen2_simularity_compare(priv, result, 0, 1); + if (simu) { + candidate = 0; + break; + } + } + + if (i == 2) { + simu = rtl8xxxu_gen2_simularity_compare(priv, result, 0, 2); + if (simu) { + candidate = 0; + break; + } + + simu = rtl8xxxu_gen2_simularity_compare(priv, result, 1, 2); + if (simu) { + candidate = 1; + } else { + for (i = 0; i < 8; i++) + reg_tmp += result[3][i]; + + if (reg_tmp) + candidate = 3; + else + candidate = -1; + } + } + } + + if (candidate >= 0) { + reg_e94 = result[candidate][0]; + reg_e9c = result[candidate][1]; + reg_ea4 = result[candidate][2]; + reg_eac = result[candidate][3]; + + dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate); + dev_dbg(dev, "%s: e94=%x e9c=%x ea4=%x eac=%x\n", + __func__, reg_e94, reg_e9c, reg_ea4, reg_eac); + + path_a_ok = true; + + if (reg_e94) + rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result, + candidate, (reg_ea4 == 0)); + } + + rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg, + priv->bb_recovery_backup, RTL8XXXU_BB_REGS); + + rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel_bb); +} + +static int rtl8710b_emu_to_active(struct rtl8xxxu_priv *priv) +{ + u8 val8; + int count, ret = 0; + + /* AFE power mode selection: 1: LDO mode, 0: Power-cut mode */ + val8 = rtl8xxxu_read8(priv, 0x5d); + val8 &= ~BIT(0); + rtl8xxxu_write8(priv, 0x5d, val8); + + val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC_8710B); + val8 |= BIT(0); + rtl8xxxu_write8(priv, REG_SYS_FUNC_8710B, val8); + + rtl8xxxu_write8(priv, 0x56, 0x0e); + + val8 = rtl8xxxu_read8(priv, 0x20); + val8 |= BIT(0); + rtl8xxxu_write8(priv, 0x20, val8); + + for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { + val8 = rtl8xxxu_read8(priv, 0x20); + if (!(val8 & BIT(0))) + break; + + udelay(10); + } + + if (!count) + ret = -EBUSY; + + return ret; +} + +static int rtl8710bu_active_to_emu(struct rtl8xxxu_priv *priv) +{ + u8 val8; + u32 val32; + int count, ret = 0; + + /* Turn off RF */ + val32 = rtl8xxxu_read32(priv, REG_SYS_FUNC_8710B); + val32 &= ~GENMASK(26, 24); + rtl8xxxu_write32(priv, REG_SYS_FUNC_8710B, val32); + + /* BB reset */ + val32 = rtl8xxxu_read32(priv, REG_SYS_FUNC_8710B); + val32 &= ~GENMASK(17, 16); + rtl8xxxu_write32(priv, REG_SYS_FUNC_8710B, val32); + + /* Turn off MAC by HW state machine */ + val8 = rtl8xxxu_read8(priv, 0x20); + val8 |= BIT(1); + rtl8xxxu_write8(priv, 0x20, val8); + + for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { + val8 = rtl8xxxu_read8(priv, 0x20); + if ((val8 & BIT(1)) == 0) { + ret = 0; + break; + } + udelay(10); + } + + if (!count) + ret = -EBUSY; + + return ret; +} + +static int rtl8710bu_active_to_lps(struct rtl8xxxu_priv *priv) +{ + struct device *dev = &priv->udev->dev; + u8 val8; + u16 val16; + u32 val32; + int retry, retval; + + /* Tx Pause */ + rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); + + retry = 100; + retval = -EBUSY; + /* + * Poll 32 bit wide REG_SCH_TX_CMD for 0x00000000 to ensure no TX is pending. + */ + do { + val32 = rtl8xxxu_read32(priv, REG_SCH_TX_CMD); + if (!val32) { + retval = 0; + break; + } + udelay(10); + } while (retry--); + + if (!retry) { + dev_warn(dev, "Failed to flush TX queue\n"); + retval = -EBUSY; + return retval; + } + + /* Disable CCK and OFDM, clock gated */ + val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); + val8 &= ~SYS_FUNC_BBRSTB; + rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); + + udelay(2); + + /* Whole BB is reset */ + val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); + val8 &= ~SYS_FUNC_BB_GLB_RSTN; + rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); + + /* Reset MAC TRX */ + val16 = rtl8xxxu_read16(priv, REG_CR); + val16 &= 0xff00; + val16 |= CR_HCI_RXDMA_ENABLE | CR_HCI_TXDMA_ENABLE; + val16 &= ~CR_SECURITY_ENABLE; + rtl8xxxu_write16(priv, REG_CR, val16); + + /* Respond TxOK to scheduler */ + val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST); + val8 |= DUAL_TSF_TX_OK; + rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8); + + return retval; +} + +static int rtl8710bu_power_on(struct rtl8xxxu_priv *priv) +{ + u32 val32; + u16 val16; + u8 val8; + int ret; + + rtl8xxxu_write8(priv, REG_USB_ACCESS_TIMEOUT, 0x80); + + val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL); + val8 &= ~BIT(5); + rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8); + + val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC_8710B); + val8 |= BIT(0); + rtl8xxxu_write8(priv, REG_SYS_FUNC_8710B, val8); + + val8 = rtl8xxxu_read8(priv, 0x20); + val8 |= BIT(0); + rtl8xxxu_write8(priv, 0x20, val8); + + rtl8xxxu_write8(priv, REG_AFE_CTRL_8710B, 0); + + val8 = rtl8xxxu_read8(priv, REG_WL_STATUS_8710B); + val8 |= BIT(1); + rtl8xxxu_write8(priv, REG_WL_STATUS_8710B, val8); + + ret = rtl8710b_emu_to_active(priv); + if (ret) + return ret; + + rtl8xxxu_write16(priv, REG_CR, 0); + + val16 = rtl8xxxu_read16(priv, REG_CR); + + val16 |= CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE | + CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | + CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE | + CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE; + rtl8xxxu_write16(priv, REG_CR, val16); + + /* Enable hardware sequence number. */ + val8 = rtl8xxxu_read8(priv, REG_HWSEQ_CTRL); + val8 |= 0x7f; + rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, val8); + + udelay(2); + + /* + * Technically the rest was in the rtl8710bu_hal_init function, + * not the power_on function, but it's fine because we only + * call power_on from init_device. + */ + + val8 = rtl8xxxu_read8(priv, 0xfef9); + val8 &= ~BIT(0); + rtl8xxxu_write8(priv, 0xfef9, val8); + + /* Clear the 0x40000138[5] to prevent CM4 Suspend */ + val32 = rtl8710b_read_syson_reg(priv, 0x138); + val32 &= ~BIT(5); + rtl8710b_write_syson_reg(priv, 0x138, val32); + + return ret; +} + +static void rtl8710bu_power_off(struct rtl8xxxu_priv *priv) +{ + u32 val32; + u8 val8; + + rtl8xxxu_flush_fifo(priv); + + rtl8xxxu_write32(priv, REG_HISR0_8710B, 0xffffffff); + rtl8xxxu_write32(priv, REG_HIMR0_8710B, 0x0); + + /* Set the 0x40000138[5] to allow CM4 Suspend */ + val32 = rtl8710b_read_syson_reg(priv, 0x138); + val32 |= BIT(5); + rtl8710b_write_syson_reg(priv, 0x138, val32); + + /* Stop rx */ + rtl8xxxu_write8(priv, REG_CR, 0x00); + + rtl8710bu_active_to_lps(priv); + + /* Reset MCU ? */ + val8 = rtl8xxxu_read8(priv, REG_8051FW_CTRL_V1_8710B + 3); + val8 &= ~BIT(0); + rtl8xxxu_write8(priv, REG_8051FW_CTRL_V1_8710B + 3, val8); + + /* Reset MCU ready status */ + rtl8xxxu_write8(priv, REG_8051FW_CTRL_V1_8710B, 0x00); + + rtl8710bu_active_to_emu(priv); +} + +static void rtl8710b_reset_8051(struct rtl8xxxu_priv *priv) +{ + u8 val8; + + val8 = rtl8xxxu_read8(priv, REG_8051FW_CTRL_V1_8710B + 3); + val8 &= ~BIT(0); + rtl8xxxu_write8(priv, REG_8051FW_CTRL_V1_8710B + 3, val8); + + udelay(50); + + val8 = rtl8xxxu_read8(priv, REG_8051FW_CTRL_V1_8710B + 3); + val8 |= BIT(0); + rtl8xxxu_write8(priv, REG_8051FW_CTRL_V1_8710B + 3, val8); +} + +static void rtl8710b_enable_rf(struct rtl8xxxu_priv *priv) +{ + u32 val32; + + rtl8xxxu_write8(priv, REG_RF_CTRL, RF_ENABLE | RF_RSTB | RF_SDMRSTB); + + val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); + val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK); + val32 |= OFDM_RF_PATH_RX_A | OFDM_RF_PATH_TX_A; + rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); + + rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); +} + +static void rtl8710b_disable_rf(struct rtl8xxxu_priv *priv) +{ + u32 val32; + + val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); + val32 &= ~OFDM_RF_PATH_TX_MASK; + rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); + + /* Power down RF module */ + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0); +} + +static void rtl8710b_usb_quirks(struct rtl8xxxu_priv *priv) +{ + u16 val16; + + rtl8xxxu_gen2_usb_quirks(priv); + + val16 = rtl8xxxu_read16(priv, REG_CR); + val16 |= (CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE); + rtl8xxxu_write16(priv, REG_CR, val16); +} + +#define XTAL1 GENMASK(29, 24) +#define XTAL0 GENMASK(23, 18) + +static void rtl8710b_set_crystal_cap(struct rtl8xxxu_priv *priv, u8 crystal_cap) +{ + struct rtl8xxxu_cfo_tracking *cfo = &priv->cfo_tracking; + u32 val32; + + if (crystal_cap == cfo->crystal_cap) + return; + + val32 = rtl8710b_read_syson_reg(priv, REG_SYS_XTAL_CTRL0_8710B); + + dev_dbg(&priv->udev->dev, + "%s: Adjusting crystal cap from 0x%x (actually 0x%x 0x%x) to 0x%x\n", + __func__, + cfo->crystal_cap, + u32_get_bits(val32, XTAL1), + u32_get_bits(val32, XTAL0), + crystal_cap); + + u32p_replace_bits(&val32, crystal_cap, XTAL1); + u32p_replace_bits(&val32, crystal_cap, XTAL0); + rtl8710b_write_syson_reg(priv, REG_SYS_XTAL_CTRL0_8710B, val32); + + cfo->crystal_cap = crystal_cap; +} + +static s8 rtl8710b_cck_rssi(struct rtl8xxxu_priv *priv, struct rtl8723au_phy_stats *phy_stats) +{ + struct jaguar2_phy_stats_type0 *phy_stats0 = (struct jaguar2_phy_stats_type0 *)phy_stats; + u8 lna_idx = (phy_stats0->lna_h << 3) | phy_stats0->lna_l; + u8 vga_idx = phy_stats0->vga; + s8 rx_pwr_all = 0x00; + + switch (lna_idx) { + case 7: + rx_pwr_all = -52 - (2 * vga_idx); + break; + case 6: + rx_pwr_all = -42 - (2 * vga_idx); + break; + case 5: + rx_pwr_all = -36 - (2 * vga_idx); + break; + case 3: + rx_pwr_all = -12 - (2 * vga_idx); + break; + case 2: + rx_pwr_all = 0 - (2 * vga_idx); + break; + default: + rx_pwr_all = 0; + break; + } + + return rx_pwr_all; +} + +struct rtl8xxxu_fileops rtl8710bu_fops = { + .identify_chip = rtl8710bu_identify_chip, + .parse_efuse = rtl8710bu_parse_efuse, + .load_firmware = rtl8710bu_load_firmware, + .power_on = rtl8710bu_power_on, + .power_off = rtl8710bu_power_off, + .read_efuse = rtl8710b_read_efuse, + .reset_8051 = rtl8710b_reset_8051, + .llt_init = rtl8xxxu_auto_llt_table, + .init_phy_bb = rtl8710bu_init_phy_bb, + .init_phy_rf = rtl8710bu_init_phy_rf, + .phy_lc_calibrate = rtl8188f_phy_lc_calibrate, + .phy_iq_calibrate = rtl8710bu_phy_iq_calibrate, + .config_channel = rtl8710bu_config_channel, + .parse_rx_desc = rtl8xxxu_parse_rxdesc24, + .parse_phystats = jaguar2_rx_parse_phystats, + .init_aggregation = rtl8710bu_init_aggregation, + .init_statistics = rtl8710bu_init_statistics, + .init_burst = rtl8xxxu_init_burst, + .enable_rf = rtl8710b_enable_rf, + .disable_rf = rtl8710b_disable_rf, + .usb_quirks = rtl8710b_usb_quirks, + .set_tx_power = rtl8188f_set_tx_power, + .update_rate_mask = rtl8xxxu_gen2_update_rate_mask, + .report_connect = rtl8xxxu_gen2_report_connect, + .report_rssi = rtl8xxxu_gen2_report_rssi, + .fill_txdesc = rtl8xxxu_fill_txdesc_v2, + .set_crystal_cap = rtl8710b_set_crystal_cap, + .cck_rssi = rtl8710b_cck_rssi, + .writeN_block_size = 4, + .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc24), + .tx_desc_size = sizeof(struct rtl8xxxu_txdesc40), + .has_tx_report = 1, + .gen2_thermal_meter = 1, + .needs_full_init = 1, + .init_reg_rxfltmap = 1, + .init_reg_pkt_life_time = 1, + .init_reg_hmtfr = 1, + .ampdu_max_time = 0x5e, + /* + * The RTL8710BU vendor driver uses 0x50 here and it works fine, + * but in rtl8xxxu 0x50 causes slow upload and random packet loss. Why? + */ + .ustime_tsf_edca = 0x28, + .max_aggr_num = 0x0c14, + .supports_ap = 1, + .max_macid_num = 16, + .max_sec_cam_num = 32, + .adda_1t_init = 0x03c00016, + .adda_1t_path_on = 0x03c00016, + .trxff_boundary = 0x3f7f, + .pbp_rx = PBP_PAGE_SIZE_256, + .pbp_tx = PBP_PAGE_SIZE_256, + .mactable = rtl8710b_mac_init_table, + .total_page_num = TX_TOTAL_PAGE_NUM_8723B, + .page_num_hi = TX_PAGE_NUM_HI_PQ_8723B, + .page_num_lo = TX_PAGE_NUM_LO_PQ_8723B, + .page_num_norm = TX_PAGE_NUM_NORM_PQ_8723B, +}; diff --git a/drivers/net/wireless/realtek/rtl8xxxu/8723a.c b/drivers/net/wireless/realtek/rtl8xxxu/8723a.c new file mode 100644 index 000000000000..9f03bf163c97 --- /dev/null +++ b/drivers/net/wireless/realtek/rtl8xxxu/8723a.c @@ -0,0 +1,547 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * RTL8XXXU mac80211 USB driver - 8723a specific subdriver + * + * Copyright (c) 2014 - 2017 Jes Sorensen + * + * Portions, notably calibration code: + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This driver was written as a replacement for the vendor provided + * rtl8723au driver. As the Realtek 8xxx chips are very similar in + * their programming interface, I have started adding support for + * additional 8xxx chips like the 8192cu, 8188cus, etc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "rtl8xxxu.h" +#include "regs.h" + +static struct rtl8xxxu_power_base rtl8723a_power_base = { + .reg_0e00 = 0x0a0c0c0c, + .reg_0e04 = 0x02040608, + .reg_0e08 = 0x00000000, + .reg_086c = 0x00000000, + + .reg_0e10 = 0x0a0c0d0e, + .reg_0e14 = 0x02040608, + .reg_0e18 = 0x0a0c0d0e, + .reg_0e1c = 0x02040608, + + .reg_0830 = 0x0a0c0c0c, + .reg_0834 = 0x02040608, + .reg_0838 = 0x00000000, + .reg_086c_2 = 0x00000000, + + .reg_083c = 0x0a0c0d0e, + .reg_0848 = 0x02040608, + .reg_084c = 0x0a0c0d0e, + .reg_0868 = 0x02040608, +}; + +static const struct rtl8xxxu_reg8val rtl8723au_mac_init_table[] = { + {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00}, + {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05}, + {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00}, + {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05}, + {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01}, + {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f}, + {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72}, + {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08}, + {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff}, + {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2}, + {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3}, + {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4}, + {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4}, + {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a}, + {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16}, + {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00}, + {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02}, + {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a}, + {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e}, + {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43}, + {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43}, + {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff}, +}; + +static const struct rtl8xxxu_rfregval rtl8723au_radioa_1t_init_table[] = { + {0x00, 0x00030159}, {0x01, 0x00031284}, + {0x02, 0x00098000}, {0x03, 0x00039c63}, + {0x04, 0x000210e7}, {0x09, 0x0002044f}, + {0x0a, 0x0001a3f1}, {0x0b, 0x00014787}, + {0x0c, 0x000896fe}, {0x0d, 0x0000e02c}, + {0x0e, 0x00039ce7}, {0x0f, 0x00000451}, + {0x19, 0x00000000}, {0x1a, 0x00030355}, + {0x1b, 0x00060a00}, {0x1c, 0x000fc378}, + {0x1d, 0x000a1250}, {0x1e, 0x0000024f}, + {0x1f, 0x00000000}, {0x20, 0x0000b614}, + {0x21, 0x0006c000}, {0x22, 0x00000000}, + {0x23, 0x00001558}, {0x24, 0x00000060}, + {0x25, 0x00000483}, {0x26, 0x0004f000}, + {0x27, 0x000ec7d9}, {0x28, 0x00057730}, + {0x29, 0x00004783}, {0x2a, 0x00000001}, + {0x2b, 0x00021334}, {0x2a, 0x00000000}, + {0x2b, 0x00000054}, {0x2a, 0x00000001}, + {0x2b, 0x00000808}, {0x2b, 0x00053333}, + {0x2c, 0x0000000c}, {0x2a, 0x00000002}, + {0x2b, 0x00000808}, {0x2b, 0x0005b333}, + {0x2c, 0x0000000d}, {0x2a, 0x00000003}, + {0x2b, 0x00000808}, {0x2b, 0x00063333}, + {0x2c, 0x0000000d}, {0x2a, 0x00000004}, + {0x2b, 0x00000808}, {0x2b, 0x0006b333}, + {0x2c, 0x0000000d}, {0x2a, 0x00000005}, + {0x2b, 0x00000808}, {0x2b, 0x00073333}, + {0x2c, 0x0000000d}, {0x2a, 0x00000006}, + {0x2b, 0x00000709}, {0x2b, 0x0005b333}, + {0x2c, 0x0000000d}, {0x2a, 0x00000007}, + {0x2b, 0x00000709}, {0x2b, 0x00063333}, + {0x2c, 0x0000000d}, {0x2a, 0x00000008}, + {0x2b, 0x0000060a}, {0x2b, 0x0004b333}, + {0x2c, 0x0000000d}, {0x2a, 0x00000009}, + {0x2b, 0x0000060a}, {0x2b, 0x00053333}, + {0x2c, 0x0000000d}, {0x2a, 0x0000000a}, + {0x2b, 0x0000060a}, {0x2b, 0x0005b333}, + {0x2c, 0x0000000d}, {0x2a, 0x0000000b}, + {0x2b, 0x0000060a}, {0x2b, 0x00063333}, + {0x2c, 0x0000000d}, {0x2a, 0x0000000c}, + {0x2b, 0x0000060a}, {0x2b, 0x0006b333}, + {0x2c, 0x0000000d}, {0x2a, 0x0000000d}, + {0x2b, 0x0000060a}, {0x2b, 0x00073333}, + {0x2c, 0x0000000d}, {0x2a, 0x0000000e}, + {0x2b, 0x0000050b}, {0x2b, 0x00066666}, + {0x2c, 0x0000001a}, {0x2a, 0x000e0000}, + {0x10, 0x0004000f}, {0x11, 0x000e31fc}, + {0x10, 0x0006000f}, {0x11, 0x000ff9f8}, + {0x10, 0x0002000f}, {0x11, 0x000203f9}, + {0x10, 0x0003000f}, {0x11, 0x000ff500}, + {0x10, 0x00000000}, {0x11, 0x00000000}, + {0x10, 0x0008000f}, {0x11, 0x0003f100}, + {0x10, 0x0009000f}, {0x11, 0x00023100}, + {0x12, 0x00032000}, {0x12, 0x00071000}, + {0x12, 0x000b0000}, {0x12, 0x000fc000}, + {0x13, 0x000287b3}, {0x13, 0x000244b7}, + {0x13, 0x000204ab}, {0x13, 0x0001c49f}, + {0x13, 0x00018493}, {0x13, 0x0001429b}, + {0x13, 0x00010299}, {0x13, 0x0000c29c}, + {0x13, 0x000081a0}, {0x13, 0x000040ac}, + {0x13, 0x00000020}, {0x14, 0x0001944c}, + {0x14, 0x00059444}, {0x14, 0x0009944c}, + {0x14, 0x000d9444}, {0x15, 0x0000f474}, + {0x15, 0x0004f477}, {0x15, 0x0008f455}, + {0x15, 0x000cf455}, {0x16, 0x00000339}, + {0x16, 0x00040339}, {0x16, 0x00080339}, + {0x16, 0x000c0366}, {0x00, 0x00010159}, + {0x18, 0x0000f401}, {0xfe, 0x00000000}, + {0xfe, 0x00000000}, {0x1f, 0x00000003}, + {0xfe, 0x00000000}, {0xfe, 0x00000000}, + {0x1e, 0x00000247}, {0x1f, 0x00000000}, + {0x00, 0x00030159}, + {0xff, 0xffffffff} +}; + +static int rtl8723au_identify_chip(struct rtl8xxxu_priv *priv) +{ + struct device *dev = &priv->udev->dev; + u32 val32, sys_cfg, vendor; + int ret = 0; + + sys_cfg = rtl8xxxu_read32(priv, REG_SYS_CFG); + priv->chip_cut = u32_get_bits(sys_cfg, SYS_CFG_CHIP_VERSION_MASK); + if (sys_cfg & SYS_CFG_TRP_VAUX_EN) { + dev_info(dev, "Unsupported test chip\n"); + ret = -ENOTSUPP; + goto out; + } + + strscpy(priv->chip_name, "8723AU", sizeof(priv->chip_name)); + priv->usb_interrupts = 1; + priv->rtl_chip = RTL8723A; + + priv->rf_paths = 1; + priv->rx_paths = 1; + priv->tx_paths = 1; + + val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL); + if (val32 & MULTI_WIFI_FUNC_EN) + priv->has_wifi = 1; + if (val32 & MULTI_BT_FUNC_EN) + priv->has_bluetooth = 1; + if (val32 & MULTI_GPS_FUNC_EN) + priv->has_gps = 1; + priv->is_multi_func = 1; + + vendor = sys_cfg & SYS_CFG_VENDOR_ID; + rtl8xxxu_identify_vendor_1bit(priv, vendor); + + val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS); + priv->rom_rev = u32_get_bits(val32, GPIO_RF_RL_ID); + + rtl8xxxu_config_endpoints_sie(priv); + + /* + * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX + */ + if (!priv->ep_tx_count) + ret = rtl8xxxu_config_endpoints_no_sie(priv); + +out: + return ret; +} + +static int rtl8723au_parse_efuse(struct rtl8xxxu_priv *priv) +{ + struct rtl8723au_efuse *efuse = &priv->efuse_wifi.efuse8723; + + if (efuse->rtl_id != cpu_to_le16(0x8129)) + return -EINVAL; + + ether_addr_copy(priv->mac_addr, efuse->mac_addr); + + memcpy(priv->cck_tx_power_index_A, + efuse->cck_tx_power_index_A, + sizeof(efuse->cck_tx_power_index_A)); + memcpy(priv->cck_tx_power_index_B, + efuse->cck_tx_power_index_B, + sizeof(efuse->cck_tx_power_index_B)); + + memcpy(priv->ht40_1s_tx_power_index_A, + efuse->ht40_1s_tx_power_index_A, + sizeof(efuse->ht40_1s_tx_power_index_A)); + memcpy(priv->ht40_1s_tx_power_index_B, + efuse->ht40_1s_tx_power_index_B, + sizeof(efuse->ht40_1s_tx_power_index_B)); + + memcpy(priv->ht20_tx_power_index_diff, + efuse->ht20_tx_power_index_diff, + sizeof(efuse->ht20_tx_power_index_diff)); + memcpy(priv->ofdm_tx_power_index_diff, + efuse->ofdm_tx_power_index_diff, + sizeof(efuse->ofdm_tx_power_index_diff)); + + memcpy(priv->ht40_max_power_offset, + efuse->ht40_max_power_offset, + sizeof(efuse->ht40_max_power_offset)); + memcpy(priv->ht20_max_power_offset, + efuse->ht20_max_power_offset, + sizeof(efuse->ht20_max_power_offset)); + + if (priv->efuse_wifi.efuse8723.version >= 0x01) + priv->default_crystal_cap = priv->efuse_wifi.efuse8723.xtal_k & 0x3f; + else + priv->fops->set_crystal_cap = NULL; + + priv->power_base = &rtl8723a_power_base; + + return 0; +} + +static int rtl8723au_load_firmware(struct rtl8xxxu_priv *priv) +{ + const char *fw_name; + int ret; + + switch (priv->chip_cut) { + case 0: + fw_name = "rtlwifi/rtl8723aufw_A.bin"; + break; + case 1: + if (priv->enable_bluetooth) + fw_name = "rtlwifi/rtl8723aufw_B.bin"; + else + fw_name = "rtlwifi/rtl8723aufw_B_NoBT.bin"; + + break; + default: + return -EINVAL; + } + + ret = rtl8xxxu_load_firmware(priv, fw_name); + return ret; +} + +static int rtl8723au_init_phy_rf(struct rtl8xxxu_priv *priv) +{ + int ret; + + ret = rtl8xxxu_init_phy_rf(priv, rtl8723au_radioa_1t_init_table, RF_A); + + /* Reduce 80M spur */ + rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x0381808d); + rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83); + rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff82); + rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83); + + return ret; +} + +static int rtl8723a_emu_to_active(struct rtl8xxxu_priv *priv) +{ + u8 val8; + u32 val32; + int count, ret = 0; + + /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface*/ + val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL); + val8 |= LDOA15_ENABLE; + rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8); + + /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/ + val8 = rtl8xxxu_read8(priv, 0x0067); + val8 &= ~BIT(4); + rtl8xxxu_write8(priv, 0x0067, val8); + + mdelay(1); + + /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */ + val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL); + val8 &= ~SYS_ISO_ANALOG_IPS; + rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8); + + /* disable SW LPS 0x04[10]= 0 */ + val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); + val8 &= ~BIT(2); + rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); + + /* wait till 0x04[17] = 1 power ready*/ + for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { + val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); + if (val32 & BIT(17)) + break; + + udelay(10); + } + + if (!count) { + ret = -EBUSY; + goto exit; + } + + /* We should be able to optimize the following three entries into one */ + + /* release WLON reset 0x04[16]= 1*/ + val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2); + val8 |= BIT(0); + rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8); + + /* disable HWPDN 0x04[15]= 0*/ + val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); + val8 &= ~BIT(7); + rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); + + /* disable WL suspend*/ + val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); + val8 &= ~(BIT(3) | BIT(4)); + rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); + + /* set, then poll until 0 */ + val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); + val32 |= APS_FSMCO_MAC_ENABLE; + rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); + + for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { + val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); + if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) { + ret = 0; + break; + } + udelay(10); + } + + if (!count) { + ret = -EBUSY; + goto exit; + } + + /* 0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */ + /* + * Note: Vendor driver actually clears this bit, despite the + * documentation claims it's being set! + */ + val8 = rtl8xxxu_read8(priv, REG_LEDCFG2); + val8 |= LEDCFG2_DPDT_SELECT; + val8 &= ~LEDCFG2_DPDT_SELECT; + rtl8xxxu_write8(priv, REG_LEDCFG2, val8); + +exit: + return ret; +} + +static int rtl8723au_power_on(struct rtl8xxxu_priv *priv) +{ + u8 val8; + u16 val16; + u32 val32; + int ret; + + /* + * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register + */ + rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0); + + rtl8xxxu_disabled_to_emu(priv); + + ret = rtl8723a_emu_to_active(priv); + if (ret) + goto exit; + + /* + * 0x0004[19] = 1, reset 8051 + */ + val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2); + val8 |= BIT(3); + rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8); + + /* + * Enable MAC DMA/WMAC/SCHEDULE/SEC block + * Set CR bit10 to enable 32k calibration. + */ + val16 = rtl8xxxu_read16(priv, REG_CR); + val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE | + CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | + CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE | + CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE | + CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE); + rtl8xxxu_write16(priv, REG_CR, val16); + + /* For EFuse PG */ + val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL); + val32 &= ~(BIT(28) | BIT(29) | BIT(30)); + val32 |= (0x06 << 28); + rtl8xxxu_write32(priv, REG_EFUSE_CTRL, val32); +exit: + return ret; +} + +#define XTAL1 GENMASK(23, 18) +#define XTAL0 GENMASK(17, 12) + +void rtl8723a_set_crystal_cap(struct rtl8xxxu_priv *priv, u8 crystal_cap) +{ + struct rtl8xxxu_cfo_tracking *cfo = &priv->cfo_tracking; + u32 val32; + + if (crystal_cap == cfo->crystal_cap) + return; + + val32 = rtl8xxxu_read32(priv, REG_MAC_PHY_CTRL); + + dev_dbg(&priv->udev->dev, + "%s: Adjusting crystal cap from 0x%x (actually 0x%lx 0x%lx) to 0x%x\n", + __func__, + cfo->crystal_cap, + FIELD_GET(XTAL1, val32), + FIELD_GET(XTAL0, val32), + crystal_cap); + + val32 &= ~(XTAL1 | XTAL0); + val32 |= FIELD_PREP(XTAL1, crystal_cap) | + FIELD_PREP(XTAL0, crystal_cap); + rtl8xxxu_write32(priv, REG_MAC_PHY_CTRL, val32); + + cfo->crystal_cap = crystal_cap; +} + +s8 rtl8723a_cck_rssi(struct rtl8xxxu_priv *priv, struct rtl8723au_phy_stats *phy_stats) +{ + u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a; + s8 rx_pwr_all = 0x00; + + switch (cck_agc_rpt & 0xc0) { + case 0xc0: + rx_pwr_all = -46 - (cck_agc_rpt & 0x3e); + break; + case 0x80: + rx_pwr_all = -26 - (cck_agc_rpt & 0x3e); + break; + case 0x40: + rx_pwr_all = -12 - (cck_agc_rpt & 0x3e); + break; + case 0x00: + rx_pwr_all = 16 - (cck_agc_rpt & 0x3e); + break; + } + + return rx_pwr_all; +} + +static int rtl8723au_led_brightness_set(struct led_classdev *led_cdev, + enum led_brightness brightness) +{ + struct rtl8xxxu_priv *priv = container_of(led_cdev, + struct rtl8xxxu_priv, + led_cdev); + u8 ledcfg = rtl8xxxu_read8(priv, REG_LEDCFG2); + + if (brightness == LED_OFF) { + ledcfg &= ~LEDCFG2_HW_LED_CONTROL; + ledcfg |= LEDCFG2_SW_LED_CONTROL | LEDCFG2_SW_LED_DISABLE; + } else if (brightness == LED_ON) { + ledcfg &= ~(LEDCFG2_HW_LED_CONTROL | LEDCFG2_SW_LED_DISABLE); + ledcfg |= LEDCFG2_SW_LED_CONTROL; + } else if (brightness == RTL8XXXU_HW_LED_CONTROL) { + ledcfg &= ~LEDCFG2_SW_LED_DISABLE; + ledcfg |= LEDCFG2_HW_LED_CONTROL | LEDCFG2_HW_LED_ENABLE; + } + + rtl8xxxu_write8(priv, REG_LEDCFG2, ledcfg); + + return 0; +} + +struct rtl8xxxu_fileops rtl8723au_fops = { + .identify_chip = rtl8723au_identify_chip, + .parse_efuse = rtl8723au_parse_efuse, + .load_firmware = rtl8723au_load_firmware, + .power_on = rtl8723au_power_on, + .power_off = rtl8xxxu_power_off, + .read_efuse = rtl8xxxu_read_efuse, + .reset_8051 = rtl8xxxu_reset_8051, + .llt_init = rtl8xxxu_init_llt_table, + .init_phy_bb = rtl8xxxu_gen1_init_phy_bb, + .init_phy_rf = rtl8723au_init_phy_rf, + .phy_lc_calibrate = rtl8723a_phy_lc_calibrate, + .phy_iq_calibrate = rtl8xxxu_gen1_phy_iq_calibrate, + .config_channel = rtl8xxxu_gen1_config_channel, + .parse_rx_desc = rtl8xxxu_parse_rxdesc16, + .parse_phystats = rtl8723au_rx_parse_phystats, + .init_aggregation = rtl8xxxu_gen1_init_aggregation, + .enable_rf = rtl8xxxu_gen1_enable_rf, + .disable_rf = rtl8xxxu_gen1_disable_rf, + .usb_quirks = rtl8xxxu_gen1_usb_quirks, + .set_tx_power = rtl8xxxu_gen1_set_tx_power, + .update_rate_mask = rtl8xxxu_update_rate_mask, + .report_connect = rtl8xxxu_gen1_report_connect, + .report_rssi = rtl8xxxu_gen1_report_rssi, + .fill_txdesc = rtl8xxxu_fill_txdesc_v1, + .set_crystal_cap = rtl8723a_set_crystal_cap, + .cck_rssi = rtl8723a_cck_rssi, + .led_classdev_brightness_set = rtl8723au_led_brightness_set, + .writeN_block_size = 1024, + .rx_agg_buf_size = 16000, + .tx_desc_size = sizeof(struct rtl8xxxu_txdesc32), + .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc16), + .max_sec_cam_num = 32, + .adda_1t_init = 0x0b1b25a0, + .adda_1t_path_on = 0x0bdb25a0, + .adda_2t_path_on_a = 0x04db25a4, + .adda_2t_path_on_b = 0x0b1b25a4, + .trxff_boundary = 0x27ff, + .pbp_rx = PBP_PAGE_SIZE_128, + .pbp_tx = PBP_PAGE_SIZE_128, + .mactable = rtl8723au_mac_init_table, + .total_page_num = TX_TOTAL_PAGE_NUM, + .page_num_hi = TX_PAGE_NUM_HI_PQ, + .page_num_lo = TX_PAGE_NUM_LO_PQ, + .page_num_norm = TX_PAGE_NUM_NORM_PQ, +}; diff --git a/drivers/net/wireless/realtek/rtl8xxxu/8723b.c b/drivers/net/wireless/realtek/rtl8xxxu/8723b.c new file mode 100644 index 000000000000..0880049373b0 --- /dev/null +++ b/drivers/net/wireless/realtek/rtl8xxxu/8723b.c @@ -0,0 +1,1779 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * RTL8XXXU mac80211 USB driver - 8723b specific subdriver + * + * Copyright (c) 2014 - 2017 Jes Sorensen + * + * Portions, notably calibration code: + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This driver was written as a replacement for the vendor provided + * rtl8723au driver. As the Realtek 8xxx chips are very similar in + * their programming interface, I have started adding support for + * additional 8xxx chips like the 8192cu, 8188cus, etc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "rtl8xxxu.h" +#include "regs.h" + +static const struct rtl8xxxu_reg8val rtl8723b_mac_init_table[] = { + {0x02f, 0x30}, {0x035, 0x00}, {0x039, 0x08}, {0x04e, 0xe0}, + {0x064, 0x00}, {0x067, 0x20}, {0x428, 0x0a}, {0x429, 0x10}, + {0x430, 0x00}, {0x431, 0x00}, + {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05}, + {0x436, 0x07}, {0x437, 0x08}, {0x43c, 0x04}, {0x43d, 0x05}, + {0x43e, 0x07}, {0x43f, 0x08}, {0x440, 0x5d}, {0x441, 0x01}, + {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, {0x446, 0x00}, + {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xf0}, {0x44a, 0x0f}, + {0x44b, 0x3e}, {0x44c, 0x10}, {0x44d, 0x00}, {0x44e, 0x00}, + {0x44f, 0x00}, {0x450, 0x00}, {0x451, 0xf0}, {0x452, 0x0f}, + {0x453, 0x00}, {0x456, 0x5e}, {0x460, 0x66}, {0x461, 0x66}, + {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff}, + {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2}, + {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3}, + {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4}, + {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4}, + {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a}, + {0x516, 0x0a}, {0x525, 0x4f}, + {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55c, 0x50}, + {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a}, + {0x620, 0xff}, {0x621, 0xff}, {0x622, 0xff}, {0x623, 0xff}, + {0x624, 0xff}, {0x625, 0xff}, {0x626, 0xff}, {0x627, 0xff}, + {0x638, 0x50}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e}, + {0x63f, 0x0e}, {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00}, + {0x652, 0xc8}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43}, + {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43}, + {0x70a, 0x65}, {0x70b, 0x87}, {0x765, 0x18}, {0x76e, 0x04}, + {0xffff, 0xff}, +}; + +static const struct rtl8xxxu_reg32val rtl8723b_phy_1t_init_table[] = { + {0x800, 0x80040000}, {0x804, 0x00000003}, + {0x808, 0x0000fc00}, {0x80c, 0x0000000a}, + {0x810, 0x10001331}, {0x814, 0x020c3d10}, + {0x818, 0x02200385}, {0x81c, 0x00000000}, + {0x820, 0x01000100}, {0x824, 0x00190204}, + {0x828, 0x00000000}, {0x82c, 0x00000000}, + {0x830, 0x00000000}, {0x834, 0x00000000}, + {0x838, 0x00000000}, {0x83c, 0x00000000}, + {0x840, 0x00010000}, {0x844, 0x00000000}, + {0x848, 0x00000000}, {0x84c, 0x00000000}, + {0x850, 0x00000000}, {0x854, 0x00000000}, + {0x858, 0x569a11a9}, {0x85c, 0x01000014}, + {0x860, 0x66f60110}, {0x864, 0x061f0649}, + {0x868, 0x00000000}, {0x86c, 0x27272700}, + {0x870, 0x07000760}, {0x874, 0x25004000}, + {0x878, 0x00000808}, {0x87c, 0x00000000}, + {0x880, 0xb0000c1c}, {0x884, 0x00000001}, + {0x888, 0x00000000}, {0x88c, 0xccc000c0}, + {0x890, 0x00000800}, {0x894, 0xfffffffe}, + {0x898, 0x40302010}, {0x89c, 0x00706050}, + {0x900, 0x00000000}, {0x904, 0x00000023}, + {0x908, 0x00000000}, {0x90c, 0x81121111}, + {0x910, 0x00000002}, {0x914, 0x00000201}, + {0xa00, 0x00d047c8}, {0xa04, 0x80ff800c}, + {0xa08, 0x8c838300}, {0xa0c, 0x2e7f120f}, + {0xa10, 0x9500bb78}, {0xa14, 0x1114d028}, + {0xa18, 0x00881117}, {0xa1c, 0x89140f00}, + {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317}, + {0xa28, 0x00000204}, {0xa2c, 0x00d30000}, + {0xa70, 0x101fbf00}, {0xa74, 0x00000007}, + {0xa78, 0x00000900}, {0xa7c, 0x225b0606}, + {0xa80, 0x21806490}, {0xb2c, 0x00000000}, + {0xc00, 0x48071d40}, {0xc04, 0x03a05611}, + {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c}, + {0xc10, 0x08800000}, {0xc14, 0x40000100}, + {0xc18, 0x08800000}, {0xc1c, 0x40000100}, + {0xc20, 0x00000000}, {0xc24, 0x00000000}, + {0xc28, 0x00000000}, {0xc2c, 0x00000000}, + {0xc30, 0x69e9ac44}, {0xc34, 0x469652af}, + {0xc38, 0x49795994}, {0xc3c, 0x0a97971c}, + {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7}, + {0xc48, 0xec020107}, {0xc4c, 0x007f037f}, + {0xc50, 0x69553420}, {0xc54, 0x43bc0094}, + {0xc58, 0x00013149}, {0xc5c, 0x00250492}, + {0xc60, 0x00000000}, {0xc64, 0x7112848b}, + {0xc68, 0x47c00bff}, {0xc6c, 0x00000036}, + {0xc70, 0x2c7f000d}, {0xc74, 0x020610db}, + {0xc78, 0x0000001f}, {0xc7c, 0x00b91612}, + {0xc80, 0x390000e4}, {0xc84, 0x20f60000}, + {0xc88, 0x40000100}, {0xc8c, 0x20200000}, + {0xc90, 0x00020e1a}, {0xc94, 0x00000000}, + {0xc98, 0x00020e1a}, {0xc9c, 0x00007f7f}, + {0xca0, 0x00000000}, {0xca4, 0x000300a0}, + {0xca8, 0x00000000}, {0xcac, 0x00000000}, + {0xcb0, 0x00000000}, {0xcb4, 0x00000000}, + {0xcb8, 0x00000000}, {0xcbc, 0x28000000}, + {0xcc0, 0x00000000}, {0xcc4, 0x00000000}, + {0xcc8, 0x00000000}, {0xccc, 0x00000000}, + {0xcd0, 0x00000000}, {0xcd4, 0x00000000}, + {0xcd8, 0x64b22427}, {0xcdc, 0x00766932}, + {0xce0, 0x00222222}, {0xce4, 0x00000000}, + {0xce8, 0x37644302}, {0xcec, 0x2f97d40c}, + {0xd00, 0x00000740}, {0xd04, 0x40020401}, + {0xd08, 0x0000907f}, {0xd0c, 0x20010201}, + {0xd10, 0xa0633333}, {0xd14, 0x3333bc53}, + {0xd18, 0x7a8f5b6f}, {0xd2c, 0xcc979975}, + {0xd30, 0x00000000}, {0xd34, 0x80608000}, + {0xd38, 0x00000000}, {0xd3c, 0x00127353}, + {0xd40, 0x00000000}, {0xd44, 0x00000000}, + {0xd48, 0x00000000}, {0xd4c, 0x00000000}, + {0xd50, 0x6437140a}, {0xd54, 0x00000000}, + {0xd58, 0x00000282}, {0xd5c, 0x30032064}, + {0xd60, 0x4653de68}, {0xd64, 0x04518a3c}, + {0xd68, 0x00002101}, {0xd6c, 0x2a201c16}, + {0xd70, 0x1812362e}, {0xd74, 0x322c2220}, + {0xd78, 0x000e3c24}, {0xe00, 0x2d2d2d2d}, + {0xe04, 0x2d2d2d2d}, {0xe08, 0x0390272d}, + {0xe10, 0x2d2d2d2d}, {0xe14, 0x2d2d2d2d}, + {0xe18, 0x2d2d2d2d}, {0xe1c, 0x2d2d2d2d}, + {0xe28, 0x00000000}, {0xe30, 0x1000dc1f}, + {0xe34, 0x10008c1f}, {0xe38, 0x02140102}, + {0xe3c, 0x681604c2}, {0xe40, 0x01007c00}, + {0xe44, 0x01004800}, {0xe48, 0xfb000000}, + {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f}, + {0xe54, 0x10008c1f}, {0xe58, 0x02140102}, + {0xe5c, 0x28160d05}, {0xe60, 0x00000008}, + {0xe68, 0x001b2556}, {0xe6c, 0x00c00096}, + {0xe70, 0x00c00096}, {0xe74, 0x01000056}, + {0xe78, 0x01000014}, {0xe7c, 0x01000056}, + {0xe80, 0x01000014}, {0xe84, 0x00c00096}, + {0xe88, 0x01000056}, {0xe8c, 0x00c00096}, + {0xed0, 0x00c00096}, {0xed4, 0x00c00096}, + {0xed8, 0x00c00096}, {0xedc, 0x000000d6}, + {0xee0, 0x000000d6}, {0xeec, 0x01c00016}, + {0xf14, 0x00000003}, {0xf4c, 0x00000000}, + {0xf00, 0x00000300}, + {0x820, 0x01000100}, {0x800, 0x83040000}, + {0xffff, 0xffffffff}, +}; + +static const struct rtl8xxxu_reg32val rtl8xxx_agc_8723bu_table[] = { + {0xc78, 0xfd000001}, {0xc78, 0xfc010001}, + {0xc78, 0xfb020001}, {0xc78, 0xfa030001}, + {0xc78, 0xf9040001}, {0xc78, 0xf8050001}, + {0xc78, 0xf7060001}, {0xc78, 0xf6070001}, + {0xc78, 0xf5080001}, {0xc78, 0xf4090001}, + {0xc78, 0xf30a0001}, {0xc78, 0xf20b0001}, + {0xc78, 0xf10c0001}, {0xc78, 0xf00d0001}, + {0xc78, 0xef0e0001}, {0xc78, 0xee0f0001}, + {0xc78, 0xed100001}, {0xc78, 0xec110001}, + {0xc78, 0xeb120001}, {0xc78, 0xea130001}, + {0xc78, 0xe9140001}, {0xc78, 0xe8150001}, + {0xc78, 0xe7160001}, {0xc78, 0xe6170001}, + {0xc78, 0xe5180001}, {0xc78, 0xe4190001}, + {0xc78, 0xe31a0001}, {0xc78, 0xa51b0001}, + {0xc78, 0xa41c0001}, {0xc78, 0xa31d0001}, + {0xc78, 0x671e0001}, {0xc78, 0x661f0001}, + {0xc78, 0x65200001}, {0xc78, 0x64210001}, + {0xc78, 0x63220001}, {0xc78, 0x4a230001}, + {0xc78, 0x49240001}, {0xc78, 0x48250001}, + {0xc78, 0x47260001}, {0xc78, 0x46270001}, + {0xc78, 0x45280001}, {0xc78, 0x44290001}, + {0xc78, 0x432a0001}, {0xc78, 0x422b0001}, + {0xc78, 0x292c0001}, {0xc78, 0x282d0001}, + {0xc78, 0x272e0001}, {0xc78, 0x262f0001}, + {0xc78, 0x0a300001}, {0xc78, 0x09310001}, + {0xc78, 0x08320001}, {0xc78, 0x07330001}, + {0xc78, 0x06340001}, {0xc78, 0x05350001}, + {0xc78, 0x04360001}, {0xc78, 0x03370001}, + {0xc78, 0x02380001}, {0xc78, 0x01390001}, + {0xc78, 0x013a0001}, {0xc78, 0x013b0001}, + {0xc78, 0x013c0001}, {0xc78, 0x013d0001}, + {0xc78, 0x013e0001}, {0xc78, 0x013f0001}, + {0xc78, 0xfc400001}, {0xc78, 0xfb410001}, + {0xc78, 0xfa420001}, {0xc78, 0xf9430001}, + {0xc78, 0xf8440001}, {0xc78, 0xf7450001}, + {0xc78, 0xf6460001}, {0xc78, 0xf5470001}, + {0xc78, 0xf4480001}, {0xc78, 0xf3490001}, + {0xc78, 0xf24a0001}, {0xc78, 0xf14b0001}, + {0xc78, 0xf04c0001}, {0xc78, 0xef4d0001}, + {0xc78, 0xee4e0001}, {0xc78, 0xed4f0001}, + {0xc78, 0xec500001}, {0xc78, 0xeb510001}, + {0xc78, 0xea520001}, {0xc78, 0xe9530001}, + {0xc78, 0xe8540001}, {0xc78, 0xe7550001}, + {0xc78, 0xe6560001}, {0xc78, 0xe5570001}, + {0xc78, 0xe4580001}, {0xc78, 0xe3590001}, + {0xc78, 0xa65a0001}, {0xc78, 0xa55b0001}, + {0xc78, 0xa45c0001}, {0xc78, 0xa35d0001}, + {0xc78, 0x675e0001}, {0xc78, 0x665f0001}, + {0xc78, 0x65600001}, {0xc78, 0x64610001}, + {0xc78, 0x63620001}, {0xc78, 0x62630001}, + {0xc78, 0x61640001}, {0xc78, 0x48650001}, + {0xc78, 0x47660001}, {0xc78, 0x46670001}, + {0xc78, 0x45680001}, {0xc78, 0x44690001}, + {0xc78, 0x436a0001}, {0xc78, 0x426b0001}, + {0xc78, 0x286c0001}, {0xc78, 0x276d0001}, + {0xc78, 0x266e0001}, {0xc78, 0x256f0001}, + {0xc78, 0x24700001}, {0xc78, 0x09710001}, + {0xc78, 0x08720001}, {0xc78, 0x07730001}, + {0xc78, 0x06740001}, {0xc78, 0x05750001}, + {0xc78, 0x04760001}, {0xc78, 0x03770001}, + {0xc78, 0x02780001}, {0xc78, 0x01790001}, + {0xc78, 0x017a0001}, {0xc78, 0x017b0001}, + {0xc78, 0x017c0001}, {0xc78, 0x017d0001}, + {0xc78, 0x017e0001}, {0xc78, 0x017f0001}, + {0xc50, 0x69553422}, + {0xc50, 0x69553420}, + {0x824, 0x00390204}, + {0xffff, 0xffffffff} +}; + +static const struct rtl8xxxu_rfregval rtl8723bu_radioa_1t_init_table[] = { + {0x00, 0x00010000}, {0xb0, 0x000dffe0}, + {0xfe, 0x00000000}, {0xfe, 0x00000000}, + {0xfe, 0x00000000}, {0xb1, 0x00000018}, + {0xfe, 0x00000000}, {0xfe, 0x00000000}, + {0xfe, 0x00000000}, {0xb2, 0x00084c00}, + {0xb5, 0x0000d2cc}, {0xb6, 0x000925aa}, + {0xb7, 0x00000010}, {0xb8, 0x0000907f}, + {0x5c, 0x00000002}, {0x7c, 0x00000002}, + {0x7e, 0x00000005}, {0x8b, 0x0006fc00}, + {0xb0, 0x000ff9f0}, {0x1c, 0x000739d2}, + {0x1e, 0x00000000}, {0xdf, 0x00000780}, + {0x50, 0x00067435}, + /* + * The 8723bu vendor driver indicates that bit 8 should be set in + * 0x51 for package types TFBGA90, TFBGA80, and TFBGA79. However + * they never actually check the package type - and just default + * to not setting it. + */ + {0x51, 0x0006b04e}, + {0x52, 0x000007d2}, {0x53, 0x00000000}, + {0x54, 0x00050400}, {0x55, 0x0004026e}, + {0xdd, 0x0000004c}, {0x70, 0x00067435}, + /* + * 0x71 has same package type condition as for register 0x51 + */ + {0x71, 0x0006b04e}, + {0x72, 0x000007d2}, {0x73, 0x00000000}, + {0x74, 0x00050400}, {0x75, 0x0004026e}, + {0xef, 0x00000100}, {0x34, 0x0000add7}, + {0x35, 0x00005c00}, {0x34, 0x00009dd4}, + {0x35, 0x00005000}, {0x34, 0x00008dd1}, + {0x35, 0x00004400}, {0x34, 0x00007dce}, + {0x35, 0x00003800}, {0x34, 0x00006cd1}, + {0x35, 0x00004400}, {0x34, 0x00005cce}, + {0x35, 0x00003800}, {0x34, 0x000048ce}, + {0x35, 0x00004400}, {0x34, 0x000034ce}, + {0x35, 0x00003800}, {0x34, 0x00002451}, + {0x35, 0x00004400}, {0x34, 0x0000144e}, + {0x35, 0x00003800}, {0x34, 0x00000051}, + {0x35, 0x00004400}, {0xef, 0x00000000}, + {0xef, 0x00000100}, {0xed, 0x00000010}, + {0x44, 0x0000add7}, {0x44, 0x00009dd4}, + {0x44, 0x00008dd1}, {0x44, 0x00007dce}, + {0x44, 0x00006cc1}, {0x44, 0x00005cce}, + {0x44, 0x000044d1}, {0x44, 0x000034ce}, + {0x44, 0x00002451}, {0x44, 0x0000144e}, + {0x44, 0x00000051}, {0xef, 0x00000000}, + {0xed, 0x00000000}, {0x7f, 0x00020080}, + {0xef, 0x00002000}, {0x3b, 0x000380ef}, + {0x3b, 0x000302fe}, {0x3b, 0x00028ce6}, + {0x3b, 0x000200bc}, {0x3b, 0x000188a5}, + {0x3b, 0x00010fbc}, {0x3b, 0x00008f71}, + {0x3b, 0x00000900}, {0xef, 0x00000000}, + {0xed, 0x00000001}, {0x40, 0x000380ef}, + {0x40, 0x000302fe}, {0x40, 0x00028ce6}, + {0x40, 0x000200bc}, {0x40, 0x000188a5}, + {0x40, 0x00010fbc}, {0x40, 0x00008f71}, + {0x40, 0x00000900}, {0xed, 0x00000000}, + {0x82, 0x00080000}, {0x83, 0x00008000}, + {0x84, 0x00048d80}, {0x85, 0x00068000}, + {0xa2, 0x00080000}, {0xa3, 0x00008000}, + {0xa4, 0x00048d80}, {0xa5, 0x00068000}, + {0xed, 0x00000002}, {0xef, 0x00000002}, + {0x56, 0x00000032}, {0x76, 0x00000032}, + {0x01, 0x00000780}, + {0xff, 0xffffffff} +}; + +static int rtl8723bu_identify_chip(struct rtl8xxxu_priv *priv) +{ + struct device *dev = &priv->udev->dev; + u32 val32, sys_cfg, vendor; + int ret = 0; + + sys_cfg = rtl8xxxu_read32(priv, REG_SYS_CFG); + priv->chip_cut = u32_get_bits(sys_cfg, SYS_CFG_CHIP_VERSION_MASK); + if (sys_cfg & SYS_CFG_TRP_VAUX_EN) { + dev_info(dev, "Unsupported test chip\n"); + ret = -ENOTSUPP; + goto out; + } + + strscpy(priv->chip_name, "8723BU", sizeof(priv->chip_name)); + priv->rtl_chip = RTL8723B; + priv->rf_paths = 1; + priv->rx_paths = 1; + priv->tx_paths = 1; + + val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL); + if (val32 & MULTI_WIFI_FUNC_EN) + priv->has_wifi = 1; + if (val32 & MULTI_BT_FUNC_EN) + priv->has_bluetooth = 1; + if (val32 & MULTI_GPS_FUNC_EN) + priv->has_gps = 1; + priv->is_multi_func = 1; + + vendor = sys_cfg & SYS_CFG_VENDOR_EXT_MASK; + rtl8xxxu_identify_vendor_2bits(priv, vendor); + + val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS); + priv->rom_rev = u32_get_bits(val32, GPIO_RF_RL_ID); + + rtl8xxxu_config_endpoints_sie(priv); + + /* + * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX + */ + if (!priv->ep_tx_count) + ret = rtl8xxxu_config_endpoints_no_sie(priv); + +out: + return ret; +} + +static void rtl8723bu_write_btreg(struct rtl8xxxu_priv *priv, u8 reg, u8 data) +{ + struct h2c_cmd h2c; + int reqnum = 0; + + memset(&h2c, 0, sizeof(struct h2c_cmd)); + h2c.bt_mp_oper.cmd = H2C_8723B_BT_MP_OPER; + h2c.bt_mp_oper.operreq = 0 | (reqnum << 4); + h2c.bt_mp_oper.opcode = BT_MP_OP_WRITE_REG_VALUE; + h2c.bt_mp_oper.data = data; + rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper)); + + reqnum++; + memset(&h2c, 0, sizeof(struct h2c_cmd)); + h2c.bt_mp_oper.cmd = H2C_8723B_BT_MP_OPER; + h2c.bt_mp_oper.operreq = 0 | (reqnum << 4); + h2c.bt_mp_oper.opcode = BT_MP_OP_WRITE_REG_VALUE; + h2c.bt_mp_oper.addr = reg; + rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper)); +} + +static void rtl8723bu_reset_8051(struct rtl8xxxu_priv *priv) +{ + u8 val8; + u16 sys_func; + + val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL); + val8 &= ~BIT(1); + rtl8xxxu_write8(priv, REG_RSV_CTRL, val8); + + val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); + val8 &= ~BIT(0); + rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); + + sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC); + sys_func &= ~SYS_FUNC_CPU_ENABLE; + rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func); + + val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL); + val8 &= ~BIT(1); + rtl8xxxu_write8(priv, REG_RSV_CTRL, val8); + + val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); + val8 |= BIT(0); + rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); + + sys_func |= SYS_FUNC_CPU_ENABLE; + rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func); +} + +static void +rtl8723b_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40) +{ + u32 val32, ofdm, mcs; + u8 cck, ofdmbase, mcsbase; + int group, tx_idx; + + tx_idx = 0; + group = rtl8xxxu_gen2_channel_to_group(channel); + + cck = priv->cck_tx_power_index_B[group]; + val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32); + val32 &= 0xffff00ff; + val32 |= (cck << 8); + rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); + + val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); + val32 &= 0xff; + val32 |= ((cck << 8) | (cck << 16) | (cck << 24)); + rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); + + ofdmbase = priv->ht40_1s_tx_power_index_B[group]; + ofdmbase += priv->ofdm_tx_power_diff[tx_idx].b; + ofdm = ofdmbase | ofdmbase << 8 | ofdmbase << 16 | ofdmbase << 24; + + rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm); + rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm); + + mcsbase = priv->ht40_1s_tx_power_index_B[group]; + if (ht40) + mcsbase += priv->ht40_tx_power_diff[tx_idx++].b; + else + mcsbase += priv->ht20_tx_power_diff[tx_idx++].b; + mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24; + + rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs); + rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs); +} + +static int rtl8723bu_parse_efuse(struct rtl8xxxu_priv *priv) +{ + struct rtl8723bu_efuse *efuse = &priv->efuse_wifi.efuse8723bu; + int i; + + if (efuse->rtl_id != cpu_to_le16(0x8129)) + return -EINVAL; + + ether_addr_copy(priv->mac_addr, efuse->mac_addr); + + memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base, + sizeof(efuse->tx_power_index_A.cck_base)); + memcpy(priv->cck_tx_power_index_B, efuse->tx_power_index_B.cck_base, + sizeof(efuse->tx_power_index_B.cck_base)); + + memcpy(priv->ht40_1s_tx_power_index_A, + efuse->tx_power_index_A.ht40_base, + sizeof(efuse->tx_power_index_A.ht40_base)); + memcpy(priv->ht40_1s_tx_power_index_B, + efuse->tx_power_index_B.ht40_base, + sizeof(efuse->tx_power_index_B.ht40_base)); + + priv->ofdm_tx_power_diff[0].a = + efuse->tx_power_index_A.ht20_ofdm_1s_diff.a; + priv->ofdm_tx_power_diff[0].b = + efuse->tx_power_index_B.ht20_ofdm_1s_diff.a; + + priv->ht20_tx_power_diff[0].a = + efuse->tx_power_index_A.ht20_ofdm_1s_diff.b; + priv->ht20_tx_power_diff[0].b = + efuse->tx_power_index_B.ht20_ofdm_1s_diff.b; + + priv->ht40_tx_power_diff[0].a = 0; + priv->ht40_tx_power_diff[0].b = 0; + + for (i = 1; i < RTL8723B_TX_COUNT; i++) { + priv->ofdm_tx_power_diff[i].a = + efuse->tx_power_index_A.pwr_diff[i - 1].ofdm; + priv->ofdm_tx_power_diff[i].b = + efuse->tx_power_index_B.pwr_diff[i - 1].ofdm; + + priv->ht20_tx_power_diff[i].a = + efuse->tx_power_index_A.pwr_diff[i - 1].ht20; + priv->ht20_tx_power_diff[i].b = + efuse->tx_power_index_B.pwr_diff[i - 1].ht20; + + priv->ht40_tx_power_diff[i].a = + efuse->tx_power_index_A.pwr_diff[i - 1].ht40; + priv->ht40_tx_power_diff[i].b = + efuse->tx_power_index_B.pwr_diff[i - 1].ht40; + } + + priv->default_crystal_cap = priv->efuse_wifi.efuse8723bu.xtal_k & 0x3f; + + return 0; +} + +static int rtl8723bu_load_firmware(struct rtl8xxxu_priv *priv) +{ + const char *fw_name; + int ret; + + if (priv->enable_bluetooth) + fw_name = "rtlwifi/rtl8723bu_bt.bin"; + else + fw_name = "rtlwifi/rtl8723bu_nic.bin"; + + ret = rtl8xxxu_load_firmware(priv, fw_name); + return ret; +} + +static void rtl8723bu_init_phy_bb(struct rtl8xxxu_priv *priv) +{ + u8 val8; + u16 val16; + + val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); + val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB | SYS_FUNC_DIO_RF; + rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); + + rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00); + + /* 6. 0x1f[7:0] = 0x07 */ + val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB; + rtl8xxxu_write8(priv, REG_RF_CTRL, val8); + + /* Why? */ + rtl8xxxu_write8(priv, REG_SYS_FUNC, 0xe3); + rtl8xxxu_write8(priv, REG_AFE_XTAL_CTRL + 1, 0x80); + rtl8xxxu_init_phy_regs(priv, rtl8723b_phy_1t_init_table); + + rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8723bu_table); +} + +static int rtl8723bu_init_phy_rf(struct rtl8xxxu_priv *priv) +{ + int ret; + + ret = rtl8xxxu_init_phy_rf(priv, rtl8723bu_radioa_1t_init_table, RF_A); + /* + * PHY LCK + */ + rtl8xxxu_write_rfreg(priv, RF_A, 0xb0, 0xdfbe0); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, 0x8c01); + msleep(200); + rtl8xxxu_write_rfreg(priv, RF_A, 0xb0, 0xdffe0); + + return ret; +} + +void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv *priv) +{ + u32 val32; + + val32 = rtl8xxxu_read32(priv, REG_PAD_CTRL1); + val32 &= ~(BIT(20) | BIT(24)); + rtl8xxxu_write32(priv, REG_PAD_CTRL1, val32); + + val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG); + val32 &= ~BIT(4); + rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32); + + val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG); + val32 |= BIT(3); + rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32); + + val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); + val32 |= BIT(24); + rtl8xxxu_write32(priv, REG_LEDCFG0, val32); + + val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); + val32 &= ~BIT(23); + rtl8xxxu_write32(priv, REG_LEDCFG0, val32); + + val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER); + val32 |= (BIT(0) | BIT(1)); + rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32); + + val32 = rtl8xxxu_read32(priv, REG_RFE_CTRL_ANTA_SRC); + val32 &= 0xffffff00; + val32 |= 0x77; + rtl8xxxu_write32(priv, REG_RFE_CTRL_ANTA_SRC, val32); + + val32 = rtl8xxxu_read32(priv, REG_PWR_DATA); + val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN; + rtl8xxxu_write32(priv, REG_PWR_DATA, val32); +} + +static int rtl8723bu_iqk_path_a(struct rtl8xxxu_priv *priv) +{ + u32 reg_eac, reg_e94, reg_e9c, path_sel, val32; + int result = 0; + + path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); + + /* + * Leave IQK mode + */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); + val32 &= 0x000000ff; + rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); + + /* + * Enable path A PA in TX IQK mode + */ + val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); + val32 |= 0x80000; + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x20000); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0003f); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xc7f87); + + /* + * Tx IQK setting + */ + rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); + rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); + + /* path-A IQK setting */ + rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); + rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); + rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); + rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); + + rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821403ea); + rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000); + rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000); + rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000); + + /* LO calibration setting */ + rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911); + + /* + * Enter IQK mode + */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); + val32 &= 0x000000ff; + val32 |= 0x80800000; + rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); + + /* + * The vendor driver indicates the USB module is always using + * S0S1 path 1 for the 8723bu. This may be different for 8192eu + */ + if (priv->rf_paths > 1) + rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000); + else + rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280); + + /* + * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu. + * No trace of this in the 8192eu or 8188eu vendor drivers. + */ + rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800); + + /* One shot, path A LOK & IQK */ + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); + + mdelay(1); + + /* Restore Ant Path */ + rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel); +#ifdef RTL8723BU_BT + /* GNT_BT = 1 */ + rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800); +#endif + + /* + * Leave IQK mode + */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); + val32 &= 0x000000ff; + rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); + + /* Check failed */ + reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); + reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); + reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); + + val32 = (reg_e9c >> 16) & 0x3ff; + if (val32 & 0x200) + val32 = 0x400 - val32; + + if (!(reg_eac & BIT(28)) && + ((reg_e94 & 0x03ff0000) != 0x01420000) && + ((reg_e9c & 0x03ff0000) != 0x00420000) && + ((reg_e94 & 0x03ff0000) < 0x01100000) && + ((reg_e94 & 0x03ff0000) > 0x00f00000) && + val32 < 0xf) + result |= 0x01; + else /* If TX not OK, ignore RX */ + goto out; + +out: + return result; +} + +static int rtl8723bu_rx_iqk_path_a(struct rtl8xxxu_priv *priv) +{ + u32 reg_ea4, reg_eac, reg_e94, reg_e9c, path_sel, val32; + int result = 0; + + path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); + + /* + * Leave IQK mode + */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); + val32 &= 0x000000ff; + rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); + + /* + * Enable path A PA in TX IQK mode + */ + val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); + val32 |= 0x80000; + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7); + + /* + * Tx IQK setting + */ + rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); + rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); + + /* path-A IQK setting */ + rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); + rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); + rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); + rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); + + rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160ff0); + rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000); + rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000); + rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000); + + /* LO calibration setting */ + rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911); + + /* + * Enter IQK mode + */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); + val32 &= 0x000000ff; + val32 |= 0x80800000; + rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); + + /* + * The vendor driver indicates the USB module is always using + * S0S1 path 1 for the 8723bu. This may be different for 8192eu + */ + if (priv->rf_paths > 1) + rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000); + else + rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280); + + /* + * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu. + * No trace of this in the 8192eu or 8188eu vendor drivers. + */ + rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800); + + /* One shot, path A LOK & IQK */ + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); + + mdelay(1); + + /* Restore Ant Path */ + rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel); +#ifdef RTL8723BU_BT + /* GNT_BT = 1 */ + rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800); +#endif + + /* + * Leave IQK mode + */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); + val32 &= 0x000000ff; + rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); + + /* Check failed */ + reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); + reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); + reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); + + val32 = (reg_e9c >> 16) & 0x3ff; + if (val32 & 0x200) + val32 = 0x400 - val32; + + if (!(reg_eac & BIT(28)) && + ((reg_e94 & 0x03ff0000) != 0x01420000) && + ((reg_e9c & 0x03ff0000) != 0x00420000) && + ((reg_e94 & 0x03ff0000) < 0x01100000) && + ((reg_e94 & 0x03ff0000) > 0x00f00000) && + val32 < 0xf) + result |= 0x01; + else /* If TX not OK, ignore RX */ + goto out; + + val32 = 0x80007c00 | (reg_e94 &0x3ff0000) | + ((reg_e9c & 0x3ff0000) >> 16); + rtl8xxxu_write32(priv, REG_TX_IQK, val32); + + /* + * Modify RX IQK mode + */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); + val32 &= 0x000000ff; + rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); + val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); + val32 |= 0x80000; + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7d77); + + /* + * PA, PAD setting + */ + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0xf80); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_55, 0x4021f); + + /* + * RX IQK setting + */ + rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); + + /* path-A IQK setting */ + rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); + rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c); + rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); + rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); + + rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82110000); + rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x2816001f); + rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000); + rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000); + + /* LO calibration setting */ + rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a8d1); + + /* + * Enter IQK mode + */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); + val32 &= 0x000000ff; + val32 |= 0x80800000; + rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); + + if (priv->rf_paths > 1) + rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000); + else + rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280); + + /* + * Disable BT + */ + rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800); + + /* One shot, path A LOK & IQK */ + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); + + mdelay(1); + + /* Restore Ant Path */ + rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel); +#ifdef RTL8723BU_BT + /* GNT_BT = 1 */ + rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800); +#endif + + /* + * Leave IQK mode + */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); + val32 &= 0x000000ff; + rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); + + /* Check failed */ + reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); + reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); + + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x780); + + val32 = (reg_eac >> 16) & 0x3ff; + if (val32 & 0x200) + val32 = 0x400 - val32; + + if (!(reg_eac & BIT(27)) && + ((reg_ea4 & 0x03ff0000) != 0x01320000) && + ((reg_eac & 0x03ff0000) != 0x00360000) && + ((reg_ea4 & 0x03ff0000) < 0x01100000) && + ((reg_ea4 & 0x03ff0000) > 0x00f00000) && + val32 < 0xf) + result |= 0x02; + else /* If TX not OK, ignore RX */ + goto out; +out: + return result; +} + +static void rtl8723bu_phy_iqcalibrate(struct rtl8xxxu_priv *priv, + int result[][8], int t) +{ + struct device *dev = &priv->udev->dev; + u32 i, val32; + int path_a_ok /*, path_b_ok */; + int retry = 2; + static const u32 adda_regs[RTL8XXXU_ADDA_REGS] = { + REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH, + REG_RX_WAIT_CCA, REG_TX_CCK_RFON, + REG_TX_CCK_BBON, REG_TX_OFDM_RFON, + REG_TX_OFDM_BBON, REG_TX_TO_RX, + REG_TX_TO_TX, REG_RX_CCK, + REG_RX_OFDM, REG_RX_WAIT_RIFS, + REG_RX_TO_RX, REG_STANDBY, + REG_SLEEP, REG_PMPD_ANAEN + }; + static const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = { + REG_TXPAUSE, REG_BEACON_CTRL, + REG_BEACON_CTRL_1, REG_GPIO_MUXCFG + }; + static const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = { + REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR, + REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, + REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE, + REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE + }; + u8 xa_agc = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1) & 0xff; + u8 xb_agc = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1) & 0xff; + + /* + * Note: IQ calibration must be performed after loading + * PHY_REG.txt , and radio_a, radio_b.txt + */ + + if (t == 0) { + /* Save ADDA parameters, turn Path A ADDA on */ + rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup, + RTL8XXXU_ADDA_REGS); + rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup); + rtl8xxxu_save_regs(priv, iqk_bb_regs, + priv->bb_backup, RTL8XXXU_BB_REGS); + } + + rtl8xxxu_path_adda_on(priv, adda_regs, true); + + /* MAC settings */ + rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup); + + val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING); + val32 |= 0x0f000000; + rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32); + + rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600); + rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4); + rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000); + + /* + * RX IQ calibration setting for 8723B D cut large current issue + * when leaving IPS + */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); + val32 &= 0x000000ff; + rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); + + val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); + val32 |= 0x80000; + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); + + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7); + + val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED); + val32 |= 0x20; + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32); + + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_43, 0x60fbd); + + for (i = 0; i < retry; i++) { + path_a_ok = rtl8723bu_iqk_path_a(priv); + if (path_a_ok == 0x01) { + val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); + val32 &= 0x000000ff; + rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); + + val32 = rtl8xxxu_read32(priv, + REG_TX_POWER_BEFORE_IQK_A); + result[t][0] = (val32 >> 16) & 0x3ff; + val32 = rtl8xxxu_read32(priv, + REG_TX_POWER_AFTER_IQK_A); + result[t][1] = (val32 >> 16) & 0x3ff; + + break; + } + } + + if (!path_a_ok) + dev_dbg(dev, "%s: Path A TX IQK failed!\n", __func__); + + for (i = 0; i < retry; i++) { + path_a_ok = rtl8723bu_rx_iqk_path_a(priv); + if (path_a_ok == 0x03) { + val32 = rtl8xxxu_read32(priv, + REG_RX_POWER_BEFORE_IQK_A_2); + result[t][2] = (val32 >> 16) & 0x3ff; + val32 = rtl8xxxu_read32(priv, + REG_RX_POWER_AFTER_IQK_A_2); + result[t][3] = (val32 >> 16) & 0x3ff; + + break; + } + } + + if (!path_a_ok) + dev_dbg(dev, "%s: Path A RX IQK failed!\n", __func__); + + if (priv->tx_paths > 1) { +#if 1 + dev_warn(dev, "%s: Path B not supported\n", __func__); +#else + + /* + * Path A into standby + */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); + val32 &= 0x000000ff; + rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x10000); + + val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); + val32 &= 0x000000ff; + val32 |= 0x80800000; + rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); + + /* Turn Path B ADDA on */ + rtl8xxxu_path_adda_on(priv, adda_regs, false); + + for (i = 0; i < retry; i++) { + path_b_ok = rtl8xxxu_iqk_path_b(priv); + if (path_b_ok == 0x03) { + val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); + result[t][4] = (val32 >> 16) & 0x3ff; + val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); + result[t][5] = (val32 >> 16) & 0x3ff; + break; + } + } + + if (!path_b_ok) + dev_dbg(dev, "%s: Path B IQK failed!\n", __func__); + + for (i = 0; i < retry; i++) { + path_b_ok = rtl8723bu_rx_iqk_path_b(priv); + if (path_a_ok == 0x03) { + val32 = rtl8xxxu_read32(priv, + REG_RX_POWER_BEFORE_IQK_B_2); + result[t][6] = (val32 >> 16) & 0x3ff; + val32 = rtl8xxxu_read32(priv, + REG_RX_POWER_AFTER_IQK_B_2); + result[t][7] = (val32 >> 16) & 0x3ff; + break; + } + } + + if (!path_b_ok) + dev_dbg(dev, "%s: Path B RX IQK failed!\n", __func__); +#endif + } + + /* Back to BB mode, load original value */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); + val32 &= 0x000000ff; + rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); + + if (t) { + /* Reload ADDA power saving parameters */ + rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup, + RTL8XXXU_ADDA_REGS); + + /* Reload MAC parameters */ + rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup); + + /* Reload BB parameters */ + rtl8xxxu_restore_regs(priv, iqk_bb_regs, + priv->bb_backup, RTL8XXXU_BB_REGS); + + /* Restore RX initial gain */ + val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); + val32 &= 0xffffff00; + rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | 0x50); + rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | xa_agc); + + if (priv->tx_paths > 1) { + val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1); + val32 &= 0xffffff00; + rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1, + val32 | 0x50); + rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1, + val32 | xb_agc); + } + + /* Load 0xe30 IQC default value */ + rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00); + rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00); + } +} + +static void rtl8723bu_phy_iq_calibrate(struct rtl8xxxu_priv *priv) +{ + struct device *dev = &priv->udev->dev; + int result[4][8]; /* last is final result */ + int i, candidate; + bool path_a_ok, path_b_ok; + u32 reg_e94, reg_e9c, reg_ea4, reg_eac; + u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc; + u32 val32, bt_control; + s32 reg_tmp = 0; + bool simu; + + rtl8xxxu_gen2_prepare_calibrate(priv, 1); + + memset(result, 0, sizeof(result)); + candidate = -1; + + path_a_ok = false; + path_b_ok = false; + + bt_control = rtl8xxxu_read32(priv, REG_BT_CONTROL_8723BU); + + for (i = 0; i < 3; i++) { + rtl8723bu_phy_iqcalibrate(priv, result, i); + + if (i == 1) { + simu = rtl8xxxu_gen2_simularity_compare(priv, + result, 0, 1); + if (simu) { + candidate = 0; + break; + } + } + + if (i == 2) { + simu = rtl8xxxu_gen2_simularity_compare(priv, + result, 0, 2); + if (simu) { + candidate = 0; + break; + } + + simu = rtl8xxxu_gen2_simularity_compare(priv, + result, 1, 2); + if (simu) { + candidate = 1; + } else { + for (i = 0; i < 8; i++) + reg_tmp += result[3][i]; + + if (reg_tmp) + candidate = 3; + else + candidate = -1; + } + } + } + + for (i = 0; i < 4; i++) { + reg_e94 = result[i][0]; + reg_e9c = result[i][1]; + reg_ea4 = result[i][2]; + reg_eac = result[i][3]; + reg_eb4 = result[i][4]; + reg_ebc = result[i][5]; + reg_ec4 = result[i][6]; + reg_ecc = result[i][7]; + } + + if (candidate >= 0) { + reg_e94 = result[candidate][0]; + priv->rege94 = reg_e94; + reg_e9c = result[candidate][1]; + priv->rege9c = reg_e9c; + reg_ea4 = result[candidate][2]; + reg_eac = result[candidate][3]; + reg_eb4 = result[candidate][4]; + priv->regeb4 = reg_eb4; + reg_ebc = result[candidate][5]; + priv->regebc = reg_ebc; + reg_ec4 = result[candidate][6]; + reg_ecc = result[candidate][7]; + dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate); + dev_dbg(dev, + "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x ecc=%x\n", + __func__, reg_e94, reg_e9c, + reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc); + path_a_ok = true; + path_b_ok = true; + } else { + reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100; + reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0; + } + + if (reg_e94 && candidate >= 0) + rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result, + candidate, (reg_ea4 == 0)); + + if (priv->tx_paths > 1 && reg_eb4) + rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result, + candidate, (reg_ec4 == 0)); + + rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg, + priv->bb_recovery_backup, RTL8XXXU_BB_REGS); + + rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, bt_control); + + val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); + val32 |= 0x80000; + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x18000); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xe6177); + val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED); + val32 |= 0x20; + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32); + rtl8xxxu_write_rfreg(priv, RF_A, 0x43, 0x300bd); + + if (priv->rf_paths > 1) + dev_dbg(dev, "%s: 8723BU 2T not supported\n", __func__); + + rtl8xxxu_gen2_prepare_calibrate(priv, 0); +} + +static int rtl8723bu_active_to_emu(struct rtl8xxxu_priv *priv) +{ + u8 val8; + u16 val16; + u32 val32; + int count, ret = 0; + + /* Turn off RF */ + rtl8xxxu_write8(priv, REG_RF_CTRL, 0); + + /* Enable rising edge triggering interrupt */ + val16 = rtl8xxxu_read16(priv, REG_GPIO_INTM); + val16 &= ~GPIO_INTM_EDGE_TRIG_IRQ; + rtl8xxxu_write16(priv, REG_GPIO_INTM, val16); + + /* Release WLON reset 0x04[16]= 1*/ + val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); + val32 |= APS_FSMCO_WLON_RESET; + rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); + + /* 0x0005[1] = 1 turn off MAC by HW state machine*/ + val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); + val8 |= BIT(1); + rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); + + for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { + val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); + if ((val8 & BIT(1)) == 0) + break; + udelay(10); + } + + if (!count) { + dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n", + __func__); + ret = -EBUSY; + goto exit; + } + + /* Enable BT control XTAL setting */ + val8 = rtl8xxxu_read8(priv, REG_AFE_MISC); + val8 &= ~AFE_MISC_WL_XTAL_CTRL; + rtl8xxxu_write8(priv, REG_AFE_MISC, val8); + + /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */ + val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL); + val8 |= SYS_ISO_ANALOG_IPS; + rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8); + + /* 0x0020[0] = 0 disable LDOA12 MACRO block*/ + val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL); + val8 &= ~LDOA15_ENABLE; + rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8); + +exit: + return ret; +} + +static int rtl8723b_emu_to_active(struct rtl8xxxu_priv *priv) +{ + u8 val8; + u32 val32; + int count, ret = 0; + + /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface */ + val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL); + val8 |= LDOA15_ENABLE; + rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8); + + /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/ + val8 = rtl8xxxu_read8(priv, 0x0067); + val8 &= ~BIT(4); + rtl8xxxu_write8(priv, 0x0067, val8); + + mdelay(1); + + /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */ + val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL); + val8 &= ~SYS_ISO_ANALOG_IPS; + rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8); + + /* Disable SW LPS 0x04[10]= 0 */ + val32 = rtl8xxxu_read8(priv, REG_APS_FSMCO); + val32 &= ~APS_FSMCO_SW_LPS; + rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); + + /* Wait until 0x04[17] = 1 power ready */ + for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { + val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); + if (val32 & BIT(17)) + break; + + udelay(10); + } + + if (!count) { + ret = -EBUSY; + goto exit; + } + + /* We should be able to optimize the following three entries into one */ + + /* Release WLON reset 0x04[16]= 1*/ + val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); + val32 |= APS_FSMCO_WLON_RESET; + rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); + + /* Disable HWPDN 0x04[15]= 0*/ + val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); + val32 &= ~APS_FSMCO_HW_POWERDOWN; + rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); + + /* Disable WL suspend*/ + val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); + val32 &= ~(APS_FSMCO_HW_SUSPEND | APS_FSMCO_PCIE); + rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); + + /* Set, then poll until 0 */ + val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); + val32 |= APS_FSMCO_MAC_ENABLE; + rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); + + for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { + val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); + if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) { + ret = 0; + break; + } + udelay(10); + } + + if (!count) { + ret = -EBUSY; + goto exit; + } + + /* Enable WL control XTAL setting */ + val8 = rtl8xxxu_read8(priv, REG_AFE_MISC); + val8 |= AFE_MISC_WL_XTAL_CTRL; + rtl8xxxu_write8(priv, REG_AFE_MISC, val8); + + /* Enable falling edge triggering interrupt */ + val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 1); + val8 |= BIT(1); + rtl8xxxu_write8(priv, REG_GPIO_INTM + 1, val8); + + /* Enable GPIO9 interrupt mode */ + val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2 + 1); + val8 |= BIT(1); + rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2 + 1, val8); + + /* Enable GPIO9 input mode */ + val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2); + val8 &= ~BIT(1); + rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2, val8); + + /* Enable HSISR GPIO[C:0] interrupt */ + val8 = rtl8xxxu_read8(priv, REG_HSIMR); + val8 |= BIT(0); + rtl8xxxu_write8(priv, REG_HSIMR, val8); + + /* Enable HSISR GPIO9 interrupt */ + val8 = rtl8xxxu_read8(priv, REG_HSIMR + 2); + val8 |= BIT(1); + rtl8xxxu_write8(priv, REG_HSIMR + 2, val8); + + val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL); + val8 |= MULTI_WIFI_HW_ROF_EN; + rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL, val8); + + /* For GPIO9 internal pull high setting BIT(14) */ + val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL + 1); + val8 |= BIT(6); + rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL + 1, val8); + +exit: + return ret; +} + +static int rtl8723bu_power_on(struct rtl8xxxu_priv *priv) +{ + u8 val8; + u16 val16; + u32 val32; + int ret; + + rtl8xxxu_disabled_to_emu(priv); + + ret = rtl8723b_emu_to_active(priv); + if (ret) + goto exit; + + /* + * Enable MAC DMA/WMAC/SCHEDULE/SEC block + * Set CR bit10 to enable 32k calibration. + */ + val16 = rtl8xxxu_read16(priv, REG_CR); + val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE | + CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | + CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE | + CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE | + CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE); + rtl8xxxu_write16(priv, REG_CR, val16); + + /* + * BT coexist power on settings. This is identical for 1 and 2 + * antenna parts. + */ + rtl8xxxu_write8(priv, REG_PAD_CTRL1 + 3, 0x20); + + val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); + val16 |= SYS_FUNC_BBRSTB | SYS_FUNC_BB_GLB_RSTN; + rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); + + rtl8xxxu_write8(priv, REG_BT_CONTROL_8723BU + 1, 0x18); + rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04); + rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00); + /* Antenna inverse */ + rtl8xxxu_write8(priv, 0xfe08, 0x01); + + val16 = rtl8xxxu_read16(priv, REG_PWR_DATA); + val16 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN; + rtl8xxxu_write16(priv, REG_PWR_DATA, val16); + + val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); + val32 |= LEDCFG0_DPDT_SELECT; + rtl8xxxu_write32(priv, REG_LEDCFG0, val32); + + val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1); + val8 &= ~PAD_CTRL1_SW_DPDT_SEL_DATA; + rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8); +exit: + return ret; +} + +static void rtl8723bu_power_off(struct rtl8xxxu_priv *priv) +{ + u8 val8; + u16 val16; + + rtl8xxxu_flush_fifo(priv); + + /* + * Disable TX report timer + */ + val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL); + val8 &= ~TX_REPORT_CTRL_TIMER_ENABLE; + rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8); + + rtl8xxxu_write8(priv, REG_CR, 0x0000); + + rtl8xxxu_active_to_lps(priv); + + /* Reset Firmware if running in RAM */ + if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL) + rtl8xxxu_firmware_self_reset(priv); + + /* Reset MCU */ + val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); + val16 &= ~SYS_FUNC_CPU_ENABLE; + rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); + + /* Reset MCU ready status */ + rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00); + + rtl8723bu_active_to_emu(priv); + + val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); + val8 |= BIT(3); /* APS_FSMCO_HW_SUSPEND */ + rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); + + /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */ + val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2); + val8 |= BIT(0); + rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8); +} + +static void rtl8723b_enable_rf(struct rtl8xxxu_priv *priv) +{ + struct h2c_cmd h2c; + u32 val32; + u8 val8; + + val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA); + val32 |= (BIT(22) | BIT(23)); + rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32); + + /* + * No indication anywhere as to what 0x0790 does. The 2 antenna + * vendor code preserves bits 6-7 here. + */ + rtl8xxxu_write8(priv, 0x0790, 0x05); + /* + * 0x0778 seems to be related to enabling the number of antennas + * In the vendor driver halbtc8723b2ant_InitHwConfig() sets it + * to 0x03, while halbtc8723b1ant_InitHwConfig() sets it to 0x01 + */ + rtl8xxxu_write8(priv, 0x0778, 0x01); + + val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG); + val8 |= BIT(5); + rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8); + + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_IQADJ_G1, 0x780); + + rtl8723bu_write_btreg(priv, 0x3c, 0x15); /* BT TRx Mask on */ + + /* + * Set BT grant to low + */ + memset(&h2c, 0, sizeof(struct h2c_cmd)); + h2c.bt_grant.cmd = H2C_8723B_BT_GRANT; + h2c.bt_grant.data = 0; + rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_grant)); + + /* + * WLAN action by PTA + */ + rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x0c); + + /* + * BT select S0/S1 controlled by WiFi + */ + val8 = rtl8xxxu_read8(priv, 0x0067); + val8 |= BIT(5); + rtl8xxxu_write8(priv, 0x0067, val8); + + val32 = rtl8xxxu_read32(priv, REG_PWR_DATA); + val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN; + rtl8xxxu_write32(priv, REG_PWR_DATA, val32); + + /* + * Bits 6/7 are marked in/out ... but for what? + */ + rtl8xxxu_write8(priv, 0x0974, 0xff); + + val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER); + val32 |= (BIT(0) | BIT(1)); + rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32); + + rtl8xxxu_write8(priv, REG_RFE_CTRL_ANTA_SRC, 0x77); + + val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); + val32 &= ~BIT(24); + val32 |= BIT(23); + rtl8xxxu_write32(priv, REG_LEDCFG0, val32); + + /* + * Fix external switch Main->S1, Aux->S0 + */ + val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1); + val8 &= ~BIT(0); + rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8); + + memset(&h2c, 0, sizeof(struct h2c_cmd)); + h2c.ant_sel_rsv.cmd = H2C_8723B_ANT_SEL_RSV; + h2c.ant_sel_rsv.ant_inverse = 1; + h2c.ant_sel_rsv.int_switch_type = 0; + rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.ant_sel_rsv)); + + /* + * Different settings per different antenna position. + * Antenna Position: | Normal Inverse + * -------------------------------------------------- + * Antenna switch to BT: | 0x280, 0x00 + * Antenna switch to WiFi: | 0x0, 0x280 + * Antenna switch to PTA: | 0x200, 0x80 + */ + rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x80); + + /* + * Software control, antenna at WiFi side + */ + rtl8723bu_set_ps_tdma(priv, 0x08, 0x00, 0x00, 0x00, 0x00); + + rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555); + rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x55555555); + rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); + rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); + + memset(&h2c, 0, sizeof(struct h2c_cmd)); + h2c.bt_info.cmd = H2C_8723B_BT_INFO; + h2c.bt_info.data = BIT(0); + rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_info)); + + memset(&h2c, 0, sizeof(struct h2c_cmd)); + h2c.ignore_wlan.cmd = H2C_8723B_BT_IGNORE_WLANACT; + h2c.ignore_wlan.data = 0; + rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.ignore_wlan)); +} + +static void rtl8723bu_init_aggregation(struct rtl8xxxu_priv *priv) +{ + u32 agg_rx; + u8 agg_ctrl; + + /* + * For now simply disable RX aggregation + */ + agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL); + agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN; + + agg_rx = rtl8xxxu_read32(priv, REG_RXDMA_AGG_PG_TH); + agg_rx &= ~RXDMA_USB_AGG_ENABLE; + agg_rx &= ~0xff0f; + + rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl); + rtl8xxxu_write32(priv, REG_RXDMA_AGG_PG_TH, agg_rx); +} + +static void rtl8723bu_init_statistics(struct rtl8xxxu_priv *priv) +{ + u32 val32; + + /* Time duration for NHM unit: 4us, 0x2710=40ms */ + rtl8xxxu_write16(priv, REG_NHM_TIMER_8723B + 2, 0x2710); + rtl8xxxu_write16(priv, REG_NHM_TH9_TH10_8723B + 2, 0xffff); + rtl8xxxu_write32(priv, REG_NHM_TH3_TO_TH0_8723B, 0xffffff52); + rtl8xxxu_write32(priv, REG_NHM_TH7_TO_TH4_8723B, 0xffffffff); + /* TH8 */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); + val32 |= 0xff; + rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); + /* Enable CCK */ + val32 = rtl8xxxu_read32(priv, REG_NHM_TH9_TH10_8723B); + val32 |= BIT(8) | BIT(9) | BIT(10); + rtl8xxxu_write32(priv, REG_NHM_TH9_TH10_8723B, val32); + /* Max power amongst all RX antennas */ + val32 = rtl8xxxu_read32(priv, REG_OFDM0_FA_RSTC); + val32 |= BIT(7); + rtl8xxxu_write32(priv, REG_OFDM0_FA_RSTC, val32); +} + +static s8 rtl8723b_cck_rssi(struct rtl8xxxu_priv *priv, struct rtl8723au_phy_stats *phy_stats) +{ + u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a; + s8 rx_pwr_all = 0x00; + u8 vga_idx, lna_idx; + + lna_idx = u8_get_bits(cck_agc_rpt, CCK_AGC_RPT_LNA_IDX_MASK); + vga_idx = u8_get_bits(cck_agc_rpt, CCK_AGC_RPT_VGA_IDX_MASK); + + switch (lna_idx) { + case 6: + rx_pwr_all = -34 - (2 * vga_idx); + break; + case 4: + rx_pwr_all = -14 - (2 * vga_idx); + break; + case 1: + rx_pwr_all = 6 - (2 * vga_idx); + break; + case 0: + rx_pwr_all = 16 - (2 * vga_idx); + break; + default: + break; + } + + return rx_pwr_all; +} + +static int rtl8723bu_led_brightness_set(struct led_classdev *led_cdev, + enum led_brightness brightness) +{ + struct rtl8xxxu_priv *priv = container_of(led_cdev, + struct rtl8xxxu_priv, + led_cdev); + u8 ledcfg = rtl8xxxu_read8(priv, REG_LEDCFG2); + + ledcfg &= LEDCFG2_DPDT_SELECT; + + if (brightness == LED_OFF) + ledcfg |= LEDCFG2_SW_LED_CONTROL | LEDCFG2_SW_LED_DISABLE; + else if (brightness == LED_ON) + ledcfg |= LEDCFG2_SW_LED_CONTROL; + else if (brightness == RTL8XXXU_HW_LED_CONTROL) + ledcfg |= LEDCFG2_HW_LED_CONTROL | LEDCFG2_HW_LED_ENABLE; + + rtl8xxxu_write8(priv, REG_LEDCFG2, ledcfg); + + return 0; +} + +struct rtl8xxxu_fileops rtl8723bu_fops = { + .identify_chip = rtl8723bu_identify_chip, + .parse_efuse = rtl8723bu_parse_efuse, + .load_firmware = rtl8723bu_load_firmware, + .power_on = rtl8723bu_power_on, + .power_off = rtl8723bu_power_off, + .read_efuse = rtl8xxxu_read_efuse, + .reset_8051 = rtl8723bu_reset_8051, + .llt_init = rtl8xxxu_auto_llt_table, + .init_phy_bb = rtl8723bu_init_phy_bb, + .init_phy_rf = rtl8723bu_init_phy_rf, + .phy_init_antenna_selection = rtl8723bu_phy_init_antenna_selection, + .phy_lc_calibrate = rtl8723a_phy_lc_calibrate, + .phy_iq_calibrate = rtl8723bu_phy_iq_calibrate, + .config_channel = rtl8xxxu_gen2_config_channel, + .parse_rx_desc = rtl8xxxu_parse_rxdesc24, + .parse_phystats = rtl8723au_rx_parse_phystats, + .init_aggregation = rtl8723bu_init_aggregation, + .init_statistics = rtl8723bu_init_statistics, + .init_burst = rtl8xxxu_init_burst, + .enable_rf = rtl8723b_enable_rf, + .disable_rf = rtl8xxxu_gen2_disable_rf, + .usb_quirks = rtl8xxxu_gen2_usb_quirks, + .set_tx_power = rtl8723b_set_tx_power, + .update_rate_mask = rtl8xxxu_gen2_update_rate_mask, + .report_connect = rtl8xxxu_gen2_report_connect, + .report_rssi = rtl8xxxu_gen2_report_rssi, + .fill_txdesc = rtl8xxxu_fill_txdesc_v2, + .set_crystal_cap = rtl8723a_set_crystal_cap, + .cck_rssi = rtl8723b_cck_rssi, + .led_classdev_brightness_set = rtl8723bu_led_brightness_set, + .writeN_block_size = 1024, + .tx_desc_size = sizeof(struct rtl8xxxu_txdesc40), + .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc24), + .has_s0s1 = 1, + .has_tx_report = 1, + .gen2_thermal_meter = 1, + .needs_full_init = 1, + .init_reg_hmtfr = 1, + .ampdu_max_time = 0x5e, + .ustime_tsf_edca = 0x50, + .max_aggr_num = 0x0c14, + .supports_ap = 1, + .max_macid_num = 128, + .max_sec_cam_num = 64, + .adda_1t_init = 0x01c00014, + .adda_1t_path_on = 0x01c00014, + .adda_2t_path_on_a = 0x01c00014, + .adda_2t_path_on_b = 0x01c00014, + .trxff_boundary = 0x3f7f, + .pbp_rx = PBP_PAGE_SIZE_256, + .pbp_tx = PBP_PAGE_SIZE_256, + .mactable = rtl8723b_mac_init_table, + .total_page_num = TX_TOTAL_PAGE_NUM_8723B, + .page_num_hi = TX_PAGE_NUM_HI_PQ_8723B, + .page_num_lo = TX_PAGE_NUM_LO_PQ_8723B, + .page_num_norm = TX_PAGE_NUM_NORM_PQ_8723B, +}; diff --git a/drivers/net/wireless/realtek/rtl8xxxu/Makefile b/drivers/net/wireless/realtek/rtl8xxxu/Makefile index fa466589eccb..580a2fa675ee 100644 --- a/drivers/net/wireless/realtek/rtl8xxxu/Makefile +++ b/drivers/net/wireless/realtek/rtl8xxxu/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_RTL8XXXU) += rtl8xxxu.o -rtl8xxxu-y := rtl8xxxu_core.o rtl8xxxu_8192e.o rtl8xxxu_8723b.o \ - rtl8xxxu_8723a.o rtl8xxxu_8192c.o rtl8xxxu_8188f.o \ - rtl8xxxu_8188e.o rtl8xxxu_8710b.o rtl8xxxu_8192f.o +rtl8xxxu-y := core.o 8192e.o 8723b.o \ + 8723a.o 8192c.o 8188f.o \ + 8188e.o 8710b.o 8192f.o diff --git a/drivers/net/wireless/realtek/rtl8xxxu/core.c b/drivers/net/wireless/realtek/rtl8xxxu/core.c new file mode 100644 index 000000000000..cda05a6e4772 --- /dev/null +++ b/drivers/net/wireless/realtek/rtl8xxxu/core.c @@ -0,0 +1,8302 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * RTL8XXXU mac80211 USB driver + * + * Copyright (c) 2014 - 2017 Jes Sorensen + * + * Portions, notably calibration code: + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This driver was written as a replacement for the vendor provided + * rtl8723au driver. As the Realtek 8xxx chips are very similar in + * their programming interface, I have started adding support for + * additional 8xxx chips like the 8192cu, 8188cus, etc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "rtl8xxxu.h" +#include "regs.h" + +#define DRIVER_NAME "rtl8xxxu" + +int rtl8xxxu_debug; +static bool rtl8xxxu_ht40_2g; +static bool rtl8xxxu_dma_aggregation; +static int rtl8xxxu_dma_agg_timeout = -1; +static int rtl8xxxu_dma_agg_pages = -1; + +MODULE_AUTHOR("Jes Sorensen "); +MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver"); +MODULE_LICENSE("GPL"); +MODULE_FIRMWARE("rtlwifi/rtl8723aufw_A.bin"); +MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B.bin"); +MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B_NoBT.bin"); +MODULE_FIRMWARE("rtlwifi/rtl8188eufw.bin"); +MODULE_FIRMWARE("rtlwifi/rtl8192cufw_A.bin"); +MODULE_FIRMWARE("rtlwifi/rtl8192cufw_B.bin"); +MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin"); +MODULE_FIRMWARE("rtlwifi/rtl8192eu_nic.bin"); +MODULE_FIRMWARE("rtlwifi/rtl8723bu_nic.bin"); +MODULE_FIRMWARE("rtlwifi/rtl8723bu_bt.bin"); +MODULE_FIRMWARE("rtlwifi/rtl8188fufw.bin"); +MODULE_FIRMWARE("rtlwifi/rtl8710bufw_SMIC.bin"); +MODULE_FIRMWARE("rtlwifi/rtl8710bufw_UMC.bin"); +MODULE_FIRMWARE("rtlwifi/rtl8192fufw.bin"); + +module_param_named(debug, rtl8xxxu_debug, int, 0600); +MODULE_PARM_DESC(debug, "Set debug mask"); +module_param_named(ht40_2g, rtl8xxxu_ht40_2g, bool, 0600); +MODULE_PARM_DESC(ht40_2g, "Enable HT40 support on the 2.4GHz band"); +module_param_named(dma_aggregation, rtl8xxxu_dma_aggregation, bool, 0600); +MODULE_PARM_DESC(dma_aggregation, "Enable DMA packet aggregation"); +module_param_named(dma_agg_timeout, rtl8xxxu_dma_agg_timeout, int, 0600); +MODULE_PARM_DESC(dma_agg_timeout, "Set DMA aggregation timeout (range 1-127)"); +module_param_named(dma_agg_pages, rtl8xxxu_dma_agg_pages, int, 0600); +MODULE_PARM_DESC(dma_agg_pages, "Set DMA aggregation pages (range 1-127, 0 to disable)"); + +#define USB_VENDOR_ID_REALTEK 0x0bda +#define RTL8XXXU_RX_URBS 32 +#define RTL8XXXU_RX_URB_PENDING_WATER 8 +#define RTL8XXXU_TX_URBS 64 +#define RTL8XXXU_TX_URB_LOW_WATER 25 +#define RTL8XXXU_TX_URB_HIGH_WATER 32 + +static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv, + struct rtl8xxxu_rx_urb *rx_urb); + +static struct ieee80211_rate rtl8xxxu_rates[] = { + { .bitrate = 10, .hw_value = DESC_RATE_1M, .flags = 0 }, + { .bitrate = 20, .hw_value = DESC_RATE_2M, .flags = 0 }, + { .bitrate = 55, .hw_value = DESC_RATE_5_5M, .flags = 0 }, + { .bitrate = 110, .hw_value = DESC_RATE_11M, .flags = 0 }, + { .bitrate = 60, .hw_value = DESC_RATE_6M, .flags = 0 }, + { .bitrate = 90, .hw_value = DESC_RATE_9M, .flags = 0 }, + { .bitrate = 120, .hw_value = DESC_RATE_12M, .flags = 0 }, + { .bitrate = 180, .hw_value = DESC_RATE_18M, .flags = 0 }, + { .bitrate = 240, .hw_value = DESC_RATE_24M, .flags = 0 }, + { .bitrate = 360, .hw_value = DESC_RATE_36M, .flags = 0 }, + { .bitrate = 480, .hw_value = DESC_RATE_48M, .flags = 0 }, + { .bitrate = 540, .hw_value = DESC_RATE_54M, .flags = 0 }, +}; + +static struct ieee80211_channel rtl8xxxu_channels_2g[] = { + { .band = NL80211_BAND_2GHZ, .center_freq = 2412, + .hw_value = 1, .max_power = 30 }, + { .band = NL80211_BAND_2GHZ, .center_freq = 2417, + .hw_value = 2, .max_power = 30 }, + { .band = NL80211_BAND_2GHZ, .center_freq = 2422, + .hw_value = 3, .max_power = 30 }, + { .band = NL80211_BAND_2GHZ, .center_freq = 2427, + .hw_value = 4, .max_power = 30 }, + { .band = NL80211_BAND_2GHZ, .center_freq = 2432, + .hw_value = 5, .max_power = 30 }, + { .band = NL80211_BAND_2GHZ, .center_freq = 2437, + .hw_value = 6, .max_power = 30 }, + { .band = NL80211_BAND_2GHZ, .center_freq = 2442, + .hw_value = 7, .max_power = 30 }, + { .band = NL80211_BAND_2GHZ, .center_freq = 2447, + .hw_value = 8, .max_power = 30 }, + { .band = NL80211_BAND_2GHZ, .center_freq = 2452, + .hw_value = 9, .max_power = 30 }, + { .band = NL80211_BAND_2GHZ, .center_freq = 2457, + .hw_value = 10, .max_power = 30 }, + { .band = NL80211_BAND_2GHZ, .center_freq = 2462, + .hw_value = 11, .max_power = 30 }, + { .band = NL80211_BAND_2GHZ, .center_freq = 2467, + .hw_value = 12, .max_power = 30 }, + { .band = NL80211_BAND_2GHZ, .center_freq = 2472, + .hw_value = 13, .max_power = 30 }, + { .band = NL80211_BAND_2GHZ, .center_freq = 2484, + .hw_value = 14, .max_power = 30 } +}; + +static struct ieee80211_supported_band rtl8xxxu_supported_band = { + .channels = rtl8xxxu_channels_2g, + .n_channels = ARRAY_SIZE(rtl8xxxu_channels_2g), + .bitrates = rtl8xxxu_rates, + .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates), +}; + +static const struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = { + {0x800, 0x80040000}, {0x804, 0x00000003}, + {0x808, 0x0000fc00}, {0x80c, 0x0000000a}, + {0x810, 0x10001331}, {0x814, 0x020c3d10}, + {0x818, 0x02200385}, {0x81c, 0x00000000}, + {0x820, 0x01000100}, {0x824, 0x00390004}, + {0x828, 0x00000000}, {0x82c, 0x00000000}, + {0x830, 0x00000000}, {0x834, 0x00000000}, + {0x838, 0x00000000}, {0x83c, 0x00000000}, + {0x840, 0x00010000}, {0x844, 0x00000000}, + {0x848, 0x00000000}, {0x84c, 0x00000000}, + {0x850, 0x00000000}, {0x854, 0x00000000}, + {0x858, 0x569a569a}, {0x85c, 0x001b25a4}, + {0x860, 0x66f60110}, {0x864, 0x061f0130}, + {0x868, 0x00000000}, {0x86c, 0x32323200}, + {0x870, 0x07000760}, {0x874, 0x22004000}, + {0x878, 0x00000808}, {0x87c, 0x00000000}, + {0x880, 0xc0083070}, {0x884, 0x000004d5}, + {0x888, 0x00000000}, {0x88c, 0xccc000c0}, + {0x890, 0x00000800}, {0x894, 0xfffffffe}, + {0x898, 0x40302010}, {0x89c, 0x00706050}, + {0x900, 0x00000000}, {0x904, 0x00000023}, + {0x908, 0x00000000}, {0x90c, 0x81121111}, + {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c}, + {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f}, + {0xa10, 0x9500bb78}, {0xa14, 0x11144028}, + {0xa18, 0x00881117}, {0xa1c, 0x89140f00}, + {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317}, + {0xa28, 0x00000204}, {0xa2c, 0x00d30000}, + {0xa70, 0x101fbf00}, {0xa74, 0x00000007}, + {0xa78, 0x00000900}, + {0xc00, 0x48071d40}, {0xc04, 0x03a05611}, + {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c}, + {0xc10, 0x08800000}, {0xc14, 0x40000100}, + {0xc18, 0x08800000}, {0xc1c, 0x40000100}, + {0xc20, 0x00000000}, {0xc24, 0x00000000}, + {0xc28, 0x00000000}, {0xc2c, 0x00000000}, + {0xc30, 0x69e9ac44}, {0xc34, 0x469652af}, + {0xc38, 0x49795994}, {0xc3c, 0x0a97971c}, + {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7}, + {0xc48, 0xec020107}, {0xc4c, 0x007f037f}, + {0xc50, 0x69543420}, {0xc54, 0x43bc0094}, + {0xc58, 0x69543420}, {0xc5c, 0x433c0094}, + {0xc60, 0x00000000}, {0xc64, 0x7112848b}, + {0xc68, 0x47c00bff}, {0xc6c, 0x00000036}, + {0xc70, 0x2c7f000d}, {0xc74, 0x018610db}, + {0xc78, 0x0000001f}, {0xc7c, 0x00b91612}, + {0xc80, 0x40000100}, {0xc84, 0x20f60000}, + {0xc88, 0x40000100}, {0xc8c, 0x20200000}, + {0xc90, 0x00121820}, {0xc94, 0x00000000}, + {0xc98, 0x00121820}, {0xc9c, 0x00007f7f}, + {0xca0, 0x00000000}, {0xca4, 0x00000080}, + {0xca8, 0x00000000}, {0xcac, 0x00000000}, + {0xcb0, 0x00000000}, {0xcb4, 0x00000000}, + {0xcb8, 0x00000000}, {0xcbc, 0x28000000}, + {0xcc0, 0x00000000}, {0xcc4, 0x00000000}, + {0xcc8, 0x00000000}, {0xccc, 0x00000000}, + {0xcd0, 0x00000000}, {0xcd4, 0x00000000}, + {0xcd8, 0x64b22427}, {0xcdc, 0x00766932}, + {0xce0, 0x00222222}, {0xce4, 0x00000000}, + {0xce8, 0x37644302}, {0xcec, 0x2f97d40c}, + {0xd00, 0x00080740}, {0xd04, 0x00020401}, + {0xd08, 0x0000907f}, {0xd0c, 0x20010201}, + {0xd10, 0xa0633333}, {0xd14, 0x3333bc43}, + {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975}, + {0xd30, 0x00000000}, {0xd34, 0x80608000}, + {0xd38, 0x00000000}, {0xd3c, 0x00027293}, + {0xd40, 0x00000000}, {0xd44, 0x00000000}, + {0xd48, 0x00000000}, {0xd4c, 0x00000000}, + {0xd50, 0x6437140a}, {0xd54, 0x00000000}, + {0xd58, 0x00000000}, {0xd5c, 0x30032064}, + {0xd60, 0x4653de68}, {0xd64, 0x04518a3c}, + {0xd68, 0x00002101}, {0xd6c, 0x2a201c16}, + {0xd70, 0x1812362e}, {0xd74, 0x322c2220}, + {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a}, + {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a}, + {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a}, + {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a}, + {0xe28, 0x00000000}, {0xe30, 0x1000dc1f}, + {0xe34, 0x10008c1f}, {0xe38, 0x02140102}, + {0xe3c, 0x681604c2}, {0xe40, 0x01007c00}, + {0xe44, 0x01004800}, {0xe48, 0xfb000000}, + {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f}, + {0xe54, 0x10008c1f}, {0xe58, 0x02140102}, + {0xe5c, 0x28160d05}, {0xe60, 0x00000008}, + {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0}, + {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0}, + {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0}, + {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0}, + {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0}, + {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0}, + {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0}, + {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0}, + {0xf14, 0x00000003}, {0xf4c, 0x00000000}, + {0xf00, 0x00000300}, + {0xffff, 0xffffffff}, +}; + +static const struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = { + {0x024, 0x0011800f}, {0x028, 0x00ffdb83}, + {0x800, 0x80040002}, {0x804, 0x00000003}, + {0x808, 0x0000fc00}, {0x80c, 0x0000000a}, + {0x810, 0x10000330}, {0x814, 0x020c3d10}, + {0x818, 0x02200385}, {0x81c, 0x00000000}, + {0x820, 0x01000100}, {0x824, 0x00390004}, + {0x828, 0x01000100}, {0x82c, 0x00390004}, + {0x830, 0x27272727}, {0x834, 0x27272727}, + {0x838, 0x27272727}, {0x83c, 0x27272727}, + {0x840, 0x00010000}, {0x844, 0x00010000}, + {0x848, 0x27272727}, {0x84c, 0x27272727}, + {0x850, 0x00000000}, {0x854, 0x00000000}, + {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4}, + {0x860, 0x66e60230}, {0x864, 0x061f0130}, + {0x868, 0x27272727}, {0x86c, 0x2b2b2b27}, + {0x870, 0x07000700}, {0x874, 0x22184000}, + {0x878, 0x08080808}, {0x87c, 0x00000000}, + {0x880, 0xc0083070}, {0x884, 0x000004d5}, + {0x888, 0x00000000}, {0x88c, 0xcc0000c0}, + {0x890, 0x00000800}, {0x894, 0xfffffffe}, + {0x898, 0x40302010}, {0x89c, 0x00706050}, + {0x900, 0x00000000}, {0x904, 0x00000023}, + {0x908, 0x00000000}, {0x90c, 0x81121313}, + {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c}, + {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f}, + {0xa10, 0x9500bb78}, {0xa14, 0x11144028}, + {0xa18, 0x00881117}, {0xa1c, 0x89140f00}, + {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317}, + {0xa28, 0x00000204}, {0xa2c, 0x00d30000}, + {0xa70, 0x101fbf00}, {0xa74, 0x00000007}, + {0xc00, 0x48071d40}, {0xc04, 0x03a05633}, + {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c}, + {0xc10, 0x08800000}, {0xc14, 0x40000100}, + {0xc18, 0x08800000}, {0xc1c, 0x40000100}, + {0xc20, 0x00000000}, {0xc24, 0x00000000}, + {0xc28, 0x00000000}, {0xc2c, 0x00000000}, + {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf}, + {0xc38, 0x49795994}, {0xc3c, 0x0a97971c}, + {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7}, + {0xc48, 0xec020107}, {0xc4c, 0x007f037f}, + {0xc50, 0x69543420}, {0xc54, 0x43bc0094}, + {0xc58, 0x69543420}, {0xc5c, 0x433c0094}, + {0xc60, 0x00000000}, {0xc64, 0x5116848b}, + {0xc68, 0x47c00bff}, {0xc6c, 0x00000036}, + {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b}, + {0xc78, 0x0000001f}, {0xc7c, 0x00b99612}, + {0xc80, 0x40000100}, {0xc84, 0x20f60000}, + {0xc88, 0x40000100}, {0xc8c, 0xa0e40000}, + {0xc90, 0x00121820}, {0xc94, 0x00000000}, + {0xc98, 0x00121820}, {0xc9c, 0x00007f7f}, + {0xca0, 0x00000000}, {0xca4, 0x00000080}, + {0xca8, 0x00000000}, {0xcac, 0x00000000}, + {0xcb0, 0x00000000}, {0xcb4, 0x00000000}, + {0xcb8, 0x00000000}, {0xcbc, 0x28000000}, + {0xcc0, 0x00000000}, {0xcc4, 0x00000000}, + {0xcc8, 0x00000000}, {0xccc, 0x00000000}, + {0xcd0, 0x00000000}, {0xcd4, 0x00000000}, + {0xcd8, 0x64b22427}, {0xcdc, 0x00766932}, + {0xce0, 0x00222222}, {0xce4, 0x00000000}, + {0xce8, 0x37644302}, {0xcec, 0x2f97d40c}, + {0xd00, 0x00080740}, {0xd04, 0x00020403}, + {0xd08, 0x0000907f}, {0xd0c, 0x20010201}, + {0xd10, 0xa0633333}, {0xd14, 0x3333bc43}, + {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975}, + {0xd30, 0x00000000}, {0xd34, 0x80608000}, + {0xd38, 0x00000000}, {0xd3c, 0x00027293}, + {0xd40, 0x00000000}, {0xd44, 0x00000000}, + {0xd48, 0x00000000}, {0xd4c, 0x00000000}, + {0xd50, 0x6437140a}, {0xd54, 0x00000000}, + {0xd58, 0x00000000}, {0xd5c, 0x30032064}, + {0xd60, 0x4653de68}, {0xd64, 0x04518a3c}, + {0xd68, 0x00002101}, {0xd6c, 0x2a201c16}, + {0xd70, 0x1812362e}, {0xd74, 0x322c2220}, + {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a}, + {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a}, + {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a}, + {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a}, + {0xe28, 0x00000000}, {0xe30, 0x1000dc1f}, + {0xe34, 0x10008c1f}, {0xe38, 0x02140102}, + {0xe3c, 0x681604c2}, {0xe40, 0x01007c00}, + {0xe44, 0x01004800}, {0xe48, 0xfb000000}, + {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f}, + {0xe54, 0x10008c1f}, {0xe58, 0x02140102}, + {0xe5c, 0x28160d05}, {0xe60, 0x00000010}, + {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4}, + {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4}, + {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4}, + {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4}, + {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4}, + {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4}, + {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4}, + {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4}, + {0xf14, 0x00000003}, {0xf4c, 0x00000000}, + {0xf00, 0x00000300}, + {0xffff, 0xffffffff}, +}; + +static const struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = { + {0x024, 0x0011800f}, {0x028, 0x00ffdb83}, + {0x040, 0x000c0004}, {0x800, 0x80040000}, + {0x804, 0x00000001}, {0x808, 0x0000fc00}, + {0x80c, 0x0000000a}, {0x810, 0x10005388}, + {0x814, 0x020c3d10}, {0x818, 0x02200385}, + {0x81c, 0x00000000}, {0x820, 0x01000100}, + {0x824, 0x00390204}, {0x828, 0x00000000}, + {0x82c, 0x00000000}, {0x830, 0x00000000}, + {0x834, 0x00000000}, {0x838, 0x00000000}, + {0x83c, 0x00000000}, {0x840, 0x00010000}, + {0x844, 0x00000000}, {0x848, 0x00000000}, + {0x84c, 0x00000000}, {0x850, 0x00000000}, + {0x854, 0x00000000}, {0x858, 0x569a569a}, + {0x85c, 0x001b25a4}, {0x860, 0x66e60230}, + {0x864, 0x061f0130}, {0x868, 0x00000000}, + {0x86c, 0x20202000}, {0x870, 0x03000300}, + {0x874, 0x22004000}, {0x878, 0x00000808}, + {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070}, + {0x884, 0x000004d5}, {0x888, 0x00000000}, + {0x88c, 0xccc000c0}, {0x890, 0x00000800}, + {0x894, 0xfffffffe}, {0x898, 0x40302010}, + {0x89c, 0x00706050}, {0x900, 0x00000000}, + {0x904, 0x00000023}, {0x908, 0x00000000}, + {0x90c, 0x81121111}, {0xa00, 0x00d047c8}, + {0xa04, 0x80ff000c}, {0xa08, 0x8c838300}, + {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78}, + {0xa14, 0x11144028}, {0xa18, 0x00881117}, + {0xa1c, 0x89140f00}, {0xa20, 0x15160000}, + {0xa24, 0x070b0f12}, {0xa28, 0x00000104}, + {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00}, + {0xa74, 0x00000007}, {0xc00, 0x48071d40}, + {0xc04, 0x03a05611}, {0xc08, 0x000000e4}, + {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000}, + {0xc14, 0x40000100}, {0xc18, 0x08800000}, + {0xc1c, 0x40000100}, {0xc20, 0x00000000}, + {0xc24, 0x00000000}, {0xc28, 0x00000000}, + {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44}, + {0xc34, 0x469652cf}, {0xc38, 0x49795994}, + {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f}, + {0xc44, 0x000100b7}, {0xc48, 0xec020107}, + {0xc4c, 0x007f037f}, {0xc50, 0x6954342e}, + {0xc54, 0x43bc0094}, {0xc58, 0x6954342f}, + {0xc5c, 0x433c0094}, {0xc60, 0x00000000}, + {0xc64, 0x5116848b}, {0xc68, 0x47c00bff}, + {0xc6c, 0x00000036}, {0xc70, 0x2c46000d}, + {0xc74, 0x018610db}, {0xc78, 0x0000001f}, + {0xc7c, 0x00b91612}, {0xc80, 0x24000090}, + {0xc84, 0x20f60000}, {0xc88, 0x24000090}, + {0xc8c, 0x20200000}, {0xc90, 0x00121820}, + {0xc94, 0x00000000}, {0xc98, 0x00121820}, + {0xc9c, 0x00007f7f}, {0xca0, 0x00000000}, + {0xca4, 0x00000080}, {0xca8, 0x00000000}, + {0xcac, 0x00000000}, {0xcb0, 0x00000000}, + {0xcb4, 0x00000000}, {0xcb8, 0x00000000}, + {0xcbc, 0x28000000}, {0xcc0, 0x00000000}, + {0xcc4, 0x00000000}, {0xcc8, 0x00000000}, + {0xccc, 0x00000000}, {0xcd0, 0x00000000}, + {0xcd4, 0x00000000}, {0xcd8, 0x64b22427}, + {0xcdc, 0x00766932}, {0xce0, 0x00222222}, + {0xce4, 0x00000000}, {0xce8, 0x37644302}, + {0xcec, 0x2f97d40c}, {0xd00, 0x00080740}, + {0xd04, 0x00020401}, {0xd08, 0x0000907f}, + {0xd0c, 0x20010201}, {0xd10, 0xa0633333}, + {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b}, + {0xd2c, 0xcc979975}, {0xd30, 0x00000000}, + {0xd34, 0x80608000}, {0xd38, 0x00000000}, + {0xd3c, 0x00027293}, {0xd40, 0x00000000}, + {0xd44, 0x00000000}, {0xd48, 0x00000000}, + {0xd4c, 0x00000000}, {0xd50, 0x6437140a}, + {0xd54, 0x00000000}, {0xd58, 0x00000000}, + {0xd5c, 0x30032064}, {0xd60, 0x4653de68}, + {0xd64, 0x04518a3c}, {0xd68, 0x00002101}, + {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e}, + {0xd74, 0x322c2220}, {0xd78, 0x000e3c24}, + {0xe00, 0x24242424}, {0xe04, 0x24242424}, + {0xe08, 0x03902024}, {0xe10, 0x24242424}, + {0xe14, 0x24242424}, {0xe18, 0x24242424}, + {0xe1c, 0x24242424}, {0xe28, 0x00000000}, + {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f}, + {0xe38, 0x02140102}, {0xe3c, 0x681604c2}, + {0xe40, 0x01007c00}, {0xe44, 0x01004800}, + {0xe48, 0xfb000000}, {0xe4c, 0x000028d1}, + {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f}, + {0xe58, 0x02140102}, {0xe5c, 0x28160d05}, + {0xe60, 0x00000008}, {0xe68, 0x001b25a4}, + {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0}, + {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0}, + {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0}, + {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0}, + {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0}, + {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0}, + {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0}, + {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448}, + {0xf14, 0x00000003}, {0xf4c, 0x00000000}, + {0xf00, 0x00000300}, + {0xffff, 0xffffffff}, +}; + +static const struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = { + {0xc78, 0x7b000001}, {0xc78, 0x7b010001}, + {0xc78, 0x7b020001}, {0xc78, 0x7b030001}, + {0xc78, 0x7b040001}, {0xc78, 0x7b050001}, + {0xc78, 0x7a060001}, {0xc78, 0x79070001}, + {0xc78, 0x78080001}, {0xc78, 0x77090001}, + {0xc78, 0x760a0001}, {0xc78, 0x750b0001}, + {0xc78, 0x740c0001}, {0xc78, 0x730d0001}, + {0xc78, 0x720e0001}, {0xc78, 0x710f0001}, + {0xc78, 0x70100001}, {0xc78, 0x6f110001}, + {0xc78, 0x6e120001}, {0xc78, 0x6d130001}, + {0xc78, 0x6c140001}, {0xc78, 0x6b150001}, + {0xc78, 0x6a160001}, {0xc78, 0x69170001}, + {0xc78, 0x68180001}, {0xc78, 0x67190001}, + {0xc78, 0x661a0001}, {0xc78, 0x651b0001}, + {0xc78, 0x641c0001}, {0xc78, 0x631d0001}, + {0xc78, 0x621e0001}, {0xc78, 0x611f0001}, + {0xc78, 0x60200001}, {0xc78, 0x49210001}, + {0xc78, 0x48220001}, {0xc78, 0x47230001}, + {0xc78, 0x46240001}, {0xc78, 0x45250001}, + {0xc78, 0x44260001}, {0xc78, 0x43270001}, + {0xc78, 0x42280001}, {0xc78, 0x41290001}, + {0xc78, 0x402a0001}, {0xc78, 0x262b0001}, + {0xc78, 0x252c0001}, {0xc78, 0x242d0001}, + {0xc78, 0x232e0001}, {0xc78, 0x222f0001}, + {0xc78, 0x21300001}, {0xc78, 0x20310001}, + {0xc78, 0x06320001}, {0xc78, 0x05330001}, + {0xc78, 0x04340001}, {0xc78, 0x03350001}, + {0xc78, 0x02360001}, {0xc78, 0x01370001}, + {0xc78, 0x00380001}, {0xc78, 0x00390001}, + {0xc78, 0x003a0001}, {0xc78, 0x003b0001}, + {0xc78, 0x003c0001}, {0xc78, 0x003d0001}, + {0xc78, 0x003e0001}, {0xc78, 0x003f0001}, + {0xc78, 0x7b400001}, {0xc78, 0x7b410001}, + {0xc78, 0x7b420001}, {0xc78, 0x7b430001}, + {0xc78, 0x7b440001}, {0xc78, 0x7b450001}, + {0xc78, 0x7a460001}, {0xc78, 0x79470001}, + {0xc78, 0x78480001}, {0xc78, 0x77490001}, + {0xc78, 0x764a0001}, {0xc78, 0x754b0001}, + {0xc78, 0x744c0001}, {0xc78, 0x734d0001}, + {0xc78, 0x724e0001}, {0xc78, 0x714f0001}, + {0xc78, 0x70500001}, {0xc78, 0x6f510001}, + {0xc78, 0x6e520001}, {0xc78, 0x6d530001}, + {0xc78, 0x6c540001}, {0xc78, 0x6b550001}, + {0xc78, 0x6a560001}, {0xc78, 0x69570001}, + {0xc78, 0x68580001}, {0xc78, 0x67590001}, + {0xc78, 0x665a0001}, {0xc78, 0x655b0001}, + {0xc78, 0x645c0001}, {0xc78, 0x635d0001}, + {0xc78, 0x625e0001}, {0xc78, 0x615f0001}, + {0xc78, 0x60600001}, {0xc78, 0x49610001}, + {0xc78, 0x48620001}, {0xc78, 0x47630001}, + {0xc78, 0x46640001}, {0xc78, 0x45650001}, + {0xc78, 0x44660001}, {0xc78, 0x43670001}, + {0xc78, 0x42680001}, {0xc78, 0x41690001}, + {0xc78, 0x406a0001}, {0xc78, 0x266b0001}, + {0xc78, 0x256c0001}, {0xc78, 0x246d0001}, + {0xc78, 0x236e0001}, {0xc78, 0x226f0001}, + {0xc78, 0x21700001}, {0xc78, 0x20710001}, + {0xc78, 0x06720001}, {0xc78, 0x05730001}, + {0xc78, 0x04740001}, {0xc78, 0x03750001}, + {0xc78, 0x02760001}, {0xc78, 0x01770001}, + {0xc78, 0x00780001}, {0xc78, 0x00790001}, + {0xc78, 0x007a0001}, {0xc78, 0x007b0001}, + {0xc78, 0x007c0001}, {0xc78, 0x007d0001}, + {0xc78, 0x007e0001}, {0xc78, 0x007f0001}, + {0xc78, 0x3800001e}, {0xc78, 0x3801001e}, + {0xc78, 0x3802001e}, {0xc78, 0x3803001e}, + {0xc78, 0x3804001e}, {0xc78, 0x3805001e}, + {0xc78, 0x3806001e}, {0xc78, 0x3807001e}, + {0xc78, 0x3808001e}, {0xc78, 0x3c09001e}, + {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e}, + {0xc78, 0x440c001e}, {0xc78, 0x480d001e}, + {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e}, + {0xc78, 0x5210001e}, {0xc78, 0x5611001e}, + {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e}, + {0xc78, 0x6014001e}, {0xc78, 0x6015001e}, + {0xc78, 0x6016001e}, {0xc78, 0x6217001e}, + {0xc78, 0x6218001e}, {0xc78, 0x6219001e}, + {0xc78, 0x621a001e}, {0xc78, 0x621b001e}, + {0xc78, 0x621c001e}, {0xc78, 0x621d001e}, + {0xc78, 0x621e001e}, {0xc78, 0x621f001e}, + {0xffff, 0xffffffff} +}; + +static const struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = { + {0xc78, 0x7b000001}, {0xc78, 0x7b010001}, + {0xc78, 0x7b020001}, {0xc78, 0x7b030001}, + {0xc78, 0x7b040001}, {0xc78, 0x7b050001}, + {0xc78, 0x7b060001}, {0xc78, 0x7b070001}, + {0xc78, 0x7b080001}, {0xc78, 0x7a090001}, + {0xc78, 0x790a0001}, {0xc78, 0x780b0001}, + {0xc78, 0x770c0001}, {0xc78, 0x760d0001}, + {0xc78, 0x750e0001}, {0xc78, 0x740f0001}, + {0xc78, 0x73100001}, {0xc78, 0x72110001}, + {0xc78, 0x71120001}, {0xc78, 0x70130001}, + {0xc78, 0x6f140001}, {0xc78, 0x6e150001}, + {0xc78, 0x6d160001}, {0xc78, 0x6c170001}, + {0xc78, 0x6b180001}, {0xc78, 0x6a190001}, + {0xc78, 0x691a0001}, {0xc78, 0x681b0001}, + {0xc78, 0x671c0001}, {0xc78, 0x661d0001}, + {0xc78, 0x651e0001}, {0xc78, 0x641f0001}, + {0xc78, 0x63200001}, {0xc78, 0x62210001}, + {0xc78, 0x61220001}, {0xc78, 0x60230001}, + {0xc78, 0x46240001}, {0xc78, 0x45250001}, + {0xc78, 0x44260001}, {0xc78, 0x43270001}, + {0xc78, 0x42280001}, {0xc78, 0x41290001}, + {0xc78, 0x402a0001}, {0xc78, 0x262b0001}, + {0xc78, 0x252c0001}, {0xc78, 0x242d0001}, + {0xc78, 0x232e0001}, {0xc78, 0x222f0001}, + {0xc78, 0x21300001}, {0xc78, 0x20310001}, + {0xc78, 0x06320001}, {0xc78, 0x05330001}, + {0xc78, 0x04340001}, {0xc78, 0x03350001}, + {0xc78, 0x02360001}, {0xc78, 0x01370001}, + {0xc78, 0x00380001}, {0xc78, 0x00390001}, + {0xc78, 0x003a0001}, {0xc78, 0x003b0001}, + {0xc78, 0x003c0001}, {0xc78, 0x003d0001}, + {0xc78, 0x003e0001}, {0xc78, 0x003f0001}, + {0xc78, 0x7b400001}, {0xc78, 0x7b410001}, + {0xc78, 0x7b420001}, {0xc78, 0x7b430001}, + {0xc78, 0x7b440001}, {0xc78, 0x7b450001}, + {0xc78, 0x7b460001}, {0xc78, 0x7b470001}, + {0xc78, 0x7b480001}, {0xc78, 0x7a490001}, + {0xc78, 0x794a0001}, {0xc78, 0x784b0001}, + {0xc78, 0x774c0001}, {0xc78, 0x764d0001}, + {0xc78, 0x754e0001}, {0xc78, 0x744f0001}, + {0xc78, 0x73500001}, {0xc78, 0x72510001}, + {0xc78, 0x71520001}, {0xc78, 0x70530001}, + {0xc78, 0x6f540001}, {0xc78, 0x6e550001}, + {0xc78, 0x6d560001}, {0xc78, 0x6c570001}, + {0xc78, 0x6b580001}, {0xc78, 0x6a590001}, + {0xc78, 0x695a0001}, {0xc78, 0x685b0001}, + {0xc78, 0x675c0001}, {0xc78, 0x665d0001}, + {0xc78, 0x655e0001}, {0xc78, 0x645f0001}, + {0xc78, 0x63600001}, {0xc78, 0x62610001}, + {0xc78, 0x61620001}, {0xc78, 0x60630001}, + {0xc78, 0x46640001}, {0xc78, 0x45650001}, + {0xc78, 0x44660001}, {0xc78, 0x43670001}, + {0xc78, 0x42680001}, {0xc78, 0x41690001}, + {0xc78, 0x406a0001}, {0xc78, 0x266b0001}, + {0xc78, 0x256c0001}, {0xc78, 0x246d0001}, + {0xc78, 0x236e0001}, {0xc78, 0x226f0001}, + {0xc78, 0x21700001}, {0xc78, 0x20710001}, + {0xc78, 0x06720001}, {0xc78, 0x05730001}, + {0xc78, 0x04740001}, {0xc78, 0x03750001}, + {0xc78, 0x02760001}, {0xc78, 0x01770001}, + {0xc78, 0x00780001}, {0xc78, 0x00790001}, + {0xc78, 0x007a0001}, {0xc78, 0x007b0001}, + {0xc78, 0x007c0001}, {0xc78, 0x007d0001}, + {0xc78, 0x007e0001}, {0xc78, 0x007f0001}, + {0xc78, 0x3800001e}, {0xc78, 0x3801001e}, + {0xc78, 0x3802001e}, {0xc78, 0x3803001e}, + {0xc78, 0x3804001e}, {0xc78, 0x3805001e}, + {0xc78, 0x3806001e}, {0xc78, 0x3807001e}, + {0xc78, 0x3808001e}, {0xc78, 0x3c09001e}, + {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e}, + {0xc78, 0x440c001e}, {0xc78, 0x480d001e}, + {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e}, + {0xc78, 0x5210001e}, {0xc78, 0x5611001e}, + {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e}, + {0xc78, 0x6014001e}, {0xc78, 0x6015001e}, + {0xc78, 0x6016001e}, {0xc78, 0x6217001e}, + {0xc78, 0x6218001e}, {0xc78, 0x6219001e}, + {0xc78, 0x621a001e}, {0xc78, 0x621b001e}, + {0xc78, 0x621c001e}, {0xc78, 0x621d001e}, + {0xc78, 0x621e001e}, {0xc78, 0x621f001e}, + {0xffff, 0xffffffff} +}; + +static const struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = { + { /* RF_A */ + .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1, + .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2, + .lssiparm = REG_FPGA0_XA_LSSI_PARM, + .hspiread = REG_HSPI_XA_READBACK, + .lssiread = REG_FPGA0_XA_LSSI_READBACK, + .rf_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL, + }, + { /* RF_B */ + .hssiparm1 = REG_FPGA0_XB_HSSI_PARM1, + .hssiparm2 = REG_FPGA0_XB_HSSI_PARM2, + .lssiparm = REG_FPGA0_XB_LSSI_PARM, + .hspiread = REG_HSPI_XB_READBACK, + .lssiread = REG_FPGA0_XB_LSSI_READBACK, + .rf_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL, + }, +}; + +const u32 rtl8xxxu_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = { + REG_OFDM0_XA_RX_IQ_IMBALANCE, + REG_OFDM0_XB_RX_IQ_IMBALANCE, + REG_OFDM0_ENERGY_CCA_THRES, + REG_OFDM0_AGC_RSSI_TABLE, + REG_OFDM0_XA_TX_IQ_IMBALANCE, + REG_OFDM0_XB_TX_IQ_IMBALANCE, + REG_OFDM0_XC_TX_AFE, + REG_OFDM0_XD_TX_AFE, + REG_OFDM0_RX_IQ_EXT_ANTA +}; + +u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr) +{ + struct usb_device *udev = priv->udev; + int len; + u8 data; + + if (priv->rtl_chip == RTL8710B && addr <= 0xff) + addr |= 0x8000; + + mutex_lock(&priv->usb_buf_mutex); + len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), + REALTEK_USB_CMD_REQ, REALTEK_USB_READ, + addr, 0, &priv->usb_buf.val8, sizeof(u8), + RTW_USB_CONTROL_MSG_TIMEOUT); + data = priv->usb_buf.val8; + mutex_unlock(&priv->usb_buf_mutex); + + if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ) + dev_info(&udev->dev, "%s(%04x) = 0x%02x, len %i\n", + __func__, addr, data, len); + return data; +} + +u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr) +{ + struct usb_device *udev = priv->udev; + int len; + u16 data; + + if (priv->rtl_chip == RTL8710B && addr <= 0xff) + addr |= 0x8000; + + mutex_lock(&priv->usb_buf_mutex); + len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), + REALTEK_USB_CMD_REQ, REALTEK_USB_READ, + addr, 0, &priv->usb_buf.val16, sizeof(u16), + RTW_USB_CONTROL_MSG_TIMEOUT); + data = le16_to_cpu(priv->usb_buf.val16); + mutex_unlock(&priv->usb_buf_mutex); + + if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ) + dev_info(&udev->dev, "%s(%04x) = 0x%04x, len %i\n", + __func__, addr, data, len); + return data; +} + +u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr) +{ + struct usb_device *udev = priv->udev; + int len; + u32 data; + + if (priv->rtl_chip == RTL8710B && addr <= 0xff) + addr |= 0x8000; + + mutex_lock(&priv->usb_buf_mutex); + len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), + REALTEK_USB_CMD_REQ, REALTEK_USB_READ, + addr, 0, &priv->usb_buf.val32, sizeof(u32), + RTW_USB_CONTROL_MSG_TIMEOUT); + data = le32_to_cpu(priv->usb_buf.val32); + mutex_unlock(&priv->usb_buf_mutex); + + if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ) + dev_info(&udev->dev, "%s(%04x) = 0x%08x, len %i\n", + __func__, addr, data, len); + return data; +} + +int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val) +{ + struct usb_device *udev = priv->udev; + int ret; + + if (priv->rtl_chip == RTL8710B && addr <= 0xff) + addr |= 0x8000; + + mutex_lock(&priv->usb_buf_mutex); + priv->usb_buf.val8 = val; + ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), + REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, + addr, 0, &priv->usb_buf.val8, sizeof(u8), + RTW_USB_CONTROL_MSG_TIMEOUT); + + mutex_unlock(&priv->usb_buf_mutex); + + if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE) + dev_info(&udev->dev, "%s(%04x) = 0x%02x\n", + __func__, addr, val); + return ret; +} + +int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val) +{ + struct usb_device *udev = priv->udev; + int ret; + + if (priv->rtl_chip == RTL8710B && addr <= 0xff) + addr |= 0x8000; + + mutex_lock(&priv->usb_buf_mutex); + priv->usb_buf.val16 = cpu_to_le16(val); + ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), + REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, + addr, 0, &priv->usb_buf.val16, sizeof(u16), + RTW_USB_CONTROL_MSG_TIMEOUT); + mutex_unlock(&priv->usb_buf_mutex); + + if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE) + dev_info(&udev->dev, "%s(%04x) = 0x%04x\n", + __func__, addr, val); + return ret; +} + +int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val) +{ + struct usb_device *udev = priv->udev; + int ret; + + if (priv->rtl_chip == RTL8710B && addr <= 0xff) + addr |= 0x8000; + + mutex_lock(&priv->usb_buf_mutex); + priv->usb_buf.val32 = cpu_to_le32(val); + ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), + REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, + addr, 0, &priv->usb_buf.val32, sizeof(u32), + RTW_USB_CONTROL_MSG_TIMEOUT); + mutex_unlock(&priv->usb_buf_mutex); + + if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE) + dev_info(&udev->dev, "%s(%04x) = 0x%08x\n", + __func__, addr, val); + return ret; +} + +int rtl8xxxu_write8_set(struct rtl8xxxu_priv *priv, u16 addr, u8 bits) +{ + u8 val8; + + val8 = rtl8xxxu_read8(priv, addr); + val8 |= bits; + return rtl8xxxu_write8(priv, addr, val8); +} + +int rtl8xxxu_write8_clear(struct rtl8xxxu_priv *priv, u16 addr, u8 bits) +{ + u8 val8; + + val8 = rtl8xxxu_read8(priv, addr); + val8 &= ~bits; + return rtl8xxxu_write8(priv, addr, val8); +} + +int rtl8xxxu_write16_set(struct rtl8xxxu_priv *priv, u16 addr, u16 bits) +{ + u16 val16; + + val16 = rtl8xxxu_read16(priv, addr); + val16 |= bits; + return rtl8xxxu_write16(priv, addr, val16); +} + +int rtl8xxxu_write16_clear(struct rtl8xxxu_priv *priv, u16 addr, u16 bits) +{ + u16 val16; + + val16 = rtl8xxxu_read16(priv, addr); + val16 &= ~bits; + return rtl8xxxu_write16(priv, addr, val16); +} + +int rtl8xxxu_write32_set(struct rtl8xxxu_priv *priv, u16 addr, u32 bits) +{ + u32 val32; + + val32 = rtl8xxxu_read32(priv, addr); + val32 |= bits; + return rtl8xxxu_write32(priv, addr, val32); +} + +int rtl8xxxu_write32_clear(struct rtl8xxxu_priv *priv, u16 addr, u32 bits) +{ + u32 val32; + + val32 = rtl8xxxu_read32(priv, addr); + val32 &= ~bits; + return rtl8xxxu_write32(priv, addr, val32); +} + +int rtl8xxxu_write32_mask(struct rtl8xxxu_priv *priv, u16 addr, + u32 mask, u32 val) +{ + u32 orig, new, shift; + + shift = __ffs(mask); + + orig = rtl8xxxu_read32(priv, addr); + new = (orig & ~mask) | ((val << shift) & mask); + return rtl8xxxu_write32(priv, addr, new); +} + +int rtl8xxxu_write_rfreg_mask(struct rtl8xxxu_priv *priv, + enum rtl8xxxu_rfpath path, u8 reg, + u32 mask, u32 val) +{ + u32 orig, new, shift; + + shift = __ffs(mask); + + orig = rtl8xxxu_read_rfreg(priv, path, reg); + new = (orig & ~mask) | ((val << shift) & mask); + return rtl8xxxu_write_rfreg(priv, path, reg, new); +} + +static int +rtl8xxxu_writeN(struct rtl8xxxu_priv *priv, u16 addr, u8 *buf, u16 len) +{ + struct usb_device *udev = priv->udev; + int blocksize = priv->fops->writeN_block_size; + int ret, i, count, remainder; + + count = len / blocksize; + remainder = len % blocksize; + + for (i = 0; i < count; i++) { + ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), + REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, + addr, 0, buf, blocksize, + RTW_USB_CONTROL_MSG_TIMEOUT); + if (ret != blocksize) + goto write_error; + + addr += blocksize; + buf += blocksize; + } + + if (remainder) { + ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), + REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, + addr, 0, buf, remainder, + RTW_USB_CONTROL_MSG_TIMEOUT); + if (ret != remainder) + goto write_error; + } + + return len; + +write_error: + dev_info(&udev->dev, + "%s: Failed to write block at addr: %04x size: %04x\n", + __func__, addr, blocksize); + return -EAGAIN; +} + +u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv, + enum rtl8xxxu_rfpath path, u8 reg) +{ + u32 hssia, val32, retval; + + hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2); + if (path != RF_A) + val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2); + else + val32 = hssia; + + val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK; + val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT); + val32 |= FPGA0_HSSI_PARM2_EDGE_READ; + hssia &= ~FPGA0_HSSI_PARM2_EDGE_READ; + rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia); + + udelay(10); + + rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32); + udelay(100); + + hssia |= FPGA0_HSSI_PARM2_EDGE_READ; + rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia); + udelay(10); + + val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1); + if (val32 & FPGA0_HSSI_PARM1_PI) + retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread); + else + retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread); + + retval &= 0xfffff; + + if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_READ) + dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n", + __func__, reg, retval); + return retval; +} + +/* + * The RTL8723BU driver indicates that registers 0xb2 and 0xb6 can + * have write issues in high temperature conditions. We may have to + * retry writing them. + */ +int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv, + enum rtl8xxxu_rfpath path, u8 reg, u32 data) +{ + int ret, retval; + u32 dataaddr, val32; + + if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE) + dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n", + __func__, reg, data); + + data &= FPGA0_LSSI_PARM_DATA_MASK; + dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data; + + if (priv->rtl_chip == RTL8192E) { + val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); + val32 &= ~0x20000; + rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); + } + + /* Use XB for path B */ + ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr); + if (ret != sizeof(dataaddr)) + retval = -EIO; + else + retval = 0; + + udelay(1); + + if (priv->rtl_chip == RTL8192E) { + val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); + val32 |= 0x20000; + rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); + } + + return retval; +} + +static int +rtl8xxxu_gen1_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c, int len) +{ + struct device *dev = &priv->udev->dev; + int mbox_nr, retry, retval = 0; + int mbox_reg, mbox_ext_reg; + u8 val8; + + mutex_lock(&priv->h2c_mutex); + + mbox_nr = priv->next_mbox; + mbox_reg = REG_HMBOX_0 + (mbox_nr * 4); + mbox_ext_reg = REG_HMBOX_EXT_0 + (mbox_nr * 2); + + /* + * MBOX ready? + */ + retry = 100; + do { + val8 = rtl8xxxu_read8(priv, REG_HMTFR); + if (!(val8 & BIT(mbox_nr))) + break; + } while (retry--); + + if (!retry) { + dev_info(dev, "%s: Mailbox busy\n", __func__); + retval = -EBUSY; + goto error; + } + + /* + * Need to swap as it's being swapped again by rtl8xxxu_write16/32() + */ + if (len > sizeof(u32)) { + rtl8xxxu_write16(priv, mbox_ext_reg, le16_to_cpu(h2c->raw.ext)); + if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C) + dev_info(dev, "H2C_EXT %04x\n", + le16_to_cpu(h2c->raw.ext)); + } + rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data)); + if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C) + dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data)); + + priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX; + +error: + mutex_unlock(&priv->h2c_mutex); + return retval; +} + +int +rtl8xxxu_gen2_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c, int len) +{ + struct device *dev = &priv->udev->dev; + int mbox_nr, retry, retval = 0; + int mbox_reg, mbox_ext_reg; + u8 val8; + + mutex_lock(&priv->h2c_mutex); + + mbox_nr = priv->next_mbox; + mbox_reg = REG_HMBOX_0 + (mbox_nr * 4); + mbox_ext_reg = REG_HMBOX_EXT0_8723B + (mbox_nr * 4); + + /* + * MBOX ready? + */ + retry = 100; + do { + val8 = rtl8xxxu_read8(priv, REG_HMTFR); + if (!(val8 & BIT(mbox_nr))) + break; + } while (retry--); + + if (!retry) { + dev_info(dev, "%s: Mailbox busy\n", __func__); + retval = -EBUSY; + goto error; + } + + /* + * Need to swap as it's being swapped again by rtl8xxxu_write16/32() + */ + if (len > sizeof(u32)) { + rtl8xxxu_write32(priv, mbox_ext_reg, + le32_to_cpu(h2c->raw_wide.ext)); + if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C) + dev_info(dev, "H2C_EXT %08x\n", + le32_to_cpu(h2c->raw_wide.ext)); + } + rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data)); + if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C) + dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data)); + + priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX; + +error: + mutex_unlock(&priv->h2c_mutex); + return retval; +} + +void rtl8xxxu_gen1_enable_rf(struct rtl8xxxu_priv *priv) +{ + u8 val8; + u32 val32; + + val8 = rtl8xxxu_read8(priv, REG_SPS0_CTRL); + val8 |= BIT(0) | BIT(3); + rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8); + + val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM); + val32 &= ~(BIT(4) | BIT(5)); + val32 |= BIT(3); + if (priv->rf_paths == 2) { + val32 &= ~(BIT(20) | BIT(21)); + val32 |= BIT(19); + } + rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32); + + val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); + val32 &= ~OFDM_RF_PATH_TX_MASK; + if (priv->tx_paths == 2) + val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B; + else if (priv->rtl_chip == RTL8192C || priv->rtl_chip == RTL8191C) + val32 |= OFDM_RF_PATH_TX_B; + else + val32 |= OFDM_RF_PATH_TX_A; + rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); + + val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); + val32 &= ~FPGA_RF_MODE_JAPAN; + rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); + + if (priv->rf_paths == 2) + rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0); + else + rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0); + + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x32d95); + if (priv->rf_paths == 2) + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x32d95); + + rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); +} + +void rtl8xxxu_gen1_disable_rf(struct rtl8xxxu_priv *priv) +{ + u8 sps0; + u32 val32; + + sps0 = rtl8xxxu_read8(priv, REG_SPS0_CTRL); + + /* RF RX code for preamble power saving */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM); + val32 &= ~(BIT(3) | BIT(4) | BIT(5)); + if (priv->rf_paths == 2) + val32 &= ~(BIT(19) | BIT(20) | BIT(21)); + rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32); + + /* Disable TX for four paths */ + val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); + val32 &= ~OFDM_RF_PATH_TX_MASK; + rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); + + /* Enable power saving */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); + val32 |= FPGA_RF_MODE_JAPAN; + rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); + + /* AFE control register to power down bits [30:22] */ + if (priv->rf_paths == 2) + rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0); + else + rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0); + + /* Power down RF module */ + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0); + if (priv->rf_paths == 2) + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0); + + sps0 &= ~(BIT(0) | BIT(3)); + rtl8xxxu_write8(priv, REG_SPS0_CTRL, sps0); +} + +static void rtl8xxxu_stop_tx_beacon(struct rtl8xxxu_priv *priv) +{ + u8 val8; + + val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2); + val8 &= ~BIT(6); + rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8); + + rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x64); + val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2); + val8 &= ~BIT(0); + rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8); +} + +static void rtl8xxxu_start_tx_beacon(struct rtl8xxxu_priv *priv) +{ + u8 val8; + + val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2); + val8 |= EN_BCNQ_DL >> 16; + rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8); + + rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x80); + val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2); + val8 &= 0xF0; + rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8); +} + + +/* + * The rtl8723a has 3 channel groups for it's efuse settings. It only + * supports the 2.4GHz band, so channels 1 - 14: + * group 0: channels 1 - 3 + * group 1: channels 4 - 9 + * group 2: channels 10 - 14 + * + * Note: We index from 0 in the code + */ +static int rtl8xxxu_gen1_channel_to_group(int channel) +{ + int group; + + if (channel < 4) + group = 0; + else if (channel < 10) + group = 1; + else + group = 2; + + return group; +} + +/* + * Valid for rtl8723bu and rtl8192eu + */ +int rtl8xxxu_gen2_channel_to_group(int channel) +{ + int group; + + if (channel < 3) + group = 0; + else if (channel < 6) + group = 1; + else if (channel < 9) + group = 2; + else if (channel < 12) + group = 3; + else + group = 4; + + return group; +} + +void rtl8xxxu_gen1_config_channel(struct ieee80211_hw *hw) +{ + struct rtl8xxxu_priv *priv = hw->priv; + u32 val32, rsr; + u8 val8, opmode; + bool ht = true; + int sec_ch_above, channel; + int i; + + opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE); + rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); + channel = hw->conf.chandef.chan->hw_value; + + switch (hw->conf.chandef.width) { + case NL80211_CHAN_WIDTH_20_NOHT: + ht = false; + fallthrough; + case NL80211_CHAN_WIDTH_20: + opmode |= BW_OPMODE_20MHZ; + rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode); + + val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); + val32 &= ~FPGA_RF_MODE; + rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); + + val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); + val32 &= ~FPGA_RF_MODE; + rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); + + val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2); + val32 |= FPGA0_ANALOG2_20MHZ; + rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32); + break; + case NL80211_CHAN_WIDTH_40: + if (hw->conf.chandef.center_freq1 > + hw->conf.chandef.chan->center_freq) { + sec_ch_above = 1; + channel += 2; + } else { + sec_ch_above = 0; + channel -= 2; + } + + opmode &= ~BW_OPMODE_20MHZ; + rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode); + rsr &= ~RSR_RSC_BANDWIDTH_40M; + if (sec_ch_above) + rsr |= RSR_RSC_UPPER_SUB_CHANNEL; + else + rsr |= RSR_RSC_LOWER_SUB_CHANNEL; + rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr); + + val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); + val32 |= FPGA_RF_MODE; + rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); + + val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); + val32 |= FPGA_RF_MODE; + rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); + + /* + * Set Control channel to upper or lower. These settings + * are required only for 40MHz + */ + val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM); + val32 &= ~CCK0_SIDEBAND; + if (!sec_ch_above) + val32 |= CCK0_SIDEBAND; + rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32); + + val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF); + val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */ + if (sec_ch_above) + val32 |= OFDM_LSTF_PRIME_CH_LOW; + else + val32 |= OFDM_LSTF_PRIME_CH_HIGH; + rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); + + val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2); + val32 &= ~FPGA0_ANALOG2_20MHZ; + rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32); + + val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); + val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL); + if (sec_ch_above) + val32 |= FPGA0_PS_UPPER_CHANNEL; + else + val32 |= FPGA0_PS_LOWER_CHANNEL; + rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); + break; + + default: + break; + } + + for (i = RF_A; i < priv->rf_paths; i++) { + val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); + val32 &= ~MODE_AG_CHANNEL_MASK; + val32 |= channel; + rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); + } + + if (ht) + val8 = 0x0e; + else + val8 = 0x0a; + + rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8); + rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8); + + rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808); + rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a); + + for (i = RF_A; i < priv->rf_paths; i++) { + val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); + if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) + val32 &= ~MODE_AG_CHANNEL_20MHZ; + else + val32 |= MODE_AG_CHANNEL_20MHZ; + rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); + } +} + +void rtl8xxxu_gen2_config_channel(struct ieee80211_hw *hw) +{ + struct rtl8xxxu_priv *priv = hw->priv; + u32 val32; + u8 val8, subchannel; + u16 rf_mode_bw; + bool ht = true; + int sec_ch_above, channel; + int i; + + rf_mode_bw = rtl8xxxu_read16(priv, REG_WMAC_TRXPTCL_CTL); + rf_mode_bw &= ~WMAC_TRXPTCL_CTL_BW_MASK; + channel = hw->conf.chandef.chan->hw_value; + +/* Hack */ + subchannel = 0; + + switch (hw->conf.chandef.width) { + case NL80211_CHAN_WIDTH_20_NOHT: + ht = false; + fallthrough; + case NL80211_CHAN_WIDTH_20: + rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_20; + subchannel = 0; + + val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); + val32 &= ~FPGA_RF_MODE; + rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); + + val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); + val32 &= ~FPGA_RF_MODE; + rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); + + val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT); + val32 &= ~(BIT(30) | BIT(31)); + rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32); + + break; + case NL80211_CHAN_WIDTH_40: + rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_40; + + if (hw->conf.chandef.center_freq1 > + hw->conf.chandef.chan->center_freq) { + sec_ch_above = 1; + channel += 2; + } else { + sec_ch_above = 0; + channel -= 2; + } + + val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); + val32 |= FPGA_RF_MODE; + rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); + + val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); + val32 |= FPGA_RF_MODE; + rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); + + /* + * Set Control channel to upper or lower. These settings + * are required only for 40MHz + */ + val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM); + val32 &= ~CCK0_SIDEBAND; + if (!sec_ch_above) + val32 |= CCK0_SIDEBAND; + rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32); + + val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF); + val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */ + if (sec_ch_above) + val32 |= OFDM_LSTF_PRIME_CH_LOW; + else + val32 |= OFDM_LSTF_PRIME_CH_HIGH; + rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); + + val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); + val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL); + if (sec_ch_above) + val32 |= FPGA0_PS_UPPER_CHANNEL; + else + val32 |= FPGA0_PS_LOWER_CHANNEL; + rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); + break; + case NL80211_CHAN_WIDTH_80: + rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_80; + break; + default: + break; + } + + for (i = RF_A; i < priv->rf_paths; i++) { + val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); + val32 &= ~MODE_AG_CHANNEL_MASK; + val32 |= channel; + rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); + } + + rtl8xxxu_write16(priv, REG_WMAC_TRXPTCL_CTL, rf_mode_bw); + rtl8xxxu_write8(priv, REG_DATA_SUBCHANNEL, subchannel); + + if (ht) + val8 = 0x0e; + else + val8 = 0x0a; + + rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8); + rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8); + + rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808); + rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a); + + for (i = RF_A; i < priv->rf_paths; i++) { + val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); + val32 &= ~MODE_AG_BW_MASK; + switch(hw->conf.chandef.width) { + case NL80211_CHAN_WIDTH_80: + val32 |= MODE_AG_BW_80MHZ_8723B; + break; + case NL80211_CHAN_WIDTH_40: + val32 |= MODE_AG_BW_40MHZ_8723B; + break; + default: + val32 |= MODE_AG_BW_20MHZ_8723B; + break; + } + rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); + } +} + +void +rtl8xxxu_gen1_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40) +{ + struct rtl8xxxu_power_base *power_base = priv->power_base; + u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS]; + u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS]; + u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b; + u8 val8, base; + int group, i; + + group = rtl8xxxu_gen1_channel_to_group(channel); + + cck[0] = priv->cck_tx_power_index_A[group]; + cck[1] = priv->cck_tx_power_index_B[group]; + + if (priv->hi_pa) { + if (cck[0] > 0x20) + cck[0] = 0x20; + if (cck[1] > 0x20) + cck[1] = 0x20; + } + + ofdm[0] = priv->ht40_1s_tx_power_index_A[group]; + ofdm[1] = priv->ht40_1s_tx_power_index_B[group]; + + ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a; + ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b; + + mcsbase[0] = ofdm[0]; + mcsbase[1] = ofdm[1]; + if (!ht40) { + mcsbase[0] += priv->ht20_tx_power_index_diff[group].a; + mcsbase[1] += priv->ht20_tx_power_index_diff[group].b; + } + + if (priv->tx_paths > 1) { + if (ofdm[0] > priv->ht40_2s_tx_power_index_diff[group].a) + ofdm[0] -= priv->ht40_2s_tx_power_index_diff[group].a; + if (ofdm[1] > priv->ht40_2s_tx_power_index_diff[group].b) + ofdm[1] -= priv->ht40_2s_tx_power_index_diff[group].b; + } + + if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL) + dev_info(&priv->udev->dev, + "%s: Setting TX power CCK A: %02x, " + "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n", + __func__, cck[0], cck[1], ofdm[0], ofdm[1]); + + for (i = 0; i < RTL8723A_MAX_RF_PATHS; i++) { + if (cck[i] > RF6052_MAX_TX_PWR) + cck[i] = RF6052_MAX_TX_PWR; + if (ofdm[i] > RF6052_MAX_TX_PWR) + ofdm[i] = RF6052_MAX_TX_PWR; + } + + val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32); + val32 &= 0xffff00ff; + val32 |= (cck[0] << 8); + rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); + + val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); + val32 &= 0xff; + val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24)); + rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); + + val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); + val32 &= 0xffffff00; + val32 |= cck[1]; + rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); + + val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32); + val32 &= 0xff; + val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24)); + rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32); + + ofdm_a = ofdmbase[0] | ofdmbase[0] << 8 | + ofdmbase[0] << 16 | ofdmbase[0] << 24; + ofdm_b = ofdmbase[1] | ofdmbase[1] << 8 | + ofdmbase[1] << 16 | ofdmbase[1] << 24; + + rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, + ofdm_a + power_base->reg_0e00); + rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, + ofdm_b + power_base->reg_0830); + + rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, + ofdm_a + power_base->reg_0e04); + rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, + ofdm_b + power_base->reg_0834); + + mcs_a = mcsbase[0] | mcsbase[0] << 8 | + mcsbase[0] << 16 | mcsbase[0] << 24; + mcs_b = mcsbase[1] | mcsbase[1] << 8 | + mcsbase[1] << 16 | mcsbase[1] << 24; + + rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, + mcs_a + power_base->reg_0e10); + rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, + mcs_b + power_base->reg_083c); + + rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, + mcs_a + power_base->reg_0e14); + rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, + mcs_b + power_base->reg_0848); + + rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, + mcs_a + power_base->reg_0e18); + rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, + mcs_b + power_base->reg_084c); + + rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, + mcs_a + power_base->reg_0e1c); + val8 = u32_get_bits(mcs_a + power_base->reg_0e1c, 0xff000000); + for (i = 0; i < 3; i++) { + base = i != 2 ? 8 : 6; + val8 = max_t(int, val8 - base, 0); + rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8); + } + + rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, + mcs_b + power_base->reg_0868); + val8 = u32_get_bits(mcs_b + power_base->reg_0868, 0xff000000); + for (i = 0; i < 3; i++) { + base = i != 2 ? 8 : 6; + val8 = max_t(int, val8 - base, 0); + rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8); + } +} + +static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv *priv, + enum nl80211_iftype linktype, int port_num) +{ + u8 val8, type; + + switch (linktype) { + case NL80211_IFTYPE_UNSPECIFIED: + type = MSR_LINKTYPE_NONE; + break; + case NL80211_IFTYPE_ADHOC: + type = MSR_LINKTYPE_ADHOC; + break; + case NL80211_IFTYPE_STATION: + type = MSR_LINKTYPE_STATION; + break; + case NL80211_IFTYPE_AP: + type = MSR_LINKTYPE_AP; + break; + default: + return; + } + + switch (port_num) { + case 0: + val8 = rtl8xxxu_read8(priv, REG_MSR) & 0x0c; + val8 |= type; + break; + case 1: + val8 = rtl8xxxu_read8(priv, REG_MSR) & 0x03; + val8 |= type << 2; + break; + default: + return; + } + + rtl8xxxu_write8(priv, REG_MSR, val8); +} + +static void +rtl8xxxu_set_retry(struct rtl8xxxu_priv *priv, u16 short_retry, u16 long_retry) +{ + u16 val16; + + val16 = ((short_retry << RETRY_LIMIT_SHORT_SHIFT) & + RETRY_LIMIT_SHORT_MASK) | + ((long_retry << RETRY_LIMIT_LONG_SHIFT) & + RETRY_LIMIT_LONG_MASK); + + rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16); +} + +static void +rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv *priv, u16 cck, u16 ofdm) +{ + u16 val16; + + val16 = ((cck << SPEC_SIFS_CCK_SHIFT) & SPEC_SIFS_CCK_MASK) | + ((ofdm << SPEC_SIFS_OFDM_SHIFT) & SPEC_SIFS_OFDM_MASK); + + rtl8xxxu_write16(priv, REG_SPEC_SIFS, val16); +} + +static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv) +{ + struct device *dev = &priv->udev->dev; + char cut = 'A' + priv->chip_cut; + + dev_info(dev, + "RTL%s rev %c (%s) romver %d, %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n", + priv->chip_name, cut, priv->chip_vendor, priv->rom_rev, + priv->tx_paths, priv->rx_paths, priv->ep_tx_count, + priv->has_wifi, priv->has_bluetooth, priv->has_gps, + priv->hi_pa); + + dev_info(dev, "RTL%s MAC: %pM\n", priv->chip_name, priv->mac_addr); +} + +void rtl8xxxu_identify_vendor_1bit(struct rtl8xxxu_priv *priv, u32 vendor) +{ + if (vendor) { + strscpy(priv->chip_vendor, "UMC", sizeof(priv->chip_vendor)); + priv->vendor_umc = 1; + } else { + strscpy(priv->chip_vendor, "TSMC", sizeof(priv->chip_vendor)); + } +} + +void rtl8xxxu_identify_vendor_2bits(struct rtl8xxxu_priv *priv, u32 vendor) +{ + switch (vendor) { + case SYS_CFG_VENDOR_ID_TSMC: + strscpy(priv->chip_vendor, "TSMC", sizeof(priv->chip_vendor)); + break; + case SYS_CFG_VENDOR_ID_SMIC: + strscpy(priv->chip_vendor, "SMIC", sizeof(priv->chip_vendor)); + priv->vendor_smic = 1; + break; + case SYS_CFG_VENDOR_ID_UMC: + strscpy(priv->chip_vendor, "UMC", sizeof(priv->chip_vendor)); + priv->vendor_umc = 1; + break; + default: + strscpy(priv->chip_vendor, "unknown", sizeof(priv->chip_vendor)); + } +} + +void rtl8xxxu_config_endpoints_sie(struct rtl8xxxu_priv *priv) +{ + u16 val16; + + val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX); + + if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) { + priv->ep_tx_high_queue = 1; + priv->ep_tx_count++; + } + + if (val16 & NORMAL_SIE_EP_TX_NORMAL_MASK) { + priv->ep_tx_normal_queue = 1; + priv->ep_tx_count++; + } + + if (val16 & NORMAL_SIE_EP_TX_LOW_MASK) { + priv->ep_tx_low_queue = 1; + priv->ep_tx_count++; + } +} + +int rtl8xxxu_config_endpoints_no_sie(struct rtl8xxxu_priv *priv) +{ + struct device *dev = &priv->udev->dev; + + switch (priv->nr_out_eps) { + case 6: + case 5: + case 4: + case 3: + priv->ep_tx_low_queue = 1; + priv->ep_tx_count++; + fallthrough; + case 2: + priv->ep_tx_normal_queue = 1; + priv->ep_tx_count++; + fallthrough; + case 1: + priv->ep_tx_high_queue = 1; + priv->ep_tx_count++; + break; + default: + dev_info(dev, "Unsupported USB TX end-points\n"); + return -ENOTSUPP; + } + + return 0; +} + +int +rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data) +{ + int i; + u8 val8; + u32 val32; + + /* Write Address */ + rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 1, offset & 0xff); + val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 2); + val8 &= 0xfc; + val8 |= (offset >> 8) & 0x03; + rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 2, val8); + + val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 3); + rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 3, val8 & 0x7f); + + /* Poll for data read */ + val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL); + for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) { + val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL); + if (val32 & BIT(31)) + break; + } + + if (i == RTL8XXXU_MAX_REG_POLL) + return -EIO; + + udelay(50); + val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL); + + *data = val32 & 0xff; + return 0; +} + +int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv) +{ + struct device *dev = &priv->udev->dev; + int i, ret = 0; + u8 val8, word_mask, header, extheader; + u16 val16, efuse_addr, offset; + u32 val32; + + val16 = rtl8xxxu_read16(priv, REG_9346CR); + if (val16 & EEPROM_ENABLE) + priv->has_eeprom = 1; + if (val16 & EEPROM_BOOT) + priv->boot_eeprom = 1; + + if (priv->is_multi_func) { + val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST); + val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT; + rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32); + } + + dev_dbg(dev, "Booting from %s\n", + priv->boot_eeprom ? "EEPROM" : "EFUSE"); + + rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_ENABLE); + + /* 1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */ + val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL); + if (!(val16 & SYS_ISO_PWC_EV12V)) { + val16 |= SYS_ISO_PWC_EV12V; + rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16); + } + /* Reset: 0x0000[28], default valid */ + val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); + if (!(val16 & SYS_FUNC_ELDR)) { + val16 |= SYS_FUNC_ELDR; + rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); + } + + /* + * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid + */ + val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR); + if (!(val16 & SYS_CLK_LOADER_ENABLE) || !(val16 & SYS_CLK_ANA8M)) { + val16 |= (SYS_CLK_LOADER_ENABLE | SYS_CLK_ANA8M); + rtl8xxxu_write16(priv, REG_SYS_CLKR, val16); + } + + /* Default value is 0xff */ + memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN); + + efuse_addr = 0; + while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) { + u16 map_addr; + + ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &header); + if (ret || header == 0xff) + goto exit; + + if ((header & 0x1f) == 0x0f) { /* extended header */ + offset = (header & 0xe0) >> 5; + + ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, + &extheader); + if (ret) + goto exit; + /* All words disabled */ + if ((extheader & 0x0f) == 0x0f) + continue; + + offset |= ((extheader & 0xf0) >> 1); + word_mask = extheader & 0x0f; + } else { + offset = (header >> 4) & 0x0f; + word_mask = header & 0x0f; + } + + /* Get word enable value from PG header */ + + /* We have 8 bits to indicate validity */ + map_addr = offset * 8; + for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) { + /* Check word enable condition in the section */ + if (word_mask & BIT(i)) { + map_addr += 2; + continue; + } + + ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8); + if (ret) + goto exit; + if (map_addr >= EFUSE_MAP_LEN - 1) { + dev_warn(dev, "%s: Illegal map_addr (%04x), " + "efuse corrupt!\n", + __func__, map_addr); + ret = -EINVAL; + goto exit; + } + priv->efuse_wifi.raw[map_addr++] = val8; + + ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8); + if (ret) + goto exit; + priv->efuse_wifi.raw[map_addr++] = val8; + } + } + +exit: + rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_DISABLE); + + return ret; +} + +static void rtl8xxxu_dump_efuse(struct rtl8xxxu_priv *priv) +{ + dev_info(&priv->udev->dev, + "Dumping efuse for RTL%s (0x%02x bytes):\n", + priv->chip_name, EFUSE_MAP_LEN); + + print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1, + priv->efuse_wifi.raw, EFUSE_MAP_LEN, true); +} + +void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv) +{ + u8 val8; + u16 sys_func; + + val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); + val8 &= ~BIT(0); + rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); + + sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC); + sys_func &= ~SYS_FUNC_CPU_ENABLE; + rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func); + + val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); + val8 |= BIT(0); + rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); + + sys_func |= SYS_FUNC_CPU_ENABLE; + rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func); +} + +static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv) +{ + struct device *dev = &priv->udev->dev; + u16 reg_mcu_fw_dl; + int ret = 0, i; + u32 val32; + + if (priv->rtl_chip == RTL8710B) + reg_mcu_fw_dl = REG_8051FW_CTRL_V1_8710B; + else + reg_mcu_fw_dl = REG_MCU_FW_DL; + + /* Poll checksum report */ + for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) { + val32 = rtl8xxxu_read32(priv, reg_mcu_fw_dl); + if (val32 & MCU_FW_DL_CSUM_REPORT) + break; + } + + if (i == RTL8XXXU_FIRMWARE_POLL_MAX) { + dev_warn(dev, "Firmware checksum poll timed out\n"); + ret = -EAGAIN; + goto exit; + } + + val32 = rtl8xxxu_read32(priv, reg_mcu_fw_dl); + val32 |= MCU_FW_DL_READY; + val32 &= ~MCU_WINT_INIT_READY; + rtl8xxxu_write32(priv, reg_mcu_fw_dl, val32); + + /* + * Reset the 8051 in order for the firmware to start running, + * otherwise it won't come up on the 8192eu + */ + priv->fops->reset_8051(priv); + + /* Wait for firmware to become ready */ + for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) { + val32 = rtl8xxxu_read32(priv, reg_mcu_fw_dl); + if (val32 & MCU_WINT_INIT_READY) + break; + + udelay(100); + } + + if (i == RTL8XXXU_FIRMWARE_POLL_MAX) { + dev_warn(dev, "Firmware failed to start\n"); + ret = -EAGAIN; + goto exit; + } + + /* + * Init H2C command + */ + if (priv->fops->init_reg_hmtfr) + rtl8xxxu_write8(priv, REG_HMTFR, 0x0f); +exit: + return ret; +} + +static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv) +{ + int pages, remainder, i, ret; + u16 reg_fw_start_address; + u16 reg_mcu_fw_dl; + u8 val8; + u16 val16; + u32 val32; + u8 *fwptr; + + if (priv->rtl_chip == RTL8192F) + reg_fw_start_address = REG_FW_START_ADDRESS_8192F; + else + reg_fw_start_address = REG_FW_START_ADDRESS; + + if (priv->rtl_chip == RTL8710B) { + reg_mcu_fw_dl = REG_8051FW_CTRL_V1_8710B; + } else { + reg_mcu_fw_dl = REG_MCU_FW_DL; + + val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC + 1); + val8 |= 4; + rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8); + + /* 8051 enable */ + val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); + val16 |= SYS_FUNC_CPU_ENABLE; + rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); + } + + val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl); + if (val8 & MCU_FW_RAM_SEL) { + dev_info(&priv->udev->dev, + "Firmware is already running, resetting the MCU.\n"); + rtl8xxxu_write8(priv, reg_mcu_fw_dl, 0x00); + priv->fops->reset_8051(priv); + } + + /* MCU firmware download enable */ + val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl); + val8 |= MCU_FW_DL_ENABLE; + rtl8xxxu_write8(priv, reg_mcu_fw_dl, val8); + + /* 8051 reset */ + val32 = rtl8xxxu_read32(priv, reg_mcu_fw_dl); + val32 &= ~BIT(19); + rtl8xxxu_write32(priv, reg_mcu_fw_dl, val32); + + if (priv->rtl_chip == RTL8710B) { + /* We must set 0x8090[8]=1 before download FW. */ + val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl + 1); + val8 |= BIT(0); + rtl8xxxu_write8(priv, reg_mcu_fw_dl + 1, val8); + } + + /* Reset firmware download checksum */ + val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl); + val8 |= MCU_FW_DL_CSUM_REPORT; + rtl8xxxu_write8(priv, reg_mcu_fw_dl, val8); + + pages = priv->fw_size / RTL_FW_PAGE_SIZE; + remainder = priv->fw_size % RTL_FW_PAGE_SIZE; + + fwptr = priv->fw_data->data; + + for (i = 0; i < pages; i++) { + val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl + 2) & 0xF8; + val8 |= i; + rtl8xxxu_write8(priv, reg_mcu_fw_dl + 2, val8); + + ret = rtl8xxxu_writeN(priv, reg_fw_start_address, + fwptr, RTL_FW_PAGE_SIZE); + if (ret != RTL_FW_PAGE_SIZE) { + ret = -EAGAIN; + goto fw_abort; + } + + fwptr += RTL_FW_PAGE_SIZE; + } + + if (remainder) { + val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl + 2) & 0xF8; + val8 |= i; + rtl8xxxu_write8(priv, reg_mcu_fw_dl + 2, val8); + ret = rtl8xxxu_writeN(priv, reg_fw_start_address, + fwptr, remainder); + if (ret != remainder) { + ret = -EAGAIN; + goto fw_abort; + } + } + + ret = 0; +fw_abort: + /* MCU firmware download disable */ + val16 = rtl8xxxu_read16(priv, reg_mcu_fw_dl); + val16 &= ~MCU_FW_DL_ENABLE; + rtl8xxxu_write16(priv, reg_mcu_fw_dl, val16); + + return ret; +} + +int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, const char *fw_name) +{ + struct device *dev = &priv->udev->dev; + const struct firmware *fw; + int ret = 0; + u16 signature; + + dev_info(dev, "%s: Loading firmware %s\n", DRIVER_NAME, fw_name); + if (request_firmware(&fw, fw_name, &priv->udev->dev)) { + dev_warn(dev, "request_firmware(%s) failed\n", fw_name); + ret = -EAGAIN; + goto exit; + } + if (!fw) { + dev_warn(dev, "Firmware data not available\n"); + ret = -EINVAL; + goto exit; + } + + priv->fw_data = kmemdup(fw->data, fw->size, GFP_KERNEL); + if (!priv->fw_data) { + ret = -ENOMEM; + goto exit; + } + priv->fw_size = fw->size - sizeof(struct rtl8xxxu_firmware_header); + + signature = le16_to_cpu(priv->fw_data->signature); + switch (signature & 0xfff0) { + case 0x92e0: + case 0x92c0: + case 0x88e0: + case 0x88c0: + case 0x5300: + case 0x2300: + case 0x88f0: + case 0x10b0: + case 0x92f0: + break; + default: + ret = -EINVAL; + dev_warn(dev, "%s: Invalid firmware signature: 0x%04x\n", + __func__, signature); + } + + dev_info(dev, "Firmware revision %i.%i (signature 0x%04x)\n", + le16_to_cpu(priv->fw_data->major_version), + priv->fw_data->minor_version, signature); + +exit: + release_firmware(fw); + return ret; +} + +void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv) +{ + u16 val16; + int i = 100; + + /* Inform 8051 to perform reset */ + rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20); + + for (i = 100; i > 0; i--) { + val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); + + if (!(val16 & SYS_FUNC_CPU_ENABLE)) { + dev_dbg(&priv->udev->dev, + "%s: Firmware self reset success!\n", __func__); + break; + } + udelay(50); + } + + if (!i) { + /* Force firmware reset */ + val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); + val16 &= ~SYS_FUNC_CPU_ENABLE; + rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); + } +} + +static int +rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv) +{ + const struct rtl8xxxu_reg8val *array = priv->fops->mactable; + int i, ret; + u16 reg; + u8 val; + + for (i = 0; ; i++) { + reg = array[i].reg; + val = array[i].val; + + if (reg == 0xffff && val == 0xff) + break; + + ret = rtl8xxxu_write8(priv, reg, val); + if (ret != 1) { + dev_warn(&priv->udev->dev, + "Failed to initialize MAC " + "(reg: %04x, val %02x)\n", reg, val); + return -EAGAIN; + } + } + + switch (priv->rtl_chip) { + case RTL8188C: + case RTL8188R: + case RTL8191C: + case RTL8192C: + case RTL8723A: + rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a); + break; + case RTL8188E: + rtl8xxxu_write16(priv, REG_MAX_AGGR_NUM, 0x0707); + break; + default: + break; + } + + return 0; +} + +int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv, + const struct rtl8xxxu_reg32val *array) +{ + int i, ret; + u16 reg; + u32 val; + + for (i = 0; ; i++) { + reg = array[i].reg; + val = array[i].val; + + if (reg == 0xffff && val == 0xffffffff) + break; + + ret = rtl8xxxu_write32(priv, reg, val); + if (ret != sizeof(val)) { + dev_warn(&priv->udev->dev, + "Failed to initialize PHY\n"); + return -EAGAIN; + } + udelay(1); + } + + return 0; +} + +void rtl8xxxu_gen1_init_phy_bb(struct rtl8xxxu_priv *priv) +{ + u8 val8, ldoa15, ldov12d, lpldo, ldohci12; + u16 val16; + u32 val32; + + val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL); + udelay(2); + val8 |= AFE_PLL_320_ENABLE; + rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8); + udelay(2); + + rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL + 1, 0xff); + udelay(2); + + val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); + val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB; + rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); + + val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL); + val32 &= ~AFE_XTAL_RF_GATE; + if (priv->has_bluetooth) + val32 &= ~AFE_XTAL_BT_GATE; + rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32); + + /* 6. 0x1f[7:0] = 0x07 */ + val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB; + rtl8xxxu_write8(priv, REG_RF_CTRL, val8); + + if (priv->hi_pa) + rtl8xxxu_init_phy_regs(priv, rtl8188ru_phy_1t_highpa_table); + else if (priv->tx_paths == 2) + rtl8xxxu_init_phy_regs(priv, rtl8192cu_phy_2t_init_table); + else + rtl8xxxu_init_phy_regs(priv, rtl8723a_phy_1t_init_table); + + if (priv->rtl_chip == RTL8188R && priv->hi_pa && + priv->vendor_umc && priv->chip_cut == 1) + rtl8xxxu_write8(priv, REG_OFDM0_AGC_PARM1 + 2, 0x50); + + if (priv->hi_pa) + rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_highpa_table); + else + rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_standard_table); + + ldoa15 = LDOA15_ENABLE | LDOA15_OBUF; + ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT); + ldohci12 = 0x57; + lpldo = 1; + val32 = (lpldo << 24) | (ldohci12 << 16) | (ldov12d << 8) | ldoa15; + rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32); +} + +/* + * Most of this is black magic retrieved from the old rtl8723au driver + */ +static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv) +{ + u32 val32; + + priv->fops->init_phy_bb(priv); + + if (priv->tx_paths == 1 && priv->rx_paths == 2) { + /* + * For 1T2R boards, patch the registers. + * + * It looks like 8191/2 1T2R boards use path B for TX + */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO); + val32 &= ~(BIT(0) | BIT(1)); + val32 |= BIT(1); + rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32); + + val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO); + val32 &= ~0x300033; + val32 |= 0x200022; + rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32); + + val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING); + val32 &= ~CCK0_AFE_RX_MASK; + val32 &= 0x00ffffff; + val32 |= 0x40000000; + val32 |= CCK0_AFE_RX_ANT_B; + rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32); + + val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); + val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK); + val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B | + OFDM_RF_PATH_TX_B); + rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); + + val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1); + val32 &= ~(BIT(4) | BIT(5)); + val32 |= BIT(4); + rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32); + + val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON); + val32 &= ~(BIT(27) | BIT(26)); + val32 |= BIT(27); + rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32); + + val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON); + val32 &= ~(BIT(27) | BIT(26)); + val32 |= BIT(27); + rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32); + + val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON); + val32 &= ~(BIT(27) | BIT(26)); + val32 |= BIT(27); + rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32); + + val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON); + val32 &= ~(BIT(27) | BIT(26)); + val32 |= BIT(27); + rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32); + + val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX); + val32 &= ~(BIT(27) | BIT(26)); + val32 |= BIT(27); + rtl8xxxu_write32(priv, REG_TX_TO_TX, val32); + } + + if (priv->fops->set_crystal_cap) + priv->fops->set_crystal_cap(priv, priv->default_crystal_cap); + + if (priv->rtl_chip == RTL8192E) + rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x000f81fb); + + return 0; +} + +static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv, + const struct rtl8xxxu_rfregval *array, + enum rtl8xxxu_rfpath path) +{ + int i, ret; + u8 reg; + u32 val; + + for (i = 0; ; i++) { + reg = array[i].reg; + val = array[i].val; + + if (reg == 0xff && val == 0xffffffff) + break; + + switch (reg) { + case 0xfe: + msleep(50); + continue; + case 0xfd: + mdelay(5); + continue; + case 0xfc: + mdelay(1); + continue; + case 0xfb: + udelay(50); + continue; + case 0xfa: + udelay(5); + continue; + case 0xf9: + udelay(1); + continue; + } + + ret = rtl8xxxu_write_rfreg(priv, path, reg, val); + if (ret) { + dev_warn(&priv->udev->dev, + "Failed to initialize RF\n"); + return -EAGAIN; + } + udelay(1); + } + + return 0; +} + +int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv, + const struct rtl8xxxu_rfregval *table, + enum rtl8xxxu_rfpath path) +{ + u32 val32; + u16 val16, rfsi_rfenv; + u16 reg_sw_ctrl, reg_int_oe, reg_hssi_parm2; + + switch (path) { + case RF_A: + reg_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL; + reg_int_oe = REG_FPGA0_XA_RF_INT_OE; + reg_hssi_parm2 = REG_FPGA0_XA_HSSI_PARM2; + break; + case RF_B: + reg_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL; + reg_int_oe = REG_FPGA0_XB_RF_INT_OE; + reg_hssi_parm2 = REG_FPGA0_XB_HSSI_PARM2; + break; + default: + dev_err(&priv->udev->dev, "%s:Unsupported RF path %c\n", + __func__, path + 'A'); + return -EINVAL; + } + /* For path B, use XB */ + rfsi_rfenv = rtl8xxxu_read16(priv, reg_sw_ctrl); + rfsi_rfenv &= FPGA0_RF_RFENV; + + /* + * These two we might be able to optimize into one + */ + val32 = rtl8xxxu_read32(priv, reg_int_oe); + val32 |= BIT(20); /* 0x10 << 16 */ + rtl8xxxu_write32(priv, reg_int_oe, val32); + udelay(1); + + val32 = rtl8xxxu_read32(priv, reg_int_oe); + val32 |= BIT(4); + rtl8xxxu_write32(priv, reg_int_oe, val32); + udelay(1); + + /* + * These two we might be able to optimize into one + */ + val32 = rtl8xxxu_read32(priv, reg_hssi_parm2); + val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN; + rtl8xxxu_write32(priv, reg_hssi_parm2, val32); + udelay(1); + + val32 = rtl8xxxu_read32(priv, reg_hssi_parm2); + val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN; + rtl8xxxu_write32(priv, reg_hssi_parm2, val32); + udelay(1); + + rtl8xxxu_init_rf_regs(priv, table, path); + + /* For path B, use XB */ + val16 = rtl8xxxu_read16(priv, reg_sw_ctrl); + val16 &= ~FPGA0_RF_RFENV; + val16 |= rfsi_rfenv; + rtl8xxxu_write16(priv, reg_sw_ctrl, val16); + + return 0; +} + +static int rtl8xxxu_llt_write(struct rtl8xxxu_priv *priv, u8 address, u8 data) +{ + int ret = -EBUSY; + int count = 0; + u32 value; + + value = LLT_OP_WRITE | address << 8 | data; + + rtl8xxxu_write32(priv, REG_LLT_INIT, value); + + do { + value = rtl8xxxu_read32(priv, REG_LLT_INIT); + if ((value & LLT_OP_MASK) == LLT_OP_INACTIVE) { + ret = 0; + break; + } + } while (count++ < 20); + + return ret; +} + +int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv) +{ + int ret; + int i, last_entry; + u8 last_tx_page; + + last_tx_page = priv->fops->total_page_num; + + if (priv->fops->last_llt_entry) + last_entry = priv->fops->last_llt_entry; + else + last_entry = 255; + + for (i = 0; i < last_tx_page; i++) { + ret = rtl8xxxu_llt_write(priv, i, i + 1); + if (ret) + goto exit; + } + + ret = rtl8xxxu_llt_write(priv, last_tx_page, 0xff); + if (ret) + goto exit; + + /* Mark remaining pages as a ring buffer */ + for (i = last_tx_page + 1; i < last_entry; i++) { + ret = rtl8xxxu_llt_write(priv, i, (i + 1)); + if (ret) + goto exit; + } + + /* Let last entry point to the start entry of ring buffer */ + ret = rtl8xxxu_llt_write(priv, last_entry, last_tx_page + 1); + if (ret) + goto exit; + +exit: + return ret; +} + +int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv) +{ + u32 val32; + int ret = 0; + int i; + + val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT); + val32 |= AUTO_LLT_INIT_LLT; + rtl8xxxu_write32(priv, REG_AUTO_LLT, val32); + + for (i = 500; i; i--) { + val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT); + if (!(val32 & AUTO_LLT_INIT_LLT)) + break; + usleep_range(2, 4); + } + + if (!i) { + ret = -EBUSY; + dev_warn(&priv->udev->dev, "LLT table init failed\n"); + } + + return ret; +} + +static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv) +{ + u16 val16, hi, lo; + u16 hiq, mgq, bkq, beq, viq, voq; + int hip, mgp, bkp, bep, vip, vop; + int ret = 0; + u32 val32; + + switch (priv->ep_tx_count) { + case 1: + if (priv->ep_tx_high_queue) { + hi = TRXDMA_QUEUE_HIGH; + } else if (priv->ep_tx_low_queue) { + hi = TRXDMA_QUEUE_LOW; + } else if (priv->ep_tx_normal_queue) { + hi = TRXDMA_QUEUE_NORMAL; + } else { + hi = 0; + ret = -EINVAL; + } + + hiq = hi; + mgq = hi; + bkq = hi; + beq = hi; + viq = hi; + voq = hi; + + hip = 0; + mgp = 0; + bkp = 0; + bep = 0; + vip = 0; + vop = 0; + break; + case 2: + if (priv->ep_tx_high_queue && priv->ep_tx_low_queue) { + hi = TRXDMA_QUEUE_HIGH; + lo = TRXDMA_QUEUE_LOW; + } else if (priv->ep_tx_normal_queue && priv->ep_tx_low_queue) { + hi = TRXDMA_QUEUE_NORMAL; + lo = TRXDMA_QUEUE_LOW; + } else if (priv->ep_tx_high_queue && priv->ep_tx_normal_queue) { + hi = TRXDMA_QUEUE_HIGH; + lo = TRXDMA_QUEUE_NORMAL; + } else { + ret = -EINVAL; + hi = 0; + lo = 0; + } + + hiq = hi; + mgq = hi; + bkq = lo; + beq = lo; + viq = hi; + voq = hi; + + hip = 0; + mgp = 0; + bkp = 1; + bep = 1; + vip = 0; + vop = 0; + break; + case 3: + beq = TRXDMA_QUEUE_LOW; + bkq = TRXDMA_QUEUE_LOW; + viq = TRXDMA_QUEUE_NORMAL; + voq = TRXDMA_QUEUE_HIGH; + mgq = TRXDMA_QUEUE_HIGH; + hiq = TRXDMA_QUEUE_HIGH; + + hip = hiq ^ 3; + mgp = mgq ^ 3; + bkp = bkq ^ 3; + bep = beq ^ 3; + vip = viq ^ 3; + vop = viq ^ 3; + break; + default: + ret = -EINVAL; + } + + /* + * None of the vendor drivers are configuring the beacon + * queue here .... why? + */ + if (!ret) { + /* Only RTL8192F seems to do it like this. */ + if (priv->rtl_chip == RTL8192F) { + val32 = rtl8xxxu_read32(priv, REG_TRXDMA_CTRL); + val32 &= 0x7; + val32 |= (voq << TRXDMA_CTRL_VOQ_SHIFT_8192F) | + (viq << TRXDMA_CTRL_VIQ_SHIFT_8192F) | + (beq << TRXDMA_CTRL_BEQ_SHIFT_8192F) | + (bkq << TRXDMA_CTRL_BKQ_SHIFT_8192F) | + (mgq << TRXDMA_CTRL_MGQ_SHIFT_8192F) | + (hiq << TRXDMA_CTRL_HIQ_SHIFT_8192F); + rtl8xxxu_write32(priv, REG_TRXDMA_CTRL, val32); + } else { + val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL); + val16 &= 0x7; + val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) | + (viq << TRXDMA_CTRL_VIQ_SHIFT) | + (beq << TRXDMA_CTRL_BEQ_SHIFT) | + (bkq << TRXDMA_CTRL_BKQ_SHIFT) | + (mgq << TRXDMA_CTRL_MGQ_SHIFT) | + (hiq << TRXDMA_CTRL_HIQ_SHIFT); + rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16); + } + + priv->pipe_out[TXDESC_QUEUE_VO] = + usb_sndbulkpipe(priv->udev, priv->out_ep[vop]); + priv->pipe_out[TXDESC_QUEUE_VI] = + usb_sndbulkpipe(priv->udev, priv->out_ep[vip]); + priv->pipe_out[TXDESC_QUEUE_BE] = + usb_sndbulkpipe(priv->udev, priv->out_ep[bep]); + priv->pipe_out[TXDESC_QUEUE_BK] = + usb_sndbulkpipe(priv->udev, priv->out_ep[bkp]); + priv->pipe_out[TXDESC_QUEUE_BEACON] = + usb_sndbulkpipe(priv->udev, priv->out_ep[0]); + priv->pipe_out[TXDESC_QUEUE_MGNT] = + usb_sndbulkpipe(priv->udev, priv->out_ep[mgp]); + priv->pipe_out[TXDESC_QUEUE_HIGH] = + usb_sndbulkpipe(priv->udev, priv->out_ep[hip]); + priv->pipe_out[TXDESC_QUEUE_CMD] = + usb_sndbulkpipe(priv->udev, priv->out_ep[0]); + } + + return ret; +} + +void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv, bool iqk_ok, + int result[][8], int candidate, bool tx_only) +{ + u32 oldval, x, tx0_a, reg; + int y, tx0_c; + u32 val32; + + if (!iqk_ok) + return; + + val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE); + oldval = val32 >> 22; + + x = result[candidate][0]; + if ((x & 0x00000200) != 0) + x = x | 0xfffffc00; + tx0_a = (x * oldval) >> 8; + + val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE); + val32 &= ~0x3ff; + val32 |= tx0_a; + rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32); + + val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); + val32 &= ~BIT(31); + if ((x * oldval >> 7) & 0x1) + val32 |= BIT(31); + rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); + + y = result[candidate][1]; + if ((y & 0x00000200) != 0) + y = y | 0xfffffc00; + tx0_c = (y * oldval) >> 8; + + val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE); + val32 &= ~0xf0000000; + val32 |= (((tx0_c & 0x3c0) >> 6) << 28); + rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32); + + val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE); + val32 &= ~0x003f0000; + val32 |= ((tx0_c & 0x3f) << 16); + rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32); + + val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); + val32 &= ~BIT(29); + if ((y * oldval >> 7) & 0x1) + val32 |= BIT(29); + rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); + + if (tx_only) { + dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__); + return; + } + + reg = result[candidate][2]; + + val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE); + val32 &= ~0x3ff; + val32 |= (reg & 0x3ff); + rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32); + + reg = result[candidate][3] & 0x3F; + + val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE); + val32 &= ~0xfc00; + val32 |= ((reg << 10) & 0xfc00); + rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32); + + reg = (result[candidate][3] >> 6) & 0xF; + + val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA); + val32 &= ~0xf0000000; + val32 |= (reg << 28); + rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32); +} + +void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv, bool iqk_ok, + int result[][8], int candidate, bool tx_only) +{ + u32 oldval, x, tx1_a, reg; + int y, tx1_c; + u32 val32; + + if (!iqk_ok) + return; + + val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE); + oldval = val32 >> 22; + + x = result[candidate][4]; + if ((x & 0x00000200) != 0) + x = x | 0xfffffc00; + tx1_a = (x * oldval) >> 8; + + val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE); + val32 &= ~0x3ff; + val32 |= tx1_a; + rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32); + + val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); + val32 &= ~BIT(27); + if ((x * oldval >> 7) & 0x1) + val32 |= BIT(27); + rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); + + y = result[candidate][5]; + if ((y & 0x00000200) != 0) + y = y | 0xfffffc00; + tx1_c = (y * oldval) >> 8; + + val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE); + val32 &= ~0xf0000000; + val32 |= (((tx1_c & 0x3c0) >> 6) << 28); + rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32); + + val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE); + val32 &= ~0x003f0000; + val32 |= ((tx1_c & 0x3f) << 16); + rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32); + + val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); + val32 &= ~BIT(25); + if ((y * oldval >> 7) & 0x1) + val32 |= BIT(25); + rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); + + if (tx_only) { + dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__); + return; + } + + reg = result[candidate][6]; + + val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE); + val32 &= ~0x3ff; + val32 |= (reg & 0x3ff); + rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32); + + reg = result[candidate][7] & 0x3f; + + val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE); + val32 &= ~0xfc00; + val32 |= ((reg << 10) & 0xfc00); + rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32); + + reg = (result[candidate][7] >> 6) & 0xf; + + if (priv->rtl_chip == RTL8192F) { + rtl8xxxu_write32_mask(priv, REG_RXIQB_EXT, 0x000000f0, reg); + } else { + val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_RSSI_TABLE); + val32 &= ~0x0000f000; + val32 |= (reg << 12); + rtl8xxxu_write32(priv, REG_OFDM0_AGC_RSSI_TABLE, val32); + } +} + +#define MAX_TOLERANCE 5 + +bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv, + int result[][8], int c1, int c2) +{ + u32 i, j, diff, simubitmap, bound = 0; + int candidate[2] = {-1, -1}; /* for path A and path B */ + bool retval = true; + + if (priv->tx_paths > 1) + bound = 8; + else + bound = 4; + + simubitmap = 0; + + for (i = 0; i < bound; i++) { + diff = (result[c1][i] > result[c2][i]) ? + (result[c1][i] - result[c2][i]) : + (result[c2][i] - result[c1][i]); + if (diff > MAX_TOLERANCE) { + if ((i == 2 || i == 6) && !simubitmap) { + if (result[c1][i] + result[c1][i + 1] == 0) + candidate[(i / 4)] = c2; + else if (result[c2][i] + result[c2][i + 1] == 0) + candidate[(i / 4)] = c1; + else + simubitmap = simubitmap | (1 << i); + } else { + simubitmap = simubitmap | (1 << i); + } + } + } + + if (simubitmap == 0) { + for (i = 0; i < (bound / 4); i++) { + if (candidate[i] >= 0) { + for (j = i * 4; j < (i + 1) * 4 - 2; j++) + result[3][j] = result[candidate[i]][j]; + retval = false; + } + } + return retval; + } else if (!(simubitmap & 0x0f)) { + /* path A OK */ + for (i = 0; i < 4; i++) + result[3][i] = result[c1][i]; + } else if (!(simubitmap & 0xf0) && priv->tx_paths > 1) { + /* path B OK */ + for (i = 4; i < 8; i++) + result[3][i] = result[c1][i]; + } + + return false; +} + +bool rtl8xxxu_gen2_simularity_compare(struct rtl8xxxu_priv *priv, + int result[][8], int c1, int c2) +{ + u32 i, j, diff, simubitmap, bound = 0; + int candidate[2] = {-1, -1}; /* for path A and path B */ + int tmp1, tmp2; + bool retval = true; + + if (priv->tx_paths > 1) + bound = 8; + else + bound = 4; + + simubitmap = 0; + + for (i = 0; i < bound; i++) { + if (i & 1) { + if ((result[c1][i] & 0x00000200)) + tmp1 = result[c1][i] | 0xfffffc00; + else + tmp1 = result[c1][i]; + + if ((result[c2][i]& 0x00000200)) + tmp2 = result[c2][i] | 0xfffffc00; + else + tmp2 = result[c2][i]; + } else { + tmp1 = result[c1][i]; + tmp2 = result[c2][i]; + } + + diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1); + + if (diff > MAX_TOLERANCE) { + if ((i == 2 || i == 6) && !simubitmap) { + if (result[c1][i] + result[c1][i + 1] == 0) + candidate[(i / 4)] = c2; + else if (result[c2][i] + result[c2][i + 1] == 0) + candidate[(i / 4)] = c1; + else + simubitmap = simubitmap | (1 << i); + } else { + simubitmap = simubitmap | (1 << i); + } + } + } + + if (simubitmap == 0) { + for (i = 0; i < (bound / 4); i++) { + if (candidate[i] >= 0) { + for (j = i * 4; j < (i + 1) * 4 - 2; j++) + result[3][j] = result[candidate[i]][j]; + retval = false; + } + } + return retval; + } else { + if (!(simubitmap & 0x03)) { + /* path A TX OK */ + for (i = 0; i < 2; i++) + result[3][i] = result[c1][i]; + } + + if (!(simubitmap & 0x0c)) { + /* path A RX OK */ + for (i = 2; i < 4; i++) + result[3][i] = result[c1][i]; + } + + if (!(simubitmap & 0x30) && priv->tx_paths > 1) { + /* path B TX OK */ + for (i = 4; i < 6; i++) + result[3][i] = result[c1][i]; + } + + if (!(simubitmap & 0xc0) && priv->tx_paths > 1) { + /* path B RX OK */ + for (i = 6; i < 8; i++) + result[3][i] = result[c1][i]; + } + } + + return false; +} + +void +rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup) +{ + int i; + + for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++) + backup[i] = rtl8xxxu_read8(priv, reg[i]); + + backup[i] = rtl8xxxu_read32(priv, reg[i]); +} + +void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv, + const u32 *reg, u32 *backup) +{ + int i; + + for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++) + rtl8xxxu_write8(priv, reg[i], backup[i]); + + rtl8xxxu_write32(priv, reg[i], backup[i]); +} + +void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs, + u32 *backup, int count) +{ + int i; + + for (i = 0; i < count; i++) + backup[i] = rtl8xxxu_read32(priv, regs[i]); +} + +void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs, + u32 *backup, int count) +{ + int i; + + for (i = 0; i < count; i++) + rtl8xxxu_write32(priv, regs[i], backup[i]); +} + + +void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs, + bool path_a_on) +{ + u32 path_on; + int i; + + if (priv->tx_paths == 1) { + path_on = priv->fops->adda_1t_path_on; + rtl8xxxu_write32(priv, regs[0], priv->fops->adda_1t_init); + } else { + path_on = path_a_on ? priv->fops->adda_2t_path_on_a : + priv->fops->adda_2t_path_on_b; + + rtl8xxxu_write32(priv, regs[0], path_on); + } + + for (i = 1 ; i < RTL8XXXU_ADDA_REGS ; i++) + rtl8xxxu_write32(priv, regs[i], path_on); +} + +void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv, + const u32 *regs, u32 *backup) +{ + int i = 0; + + rtl8xxxu_write8(priv, regs[i], 0x3f); + + for (i = 1 ; i < (RTL8XXXU_MAC_REGS - 1); i++) + rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3))); + + rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5))); +} + +static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv *priv) +{ + u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32; + int result = 0; + + /* path-A IQK setting */ + rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f); + rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f); + rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102); + + val32 = (priv->rf_paths > 1) ? 0x28160202 : + /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */ + 0x28160502; + rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32); + + /* path-B IQK setting */ + if (priv->rf_paths > 1) { + rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22); + rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22); + rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102); + rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202); + } + + /* LO calibration setting */ + rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1); + + /* One shot, path A LOK & IQK */ + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); + rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); + + mdelay(1); + + /* Check failed */ + reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); + reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); + reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); + reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); + + if (!(reg_eac & BIT(28)) && + ((reg_e94 & 0x03ff0000) != 0x01420000) && + ((reg_e9c & 0x03ff0000) != 0x00420000)) + result |= 0x01; + else /* If TX not OK, ignore RX */ + goto out; + + /* If TX is OK, check whether RX is OK */ + if (!(reg_eac & BIT(27)) && + ((reg_ea4 & 0x03ff0000) != 0x01320000) && + ((reg_eac & 0x03ff0000) != 0x00360000)) + result |= 0x02; + else + dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n", + __func__); +out: + return result; +} + +static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv *priv) +{ + u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc; + int result = 0; + + /* One shot, path B LOK & IQK */ + rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002); + rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000); + + mdelay(1); + + /* Check failed */ + reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); + reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); + reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); + reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2); + reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2); + + if (!(reg_eac & BIT(31)) && + ((reg_eb4 & 0x03ff0000) != 0x01420000) && + ((reg_ebc & 0x03ff0000) != 0x00420000)) + result |= 0x01; + else + goto out; + + if (!(reg_eac & BIT(30)) && + (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) && + (((reg_ecc & 0x03ff0000) >> 16) != 0x36)) + result |= 0x02; + else + dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n", + __func__); +out: + return result; +} + +static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv, + int result[][8], int t) +{ + struct device *dev = &priv->udev->dev; + u32 i, val32; + int path_a_ok, path_b_ok; + int retry = 2; + static const u32 adda_regs[RTL8XXXU_ADDA_REGS] = { + REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH, + REG_RX_WAIT_CCA, REG_TX_CCK_RFON, + REG_TX_CCK_BBON, REG_TX_OFDM_RFON, + REG_TX_OFDM_BBON, REG_TX_TO_RX, + REG_TX_TO_TX, REG_RX_CCK, + REG_RX_OFDM, REG_RX_WAIT_RIFS, + REG_RX_TO_RX, REG_STANDBY, + REG_SLEEP, REG_PMPD_ANAEN + }; + static const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = { + REG_TXPAUSE, REG_BEACON_CTRL, + REG_BEACON_CTRL_1, REG_GPIO_MUXCFG + }; + static const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = { + REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR, + REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, + REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE, + REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE + }; + + /* + * Note: IQ calibration must be performed after loading + * PHY_REG.txt , and radio_a, radio_b.txt + */ + + if (t == 0) { + /* Save ADDA parameters, turn Path A ADDA on */ + rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup, + RTL8XXXU_ADDA_REGS); + rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup); + rtl8xxxu_save_regs(priv, iqk_bb_regs, + priv->bb_backup, RTL8XXXU_BB_REGS); + } + + rtl8xxxu_path_adda_on(priv, adda_regs, true); + + if (t == 0) { + val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1); + if (val32 & FPGA0_HSSI_PARM1_PI) + priv->pi_enabled = 1; + } + + if (!priv->pi_enabled) { + /* Switch BB to PI mode to do IQ Calibration. */ + rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100); + rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100); + } + + val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); + val32 &= ~FPGA_RF_MODE_CCK; + rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); + + rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600); + rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4); + rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000); + + if (!priv->no_pape) { + val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL); + val32 |= (FPGA0_RF_PAPE | + (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT)); + rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32); + } + + val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE); + val32 &= ~BIT(10); + rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32); + val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE); + val32 &= ~BIT(10); + rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32); + + if (priv->tx_paths > 1) { + rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000); + rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000); + } + + /* MAC settings */ + rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup); + + /* Page B init */ + rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000); + + if (priv->tx_paths > 1) + rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000); + + /* IQ calibration setting */ + rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); + rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); + rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); + + for (i = 0; i < retry; i++) { + path_a_ok = rtl8xxxu_iqk_path_a(priv); + if (path_a_ok == 0x03) { + val32 = rtl8xxxu_read32(priv, + REG_TX_POWER_BEFORE_IQK_A); + result[t][0] = (val32 >> 16) & 0x3ff; + val32 = rtl8xxxu_read32(priv, + REG_TX_POWER_AFTER_IQK_A); + result[t][1] = (val32 >> 16) & 0x3ff; + val32 = rtl8xxxu_read32(priv, + REG_RX_POWER_BEFORE_IQK_A_2); + result[t][2] = (val32 >> 16) & 0x3ff; + val32 = rtl8xxxu_read32(priv, + REG_RX_POWER_AFTER_IQK_A_2); + result[t][3] = (val32 >> 16) & 0x3ff; + break; + } else if (i == (retry - 1) && path_a_ok == 0x01) { + /* TX IQK OK */ + dev_dbg(dev, "%s: Path A IQK Only Tx Success!!\n", + __func__); + + val32 = rtl8xxxu_read32(priv, + REG_TX_POWER_BEFORE_IQK_A); + result[t][0] = (val32 >> 16) & 0x3ff; + val32 = rtl8xxxu_read32(priv, + REG_TX_POWER_AFTER_IQK_A); + result[t][1] = (val32 >> 16) & 0x3ff; + } + } + + if (!path_a_ok) + dev_dbg(dev, "%s: Path A IQK failed!\n", __func__); + + if (priv->tx_paths > 1) { + /* + * Path A into standby + */ + rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0); + rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000); + rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); + + /* Turn Path B ADDA on */ + rtl8xxxu_path_adda_on(priv, adda_regs, false); + + for (i = 0; i < retry; i++) { + path_b_ok = rtl8xxxu_iqk_path_b(priv); + if (path_b_ok == 0x03) { + val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); + result[t][4] = (val32 >> 16) & 0x3ff; + val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); + result[t][5] = (val32 >> 16) & 0x3ff; + val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2); + result[t][6] = (val32 >> 16) & 0x3ff; + val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2); + result[t][7] = (val32 >> 16) & 0x3ff; + break; + } else if (i == (retry - 1) && path_b_ok == 0x01) { + /* TX IQK OK */ + val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); + result[t][4] = (val32 >> 16) & 0x3ff; + val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); + result[t][5] = (val32 >> 16) & 0x3ff; + } + } + + if (!path_b_ok) + dev_dbg(dev, "%s: Path B IQK failed!\n", __func__); + } + + /* Back to BB mode, load original value */ + rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0); + + if (t) { + if (!priv->pi_enabled) { + /* + * Switch back BB to SI mode after finishing + * IQ Calibration + */ + val32 = 0x01000000; + rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32); + rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32); + } + + /* Reload ADDA power saving parameters */ + rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup, + RTL8XXXU_ADDA_REGS); + + /* Reload MAC parameters */ + rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup); + + /* Reload BB parameters */ + rtl8xxxu_restore_regs(priv, iqk_bb_regs, + priv->bb_backup, RTL8XXXU_BB_REGS); + + /* Restore RX initial gain */ + rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3); + + if (priv->tx_paths > 1) { + rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, + 0x00032ed3); + } + + /* Load 0xe30 IQC default value */ + rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00); + rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00); + } +} + +void rtl8xxxu_gen2_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start) +{ + struct h2c_cmd h2c; + + memset(&h2c, 0, sizeof(struct h2c_cmd)); + h2c.bt_wlan_calibration.cmd = H2C_8723B_BT_WLAN_CALIBRATION; + h2c.bt_wlan_calibration.data = start; + + rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_wlan_calibration)); +} + +void rtl8xxxu_gen1_phy_iq_calibrate(struct rtl8xxxu_priv *priv) +{ + struct device *dev = &priv->udev->dev; + int result[4][8]; /* last is final result */ + int i, candidate; + bool path_a_ok, path_b_ok; + u32 reg_e94, reg_e9c, reg_ea4, reg_eac; + u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc; + s32 reg_tmp = 0; + bool simu; + + memset(result, 0, sizeof(result)); + candidate = -1; + + path_a_ok = false; + path_b_ok = false; + + rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); + + for (i = 0; i < 3; i++) { + rtl8xxxu_phy_iqcalibrate(priv, result, i); + + if (i == 1) { + simu = rtl8xxxu_simularity_compare(priv, result, 0, 1); + if (simu) { + candidate = 0; + break; + } + } + + if (i == 2) { + simu = rtl8xxxu_simularity_compare(priv, result, 0, 2); + if (simu) { + candidate = 0; + break; + } + + simu = rtl8xxxu_simularity_compare(priv, result, 1, 2); + if (simu) { + candidate = 1; + } else { + for (i = 0; i < 8; i++) + reg_tmp += result[3][i]; + + if (reg_tmp) + candidate = 3; + else + candidate = -1; + } + } + } + + for (i = 0; i < 4; i++) { + reg_e94 = result[i][0]; + reg_e9c = result[i][1]; + reg_ea4 = result[i][2]; + reg_eac = result[i][3]; + reg_eb4 = result[i][4]; + reg_ebc = result[i][5]; + reg_ec4 = result[i][6]; + reg_ecc = result[i][7]; + } + + if (candidate >= 0) { + reg_e94 = result[candidate][0]; + priv->rege94 = reg_e94; + reg_e9c = result[candidate][1]; + priv->rege9c = reg_e9c; + reg_ea4 = result[candidate][2]; + reg_eac = result[candidate][3]; + reg_eb4 = result[candidate][4]; + priv->regeb4 = reg_eb4; + reg_ebc = result[candidate][5]; + priv->regebc = reg_ebc; + reg_ec4 = result[candidate][6]; + reg_ecc = result[candidate][7]; + dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate); + dev_dbg(dev, + "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x ecc=%x\n", + __func__, reg_e94, reg_e9c, + reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc); + path_a_ok = true; + path_b_ok = true; + } else { + reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100; + reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0; + } + + if (reg_e94 && candidate >= 0) + rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result, + candidate, (reg_ea4 == 0)); + + if (priv->tx_paths > 1 && reg_eb4) + rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result, + candidate, (reg_ec4 == 0)); + + rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg, + priv->bb_recovery_backup, RTL8XXXU_BB_REGS); +} + +void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv) +{ + u32 val32; + u32 rf_amode, rf_bmode = 0, lstf; + + /* Check continuous TX and Packet TX */ + lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF); + + if (lstf & OFDM_LSTF_MASK) { + /* Disable all continuous TX */ + val32 = lstf & ~OFDM_LSTF_MASK; + rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); + + /* Read original RF mode Path A */ + rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_AC); + + /* Set RF mode to standby Path A */ + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, + (rf_amode & 0x8ffff) | 0x10000); + + /* Path-B */ + if (priv->tx_paths > 1) { + rf_bmode = rtl8xxxu_read_rfreg(priv, RF_B, + RF6052_REG_AC); + + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, + (rf_bmode & 0x8ffff) | 0x10000); + } + } else { + /* Deal with Packet TX case */ + /* block all queues */ + rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); + } + + /* Start LC calibration */ + if (priv->fops->has_s0s1) + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdfbe0); + val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG); + val32 |= 0x08000; + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32); + + msleep(100); + + if (priv->fops->has_s0s1) + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdffe0); + + /* Restore original parameters */ + if (lstf & OFDM_LSTF_MASK) { + /* Path-A */ + rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf); + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, rf_amode); + + /* Path-B */ + if (priv->tx_paths > 1) + rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, + rf_bmode); + } else /* Deal with Packet TX case */ + rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); +} + +static int rtl8xxxu_set_mac(struct rtl8xxxu_priv *priv, int port_num) +{ + int i; + u16 reg; + + switch (port_num) { + case 0: + reg = REG_MACID; + break; + case 1: + reg = REG_MACID1; + break; + default: + WARN_ONCE(1, "%s: invalid port_num\n", __func__); + return -EINVAL; + } + + for (i = 0; i < ETH_ALEN; i++) + rtl8xxxu_write8(priv, reg + i, priv->vifs[port_num]->addr[i]); + + return 0; +} + +static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv *priv, const u8 *bssid, int port_num) +{ + int i; + u16 reg; + + dev_dbg(&priv->udev->dev, "%s: (%pM)\n", __func__, bssid); + + switch (port_num) { + case 0: + reg = REG_BSSID; + break; + case 1: + reg = REG_BSSID1; + break; + default: + WARN_ONCE(1, "%s: invalid port_num\n", __func__); + return -EINVAL; + } + + for (i = 0; i < ETH_ALEN; i++) + rtl8xxxu_write8(priv, reg + i, bssid[i]); + + return 0; +} + +static void +rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv *priv, u8 ampdu_factor) +{ + u8 vals[4] = { 0x41, 0xa8, 0x72, 0xb9 }; + u8 max_agg = 0xf; + int i; + + ampdu_factor = 1 << (ampdu_factor + 2); + if (ampdu_factor > max_agg) + ampdu_factor = max_agg; + + for (i = 0; i < 4; i++) { + if ((vals[i] & 0xf0) > (ampdu_factor << 4)) + vals[i] = (vals[i] & 0x0f) | (ampdu_factor << 4); + + if ((vals[i] & 0x0f) > ampdu_factor) + vals[i] = (vals[i] & 0xf0) | ampdu_factor; + + rtl8xxxu_write8(priv, REG_AGGLEN_LMT + i, vals[i]); + } +} + +static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv *priv, u8 density) +{ + u8 val8; + + val8 = rtl8xxxu_read8(priv, REG_AMPDU_MIN_SPACE); + val8 &= 0xf8; + val8 |= density; + rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8); +} + +static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv *priv) +{ + u8 val8; + int count, ret = 0; + + /* Start of rtl8723AU_card_enable_flow */ + /* Act to Cardemu sequence*/ + /* Turn off RF */ + rtl8xxxu_write8(priv, REG_RF_CTRL, 0); + + /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */ + val8 = rtl8xxxu_read8(priv, REG_LEDCFG2); + val8 &= ~LEDCFG2_DPDT_SELECT; + rtl8xxxu_write8(priv, REG_LEDCFG2, val8); + + /* 0x0005[1] = 1 turn off MAC by HW state machine*/ + val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); + val8 |= BIT(1); + rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); + + for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { + val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); + if ((val8 & BIT(1)) == 0) + break; + udelay(10); + } + + if (!count) { + dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n", + __func__); + ret = -EBUSY; + goto exit; + } + + /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */ + val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL); + val8 |= SYS_ISO_ANALOG_IPS; + rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8); + + /* 0x0020[0] = 0 disable LDOA12 MACRO block*/ + val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL); + val8 &= ~LDOA15_ENABLE; + rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8); + +exit: + return ret; +} + +int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv) +{ + u8 val8; + u8 val32; + int count, ret = 0; + + rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); + + /* + * Poll - wait for RX packet to complete + */ + for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { + val32 = rtl8xxxu_read32(priv, 0x5f8); + if (!val32) + break; + udelay(10); + } + + if (!count) { + dev_warn(&priv->udev->dev, + "%s: RX poll timed out (0x05f8)\n", __func__); + ret = -EBUSY; + goto exit; + } + + /* Disable CCK and OFDM, clock gated */ + val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); + val8 &= ~SYS_FUNC_BBRSTB; + rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); + + udelay(2); + + /* Reset baseband */ + val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); + val8 &= ~SYS_FUNC_BB_GLB_RSTN; + rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); + + /* Reset MAC TRX */ + val8 = rtl8xxxu_read8(priv, REG_CR); + val8 = CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE; + rtl8xxxu_write8(priv, REG_CR, val8); + + /* Reset MAC TRX */ + val8 = rtl8xxxu_read8(priv, REG_CR + 1); + val8 &= ~BIT(1); /* CR_SECURITY_ENABLE */ + rtl8xxxu_write8(priv, REG_CR + 1, val8); + + /* Respond TX OK to scheduler */ + val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST); + val8 |= DUAL_TSF_TX_OK; + rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8); + +exit: + return ret; +} + +void rtl8xxxu_disabled_to_emu(struct rtl8xxxu_priv *priv) +{ + u8 val8; + + /* Clear suspend enable and power down enable*/ + val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); + val8 &= ~(BIT(3) | BIT(7)); + rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); + + /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ + val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2); + val8 &= ~BIT(0); + rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8); + + /* 0x04[12:11] = 11 enable WL suspend*/ + val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); + val8 &= ~(BIT(3) | BIT(4)); + rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); +} + +static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv *priv) +{ + u8 val8; + + /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */ + rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20); + + /* 0x04[12:11] = 01 enable WL suspend */ + val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); + val8 &= ~BIT(4); + val8 |= BIT(3); + rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); + + val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); + val8 |= BIT(7); + rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); + + /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */ + val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2); + val8 |= BIT(0); + rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8); + + return 0; +} + +int rtl8xxxu_flush_fifo(struct rtl8xxxu_priv *priv) +{ + struct device *dev = &priv->udev->dev; + u32 val32; + int retry, retval; + + rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); + + val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM); + val32 |= RXPKT_NUM_RW_RELEASE_EN; + rtl8xxxu_write32(priv, REG_RXPKT_NUM, val32); + + retry = 100; + retval = -EBUSY; + + do { + val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM); + if (val32 & RXPKT_NUM_RXDMA_IDLE) { + retval = 0; + break; + } + } while (retry--); + + rtl8xxxu_write16(priv, REG_RQPN_NPQ, 0); + rtl8xxxu_write32(priv, REG_RQPN, 0x80000000); + mdelay(2); + + if (!retry) + dev_warn(dev, "Failed to flush FIFO\n"); + + return retval; +} + +void rtl8xxxu_gen1_usb_quirks(struct rtl8xxxu_priv *priv) +{ + /* Fix USB interface interference issue */ + rtl8xxxu_write8(priv, 0xfe40, 0xe0); + rtl8xxxu_write8(priv, 0xfe41, 0x8d); + rtl8xxxu_write8(priv, 0xfe42, 0x80); + /* + * This sets TXDMA_OFFSET_DROP_DATA_EN (bit 9) as well as bits + * 8 and 5, for which I have found no documentation. + */ + rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320); + + /* + * Solve too many protocol error on USB bus. + * Can't do this for 8188/8192 UMC A cut parts + */ + if (!(!priv->chip_cut && priv->vendor_umc)) { + rtl8xxxu_write8(priv, 0xfe40, 0xe6); + rtl8xxxu_write8(priv, 0xfe41, 0x94); + rtl8xxxu_write8(priv, 0xfe42, 0x80); + + rtl8xxxu_write8(priv, 0xfe40, 0xe0); + rtl8xxxu_write8(priv, 0xfe41, 0x19); + rtl8xxxu_write8(priv, 0xfe42, 0x80); + + rtl8xxxu_write8(priv, 0xfe40, 0xe5); + rtl8xxxu_write8(priv, 0xfe41, 0x91); + rtl8xxxu_write8(priv, 0xfe42, 0x80); + + rtl8xxxu_write8(priv, 0xfe40, 0xe2); + rtl8xxxu_write8(priv, 0xfe41, 0x81); + rtl8xxxu_write8(priv, 0xfe42, 0x80); + } +} + +void rtl8xxxu_gen2_usb_quirks(struct rtl8xxxu_priv *priv) +{ + u32 val32; + + val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK); + val32 |= TXDMA_OFFSET_DROP_DATA_EN; + rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32); +} + +void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv) +{ + u8 val8; + u16 val16; + u32 val32; + + /* + * Workaround for 8188RU LNA power leakage problem. + */ + if (priv->rtl_chip == RTL8188R) { + val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM); + val32 |= BIT(1); + rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32); + } + + rtl8xxxu_flush_fifo(priv); + + rtl8xxxu_active_to_lps(priv); + + /* Turn off RF */ + rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00); + + /* Reset Firmware if running in RAM */ + if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL) + rtl8xxxu_firmware_self_reset(priv); + + /* Reset MCU */ + val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); + val16 &= ~SYS_FUNC_CPU_ENABLE; + rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); + + /* Reset MCU ready status */ + rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00); + + rtl8xxxu_active_to_emu(priv); + rtl8xxxu_emu_to_disabled(priv); + + /* Reset MCU IO Wrapper */ + val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); + val8 &= ~BIT(0); + rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); + + val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); + val8 |= BIT(0); + rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); + + /* RSV_CTRL 0x1C[7:0] = 0x0e lock ISO/CLK/Power control register */ + rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e); +} + +void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv, + u8 arg1, u8 arg2, u8 arg3, u8 arg4, u8 arg5) +{ + struct h2c_cmd h2c; + + memset(&h2c, 0, sizeof(struct h2c_cmd)); + h2c.b_type_dma.cmd = H2C_8723B_B_TYPE_TDMA; + h2c.b_type_dma.data1 = arg1; + h2c.b_type_dma.data2 = arg2; + h2c.b_type_dma.data3 = arg3; + h2c.b_type_dma.data4 = arg4; + h2c.b_type_dma.data5 = arg5; + rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.b_type_dma)); +} + +void rtl8xxxu_gen2_disable_rf(struct rtl8xxxu_priv *priv) +{ + u32 val32; + + val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA); + val32 &= ~(BIT(22) | BIT(23)); + rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32); +} + +static void rtl8xxxu_init_queue_reserved_page(struct rtl8xxxu_priv *priv) +{ + struct rtl8xxxu_fileops *fops = priv->fops; + u32 hq, lq, nq, eq, pubq; + u32 val32; + + hq = 0; + lq = 0; + nq = 0; + eq = 0; + pubq = 0; + + if (priv->ep_tx_high_queue) + hq = fops->page_num_hi; + if (priv->ep_tx_low_queue) + lq = fops->page_num_lo; + if (priv->ep_tx_normal_queue) + nq = fops->page_num_norm; + + val32 = (nq << RQPN_NPQ_SHIFT) | (eq << RQPN_EPQ_SHIFT); + rtl8xxxu_write32(priv, REG_RQPN_NPQ, val32); + + pubq = fops->total_page_num - hq - lq - nq - 1; + + val32 = RQPN_LOAD; + val32 |= (hq << RQPN_HI_PQ_SHIFT); + val32 |= (lq << RQPN_LO_PQ_SHIFT); + val32 |= (pubq << RQPN_PUB_PQ_SHIFT); + + rtl8xxxu_write32(priv, REG_RQPN, val32); +} + +void rtl8xxxu_init_burst(struct rtl8xxxu_priv *priv) +{ + u8 val8; + + /* + * For USB high speed set 512B packets + */ + val8 = rtl8xxxu_read8(priv, REG_RXDMA_PRO_8723B); + u8p_replace_bits(&val8, 1, RXDMA_PRO_DMA_BURST_SIZE); + u8p_replace_bits(&val8, 3, RXDMA_PRO_DMA_BURST_CNT); + val8 |= RXDMA_PRO_DMA_MODE; + rtl8xxxu_write8(priv, REG_RXDMA_PRO_8723B, val8); + + /* + * Enable single packet AMPDU + */ + val8 = rtl8xxxu_read8(priv, REG_HT_SINGLE_AMPDU_8723B); + val8 |= HT_SINGLE_AMPDU_ENABLE; + rtl8xxxu_write8(priv, REG_HT_SINGLE_AMPDU_8723B, val8); + + rtl8xxxu_write16(priv, REG_MAX_AGGR_NUM, priv->fops->max_aggr_num); + rtl8xxxu_write8(priv, REG_AMPDU_MAX_TIME_8723B, + priv->fops->ampdu_max_time); + rtl8xxxu_write32(priv, REG_AGGLEN_LMT, 0xffffffff); + rtl8xxxu_write8(priv, REG_RX_PKT_LIMIT, 0x18); + rtl8xxxu_write8(priv, REG_PIFS, 0x00); + if (priv->rtl_chip == RTL8188F || priv->rtl_chip == RTL8710B || + priv->rtl_chip == RTL8192F) { + rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, FWHW_TXQ_CTRL_AMPDU_RETRY); + rtl8xxxu_write32(priv, REG_FAST_EDCA_CTRL, 0x03086666); + } + rtl8xxxu_write8(priv, REG_USTIME_TSF_8723B, priv->fops->ustime_tsf_edca); + rtl8xxxu_write8(priv, REG_USTIME_EDCA, priv->fops->ustime_tsf_edca); + + /* to prevent mac is reseted by bus. */ + val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL); + val8 |= RSV_CTRL_WLOCK_1C | RSV_CTRL_DIS_PRST; + rtl8xxxu_write8(priv, REG_RSV_CTRL, val8); +} + +static u8 rtl8xxxu_acquire_macid(struct rtl8xxxu_priv *priv) +{ + u8 macid; + + macid = find_first_zero_bit(priv->mac_id_map, RTL8XXXU_MAX_MAC_ID_NUM); + if (macid < RTL8XXXU_MAX_MAC_ID_NUM) + set_bit(macid, priv->mac_id_map); + + return macid; +} + +static void rtl8xxxu_release_macid(struct rtl8xxxu_priv *priv, u8 macid) +{ + clear_bit(macid, priv->mac_id_map); +} + +static inline u8 rtl8xxxu_get_macid(struct rtl8xxxu_priv *priv, + struct ieee80211_sta *sta) +{ + struct rtl8xxxu_sta_info *sta_info; + + if (!sta) + return 0; + + sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv; + if (!sta_info) + return 0; + + return sta_info->macid; +} + +static int rtl8xxxu_init_device(struct ieee80211_hw *hw) +{ + struct rtl8xxxu_priv *priv = hw->priv; + struct device *dev = &priv->udev->dev; + struct rtl8xxxu_fileops *fops = priv->fops; + bool macpower; + int ret; + u8 val8; + u16 val16; + u32 val32; + + /* Check if MAC is already powered on */ + val8 = rtl8xxxu_read8(priv, REG_CR); + val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR); + + /* + * Fix 92DU-VC S3 hang with the reason is that secondary mac is not + * initialized. First MAC returns 0xea, second MAC returns 0x00 + */ + if (val8 == 0xea || !(val16 & SYS_CLK_MAC_CLK_ENABLE)) + macpower = false; + else + macpower = true; + + if (fops->needs_full_init) + macpower = false; + + ret = fops->power_on(priv); + if (ret < 0) { + dev_warn(dev, "%s: Failed power on\n", __func__); + goto exit; + } + + if (!macpower) + rtl8xxxu_init_queue_reserved_page(priv); + + ret = rtl8xxxu_init_queue_priority(priv); + dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret); + if (ret) + goto exit; + + /* + * Set RX page boundary + */ + rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, fops->trxff_boundary); + + ret = rtl8xxxu_download_firmware(priv); + dev_dbg(dev, "%s: download_firmware %i\n", __func__, ret); + if (ret) + goto exit; + ret = rtl8xxxu_start_firmware(priv); + dev_dbg(dev, "%s: start_firmware %i\n", __func__, ret); + if (ret) + goto exit; + + if (fops->phy_init_antenna_selection) + fops->phy_init_antenna_selection(priv); + + ret = rtl8xxxu_init_mac(priv); + + dev_dbg(dev, "%s: init_mac %i\n", __func__, ret); + if (ret) + goto exit; + + ret = rtl8xxxu_init_phy_bb(priv); + dev_dbg(dev, "%s: init_phy_bb %i\n", __func__, ret); + if (ret) + goto exit; + + ret = fops->init_phy_rf(priv); + if (ret) + goto exit; + + /* Mac APLL Setting */ + if (priv->rtl_chip == RTL8192F) + rtl8xxxu_write16_set(priv, REG_AFE_CTRL4, BIT(4) | BIT(15)); + + /* RFSW Control - clear bit 14 ?? */ + if (priv->rtl_chip != RTL8723B && priv->rtl_chip != RTL8192E && + priv->rtl_chip != RTL8188E && priv->rtl_chip != RTL8710B && + priv->rtl_chip != RTL8192F) + rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003); + + val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW | + FPGA0_RF_ANTSWB | + ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB) << FPGA0_RF_BD_CTRL_SHIFT); + if (!priv->no_pape) { + val32 |= (FPGA0_RF_PAPE | + (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT)); + } + rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32); + + /* 0x860[6:5]= 00 - why? - this sets antenna B */ + if (priv->rtl_chip != RTL8192E && priv->rtl_chip != RTL8188E && + priv->rtl_chip != RTL8710B && priv->rtl_chip != RTL8192F) + rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66f60210); + + if (!macpower) { + /* + * Set TX buffer boundary + */ + val8 = fops->total_page_num + 1; + + rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8); + rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8); + rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8); + rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8); + rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8); + } + + /* + * The vendor drivers set PBP for all devices, except 8192e. + * There is no explanation for this in any of the sources. + */ + val8 = (fops->pbp_rx << PBP_PAGE_SIZE_RX_SHIFT) | + (fops->pbp_tx << PBP_PAGE_SIZE_TX_SHIFT); + if (priv->rtl_chip != RTL8192E) + rtl8xxxu_write8(priv, REG_PBP, val8); + + dev_dbg(dev, "%s: macpower %i\n", __func__, macpower); + if (!macpower) { + ret = fops->llt_init(priv); + if (ret) { + dev_warn(dev, "%s: LLT table init failed\n", __func__); + goto exit; + } + + /* + * Chip specific quirks + */ + fops->usb_quirks(priv); + + /* + * Enable TX report and TX report timer for 8723bu/8188eu/... + */ + if (fops->has_tx_report) { + /* + * The RTL8188EU has two types of TX reports: + * rpt_sel=1: + * One report for one frame. We can use this for frames + * with IEEE80211_TX_CTL_REQ_TX_STATUS. + * rpt_sel=2: + * One report for many frames transmitted over a period + * of time. (This is what REG_TX_REPORT_TIME is for.) The + * report includes the number of frames transmitted + * successfully, and the number of unsuccessful + * transmissions. We use this for software rate control. + * + * Bit 0 of REG_TX_REPORT_CTRL is required for both types. + * Bit 1 (TX_REPORT_CTRL_TIMER_ENABLE) is required for + * type 2. + */ + val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL); + if (priv->rtl_chip == RTL8188E) + val8 |= BIT(0); + val8 |= TX_REPORT_CTRL_TIMER_ENABLE; + rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8); + /* Set MAX RPT MACID */ + rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL + 1, 0x02); + /* TX report Timer. Unit: 32us */ + rtl8xxxu_write16(priv, REG_TX_REPORT_TIME, 0xcdf0); + + /* tmp ps ? */ + val8 = rtl8xxxu_read8(priv, 0xa3); + val8 &= 0xf8; + rtl8xxxu_write8(priv, 0xa3, val8); + } + + if (priv->rtl_chip == RTL8710B || priv->rtl_chip == RTL8192F) + rtl8xxxu_write8(priv, REG_EARLY_MODE_CONTROL_8710B, 0); + } + + /* + * Unit in 8 bytes. + * Get Rx PHY status in order to report RSSI and others. + */ + rtl8xxxu_write8(priv, REG_RX_DRVINFO_SZ, 4); + + if (priv->rtl_chip == RTL8192E) { + rtl8xxxu_write32(priv, REG_HIMR0, 0x00); + rtl8xxxu_write32(priv, REG_HIMR1, 0x00); + } else if (priv->rtl_chip == RTL8188F) { + rtl8xxxu_write32(priv, REG_HISR0, 0xffffffff); + rtl8xxxu_write32(priv, REG_HISR1, 0xffffffff); + } else if (priv->rtl_chip == RTL8188E) { + rtl8xxxu_write32(priv, REG_HISR0, 0xffffffff); + val32 = IMR0_PSTIMEOUT | IMR0_TBDER | IMR0_CPWM | IMR0_CPWM2; + rtl8xxxu_write32(priv, REG_HIMR0, val32); + val32 = IMR1_TXERR | IMR1_RXERR | IMR1_TXFOVW | IMR1_RXFOVW; + rtl8xxxu_write32(priv, REG_HIMR1, val32); + val8 = rtl8xxxu_read8(priv, REG_USB_SPECIAL_OPTION); + val8 |= USB_SPEC_INT_BULK_SELECT; + rtl8xxxu_write8(priv, REG_USB_SPECIAL_OPTION, val8); + } else if (priv->rtl_chip == RTL8710B) { + rtl8xxxu_write32(priv, REG_HIMR0_8710B, 0); + } else if (priv->rtl_chip != RTL8192F) { + /* + * Enable all interrupts - not obvious USB needs to do this + */ + rtl8xxxu_write32(priv, REG_HISR, 0xffffffff); + rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff); + } + + /* + * Configure initial WMAC settings + */ + val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST | + RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL | + RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC; + rtl8xxxu_write32(priv, REG_RCR, val32); + priv->regrcr = val32; + + if (fops->init_reg_rxfltmap) { + /* Accept all data frames */ + rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff); + + /* + * Since ADF is removed from RCR, ps-poll will not be indicate to driver, + * RxFilterMap should mask ps-poll to gurantee AP mode can rx ps-poll. + */ + rtl8xxxu_write16(priv, REG_RXFLTMAP1, 0x400); + + /* Accept all management frames */ + rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff); + } else { + /* + * Accept all multicast + */ + rtl8xxxu_write32(priv, REG_MAR, 0xffffffff); + rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff); + } + + /* + * Init adaptive controls + */ + val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); + val32 &= ~RESPONSE_RATE_BITMAP_ALL; + val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M; + rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); + + /* CCK = 0x0a, OFDM = 0x10 */ + rtl8xxxu_set_spec_sifs(priv, 0x10, 0x10); + rtl8xxxu_set_retry(priv, 0x30, 0x30); + rtl8xxxu_set_spec_sifs(priv, 0x0a, 0x10); + + /* + * Init EDCA + */ + rtl8xxxu_write16(priv, REG_MAC_SPEC_SIFS, 0x100a); + + /* Set CCK SIFS */ + rtl8xxxu_write16(priv, REG_SIFS_CCK, 0x100a); + + /* Set OFDM SIFS */ + rtl8xxxu_write16(priv, REG_SIFS_OFDM, 0x100a); + + /* TXOP */ + rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b); + rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f); + rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324); + rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226); + + /* Set data auto rate fallback retry count */ + rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000); + rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404); + rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201); + rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605); + + val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL); + val8 |= FWHW_TXQ_CTRL_AMPDU_RETRY; + rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, val8); + + /* Set ACK timeout */ + rtl8xxxu_write8(priv, REG_ACKTO, 0x40); + + /* + * Initialize beacon parameters + */ + val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8); + rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16); + rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404); + if (priv->rtl_chip != RTL8188F && priv->rtl_chip != RTL8710B && + priv->rtl_chip != RTL8192F) + /* Firmware will control REG_DRVERLYINT when power saving is enable, */ + /* so don't set this register on STA mode. */ + rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME); + rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME); + rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F); + + /* + * Initialize burst parameters + */ + if (priv->fops->init_burst) + priv->fops->init_burst(priv); + + if (fops->init_aggregation) + fops->init_aggregation(priv); + + if (fops->init_reg_pkt_life_time) { + rtl8xxxu_write16(priv, REG_PKT_VO_VI_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */ + rtl8xxxu_write16(priv, REG_PKT_BE_BK_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */ + } + + /* + * Enable CCK and OFDM block + */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); + val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM); + rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); + + /* + * Invalidate all CAM entries - bit 30 is undocumented + */ + rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30)); + + /* + * Start out with default power levels for channel 6, 20MHz + */ + fops->set_tx_power(priv, 1, false); + + /* Let the 8051 take control of antenna setting */ + if (priv->rtl_chip != RTL8192E && priv->rtl_chip != RTL8188F && + priv->rtl_chip != RTL8710B && priv->rtl_chip != RTL8192C) { + val8 = rtl8xxxu_read8(priv, REG_LEDCFG2); + val8 |= LEDCFG2_DPDT_SELECT; + rtl8xxxu_write8(priv, REG_LEDCFG2, val8); + } + + rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, 0xff); + + /* Disable BAR - not sure if this has any effect on USB */ + rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff); + + if (priv->rtl_chip != RTL8188F && priv->rtl_chip != RTL8188E && + priv->rtl_chip != RTL8710B && priv->rtl_chip != RTL8192F) + rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0); + + if (fops->init_statistics) + fops->init_statistics(priv); + + if (priv->rtl_chip == RTL8192E) { + /* + * 0x4c6[3] 1: RTS BW = Data BW + * 0: RTS BW depends on CCA / secondary CCA result. + */ + val8 = rtl8xxxu_read8(priv, REG_QUEUE_CTRL); + val8 &= ~BIT(3); + rtl8xxxu_write8(priv, REG_QUEUE_CTRL, val8); + /* + * Reset USB mode switch setting + */ + rtl8xxxu_write8(priv, REG_ACLK_MON, 0x00); + } else if (priv->rtl_chip == RTL8188F || priv->rtl_chip == RTL8188E || + priv->rtl_chip == RTL8192F) { + /* + * Init GPIO settings for 8188f, 8188e, 8192f + */ + val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG); + val8 &= ~GPIO_MUXCFG_IO_SEL_ENBT; + rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8); + } + + if (priv->rtl_chip == RTL8188F) + /* CCK PD */ + rtl8xxxu_write8(priv, REG_CCK_PD_THRESH, CCK_PD_TYPE1_LV1_TH); + + fops->phy_lc_calibrate(priv); + + fops->phy_iq_calibrate(priv); + + /* + * This should enable thermal meter + */ + if (fops->gen2_thermal_meter) { + if (priv->rtl_chip == RTL8188F || priv->rtl_chip == RTL8710B) { + val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_T_METER_8723B); + val32 |= 0x30000; + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER_8723B, val32); + } else { + rtl8xxxu_write_rfreg(priv, + RF_A, RF6052_REG_T_METER_8723B, 0x37cf8); + } + } else { + rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60); + } + + /* Set NAV_UPPER to 30000us */ + val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT); + rtl8xxxu_write8(priv, REG_NAV_UPPER, val8); + + if (priv->rtl_chip == RTL8723A) { + /* + * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test, + * but we need to find root cause. + * This is 8723au only. + */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); + if ((val32 & 0xff000000) != 0x83000000) { + val32 |= FPGA_RF_MODE_CCK; + rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); + } + } else if (priv->rtl_chip == RTL8192E || priv->rtl_chip == RTL8188E) { + rtl8xxxu_write8(priv, REG_USB_HRPWM, 0x00); + } + + val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL); + val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK; + /* ack for xmit mgmt frames. */ + rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32); + + if (priv->rtl_chip == RTL8192E) { + /* + * Fix LDPC rx hang issue. + */ + val32 = rtl8xxxu_read32(priv, REG_AFE_MISC); + rtl8xxxu_write8(priv, REG_8192E_LDOV12_CTRL, 0x75); + val32 &= 0xfff00fff; + val32 |= 0x0007e000; + rtl8xxxu_write32(priv, REG_AFE_MISC, val32); + + /* + * 0x824[9] = 0x82C[9] = 0xA80[7] those registers setting + * should be equal or CCK RSSI report may be incorrect + */ + val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2); + priv->cck_agc_report_type = + u32_get_bits(val32, FPGA0_HSSI_PARM2_CCK_HIGH_PWR); + + val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_HSSI_PARM2); + if (priv->cck_agc_report_type != + u32_get_bits(val32, FPGA0_HSSI_PARM2_CCK_HIGH_PWR)) { + if (priv->cck_agc_report_type) + val32 |= FPGA0_HSSI_PARM2_CCK_HIGH_PWR; + else + val32 &= ~FPGA0_HSSI_PARM2_CCK_HIGH_PWR; + rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM2, val32); + } + + val32 = rtl8xxxu_read32(priv, REG_AGC_RPT); + if (priv->cck_agc_report_type) + val32 |= AGC_RPT_CCK; + else + val32 &= ~AGC_RPT_CCK; + rtl8xxxu_write32(priv, REG_AGC_RPT, val32); + } + + if (priv->rtl_chip == RTL8710B) { + /* + * 0x76D[5:4] is Port0,Port1 Enable Bit. + * This is only for 8710B, 2b'00 for MP and 2b'11 for Normal Driver + */ + val8 = rtl8xxxu_read8(priv, REG_PORT_CONTROL_8710B); + val8 |= BIT(5) | BIT(4); + rtl8xxxu_write8(priv, REG_PORT_CONTROL_8710B, val8); + + /* Set 0x5c[8] and [2:0] = 1, LDO mode */ + val32 = rtl8xxxu_read32(priv, REG_WL_RF_PSS_8710B); + val32 |= 0x107; + rtl8xxxu_write32(priv, REG_WL_RF_PSS_8710B, val32); + } + + val32 = rtl8xxxu_read32(priv, 0xa9c); + priv->cck_new_agc = u32_get_bits(val32, BIT(17)); + + /* Initialise the center frequency offset tracking */ + if (priv->fops->set_crystal_cap) { + val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING); + priv->cfo_tracking.atc_status = val32 & CFO_TRACKING_ATC_STATUS; + priv->cfo_tracking.adjust = true; + priv->cfo_tracking.crystal_cap = priv->default_crystal_cap; + } + + if (priv->rtl_chip == RTL8188E) + rtl8188e_ra_info_init_all(&priv->ra_info); + + set_bit(RTL8XXXU_BC_MC_MACID, priv->mac_id_map); + set_bit(RTL8XXXU_BC_MC_MACID1, priv->mac_id_map); + +exit: + return ret; +} + +static void rtl8xxxu_cam_write(struct rtl8xxxu_priv *priv, + struct ieee80211_key_conf *key, const u8 *mac) +{ + u32 cmd, val32, addr, ctrl; + int j, i, tmp_debug; + + tmp_debug = rtl8xxxu_debug; + if (rtl8xxxu_debug & RTL8XXXU_DEBUG_KEY) + rtl8xxxu_debug |= RTL8XXXU_DEBUG_REG_WRITE; + + /* + * This is a bit of a hack - the lower bits of the cipher + * suite selector happens to match the cipher index in the CAM + */ + addr = key->hw_key_idx << CAM_CMD_KEY_SHIFT; + ctrl = (key->cipher & 0x0f) << 2 | key->keyidx | CAM_WRITE_VALID; + if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) + ctrl |= BIT(6); + + for (j = 5; j >= 0; j--) { + switch (j) { + case 0: + val32 = ctrl | (mac[0] << 16) | (mac[1] << 24); + break; + case 1: + val32 = mac[2] | (mac[3] << 8) | + (mac[4] << 16) | (mac[5] << 24); + break; + default: + i = (j - 2) << 2; + val32 = key->key[i] | (key->key[i + 1] << 8) | + key->key[i + 2] << 16 | key->key[i + 3] << 24; + break; + } + + rtl8xxxu_write32(priv, REG_CAM_WRITE, val32); + cmd = CAM_CMD_POLLING | CAM_CMD_WRITE | (addr + j); + rtl8xxxu_write32(priv, REG_CAM_CMD, cmd); + udelay(100); + } + + rtl8xxxu_debug = tmp_debug; +} + +static +int rtl8xxxu_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant) +{ + struct rtl8xxxu_priv *priv = hw->priv; + + *tx_ant = BIT(priv->tx_paths) - 1; + *rx_ant = BIT(priv->rx_paths) - 1; + + return 0; +} + +static int rtl8xxxu_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta, + bool set) +{ + struct rtl8xxxu_priv *priv = hw->priv; + + schedule_delayed_work(&priv->update_beacon_work, 0); + + return 0; +} + +static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, const u8 *mac) +{ + struct rtl8xxxu_priv *priv = hw->priv; + u8 val8; + + val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL); + val8 |= BEACON_DISABLE_TSF_UPDATE; + rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8); +} + +static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw, + struct ieee80211_vif *vif) +{ + struct rtl8xxxu_priv *priv = hw->priv; + u8 val8; + + val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL); + val8 &= ~BEACON_DISABLE_TSF_UPDATE; + rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8); +} + +void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv, + u32 ramask, u8 rateid, int sgi, int txbw_40mhz, + u8 macid) +{ + struct h2c_cmd h2c; + + memset(&h2c, 0, sizeof(struct h2c_cmd)); + + h2c.ramask.cmd = H2C_SET_RATE_MASK; + h2c.ramask.mask_lo = cpu_to_le16(ramask & 0xffff); + h2c.ramask.mask_hi = cpu_to_le16(ramask >> 16); + + h2c.ramask.arg = 0x80; + if (sgi) + h2c.ramask.arg |= 0x20; + + dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n", + __func__, ramask, h2c.ramask.arg, sizeof(h2c.ramask)); + rtl8xxxu_gen1_h2c_cmd(priv, &h2c, sizeof(h2c.ramask)); +} + +void rtl8xxxu_gen2_update_rate_mask(struct rtl8xxxu_priv *priv, + u32 ramask, u8 rateid, int sgi, int txbw_40mhz, + u8 macid) +{ + struct h2c_cmd h2c; + u8 bw; + + if (txbw_40mhz) + bw = RTL8XXXU_CHANNEL_WIDTH_40; + else + bw = RTL8XXXU_CHANNEL_WIDTH_20; + + memset(&h2c, 0, sizeof(struct h2c_cmd)); + + h2c.b_macid_cfg.cmd = H2C_8723B_MACID_CFG_RAID; + h2c.b_macid_cfg.ramask0 = ramask & 0xff; + h2c.b_macid_cfg.ramask1 = (ramask >> 8) & 0xff; + h2c.b_macid_cfg.ramask2 = (ramask >> 16) & 0xff; + h2c.b_macid_cfg.ramask3 = (ramask >> 24) & 0xff; + h2c.b_macid_cfg.macid = macid; + + h2c.b_macid_cfg.data1 = rateid; + if (sgi) + h2c.b_macid_cfg.data1 |= BIT(7); + + h2c.b_macid_cfg.data2 = bw; + + dev_dbg(&priv->udev->dev, "%s: rate mask %08x, rateid %02x, sgi %d, size %zi\n", + __func__, ramask, rateid, sgi, sizeof(h2c.b_macid_cfg)); + rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.b_macid_cfg)); +} + +void rtl8xxxu_gen1_report_connect(struct rtl8xxxu_priv *priv, + u8 macid, u8 role, bool connect) +{ + struct h2c_cmd h2c; + + memset(&h2c, 0, sizeof(struct h2c_cmd)); + + h2c.joinbss.cmd = H2C_JOIN_BSS_REPORT; + + if (connect) + h2c.joinbss.data = H2C_JOIN_BSS_CONNECT; + else + h2c.joinbss.data = H2C_JOIN_BSS_DISCONNECT; + + rtl8xxxu_gen1_h2c_cmd(priv, &h2c, sizeof(h2c.joinbss)); +} + +void rtl8xxxu_gen2_report_connect(struct rtl8xxxu_priv *priv, + u8 macid, u8 role, bool connect) +{ + /* + * The firmware turns on the rate control when it knows it's + * connected to a network. + */ + struct h2c_cmd h2c; + + memset(&h2c, 0, sizeof(struct h2c_cmd)); + + h2c.media_status_rpt.cmd = H2C_8723B_MEDIA_STATUS_RPT; + if (connect) + h2c.media_status_rpt.parm |= BIT(0); + else + h2c.media_status_rpt.parm &= ~BIT(0); + + h2c.media_status_rpt.parm |= ((role << 4) & 0xf0); + h2c.media_status_rpt.macid = macid; + + rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.media_status_rpt)); +} + +void rtl8xxxu_gen1_report_rssi(struct rtl8xxxu_priv *priv, u8 macid, u8 rssi) +{ + struct h2c_cmd h2c; + const int h2c_size = 4; + + memset(&h2c, 0, sizeof(struct h2c_cmd)); + + h2c.rssi_report.cmd = H2C_SET_RSSI; + h2c.rssi_report.macid = macid; + h2c.rssi_report.rssi = rssi; + + rtl8xxxu_gen1_h2c_cmd(priv, &h2c, h2c_size); +} + +void rtl8xxxu_gen2_report_rssi(struct rtl8xxxu_priv *priv, u8 macid, u8 rssi) +{ + struct h2c_cmd h2c; + int h2c_size = sizeof(h2c.rssi_report); + + if (priv->rtl_chip == RTL8723B) + h2c_size = 4; + + memset(&h2c, 0, sizeof(struct h2c_cmd)); + + h2c.rssi_report.cmd = H2C_8723B_RSSI_SETTING; + h2c.rssi_report.macid = macid; + h2c.rssi_report.rssi = rssi; + + rtl8xxxu_gen2_h2c_cmd(priv, &h2c, h2c_size); +} + +void rtl8xxxu_gen1_init_aggregation(struct rtl8xxxu_priv *priv) +{ + u8 agg_ctrl, usb_spec, page_thresh, timeout; + + usb_spec = rtl8xxxu_read8(priv, REG_USB_SPECIAL_OPTION); + usb_spec &= ~USB_SPEC_USB_AGG_ENABLE; + rtl8xxxu_write8(priv, REG_USB_SPECIAL_OPTION, usb_spec); + + agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL); + agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN; + + if (!rtl8xxxu_dma_aggregation) { + rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl); + return; + } + + agg_ctrl |= TRXDMA_CTRL_RXDMA_AGG_EN; + rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl); + + /* + * The number of packets we can take looks to be buffer size / 512 + * which matches the 512 byte rounding we have to do when de-muxing + * the packets. + * + * Sample numbers from the vendor driver: + * USB High-Speed mode values: + * RxAggBlockCount = 8 : 512 byte unit + * RxAggBlockTimeout = 6 + * RxAggPageCount = 48 : 128 byte unit + * RxAggPageTimeout = 4 or 6 (absolute time 34ms/(2^6)) + */ + + page_thresh = (priv->fops->rx_agg_buf_size / 512); + if (rtl8xxxu_dma_agg_pages >= 0) { + if (rtl8xxxu_dma_agg_pages <= page_thresh) + timeout = page_thresh; + else if (rtl8xxxu_dma_agg_pages <= 6) + dev_err(&priv->udev->dev, + "%s: dma_agg_pages=%i too small, minimum is 6\n", + __func__, rtl8xxxu_dma_agg_pages); + else + dev_err(&priv->udev->dev, + "%s: dma_agg_pages=%i larger than limit %i\n", + __func__, rtl8xxxu_dma_agg_pages, page_thresh); + } + rtl8xxxu_write8(priv, REG_RXDMA_AGG_PG_TH, page_thresh); + /* + * REG_RXDMA_AGG_PG_TH + 1 seems to be the timeout register on + * gen2 chips and rtl8188eu. The rtl8723au seems unhappy if we + * don't set it, so better set both. + */ + timeout = 4; + + if (rtl8xxxu_dma_agg_timeout >= 0) { + if (rtl8xxxu_dma_agg_timeout <= 127) + timeout = rtl8xxxu_dma_agg_timeout; + else + dev_err(&priv->udev->dev, + "%s: Invalid dma_agg_timeout: %i\n", + __func__, rtl8xxxu_dma_agg_timeout); + } + + rtl8xxxu_write8(priv, REG_RXDMA_AGG_PG_TH + 1, timeout); + rtl8xxxu_write8(priv, REG_USB_DMA_AGG_TO, timeout); + priv->rx_buf_aggregation = 1; +} + +static const struct ieee80211_rate rtl8xxxu_legacy_ratetable[] = { + {.bitrate = 10, .hw_value = 0x00,}, + {.bitrate = 20, .hw_value = 0x01,}, + {.bitrate = 55, .hw_value = 0x02,}, + {.bitrate = 110, .hw_value = 0x03,}, + {.bitrate = 60, .hw_value = 0x04,}, + {.bitrate = 90, .hw_value = 0x05,}, + {.bitrate = 120, .hw_value = 0x06,}, + {.bitrate = 180, .hw_value = 0x07,}, + {.bitrate = 240, .hw_value = 0x08,}, + {.bitrate = 360, .hw_value = 0x09,}, + {.bitrate = 480, .hw_value = 0x0a,}, + {.bitrate = 540, .hw_value = 0x0b,}, +}; + +static void rtl8xxxu_desc_to_mcsrate(u16 rate, u8 *mcs, u8 *nss) +{ + if (rate <= DESC_RATE_54M) + return; + + if (rate >= DESC_RATE_MCS0 && rate <= DESC_RATE_MCS15) { + if (rate < DESC_RATE_MCS8) + *nss = 1; + else + *nss = 2; + *mcs = rate - DESC_RATE_MCS0; + } +} + +static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg) +{ + struct ieee80211_hw *hw = priv->hw; + u32 val32; + u8 rate_idx = 0; + + rate_cfg &= RESPONSE_RATE_BITMAP_ALL; + + val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); + if (hw->conf.chandef.chan->band == NL80211_BAND_5GHZ) + val32 &= RESPONSE_RATE_RRSR_INIT_5G; + else + val32 &= RESPONSE_RATE_RRSR_INIT_2G; + val32 |= rate_cfg; + rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); + + dev_dbg(&priv->udev->dev, "%s: rates %08x\n", __func__, rate_cfg); + + if (rate_cfg) + rate_idx = __fls(rate_cfg); + + rtl8xxxu_write8(priv, REG_INIRTS_RATE_SEL, rate_idx); +} + +static u16 +rtl8xxxu_wireless_mode(struct ieee80211_hw *hw, struct ieee80211_sta *sta) +{ + u16 network_type = WIRELESS_MODE_UNKNOWN; + + if (hw->conf.chandef.chan->band == NL80211_BAND_5GHZ) { + if (sta->deflink.vht_cap.vht_supported) + network_type = WIRELESS_MODE_AC; + else if (sta->deflink.ht_cap.ht_supported) + network_type = WIRELESS_MODE_N_5G; + + network_type |= WIRELESS_MODE_A; + } else { + if (sta->deflink.vht_cap.vht_supported) + network_type = WIRELESS_MODE_AC; + else if (sta->deflink.ht_cap.ht_supported) + network_type = WIRELESS_MODE_N_24G; + + if (sta->deflink.supp_rates[0] <= 0xf) + network_type |= WIRELESS_MODE_B; + else if (sta->deflink.supp_rates[0] & 0xf) + network_type |= (WIRELESS_MODE_B | WIRELESS_MODE_G); + else + network_type |= WIRELESS_MODE_G; + } + + return network_type; +} + +static void rtl8xxxu_set_aifs(struct rtl8xxxu_priv *priv, u8 slot_time) +{ + u32 reg_edca_param[IEEE80211_NUM_ACS] = { + [IEEE80211_AC_VO] = REG_EDCA_VO_PARAM, + [IEEE80211_AC_VI] = REG_EDCA_VI_PARAM, + [IEEE80211_AC_BE] = REG_EDCA_BE_PARAM, + [IEEE80211_AC_BK] = REG_EDCA_BK_PARAM, + }; + u32 val32; + u16 wireless_mode = 0; + u8 aifs, aifsn, sifs; + int i; + + for (i = 0; i < ARRAY_SIZE(priv->vifs); i++) { + struct ieee80211_sta *sta; + + if (!priv->vifs[i]) + continue; + + rcu_read_lock(); + sta = ieee80211_find_sta(priv->vifs[i], priv->vifs[i]->bss_conf.bssid); + if (sta) + wireless_mode = rtl8xxxu_wireless_mode(priv->hw, sta); + rcu_read_unlock(); + + if (wireless_mode) + break; + } + + if (priv->hw->conf.chandef.chan->band == NL80211_BAND_5GHZ || + (wireless_mode & WIRELESS_MODE_N_24G)) + sifs = 16; + else + sifs = 10; + + for (i = 0; i < IEEE80211_NUM_ACS; i++) { + val32 = rtl8xxxu_read32(priv, reg_edca_param[i]); + + /* It was set in conf_tx. */ + aifsn = val32 & 0xff; + + /* aifsn not set yet or already fixed */ + if (aifsn < 2 || aifsn > 15) + continue; + + aifs = aifsn * slot_time + sifs; + + val32 &= ~0xff; + val32 |= aifs; + rtl8xxxu_write32(priv, reg_edca_param[i], val32); + } +} + +void rtl8xxxu_update_ra_report(struct rtl8xxxu_ra_report *rarpt, + u8 rate, u8 sgi, u8 bw) +{ + u8 mcs, nss; + + rarpt->txrate.flags = 0; + + if (rate <= DESC_RATE_54M) { + rarpt->txrate.legacy = rtl8xxxu_legacy_ratetable[rate].bitrate; + } else { + rtl8xxxu_desc_to_mcsrate(rate, &mcs, &nss); + rarpt->txrate.flags |= RATE_INFO_FLAGS_MCS; + + rarpt->txrate.mcs = mcs; + rarpt->txrate.nss = nss; + + if (sgi) + rarpt->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; + + rarpt->txrate.bw = bw; + } + + rarpt->bit_rate = cfg80211_calculate_bitrate(&rarpt->txrate); + rarpt->desc_rate = rate; +} + +static void +rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif, + struct ieee80211_bss_conf *bss_conf, u64 changed) +{ + struct rtl8xxxu_vif *rtlvif = (struct rtl8xxxu_vif *)vif->drv_priv; + struct rtl8xxxu_priv *priv = hw->priv; + struct device *dev = &priv->udev->dev; + struct rtl8xxxu_sta_info *sta_info; + struct ieee80211_sta *sta; + struct rtl8xxxu_ra_report *rarpt; + u8 val8, macid; + u32 val32; + + rarpt = &priv->ra_report; + + if (changed & BSS_CHANGED_ASSOC) { + dev_dbg(dev, "Changed ASSOC: %i!\n", vif->cfg.assoc); + + rtl8xxxu_set_linktype(priv, vif->type, rtlvif->port_num); + + if (vif->cfg.assoc) { + u32 ramask; + int sgi = 0; + u8 highest_rate; + u8 bw; + + rcu_read_lock(); + sta = ieee80211_find_sta(vif, bss_conf->bssid); + if (!sta) { + dev_info(dev, "%s: ASSOC no sta found\n", + __func__); + rcu_read_unlock(); + goto error; + } + macid = rtl8xxxu_get_macid(priv, sta); + + if (sta->deflink.ht_cap.ht_supported) + dev_info(dev, "%s: HT supported\n", __func__); + if (sta->deflink.vht_cap.vht_supported) + dev_info(dev, "%s: VHT supported\n", __func__); + + /* TODO: Set bits 28-31 for rate adaptive id */ + ramask = (sta->deflink.supp_rates[0] & 0xfff) | + sta->deflink.ht_cap.mcs.rx_mask[0] << 12 | + sta->deflink.ht_cap.mcs.rx_mask[1] << 20; + if (sta->deflink.ht_cap.cap & + (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20)) + sgi = 1; + + highest_rate = fls(ramask) - 1; + if (rtl8xxxu_ht40_2g && + (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)) + bw = RATE_INFO_BW_40; + else + bw = RATE_INFO_BW_20; + + sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv; + sta_info->rssi_level = RTL8XXXU_RATR_STA_INIT; + rcu_read_unlock(); + + rtl8xxxu_update_ra_report(rarpt, highest_rate, sgi, bw); + + priv->fops->update_rate_mask(priv, ramask, 0, sgi, + bw == RATE_INFO_BW_40, macid); + + rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff); + + if (rtlvif->port_num == 0) + rtl8xxxu_stop_tx_beacon(priv); + + /* joinbss sequence */ + rtl8xxxu_write16(priv, REG_BCN_PSR_RPT, + 0xc000 | vif->cfg.aid); + + priv->fops->report_connect(priv, 0, H2C_MACID_ROLE_AP, true); + } else { + val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL); + val8 |= BEACON_DISABLE_TSF_UPDATE; + rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8); + + priv->fops->report_connect(priv, 0, H2C_MACID_ROLE_AP, false); + } + } + + if (changed & BSS_CHANGED_ERP_PREAMBLE) { + dev_dbg(dev, "Changed ERP_PREAMBLE: Use short preamble %i\n", + bss_conf->use_short_preamble); + val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); + if (bss_conf->use_short_preamble) + val32 |= RSR_ACK_SHORT_PREAMBLE; + else + val32 &= ~RSR_ACK_SHORT_PREAMBLE; + rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); + } + + if (changed & BSS_CHANGED_ERP_SLOT) { + dev_dbg(dev, "Changed ERP_SLOT: short_slot_time %i\n", + bss_conf->use_short_slot); + + if (bss_conf->use_short_slot) + val8 = 9; + else + val8 = 20; + rtl8xxxu_write8(priv, REG_SLOT, val8); + + rtl8xxxu_set_aifs(priv, val8); + } + + if (changed & BSS_CHANGED_BSSID) { + dev_dbg(dev, "Changed BSSID!\n"); + rtl8xxxu_set_bssid(priv, bss_conf->bssid, rtlvif->port_num); + } + + if (changed & BSS_CHANGED_BASIC_RATES) { + dev_dbg(dev, "Changed BASIC_RATES!\n"); + rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates); + } + + if (changed & BSS_CHANGED_BEACON_ENABLED) { + if (bss_conf->enable_beacon) + rtl8xxxu_start_tx_beacon(priv); + else + rtl8xxxu_stop_tx_beacon(priv); + } + + if (changed & BSS_CHANGED_BEACON) + schedule_delayed_work(&priv->update_beacon_work, 0); + +error: + return; +} + +static int rtl8xxxu_start_ap(struct ieee80211_hw *hw, struct ieee80211_vif *vif, + struct ieee80211_bss_conf *link_conf) +{ + struct rtl8xxxu_vif *rtlvif = (struct rtl8xxxu_vif *)vif->drv_priv; + struct rtl8xxxu_priv *priv = hw->priv; + struct device *dev = &priv->udev->dev; + + dev_dbg(dev, "Start AP mode\n"); + rtl8xxxu_set_bssid(priv, vif->bss_conf.bssid, rtlvif->port_num); + rtl8xxxu_write16(priv, REG_BCN_INTERVAL, vif->bss_conf.beacon_int); + priv->fops->report_connect(priv, RTL8XXXU_BC_MC_MACID, 0, true); + + return 0; +} + +static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue) +{ + u32 rtlqueue; + + switch (queue) { + case IEEE80211_AC_VO: + rtlqueue = TXDESC_QUEUE_VO; + break; + case IEEE80211_AC_VI: + rtlqueue = TXDESC_QUEUE_VI; + break; + case IEEE80211_AC_BE: + rtlqueue = TXDESC_QUEUE_BE; + break; + case IEEE80211_AC_BK: + rtlqueue = TXDESC_QUEUE_BK; + break; + default: + rtlqueue = TXDESC_QUEUE_BE; + } + + return rtlqueue; +} + +static u32 rtl8xxxu_queue_select(struct ieee80211_hdr *hdr, struct sk_buff *skb) +{ + u32 queue; + + if (unlikely(ieee80211_is_beacon(hdr->frame_control))) + queue = TXDESC_QUEUE_BEACON; + else if (ieee80211_is_mgmt(hdr->frame_control)) + queue = TXDESC_QUEUE_MGNT; + else + queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb)); + + return queue; +} + +/* + * Despite newer chips 8723b/8812/8821 having a larger TX descriptor + * format. The descriptor checksum is still only calculated over the + * initial 32 bytes of the descriptor! + */ +static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_txdesc32 *tx_desc) +{ + __le16 *ptr = (__le16 *)tx_desc; + u16 csum = 0; + int i; + + /* + * Clear csum field before calculation, as the csum field is + * in the middle of the struct. + */ + tx_desc->csum = cpu_to_le16(0); + + for (i = 0; i < (sizeof(struct rtl8xxxu_txdesc32) / sizeof(u16)); i++) + csum = csum ^ le16_to_cpu(ptr[i]); + + tx_desc->csum |= cpu_to_le16(csum); +} + +static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv *priv) +{ + struct rtl8xxxu_tx_urb *tx_urb, *tmp; + unsigned long flags; + + spin_lock_irqsave(&priv->tx_urb_lock, flags); + list_for_each_entry_safe(tx_urb, tmp, &priv->tx_urb_free_list, list) { + list_del(&tx_urb->list); + priv->tx_urb_free_count--; + usb_free_urb(&tx_urb->urb); + } + spin_unlock_irqrestore(&priv->tx_urb_lock, flags); +} + +static struct rtl8xxxu_tx_urb * +rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv *priv) +{ + struct rtl8xxxu_tx_urb *tx_urb; + unsigned long flags; + + spin_lock_irqsave(&priv->tx_urb_lock, flags); + tx_urb = list_first_entry_or_null(&priv->tx_urb_free_list, + struct rtl8xxxu_tx_urb, list); + if (tx_urb) { + list_del(&tx_urb->list); + priv->tx_urb_free_count--; + if (priv->tx_urb_free_count < RTL8XXXU_TX_URB_LOW_WATER && + !priv->tx_stopped) { + priv->tx_stopped = true; + ieee80211_stop_queues(priv->hw); + } + } + + spin_unlock_irqrestore(&priv->tx_urb_lock, flags); + + return tx_urb; +} + +static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv *priv, + struct rtl8xxxu_tx_urb *tx_urb) +{ + unsigned long flags; + + INIT_LIST_HEAD(&tx_urb->list); + + spin_lock_irqsave(&priv->tx_urb_lock, flags); + + list_add(&tx_urb->list, &priv->tx_urb_free_list); + priv->tx_urb_free_count++; + if (priv->tx_urb_free_count > RTL8XXXU_TX_URB_HIGH_WATER && + priv->tx_stopped) { + priv->tx_stopped = false; + ieee80211_wake_queues(priv->hw); + } + + spin_unlock_irqrestore(&priv->tx_urb_lock, flags); +} + +static void rtl8xxxu_tx_complete(struct urb *urb) +{ + struct sk_buff *skb = (struct sk_buff *)urb->context; + struct ieee80211_tx_info *tx_info; + struct ieee80211_hw *hw; + struct rtl8xxxu_priv *priv; + struct rtl8xxxu_tx_urb *tx_urb = + container_of(urb, struct rtl8xxxu_tx_urb, urb); + + tx_info = IEEE80211_SKB_CB(skb); + hw = tx_info->rate_driver_data[0]; + priv = hw->priv; + + skb_pull(skb, priv->fops->tx_desc_size); + + ieee80211_tx_info_clear_status(tx_info); + tx_info->status.rates[0].idx = -1; + tx_info->status.rates[0].count = 0; + + if (!urb->status) + tx_info->flags |= IEEE80211_TX_STAT_ACK; + + ieee80211_tx_status_irqsafe(hw, skb); + + rtl8xxxu_free_tx_urb(priv, tx_urb); +} + +static void rtl8xxxu_dump_action(struct device *dev, + struct ieee80211_hdr *hdr) +{ + struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr; + u16 cap, timeout; + + if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION)) + return; + + switch (mgmt->u.action.u.addba_resp.action_code) { + case WLAN_ACTION_ADDBA_RESP: + cap = le16_to_cpu(mgmt->u.action.u.addba_resp.capab); + timeout = le16_to_cpu(mgmt->u.action.u.addba_resp.timeout); + dev_info(dev, "WLAN_ACTION_ADDBA_RESP: " + "timeout %i, tid %02x, buf_size %02x, policy %02x, " + "status %02x\n", + timeout, + (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2, + (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6, + (cap >> 1) & 0x1, + le16_to_cpu(mgmt->u.action.u.addba_resp.status)); + break; + case WLAN_ACTION_ADDBA_REQ: + cap = le16_to_cpu(mgmt->u.action.u.addba_req.capab); + timeout = le16_to_cpu(mgmt->u.action.u.addba_req.timeout); + dev_info(dev, "WLAN_ACTION_ADDBA_REQ: " + "timeout %i, tid %02x, buf_size %02x, policy %02x\n", + timeout, + (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2, + (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6, + (cap >> 1) & 0x1); + break; + default: + dev_info(dev, "action frame %02x\n", + mgmt->u.action.u.addba_resp.action_code); + break; + } +} + +/* + * Fill in v1 (gen1) specific TX descriptor bits. + * This format is used on 8188cu/8192cu/8723au + */ +void +rtl8xxxu_fill_txdesc_v1(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, + struct ieee80211_tx_info *tx_info, + struct rtl8xxxu_txdesc32 *tx_desc, bool sgi, + bool short_preamble, bool ampdu_enable, u32 rts_rate, + u8 macid) +{ + struct rtl8xxxu_priv *priv = hw->priv; + struct device *dev = &priv->udev->dev; + u8 *qc = ieee80211_get_qos_ctl(hdr); + u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK; + u32 rate = 0; + u16 seq_number; + + if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX) + dev_info(dev, "%s: TX rate: %d, pkt size %u\n", + __func__, rate, le16_to_cpu(tx_desc->pkt_size)); + + seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); + + tx_desc->txdw5 = cpu_to_le32(rate); + + if (ieee80211_is_data(hdr->frame_control)) + tx_desc->txdw5 |= cpu_to_le32(0x0001ff00); + + tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC32_SEQ_SHIFT); + + if (ampdu_enable && test_bit(tid, priv->tid_tx_operational)) + tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_ENABLE); + else + tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_BREAK); + + if (ieee80211_is_mgmt(hdr->frame_control)) { + tx_desc->txdw5 = cpu_to_le32(rate); + tx_desc->txdw4 |= cpu_to_le32(TXDESC32_USE_DRIVER_RATE); + tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC32_RETRY_LIMIT_SHIFT); + tx_desc->txdw5 |= cpu_to_le32(TXDESC32_RETRY_LIMIT_ENABLE); + } + + if (ieee80211_is_data_qos(hdr->frame_control)) + tx_desc->txdw4 |= cpu_to_le32(TXDESC32_QOS); + + if (short_preamble) + tx_desc->txdw4 |= cpu_to_le32(TXDESC32_SHORT_PREAMBLE); + + if (sgi) + tx_desc->txdw5 |= cpu_to_le32(TXDESC32_SHORT_GI); + + /* + * rts_rate is zero if RTS/CTS or CTS to SELF are not enabled + */ + tx_desc->txdw4 |= cpu_to_le32(rts_rate << TXDESC32_RTS_RATE_SHIFT); + if (ampdu_enable || tx_info->control.use_rts) { + tx_desc->txdw4 |= cpu_to_le32(TXDESC32_RTS_CTS_ENABLE); + tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE); + } else if (tx_info->control.use_cts_prot) { + tx_desc->txdw4 |= cpu_to_le32(TXDESC32_CTS_SELF_ENABLE); + tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE); + } +} + +/* + * Fill in v2 (gen2) specific TX descriptor bits. + * This format is used on 8192eu/8723bu + */ +void +rtl8xxxu_fill_txdesc_v2(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, + struct ieee80211_tx_info *tx_info, + struct rtl8xxxu_txdesc32 *tx_desc32, bool sgi, + bool short_preamble, bool ampdu_enable, u32 rts_rate, + u8 macid) +{ + struct rtl8xxxu_priv *priv = hw->priv; + struct device *dev = &priv->udev->dev; + struct rtl8xxxu_txdesc40 *tx_desc40; + u8 *qc = ieee80211_get_qos_ctl(hdr); + u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK; + u32 rate = 0; + u16 seq_number; + + tx_desc40 = (struct rtl8xxxu_txdesc40 *)tx_desc32; + + if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX) + dev_info(dev, "%s: TX rate: %d, pkt size %u\n", + __func__, rate, le16_to_cpu(tx_desc40->pkt_size)); + + tx_desc40->txdw1 |= cpu_to_le32(macid << TXDESC40_MACID_SHIFT); + + seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); + + tx_desc40->txdw4 = cpu_to_le32(rate); + if (ieee80211_is_data(hdr->frame_control)) { + tx_desc40->txdw4 |= cpu_to_le32(0x1f << + TXDESC40_DATA_RATE_FB_SHIFT); + } + + tx_desc40->txdw9 = cpu_to_le32((u32)seq_number << TXDESC40_SEQ_SHIFT); + + if (ampdu_enable && test_bit(tid, priv->tid_tx_operational)) + tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_ENABLE); + else + tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_BREAK); + + if (ieee80211_is_mgmt(hdr->frame_control)) { + tx_desc40->txdw4 = cpu_to_le32(rate); + tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_USE_DRIVER_RATE); + tx_desc40->txdw4 |= + cpu_to_le32(6 << TXDESC40_RETRY_LIMIT_SHIFT); + tx_desc40->txdw4 |= cpu_to_le32(TXDESC40_RETRY_LIMIT_ENABLE); + } + + if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) + tx_desc40->txdw8 |= cpu_to_le32(TXDESC40_HW_SEQ_ENABLE); + + if (short_preamble) + tx_desc40->txdw5 |= cpu_to_le32(TXDESC40_SHORT_PREAMBLE); + + tx_desc40->txdw4 |= cpu_to_le32(rts_rate << TXDESC40_RTS_RATE_SHIFT); + + /* + * rts_rate is zero if RTS/CTS or CTS to SELF are not enabled + */ + if (ampdu_enable || tx_info->control.use_rts) { + tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_RTS_CTS_ENABLE); + tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_HW_RTS_ENABLE); + } else if (tx_info->control.use_cts_prot) { + /* + * For some reason the vendor driver doesn't set + * TXDESC40_HW_RTS_ENABLE for CTS to SELF + */ + tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_CTS_SELF_ENABLE); + } +} + +/* + * Fill in v3 (gen1) specific TX descriptor bits. + * This format is a hybrid between the v1 and v2 formats, only seen + * on 8188eu devices so far. + */ +void +rtl8xxxu_fill_txdesc_v3(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, + struct ieee80211_tx_info *tx_info, + struct rtl8xxxu_txdesc32 *tx_desc, bool sgi, + bool short_preamble, bool ampdu_enable, u32 rts_rate, + u8 macid) +{ + struct rtl8xxxu_priv *priv = hw->priv; + struct device *dev = &priv->udev->dev; + struct rtl8xxxu_ra_info *ra = &priv->ra_info; + u8 *qc = ieee80211_get_qos_ctl(hdr); + u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK; + u32 rate = 0; + u16 seq_number; + + seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); + + if (ieee80211_is_data(hdr->frame_control)) { + rate = ra->decision_rate; + tx_desc->txdw5 = cpu_to_le32(rate); + tx_desc->txdw4 |= cpu_to_le32(TXDESC32_USE_DRIVER_RATE); + tx_desc->txdw4 |= le32_encode_bits(ra->pt_stage, TXDESC32_PT_STAGE_MASK); + /* Data/RTS rate FB limit */ + tx_desc->txdw5 |= cpu_to_le32(0x0001ff00); + } + + if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX) + dev_info(dev, "%s: TX rate: %d, pkt size %d\n", + __func__, rate, le16_to_cpu(tx_desc->pkt_size)); + + tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC32_SEQ_SHIFT); + + if (ampdu_enable && test_bit(tid, priv->tid_tx_operational)) + tx_desc->txdw2 |= cpu_to_le32(TXDESC40_AGG_ENABLE); + else + tx_desc->txdw2 |= cpu_to_le32(TXDESC40_AGG_BREAK); + + if (ieee80211_is_mgmt(hdr->frame_control)) { + tx_desc->txdw5 = cpu_to_le32(rate); + tx_desc->txdw4 |= cpu_to_le32(TXDESC32_USE_DRIVER_RATE); + tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC32_RETRY_LIMIT_SHIFT); + tx_desc->txdw5 |= cpu_to_le32(TXDESC32_RETRY_LIMIT_ENABLE); + } + + if (ieee80211_is_data_qos(hdr->frame_control)) { + tx_desc->txdw4 |= cpu_to_le32(TXDESC32_QOS); + + if (conf_is_ht40(&hw->conf)) { + tx_desc->txdw4 |= cpu_to_le32(TXDESC_DATA_BW); + + if (conf_is_ht40_minus(&hw->conf)) + tx_desc->txdw4 |= cpu_to_le32(TXDESC_PRIME_CH_OFF_UPPER); + else + tx_desc->txdw4 |= cpu_to_le32(TXDESC_PRIME_CH_OFF_LOWER); + } + } + + if (short_preamble) + tx_desc->txdw4 |= cpu_to_le32(TXDESC32_SHORT_PREAMBLE); + + if (sgi && ra->rate_sgi) + tx_desc->txdw5 |= cpu_to_le32(TXDESC32_SHORT_GI); + + /* + * rts_rate is zero if RTS/CTS or CTS to SELF are not enabled + */ + tx_desc->txdw4 |= cpu_to_le32(rts_rate << TXDESC32_RTS_RATE_SHIFT); + if (ampdu_enable || tx_info->control.use_rts) { + tx_desc->txdw4 |= cpu_to_le32(TXDESC32_RTS_CTS_ENABLE); + tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE); + } else if (tx_info->control.use_cts_prot) { + tx_desc->txdw4 |= cpu_to_le32(TXDESC32_CTS_SELF_ENABLE); + tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE); + } + + tx_desc->txdw2 |= cpu_to_le32(TXDESC_ANTENNA_SELECT_A | + TXDESC_ANTENNA_SELECT_B); + tx_desc->txdw7 |= cpu_to_le16(TXDESC_ANTENNA_SELECT_C >> 16); +} + +static void rtl8xxxu_tx(struct ieee80211_hw *hw, + struct ieee80211_tx_control *control, + struct sk_buff *skb) +{ + struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; + struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); + struct rtl8xxxu_priv *priv = hw->priv; + struct rtl8xxxu_txdesc32 *tx_desc; + struct rtl8xxxu_tx_urb *tx_urb; + struct ieee80211_sta *sta = NULL; + struct ieee80211_vif *vif = tx_info->control.vif; + struct rtl8xxxu_vif *rtlvif = vif ? (struct rtl8xxxu_vif *)vif->drv_priv : NULL; + struct device *dev = &priv->udev->dev; + u32 queue, rts_rate; + u16 pktlen = skb->len; + int tx_desc_size = priv->fops->tx_desc_size; + u8 macid; + int ret; + bool ampdu_enable, sgi = false, short_preamble = false, bmc = false; + + if (skb_headroom(skb) < tx_desc_size) { + dev_warn(dev, + "%s: Not enough headroom (%i) for tx descriptor\n", + __func__, skb_headroom(skb)); + goto error; + } + + if (unlikely(skb->len > (65535 - tx_desc_size))) { + dev_warn(dev, "%s: Trying to send over-sized skb (%i)\n", + __func__, skb->len); + goto error; + } + + tx_urb = rtl8xxxu_alloc_tx_urb(priv); + if (!tx_urb) { + dev_warn(dev, "%s: Unable to allocate tx urb\n", __func__); + goto error; + } + + if (ieee80211_is_action(hdr->frame_control)) + rtl8xxxu_dump_action(dev, hdr); + + tx_info->rate_driver_data[0] = hw; + + if (control && control->sta) + sta = control->sta; + + queue = rtl8xxxu_queue_select(hdr, skb); + + tx_desc = skb_push(skb, tx_desc_size); + + memset(tx_desc, 0, tx_desc_size); + tx_desc->pkt_size = cpu_to_le16(pktlen); + tx_desc->pkt_offset = tx_desc_size; + + /* These bits mean different things to the RTL8192F. */ + if (priv->rtl_chip != RTL8192F) + tx_desc->txdw0 = + TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT; + if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) || + is_broadcast_ether_addr(ieee80211_get_DA(hdr))) { + tx_desc->txdw0 |= TXDESC_BROADMULTICAST; + bmc = true; + } + + + tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT); + macid = rtl8xxxu_get_macid(priv, sta); + + if (tx_info->control.hw_key) { + switch (tx_info->control.hw_key->cipher) { + case WLAN_CIPHER_SUITE_WEP40: + case WLAN_CIPHER_SUITE_WEP104: + case WLAN_CIPHER_SUITE_TKIP: + tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4); + break; + case WLAN_CIPHER_SUITE_CCMP: + tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES); + break; + default: + break; + } + if (bmc && rtlvif && rtlvif->hw_key_idx != 0xff) { + tx_desc->txdw1 |= cpu_to_le32(TXDESC_EN_DESC_ID); + macid = rtlvif->hw_key_idx; + } + } + + /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */ + ampdu_enable = false; + if (ieee80211_is_data_qos(hdr->frame_control) && sta) { + if (sta->deflink.ht_cap.ht_supported) { + u32 ampdu, val32; + u8 *qc = ieee80211_get_qos_ctl(hdr); + u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK; + + ampdu = (u32)sta->deflink.ht_cap.ampdu_density; + val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT; + tx_desc->txdw2 |= cpu_to_le32(val32); + + ampdu_enable = true; + + if (!test_bit(tid, priv->tx_aggr_started) && + !(skb->protocol == cpu_to_be16(ETH_P_PAE))) + if (!ieee80211_start_tx_ba_session(sta, tid, 0)) + set_bit(tid, priv->tx_aggr_started); + } + } + + if (ieee80211_is_data_qos(hdr->frame_control) && + sta && sta->deflink.ht_cap.cap & + (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20)) + sgi = true; + + if (sta && vif && vif->bss_conf.use_short_preamble) + short_preamble = true; + + if (skb->len > hw->wiphy->rts_threshold) + tx_info->control.use_rts = true; + + if (sta && vif && vif->bss_conf.use_cts_prot) + tx_info->control.use_cts_prot = true; + + if (ampdu_enable || tx_info->control.use_rts || + tx_info->control.use_cts_prot) + rts_rate = DESC_RATE_24M; + else + rts_rate = 0; + + priv->fops->fill_txdesc(hw, hdr, tx_info, tx_desc, sgi, short_preamble, + ampdu_enable, rts_rate, macid); + + rtl8xxxu_calc_tx_desc_csum(tx_desc); + + /* avoid zero checksum make tx hang */ + if (priv->rtl_chip == RTL8710B || priv->rtl_chip == RTL8192F) + tx_desc->csum = ~tx_desc->csum; + + usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue], + skb->data, skb->len, rtl8xxxu_tx_complete, skb); + + usb_anchor_urb(&tx_urb->urb, &priv->tx_anchor); + ret = usb_submit_urb(&tx_urb->urb, GFP_ATOMIC); + if (ret) { + usb_unanchor_urb(&tx_urb->urb); + rtl8xxxu_free_tx_urb(priv, tx_urb); + goto error; + } + return; +error: + dev_kfree_skb(skb); +} + +static void rtl8xxxu_send_beacon_frame(struct ieee80211_hw *hw, + struct ieee80211_vif *vif) +{ + struct rtl8xxxu_priv *priv = hw->priv; + struct sk_buff *skb = ieee80211_beacon_get(hw, vif, 0); + struct device *dev = &priv->udev->dev; + int retry; + u8 val8; + + /* BCN_VALID, write 1 to clear, cleared by SW */ + val8 = rtl8xxxu_read8(priv, REG_TDECTRL + 2); + val8 |= BIT_BCN_VALID >> 16; + rtl8xxxu_write8(priv, REG_TDECTRL + 2, val8); + + /* SW_BCN_SEL - Port0 */ + val8 = rtl8xxxu_read8(priv, REG_DWBCN1_CTRL_8723B + 2); + val8 &= ~(BIT_SW_BCN_SEL >> 16); + rtl8xxxu_write8(priv, REG_DWBCN1_CTRL_8723B + 2, val8); + + if (skb) + rtl8xxxu_tx(hw, NULL, skb); + + retry = 100; + do { + val8 = rtl8xxxu_read8(priv, REG_TDECTRL + 2); + if (val8 & (BIT_BCN_VALID >> 16)) + break; + usleep_range(10, 20); + } while (--retry); + + if (!retry) + dev_err(dev, "%s: Failed to read beacon valid bit\n", __func__); +} + +static void rtl8xxxu_update_beacon_work_callback(struct work_struct *work) +{ + struct rtl8xxxu_priv *priv = + container_of(work, struct rtl8xxxu_priv, update_beacon_work.work); + struct ieee80211_hw *hw = priv->hw; + struct ieee80211_vif *vif = priv->vifs[0]; + + if (!vif) { + WARN_ONCE(true, "no vif to update beacon\n"); + return; + } + + if (vif->bss_conf.csa_active) { + if (ieee80211_beacon_cntdwn_is_complete(vif, 0)) { + ieee80211_csa_finish(vif, 0); + return; + } + schedule_delayed_work(&priv->update_beacon_work, + msecs_to_jiffies(vif->bss_conf.beacon_int)); + } + rtl8xxxu_send_beacon_frame(hw, vif); +} + +static inline bool rtl8xxxu_is_packet_match_bssid(struct rtl8xxxu_priv *priv, + struct ieee80211_hdr *hdr, + int port_num) +{ + return priv->vifs[port_num] && + priv->vifs[port_num]->type == NL80211_IFTYPE_STATION && + priv->vifs[port_num]->cfg.assoc && + ether_addr_equal(priv->vifs[port_num]->bss_conf.bssid, hdr->addr2); +} + +static inline bool rtl8xxxu_is_sta_sta(struct rtl8xxxu_priv *priv) +{ + return (priv->vifs[0] && priv->vifs[0]->cfg.assoc && + priv->vifs[0]->type == NL80211_IFTYPE_STATION) && + (priv->vifs[1] && priv->vifs[1]->cfg.assoc && + priv->vifs[1]->type == NL80211_IFTYPE_STATION); +} + +void rtl8723au_rx_parse_phystats(struct rtl8xxxu_priv *priv, + struct ieee80211_rx_status *rx_status, + struct rtl8723au_phy_stats *phy_stats, + u32 rxmcs, struct ieee80211_hdr *hdr, + bool crc_icv_err) +{ + if (phy_stats->sgi_en) + rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; + + if (rxmcs < DESC_RATE_6M) { + /* + * Handle PHY stats for CCK rates + */ + rx_status->signal = priv->fops->cck_rssi(priv, phy_stats); + } else { + bool parse_cfo = priv->fops->set_crystal_cap && + !crc_icv_err && + !ieee80211_is_ctl(hdr->frame_control) && + !rtl8xxxu_is_sta_sta(priv) && + (rtl8xxxu_is_packet_match_bssid(priv, hdr, 0) || + rtl8xxxu_is_packet_match_bssid(priv, hdr, 1)); + + if (parse_cfo) { + priv->cfo_tracking.cfo_tail[0] = phy_stats->path_cfotail[0]; + priv->cfo_tracking.cfo_tail[1] = phy_stats->path_cfotail[1]; + + priv->cfo_tracking.packet_count++; + } + + rx_status->signal = + (phy_stats->cck_sig_qual_ofdm_pwdb_all >> 1) - 110; + } +} + +static void jaguar2_rx_parse_phystats_type0(struct rtl8xxxu_priv *priv, + struct ieee80211_rx_status *rx_status, + struct jaguar2_phy_stats_type0 *phy_stats0, + u32 rxmcs, struct ieee80211_hdr *hdr, + bool crc_icv_err) +{ + s8 rx_power = phy_stats0->pwdb - 110; + + if (!priv->cck_new_agc) + rx_power = priv->fops->cck_rssi(priv, (struct rtl8723au_phy_stats *)phy_stats0); + + rx_status->signal = rx_power; +} + +static void jaguar2_rx_parse_phystats_type1(struct rtl8xxxu_priv *priv, + struct ieee80211_rx_status *rx_status, + struct jaguar2_phy_stats_type1 *phy_stats1, + u32 rxmcs, struct ieee80211_hdr *hdr, + bool crc_icv_err) +{ + bool parse_cfo = priv->fops->set_crystal_cap && + !crc_icv_err && + !ieee80211_is_ctl(hdr->frame_control) && + !rtl8xxxu_is_sta_sta(priv) && + (rtl8xxxu_is_packet_match_bssid(priv, hdr, 0) || + rtl8xxxu_is_packet_match_bssid(priv, hdr, 1)); + u8 pwdb_max = 0; + int rx_path; + + if (parse_cfo) { + /* Only path-A and path-B have CFO tail and short CFO */ + priv->cfo_tracking.cfo_tail[RF_A] = phy_stats1->cfo_tail[RF_A]; + priv->cfo_tracking.cfo_tail[RF_B] = phy_stats1->cfo_tail[RF_B]; + + priv->cfo_tracking.packet_count++; + } + + for (rx_path = 0; rx_path < priv->rx_paths; rx_path++) + pwdb_max = max(pwdb_max, phy_stats1->pwdb[rx_path]); + + rx_status->signal = pwdb_max - 110; +} + +static void jaguar2_rx_parse_phystats_type2(struct rtl8xxxu_priv *priv, + struct ieee80211_rx_status *rx_status, + struct jaguar2_phy_stats_type2 *phy_stats2, + u32 rxmcs, struct ieee80211_hdr *hdr, + bool crc_icv_err) +{ + u8 pwdb_max = 0; + int rx_path; + + for (rx_path = 0; rx_path < priv->rx_paths; rx_path++) + pwdb_max = max(pwdb_max, phy_stats2->pwdb[rx_path]); + + rx_status->signal = pwdb_max - 110; +} + +void jaguar2_rx_parse_phystats(struct rtl8xxxu_priv *priv, + struct ieee80211_rx_status *rx_status, + struct rtl8723au_phy_stats *phy_stats, + u32 rxmcs, struct ieee80211_hdr *hdr, + bool crc_icv_err) +{ + struct jaguar2_phy_stats_type0 *phy_stats0 = (struct jaguar2_phy_stats_type0 *)phy_stats; + struct jaguar2_phy_stats_type1 *phy_stats1 = (struct jaguar2_phy_stats_type1 *)phy_stats; + struct jaguar2_phy_stats_type2 *phy_stats2 = (struct jaguar2_phy_stats_type2 *)phy_stats; + + switch (phy_stats0->page_num) { + case 0: + /* CCK */ + jaguar2_rx_parse_phystats_type0(priv, rx_status, phy_stats0, + rxmcs, hdr, crc_icv_err); + break; + case 1: + /* OFDM */ + jaguar2_rx_parse_phystats_type1(priv, rx_status, phy_stats1, + rxmcs, hdr, crc_icv_err); + break; + case 2: + /* Also OFDM but different (how?) */ + jaguar2_rx_parse_phystats_type2(priv, rx_status, phy_stats2, + rxmcs, hdr, crc_icv_err); + break; + default: + return; + } +} + +static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv *priv) +{ + struct rtl8xxxu_rx_urb *rx_urb, *tmp; + unsigned long flags; + + spin_lock_irqsave(&priv->rx_urb_lock, flags); + + list_for_each_entry_safe(rx_urb, tmp, + &priv->rx_urb_pending_list, list) { + list_del(&rx_urb->list); + priv->rx_urb_pending_count--; + usb_free_urb(&rx_urb->urb); + } + + spin_unlock_irqrestore(&priv->rx_urb_lock, flags); +} + +static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv, + struct rtl8xxxu_rx_urb *rx_urb) +{ + struct sk_buff *skb; + unsigned long flags; + int pending = 0; + + spin_lock_irqsave(&priv->rx_urb_lock, flags); + + if (!priv->shutdown) { + list_add_tail(&rx_urb->list, &priv->rx_urb_pending_list); + priv->rx_urb_pending_count++; + pending = priv->rx_urb_pending_count; + } else { + skb = (struct sk_buff *)rx_urb->urb.context; + dev_kfree_skb_irq(skb); + usb_free_urb(&rx_urb->urb); + } + + spin_unlock_irqrestore(&priv->rx_urb_lock, flags); + + if (pending > RTL8XXXU_RX_URB_PENDING_WATER) + schedule_work(&priv->rx_urb_wq); +} + +static void rtl8xxxu_rx_urb_work(struct work_struct *work) +{ + struct rtl8xxxu_priv *priv; + struct rtl8xxxu_rx_urb *rx_urb, *tmp; + struct list_head local; + struct sk_buff *skb; + unsigned long flags; + int ret; + + priv = container_of(work, struct rtl8xxxu_priv, rx_urb_wq); + INIT_LIST_HEAD(&local); + + spin_lock_irqsave(&priv->rx_urb_lock, flags); + + list_splice_init(&priv->rx_urb_pending_list, &local); + priv->rx_urb_pending_count = 0; + + spin_unlock_irqrestore(&priv->rx_urb_lock, flags); + + list_for_each_entry_safe(rx_urb, tmp, &local, list) { + list_del_init(&rx_urb->list); + ret = rtl8xxxu_submit_rx_urb(priv, rx_urb); + /* + * If out of memory or temporary error, put it back on the + * queue and try again. Otherwise the device is dead/gone + * and we should drop it. + */ + switch (ret) { + case 0: + break; + case -ENOMEM: + case -EAGAIN: + rtl8xxxu_queue_rx_urb(priv, rx_urb); + break; + default: + dev_warn(&priv->udev->dev, + "failed to requeue urb with error %i\n", ret); + skb = (struct sk_buff *)rx_urb->urb.context; + dev_kfree_skb(skb); + usb_free_urb(&rx_urb->urb); + } + } +} + +/* + * The RTL8723BU/RTL8192EU vendor driver use coexistence table type + * 0-7 to represent writing different combinations of register values + * to REG_BT_COEX_TABLEs. It's for different kinds of coexistence use + * cases which Realtek doesn't provide detail for these settings. Keep + * this aligned with vendor driver for easier maintenance. + */ +static +void rtl8723bu_set_coex_with_type(struct rtl8xxxu_priv *priv, u8 type) +{ + switch (type) { + case 0: + rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555); + rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x55555555); + rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); + rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); + break; + case 1: + case 3: + rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555); + rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x5a5a5a5a); + rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); + rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); + break; + case 2: + rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x5a5a5a5a); + rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x5a5a5a5a); + rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); + rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); + break; + case 4: + rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x5a5a5a5a); + rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaaaa5a5a); + rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); + rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); + break; + case 5: + rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x5a5a5a5a); + rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaa5a5a5a); + rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); + rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); + break; + case 6: + rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555); + rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaaaaaaaa); + rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); + rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); + break; + case 7: + rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0xaaaaaaaa); + rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaaaaaaaa); + rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); + rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); + break; + default: + break; + } +} + +static +void rtl8723bu_update_bt_link_info(struct rtl8xxxu_priv *priv, u8 bt_info) +{ + struct rtl8xxxu_btcoex *btcoex = &priv->bt_coex; + + if (bt_info & BT_INFO_8723B_1ANT_B_INQ_PAGE) + btcoex->c2h_bt_inquiry = true; + else + btcoex->c2h_bt_inquiry = false; + + if (!(bt_info & BT_INFO_8723B_1ANT_B_CONNECTION)) { + btcoex->bt_status = BT_8723B_1ANT_STATUS_NON_CONNECTED_IDLE; + btcoex->has_sco = false; + btcoex->has_hid = false; + btcoex->has_pan = false; + btcoex->has_a2dp = false; + } else { + if ((bt_info & 0x1f) == BT_INFO_8723B_1ANT_B_CONNECTION) + btcoex->bt_status = BT_8723B_1ANT_STATUS_CONNECTED_IDLE; + else if ((bt_info & BT_INFO_8723B_1ANT_B_SCO_ESCO) || + (bt_info & BT_INFO_8723B_1ANT_B_SCO_BUSY)) + btcoex->bt_status = BT_8723B_1ANT_STATUS_SCO_BUSY; + else if (bt_info & BT_INFO_8723B_1ANT_B_ACL_BUSY) + btcoex->bt_status = BT_8723B_1ANT_STATUS_ACL_BUSY; + else + btcoex->bt_status = BT_8723B_1ANT_STATUS_MAX; + + if (bt_info & BT_INFO_8723B_1ANT_B_FTP) + btcoex->has_pan = true; + else + btcoex->has_pan = false; + + if (bt_info & BT_INFO_8723B_1ANT_B_A2DP) + btcoex->has_a2dp = true; + else + btcoex->has_a2dp = false; + + if (bt_info & BT_INFO_8723B_1ANT_B_HID) + btcoex->has_hid = true; + else + btcoex->has_hid = false; + + if (bt_info & BT_INFO_8723B_1ANT_B_SCO_ESCO) + btcoex->has_sco = true; + else + btcoex->has_sco = false; + } + + if (!btcoex->has_a2dp && !btcoex->has_sco && + !btcoex->has_pan && btcoex->has_hid) + btcoex->hid_only = true; + else + btcoex->hid_only = false; + + if (!btcoex->has_sco && !btcoex->has_pan && + !btcoex->has_hid && btcoex->has_a2dp) + btcoex->has_a2dp = true; + else + btcoex->has_a2dp = false; + + if (btcoex->bt_status == BT_8723B_1ANT_STATUS_SCO_BUSY || + btcoex->bt_status == BT_8723B_1ANT_STATUS_ACL_BUSY) + btcoex->bt_busy = true; + else + btcoex->bt_busy = false; +} + +static inline bool rtl8xxxu_is_assoc(struct rtl8xxxu_priv *priv) +{ + return (priv->vifs[0] && priv->vifs[0]->cfg.assoc) || + (priv->vifs[1] && priv->vifs[1]->cfg.assoc); +} + +static +void rtl8723bu_handle_bt_inquiry(struct rtl8xxxu_priv *priv) +{ + struct rtl8xxxu_btcoex *btcoex; + + btcoex = &priv->bt_coex; + + if (!rtl8xxxu_is_assoc(priv)) { + rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0); + rtl8723bu_set_coex_with_type(priv, 0); + } else if (btcoex->has_sco || btcoex->has_hid || btcoex->has_a2dp) { + rtl8723bu_set_ps_tdma(priv, 0x61, 0x35, 0x3, 0x11, 0x11); + rtl8723bu_set_coex_with_type(priv, 4); + } else if (btcoex->has_pan) { + rtl8723bu_set_ps_tdma(priv, 0x61, 0x3f, 0x3, 0x11, 0x11); + rtl8723bu_set_coex_with_type(priv, 4); + } else { + rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0); + rtl8723bu_set_coex_with_type(priv, 7); + } +} + +static +void rtl8723bu_handle_bt_info(struct rtl8xxxu_priv *priv) +{ + struct rtl8xxxu_btcoex *btcoex; + + btcoex = &priv->bt_coex; + + if (rtl8xxxu_is_assoc(priv)) { + u32 val32 = 0; + u32 high_prio_tx = 0, high_prio_rx = 0; + + val32 = rtl8xxxu_read32(priv, 0x770); + high_prio_tx = val32 & 0x0000ffff; + high_prio_rx = (val32 & 0xffff0000) >> 16; + + if (btcoex->bt_busy) { + if (btcoex->hid_only) { + rtl8723bu_set_ps_tdma(priv, 0x61, 0x20, + 0x3, 0x11, 0x11); + rtl8723bu_set_coex_with_type(priv, 5); + } else if (btcoex->a2dp_only) { + rtl8723bu_set_ps_tdma(priv, 0x61, 0x35, + 0x3, 0x11, 0x11); + rtl8723bu_set_coex_with_type(priv, 4); + } else if ((btcoex->has_a2dp && btcoex->has_pan) || + (btcoex->has_hid && btcoex->has_a2dp && + btcoex->has_pan)) { + rtl8723bu_set_ps_tdma(priv, 0x51, 0x21, + 0x3, 0x10, 0x10); + rtl8723bu_set_coex_with_type(priv, 4); + } else if (btcoex->has_hid && btcoex->has_a2dp) { + rtl8723bu_set_ps_tdma(priv, 0x51, 0x21, + 0x3, 0x10, 0x10); + rtl8723bu_set_coex_with_type(priv, 3); + } else { + rtl8723bu_set_ps_tdma(priv, 0x61, 0x35, + 0x3, 0x11, 0x11); + rtl8723bu_set_coex_with_type(priv, 4); + } + } else { + rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0); + if (high_prio_tx + high_prio_rx <= 60) + rtl8723bu_set_coex_with_type(priv, 2); + else + rtl8723bu_set_coex_with_type(priv, 7); + } + } else { + rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0); + rtl8723bu_set_coex_with_type(priv, 0); + } +} + +static void rtl8xxxu_c2hcmd_callback(struct work_struct *work) +{ + struct rtl8xxxu_priv *priv; + struct rtl8723bu_c2h *c2h; + struct sk_buff *skb = NULL; + u8 bt_info = 0; + struct rtl8xxxu_btcoex *btcoex; + struct rtl8xxxu_ra_report *rarpt; + u8 bw; + + priv = container_of(work, struct rtl8xxxu_priv, c2hcmd_work); + btcoex = &priv->bt_coex; + rarpt = &priv->ra_report; + + while (!skb_queue_empty(&priv->c2hcmd_queue)) { + skb = skb_dequeue(&priv->c2hcmd_queue); + + c2h = (struct rtl8723bu_c2h *)skb->data; + + switch (c2h->id) { + case C2H_8723B_BT_INFO: + bt_info = c2h->bt_info.bt_info; + + rtl8723bu_update_bt_link_info(priv, bt_info); + if (btcoex->c2h_bt_inquiry) { + rtl8723bu_handle_bt_inquiry(priv); + break; + } + rtl8723bu_handle_bt_info(priv); + break; + case C2H_8723B_RA_REPORT: + bw = rarpt->txrate.bw; + + if (skb->len >= offsetofend(typeof(*c2h), ra_report.bw)) { + if (c2h->ra_report.bw == RTL8XXXU_CHANNEL_WIDTH_40) + bw = RATE_INFO_BW_40; + else + bw = RATE_INFO_BW_20; + } + + rtl8xxxu_update_ra_report(rarpt, c2h->ra_report.rate, + c2h->ra_report.sgi, bw); + break; + default: + break; + } + + dev_kfree_skb(skb); + } +} + +static void rtl8723bu_handle_c2h(struct rtl8xxxu_priv *priv, + struct sk_buff *skb) +{ + struct rtl8723bu_c2h *c2h = (struct rtl8723bu_c2h *)skb->data; + struct device *dev = &priv->udev->dev; + int len; + + len = skb->len - 2; + + dev_dbg(dev, "C2H ID %02x seq %02x, len %02x source %02x\n", + c2h->id, c2h->seq, len, c2h->bt_info.response_source); + + switch(c2h->id) { + case C2H_8723B_BT_INFO: + if (c2h->bt_info.response_source > + BT_INFO_SRC_8723B_BT_ACTIVE_SEND) + dev_dbg(dev, "C2H_BT_INFO WiFi only firmware\n"); + else + dev_dbg(dev, "C2H_BT_INFO BT/WiFi coexist firmware\n"); + + if (c2h->bt_info.bt_has_reset) + dev_dbg(dev, "BT has been reset\n"); + if (c2h->bt_info.tx_rx_mask) + dev_dbg(dev, "BT TRx mask\n"); + + break; + case C2H_8723B_BT_MP_INFO: + dev_dbg(dev, "C2H_MP_INFO ext ID %02x, status %02x\n", + c2h->bt_mp_info.ext_id, c2h->bt_mp_info.status); + break; + case C2H_8723B_RA_REPORT: + dev_dbg(dev, + "C2H RA RPT: rate %02x, unk %i, macid %02x, noise %i\n", + c2h->ra_report.rate, c2h->ra_report.sgi, + c2h->ra_report.macid, c2h->ra_report.noisy_state); + break; + default: + dev_info(dev, "Unhandled C2H event %02x seq %02x\n", + c2h->id, c2h->seq); + print_hex_dump(KERN_INFO, "C2H content: ", DUMP_PREFIX_NONE, + 16, 1, c2h->raw.payload, len, false); + break; + } + + skb_queue_tail(&priv->c2hcmd_queue, skb); + + schedule_work(&priv->c2hcmd_work); +} + +static void rtl8188e_c2hcmd_callback(struct work_struct *work) +{ + struct rtl8xxxu_priv *priv = container_of(work, struct rtl8xxxu_priv, c2hcmd_work); + struct device *dev = &priv->udev->dev; + struct sk_buff *skb = NULL; + struct rtl8xxxu_rxdesc16 *rx_desc; + + while (!skb_queue_empty(&priv->c2hcmd_queue)) { + skb = skb_dequeue(&priv->c2hcmd_queue); + + rx_desc = (struct rtl8xxxu_rxdesc16 *)(skb->data - sizeof(struct rtl8xxxu_rxdesc16)); + + switch (rx_desc->rpt_sel) { + case 1: + dev_dbg(dev, "C2H TX report type 1\n"); + + break; + case 2: + dev_dbg(dev, "C2H TX report type 2\n"); + + rtl8188e_handle_ra_tx_report2(priv, skb); + + break; + case 3: + dev_dbg(dev, "C2H USB interrupt report\n"); + + break; + default: + dev_warn(dev, "%s: rpt_sel should not be %d\n", + __func__, rx_desc->rpt_sel); + + break; + } + + dev_kfree_skb(skb); + } +} + +#define rtl8xxxu_iterate_vifs_atomic(priv, iterator, data) \ + ieee80211_iterate_active_interfaces_atomic((priv)->hw, \ + IEEE80211_IFACE_ITER_NORMAL, iterator, data) + +struct rtl8xxxu_rx_update_rssi_data { + struct rtl8xxxu_priv *priv; + struct ieee80211_hdr *hdr; + struct ieee80211_rx_status *rx_status; + u8 *bssid; +}; + +static void rtl8xxxu_rx_update_rssi_iter(void *data, u8 *mac, + struct ieee80211_vif *vif) +{ + struct rtl8xxxu_rx_update_rssi_data *iter_data = data; + struct ieee80211_sta *sta; + struct ieee80211_hdr *hdr = iter_data->hdr; + struct rtl8xxxu_priv *priv = iter_data->priv; + struct rtl8xxxu_sta_info *sta_info; + struct ieee80211_rx_status *rx_status = iter_data->rx_status; + u8 *bssid = iter_data->bssid; + + if (!ether_addr_equal(vif->bss_conf.bssid, bssid)) + return; + + if (!(ether_addr_equal(vif->addr, hdr->addr1) || + ieee80211_is_beacon(hdr->frame_control))) + return; + + sta = ieee80211_find_sta_by_ifaddr(priv->hw, hdr->addr2, + vif->addr); + if (!sta) + return; + + sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv; + ewma_rssi_add(&sta_info->avg_rssi, -rx_status->signal); +} + +static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr) +{ + __le16 fc = hdr->frame_control; + u8 *bssid; + + if (ieee80211_has_tods(fc)) + bssid = hdr->addr1; + else if (ieee80211_has_fromds(fc)) + bssid = hdr->addr2; + else + bssid = hdr->addr3; + + return bssid; +} + +static void rtl8xxxu_rx_update_rssi(struct rtl8xxxu_priv *priv, + struct ieee80211_rx_status *rx_status, + struct ieee80211_hdr *hdr) +{ + struct rtl8xxxu_rx_update_rssi_data data = {}; + + if (ieee80211_is_ctl(hdr->frame_control)) + return; + + data.priv = priv; + data.hdr = hdr; + data.rx_status = rx_status; + data.bssid = get_hdr_bssid(hdr); + + rtl8xxxu_iterate_vifs_atomic(priv, rtl8xxxu_rx_update_rssi_iter, &data); +} + +int rtl8xxxu_parse_rxdesc16(struct rtl8xxxu_priv *priv, struct sk_buff *skb) +{ + struct ieee80211_hw *hw = priv->hw; + struct ieee80211_rx_status *rx_status; + struct rtl8xxxu_rxdesc16 *rx_desc; + struct rtl8723au_phy_stats *phy_stats; + struct sk_buff *next_skb = NULL; + __le32 *_rx_desc_le; + u32 *_rx_desc; + int drvinfo_sz, desc_shift; + int i, pkt_cnt, pkt_len, urb_len, pkt_offset; + + urb_len = skb->len; + pkt_cnt = 0; + + if (urb_len < sizeof(struct rtl8xxxu_rxdesc16)) { + kfree_skb(skb); + return RX_TYPE_ERROR; + } + + do { + rx_desc = (struct rtl8xxxu_rxdesc16 *)skb->data; + _rx_desc_le = (__le32 *)skb->data; + _rx_desc = (u32 *)skb->data; + + for (i = 0; + i < (sizeof(struct rtl8xxxu_rxdesc16) / sizeof(u32)); i++) + _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]); + + /* + * Only read pkt_cnt from the header if we're parsing the + * first packet + */ + if (!pkt_cnt) + pkt_cnt = rx_desc->pkt_cnt; + pkt_len = rx_desc->pktlen; + + drvinfo_sz = rx_desc->drvinfo_sz * 8; + desc_shift = rx_desc->shift; + pkt_offset = roundup(pkt_len + drvinfo_sz + desc_shift + + sizeof(struct rtl8xxxu_rxdesc16), 128); + + /* + * Only clone the skb if there's enough data at the end to + * at least cover the rx descriptor + */ + if (pkt_cnt > 1 && + urb_len >= (pkt_offset + sizeof(struct rtl8xxxu_rxdesc16))) + next_skb = skb_clone(skb, GFP_ATOMIC); + + rx_status = IEEE80211_SKB_RXCB(skb); + memset(rx_status, 0, sizeof(struct ieee80211_rx_status)); + + skb_pull(skb, sizeof(struct rtl8xxxu_rxdesc16)); + + if (rx_desc->rpt_sel) { + skb_queue_tail(&priv->c2hcmd_queue, skb); + schedule_work(&priv->c2hcmd_work); + } else { + struct ieee80211_hdr *hdr; + + phy_stats = (struct rtl8723au_phy_stats *)skb->data; + + skb_pull(skb, drvinfo_sz + desc_shift); + + skb_trim(skb, pkt_len); + + hdr = (struct ieee80211_hdr *)skb->data; + if (rx_desc->phy_stats) { + priv->fops->parse_phystats( + priv, rx_status, phy_stats, + rx_desc->rxmcs, + hdr, + rx_desc->crc32 || rx_desc->icverr); + if (!rx_desc->crc32 && !rx_desc->icverr) + rtl8xxxu_rx_update_rssi(priv, + rx_status, + hdr); + } + + rx_status->mactime = rx_desc->tsfl; + rx_status->flag |= RX_FLAG_MACTIME_START; + + if (!rx_desc->swdec && + rx_desc->security != RX_DESC_ENC_NONE) + rx_status->flag |= RX_FLAG_DECRYPTED; + if (rx_desc->crc32) + rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; + if (rx_desc->bw) + rx_status->bw = RATE_INFO_BW_40; + + if (rx_desc->rxht) { + rx_status->encoding = RX_ENC_HT; + rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0; + } else { + rx_status->rate_idx = rx_desc->rxmcs; + } + + rx_status->freq = hw->conf.chandef.chan->center_freq; + rx_status->band = hw->conf.chandef.chan->band; + + ieee80211_rx_irqsafe(hw, skb); + } + + skb = next_skb; + if (skb) + skb_pull(next_skb, pkt_offset); + + pkt_cnt--; + urb_len -= pkt_offset; + next_skb = NULL; + } while (skb && pkt_cnt > 0 && + urb_len >= sizeof(struct rtl8xxxu_rxdesc16)); + + return RX_TYPE_DATA_PKT; +} + +int rtl8xxxu_parse_rxdesc24(struct rtl8xxxu_priv *priv, struct sk_buff *skb) +{ + struct ieee80211_hw *hw = priv->hw; + struct ieee80211_rx_status *rx_status; + struct rtl8xxxu_rxdesc24 *rx_desc; + struct rtl8723au_phy_stats *phy_stats; + struct sk_buff *next_skb = NULL; + __le32 *_rx_desc_le; + u32 *_rx_desc; + int drvinfo_sz, desc_shift; + int i, pkt_len, urb_len, pkt_offset; + + urb_len = skb->len; + + if (urb_len < sizeof(struct rtl8xxxu_rxdesc24)) { + kfree_skb(skb); + return RX_TYPE_ERROR; + } + + do { + rx_desc = (struct rtl8xxxu_rxdesc24 *)skb->data; + _rx_desc_le = (__le32 *)skb->data; + _rx_desc = (u32 *)skb->data; + + for (i = 0; i < (sizeof(struct rtl8xxxu_rxdesc24) / sizeof(u32)); i++) + _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]); + + pkt_len = rx_desc->pktlen; + + drvinfo_sz = rx_desc->drvinfo_sz * 8; + desc_shift = rx_desc->shift; + pkt_offset = roundup(pkt_len + drvinfo_sz + desc_shift + + sizeof(struct rtl8xxxu_rxdesc24), 8); + + /* + * Only clone the skb if there's enough data at the end to + * at least cover the rx descriptor + */ + if (urb_len >= (pkt_offset + sizeof(struct rtl8xxxu_rxdesc24))) + next_skb = skb_clone(skb, GFP_ATOMIC); + + rx_status = IEEE80211_SKB_RXCB(skb); + memset(rx_status, 0, sizeof(struct ieee80211_rx_status)); + + skb_pull(skb, sizeof(struct rtl8xxxu_rxdesc24)); + + phy_stats = (struct rtl8723au_phy_stats *)skb->data; + + skb_pull(skb, drvinfo_sz + desc_shift); + + skb_trim(skb, pkt_len); + + if (rx_desc->rpt_sel) { + struct device *dev = &priv->udev->dev; + dev_dbg(dev, "%s: C2H packet\n", __func__); + rtl8723bu_handle_c2h(priv, skb); + } else { + struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; + + if (rx_desc->phy_stats) { + priv->fops->parse_phystats(priv, rx_status, phy_stats, + rx_desc->rxmcs, hdr, + rx_desc->crc32 || rx_desc->icverr); + if (!rx_desc->crc32 && !rx_desc->icverr) + rtl8xxxu_rx_update_rssi(priv, + rx_status, + hdr); + } + + rx_status->mactime = rx_desc->tsfl; + rx_status->flag |= RX_FLAG_MACTIME_START; + + if (!rx_desc->swdec && + rx_desc->security != RX_DESC_ENC_NONE) + rx_status->flag |= RX_FLAG_DECRYPTED; + if (rx_desc->crc32) + rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; + if (rx_desc->bw) + rx_status->bw = RATE_INFO_BW_40; + + if (rx_desc->rxmcs >= DESC_RATE_MCS0) { + rx_status->encoding = RX_ENC_HT; + rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0; + } else { + rx_status->rate_idx = rx_desc->rxmcs; + } + + rx_status->freq = hw->conf.chandef.chan->center_freq; + rx_status->band = hw->conf.chandef.chan->band; + + ieee80211_rx_irqsafe(hw, skb); + } + + skb = next_skb; + if (skb) + skb_pull(next_skb, pkt_offset); + + urb_len -= pkt_offset; + next_skb = NULL; + } while (skb && urb_len >= sizeof(struct rtl8xxxu_rxdesc24)); + + return RX_TYPE_DATA_PKT; +} + +static void rtl8xxxu_rx_complete(struct urb *urb) +{ + struct rtl8xxxu_rx_urb *rx_urb = + container_of(urb, struct rtl8xxxu_rx_urb, urb); + struct ieee80211_hw *hw = rx_urb->hw; + struct rtl8xxxu_priv *priv = hw->priv; + struct sk_buff *skb = (struct sk_buff *)urb->context; + struct device *dev = &priv->udev->dev; + + skb_put(skb, urb->actual_length); + + if (urb->status == 0) { + priv->fops->parse_rx_desc(priv, skb); + + skb = NULL; + rx_urb->urb.context = NULL; + rtl8xxxu_queue_rx_urb(priv, rx_urb); + } else { + dev_dbg(dev, "%s: status %i\n", __func__, urb->status); + goto cleanup; + } + return; + +cleanup: + usb_free_urb(urb); + dev_kfree_skb(skb); +} + +static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv, + struct rtl8xxxu_rx_urb *rx_urb) +{ + struct rtl8xxxu_fileops *fops = priv->fops; + struct sk_buff *skb; + int skb_size; + int ret, rx_desc_sz; + + rx_desc_sz = fops->rx_desc_size; + + if (priv->rx_buf_aggregation && fops->rx_agg_buf_size) { + skb_size = fops->rx_agg_buf_size; + skb_size += (rx_desc_sz + sizeof(struct rtl8723au_phy_stats)); + } else { + skb_size = IEEE80211_MAX_FRAME_LEN; + } + + skb = __netdev_alloc_skb(NULL, skb_size, GFP_KERNEL); + if (!skb) + return -ENOMEM; + + memset(skb->data, 0, rx_desc_sz); + usb_fill_bulk_urb(&rx_urb->urb, priv->udev, priv->pipe_in, skb->data, + skb_size, rtl8xxxu_rx_complete, skb); + usb_anchor_urb(&rx_urb->urb, &priv->rx_anchor); + ret = usb_submit_urb(&rx_urb->urb, GFP_ATOMIC); + if (ret) + usb_unanchor_urb(&rx_urb->urb); + return ret; +} + +static void rtl8xxxu_int_complete(struct urb *urb) +{ + struct rtl8xxxu_priv *priv = (struct rtl8xxxu_priv *)urb->context; + struct device *dev = &priv->udev->dev; + int ret; + + if (rtl8xxxu_debug & RTL8XXXU_DEBUG_INTERRUPT) + dev_dbg(dev, "%s: status %i\n", __func__, urb->status); + if (urb->status == 0) { + usb_anchor_urb(urb, &priv->int_anchor); + ret = usb_submit_urb(urb, GFP_ATOMIC); + if (ret) + usb_unanchor_urb(urb); + } else { + dev_dbg(dev, "%s: Error %i\n", __func__, urb->status); + } +} + + +static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw) +{ + struct rtl8xxxu_priv *priv = hw->priv; + struct urb *urb; + u32 val32; + int ret; + + urb = usb_alloc_urb(0, GFP_KERNEL); + if (!urb) + return -ENOMEM; + + usb_fill_int_urb(urb, priv->udev, priv->pipe_interrupt, + priv->int_buf, USB_INTR_CONTENT_LENGTH, + rtl8xxxu_int_complete, priv, 1); + usb_anchor_urb(urb, &priv->int_anchor); + ret = usb_submit_urb(urb, GFP_KERNEL); + if (ret) { + usb_unanchor_urb(urb); + goto error; + } + + val32 = rtl8xxxu_read32(priv, REG_USB_HIMR); + val32 |= USB_HIMR_CPWM; + rtl8xxxu_write32(priv, REG_USB_HIMR, val32); + +error: + usb_free_urb(urb); + return ret; +} + +static void rtl8xxxu_switch_ports(struct rtl8xxxu_priv *priv) +{ + u8 macid[ETH_ALEN], bssid[ETH_ALEN], macid_1[ETH_ALEN], bssid_1[ETH_ALEN]; + u8 msr, bcn_ctrl, bcn_ctrl_1, atimwnd[2], atimwnd_1[2]; + struct rtl8xxxu_vif *rtlvif; + struct ieee80211_vif *vif; + u8 tsftr[8], tsftr_1[8]; + int i; + + msr = rtl8xxxu_read8(priv, REG_MSR); + bcn_ctrl = rtl8xxxu_read8(priv, REG_BEACON_CTRL); + bcn_ctrl_1 = rtl8xxxu_read8(priv, REG_BEACON_CTRL_1); + + for (i = 0; i < ARRAY_SIZE(atimwnd); i++) + atimwnd[i] = rtl8xxxu_read8(priv, REG_ATIMWND + i); + for (i = 0; i < ARRAY_SIZE(atimwnd_1); i++) + atimwnd_1[i] = rtl8xxxu_read8(priv, REG_ATIMWND_1 + i); + + for (i = 0; i < ARRAY_SIZE(tsftr); i++) + tsftr[i] = rtl8xxxu_read8(priv, REG_TSFTR + i); + for (i = 0; i < ARRAY_SIZE(tsftr); i++) + tsftr_1[i] = rtl8xxxu_read8(priv, REG_TSFTR1 + i); + + for (i = 0; i < ARRAY_SIZE(macid); i++) + macid[i] = rtl8xxxu_read8(priv, REG_MACID + i); + + for (i = 0; i < ARRAY_SIZE(bssid); i++) + bssid[i] = rtl8xxxu_read8(priv, REG_BSSID + i); + + for (i = 0; i < ARRAY_SIZE(macid_1); i++) + macid_1[i] = rtl8xxxu_read8(priv, REG_MACID1 + i); + + for (i = 0; i < ARRAY_SIZE(bssid_1); i++) + bssid_1[i] = rtl8xxxu_read8(priv, REG_BSSID1 + i); + + /* disable bcn function, disable update TSF */ + rtl8xxxu_write8(priv, REG_BEACON_CTRL, (bcn_ctrl & + (~BEACON_FUNCTION_ENABLE)) | BEACON_DISABLE_TSF_UPDATE); + rtl8xxxu_write8(priv, REG_BEACON_CTRL_1, (bcn_ctrl_1 & + (~BEACON_FUNCTION_ENABLE)) | BEACON_DISABLE_TSF_UPDATE); + + /* switch msr */ + msr = (msr & 0xf0) | ((msr & 0x03) << 2) | ((msr & 0x0c) >> 2); + rtl8xxxu_write8(priv, REG_MSR, msr); + + /* write port0 */ + rtl8xxxu_write8(priv, REG_BEACON_CTRL, bcn_ctrl_1 & ~BEACON_FUNCTION_ENABLE); + for (i = 0; i < ARRAY_SIZE(atimwnd_1); i++) + rtl8xxxu_write8(priv, REG_ATIMWND + i, atimwnd_1[i]); + for (i = 0; i < ARRAY_SIZE(tsftr_1); i++) + rtl8xxxu_write8(priv, REG_TSFTR + i, tsftr_1[i]); + for (i = 0; i < ARRAY_SIZE(macid_1); i++) + rtl8xxxu_write8(priv, REG_MACID + i, macid_1[i]); + for (i = 0; i < ARRAY_SIZE(bssid_1); i++) + rtl8xxxu_write8(priv, REG_BSSID + i, bssid_1[i]); + + /* write port1 */ + rtl8xxxu_write8(priv, REG_BEACON_CTRL_1, bcn_ctrl & ~BEACON_FUNCTION_ENABLE); + for (i = 0; i < ARRAY_SIZE(atimwnd); i++) + rtl8xxxu_write8(priv, REG_ATIMWND_1 + i, atimwnd[i]); + for (i = 0; i < ARRAY_SIZE(tsftr); i++) + rtl8xxxu_write8(priv, REG_TSFTR1 + i, tsftr[i]); + for (i = 0; i < ARRAY_SIZE(macid); i++) + rtl8xxxu_write8(priv, REG_MACID1 + i, macid[i]); + for (i = 0; i < ARRAY_SIZE(bssid); i++) + rtl8xxxu_write8(priv, REG_BSSID1 + i, bssid[i]); + + /* write bcn ctl */ + rtl8xxxu_write8(priv, REG_BEACON_CTRL, bcn_ctrl_1); + rtl8xxxu_write8(priv, REG_BEACON_CTRL_1, bcn_ctrl); + + vif = priv->vifs[0]; + priv->vifs[0] = priv->vifs[1]; + priv->vifs[1] = vif; + + /* priv->vifs[0] is NULL here, based on how this function is currently + * called from rtl8xxxu_add_interface(). + * When this function will be used in the future for a different + * scenario, please check whether vifs[0] or vifs[1] can be NULL and if + * necessary add code to set port_num = 1. + */ + rtlvif = (struct rtl8xxxu_vif *)priv->vifs[1]->drv_priv; + rtlvif->port_num = 1; +} + +static int rtl8xxxu_add_interface(struct ieee80211_hw *hw, + struct ieee80211_vif *vif) +{ + struct rtl8xxxu_vif *rtlvif = (struct rtl8xxxu_vif *)vif->drv_priv; + struct rtl8xxxu_priv *priv = hw->priv; + int port_num; + u8 val8; + + if (!priv->vifs[0]) + port_num = 0; + else if (!priv->vifs[1]) + port_num = 1; + else + return -EOPNOTSUPP; + + switch (vif->type) { + case NL80211_IFTYPE_STATION: + if (port_num == 0) { + rtl8xxxu_stop_tx_beacon(priv); + + val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL); + val8 |= BEACON_ATIM | BEACON_FUNCTION_ENABLE | + BEACON_DISABLE_TSF_UPDATE; + rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8); + } + break; + case NL80211_IFTYPE_AP: + if (port_num == 1) { + rtl8xxxu_switch_ports(priv); + port_num = 0; + } + + rtl8xxxu_write8(priv, REG_BEACON_CTRL, + BEACON_DISABLE_TSF_UPDATE | BEACON_CTRL_MBSSID); + rtl8xxxu_write8(priv, REG_ATIMWND, 0x0c); /* 12ms */ + rtl8xxxu_write16(priv, REG_TSFTR_SYN_OFFSET, 0x7fff); /* ~32ms */ + rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, DUAL_TSF_RESET_TSF0); + + /* enable BCN0 function */ + rtl8xxxu_write8(priv, REG_BEACON_CTRL, + BEACON_DISABLE_TSF_UPDATE | + BEACON_FUNCTION_ENABLE | BEACON_CTRL_MBSSID | + BEACON_CTRL_TX_BEACON_RPT); + + /* select BCN on port 0 */ + val8 = rtl8xxxu_read8(priv, REG_CCK_CHECK); + val8 &= ~BIT_BCN_PORT_SEL; + rtl8xxxu_write8(priv, REG_CCK_CHECK, val8); + break; + default: + return -EOPNOTSUPP; + } + + priv->vifs[port_num] = vif; + rtlvif->port_num = port_num; + rtlvif->hw_key_idx = 0xff; + + rtl8xxxu_set_linktype(priv, vif->type, port_num); + ether_addr_copy(priv->mac_addr, vif->addr); + rtl8xxxu_set_mac(priv, port_num); + + return 0; +} + +static void rtl8xxxu_remove_interface(struct ieee80211_hw *hw, + struct ieee80211_vif *vif) +{ + struct rtl8xxxu_vif *rtlvif = (struct rtl8xxxu_vif *)vif->drv_priv; + struct rtl8xxxu_priv *priv = hw->priv; + + dev_dbg(&priv->udev->dev, "%s\n", __func__); + + priv->vifs[rtlvif->port_num] = NULL; +} + +static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed) +{ + struct rtl8xxxu_priv *priv = hw->priv; + struct device *dev = &priv->udev->dev; + int ret = 0, channel; + bool ht40; + + if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL) + dev_info(dev, + "%s: channel: %i (changed %08x chandef.width %02x)\n", + __func__, hw->conf.chandef.chan->hw_value, + changed, hw->conf.chandef.width); + + if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { + switch (hw->conf.chandef.width) { + case NL80211_CHAN_WIDTH_20_NOHT: + case NL80211_CHAN_WIDTH_20: + ht40 = false; + break; + case NL80211_CHAN_WIDTH_40: + ht40 = true; + break; + default: + ret = -ENOTSUPP; + goto exit; + } + + channel = hw->conf.chandef.chan->hw_value; + + priv->fops->set_tx_power(priv, channel, ht40); + + priv->fops->config_channel(hw); + } + +exit: + return ret; +} + +static int rtl8xxxu_conf_tx(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + unsigned int link_id, u16 queue, + const struct ieee80211_tx_queue_params *param) +{ + struct rtl8xxxu_priv *priv = hw->priv; + struct device *dev = &priv->udev->dev; + u32 val32; + u8 aifs, acm_ctrl, acm_bit; + + aifs = param->aifs; + + val32 = aifs | + fls(param->cw_min) << EDCA_PARAM_ECW_MIN_SHIFT | + fls(param->cw_max) << EDCA_PARAM_ECW_MAX_SHIFT | + (u32)param->txop << EDCA_PARAM_TXOP_SHIFT; + + acm_ctrl = rtl8xxxu_read8(priv, REG_ACM_HW_CTRL); + dev_dbg(dev, + "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n", + __func__, queue, val32, param->acm, acm_ctrl); + + switch (queue) { + case IEEE80211_AC_VO: + acm_bit = ACM_HW_CTRL_VO; + rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32); + break; + case IEEE80211_AC_VI: + acm_bit = ACM_HW_CTRL_VI; + rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32); + break; + case IEEE80211_AC_BE: + acm_bit = ACM_HW_CTRL_BE; + rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32); + break; + case IEEE80211_AC_BK: + acm_bit = ACM_HW_CTRL_BK; + rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32); + break; + default: + acm_bit = 0; + break; + } + + if (param->acm) + acm_ctrl |= acm_bit; + else + acm_ctrl &= ~acm_bit; + rtl8xxxu_write8(priv, REG_ACM_HW_CTRL, acm_ctrl); + + return 0; +} + +static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw, + unsigned int changed_flags, + unsigned int *total_flags, u64 multicast) +{ + struct rtl8xxxu_priv *priv = hw->priv; + u32 rcr = priv->regrcr; + + dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n", + __func__, changed_flags, *total_flags); + + /* + * FIF_ALLMULTI ignored as all multicast frames are accepted (REG_MAR) + */ + + if (*total_flags & FIF_FCSFAIL) + rcr |= RCR_ACCEPT_CRC32; + else + rcr &= ~RCR_ACCEPT_CRC32; + + /* + * FIF_PLCPFAIL not supported? + */ + + if (*total_flags & FIF_BCN_PRBRESP_PROMISC) + rcr &= ~(RCR_CHECK_BSSID_BEACON | RCR_CHECK_BSSID_MATCH); + else + rcr |= RCR_CHECK_BSSID_BEACON | RCR_CHECK_BSSID_MATCH; + + if (priv->vifs[0] && priv->vifs[0]->type == NL80211_IFTYPE_AP) + rcr &= ~(RCR_CHECK_BSSID_MATCH | RCR_CHECK_BSSID_BEACON); + + if (*total_flags & FIF_CONTROL) + rcr |= RCR_ACCEPT_CTRL_FRAME; + else + rcr &= ~RCR_ACCEPT_CTRL_FRAME; + + if (*total_flags & FIF_OTHER_BSS) + rcr |= RCR_ACCEPT_AP; + else + rcr &= ~RCR_ACCEPT_AP; + + if (*total_flags & FIF_PSPOLL) + rcr |= RCR_ACCEPT_PM; + else + rcr &= ~RCR_ACCEPT_PM; + + /* + * FIF_PROBE_REQ ignored as probe requests always seem to be accepted + */ + + rtl8xxxu_write32(priv, REG_RCR, rcr); + priv->regrcr = rcr; + + *total_flags &= (FIF_ALLMULTI | FIF_FCSFAIL | FIF_BCN_PRBRESP_PROMISC | + FIF_CONTROL | FIF_OTHER_BSS | FIF_PSPOLL | + FIF_PROBE_REQ); +} + +static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, u32 rts) +{ + if (rts > 2347 && rts != (u32)-1) + return -EINVAL; + + return 0; +} + +static int rtl8xxxu_get_free_sec_cam(struct ieee80211_hw *hw) +{ + struct rtl8xxxu_priv *priv = hw->priv; + + return find_first_zero_bit(priv->cam_map, priv->fops->max_sec_cam_num); +} + +static int rtl8xxxu_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, + struct ieee80211_vif *vif, + struct ieee80211_sta *sta, + struct ieee80211_key_conf *key) +{ + struct rtl8xxxu_vif *rtlvif = (struct rtl8xxxu_vif *)vif->drv_priv; + struct rtl8xxxu_priv *priv = hw->priv; + struct device *dev = &priv->udev->dev; + u8 mac_addr[ETH_ALEN]; + u8 val8; + u16 val16; + u32 val32; + int retval = -EOPNOTSUPP; + + dev_dbg(dev, "%s: cmd %02x, cipher %08x, index %i\n", + __func__, cmd, key->cipher, key->keyidx); + + if (key->keyidx > 3) + return -EOPNOTSUPP; + + switch (key->cipher) { + case WLAN_CIPHER_SUITE_WEP40: + case WLAN_CIPHER_SUITE_WEP104: + + break; + case WLAN_CIPHER_SUITE_CCMP: + key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX; + break; + case WLAN_CIPHER_SUITE_TKIP: + key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; + break; + default: + return -EOPNOTSUPP; + } + + if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) { + dev_dbg(dev, "%s: pairwise key\n", __func__); + ether_addr_copy(mac_addr, sta->addr); + } else { + dev_dbg(dev, "%s: group key\n", __func__); + ether_addr_copy(mac_addr, vif->bss_conf.bssid); + } + + val16 = rtl8xxxu_read16(priv, REG_CR); + val16 |= CR_SECURITY_ENABLE; + rtl8xxxu_write16(priv, REG_CR, val16); + + val8 = SEC_CFG_TX_SEC_ENABLE | SEC_CFG_TXBC_USE_DEFKEY | + SEC_CFG_RX_SEC_ENABLE | SEC_CFG_RXBC_USE_DEFKEY; + val8 |= SEC_CFG_TX_USE_DEFKEY | SEC_CFG_RX_USE_DEFKEY; + rtl8xxxu_write8(priv, REG_SECURITY_CFG, val8); + + switch (cmd) { + case SET_KEY: + + retval = rtl8xxxu_get_free_sec_cam(hw); + if (retval < 0) + return -EOPNOTSUPP; + + key->hw_key_idx = retval; + + if (vif->type == NL80211_IFTYPE_AP && !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) + rtlvif->hw_key_idx = key->hw_key_idx; + + key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; + rtl8xxxu_cam_write(priv, key, mac_addr); + set_bit(key->hw_key_idx, priv->cam_map); + retval = 0; + break; + case DISABLE_KEY: + rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000); + val32 = CAM_CMD_POLLING | CAM_CMD_WRITE | + key->hw_key_idx << CAM_CMD_KEY_SHIFT; + rtl8xxxu_write32(priv, REG_CAM_CMD, val32); + rtlvif->hw_key_idx = 0xff; + clear_bit(key->hw_key_idx, priv->cam_map); + retval = 0; + break; + default: + dev_warn(dev, "%s: Unsupported command %02x\n", __func__, cmd); + } + + return retval; +} + +static int +rtl8xxxu_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, + struct ieee80211_ampdu_params *params) +{ + struct rtl8xxxu_priv *priv = hw->priv; + struct device *dev = &priv->udev->dev; + u8 ampdu_factor, ampdu_density; + struct ieee80211_sta *sta = params->sta; + u16 tid = params->tid; + enum ieee80211_ampdu_mlme_action action = params->action; + + switch (action) { + case IEEE80211_AMPDU_TX_START: + dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_START\n", __func__); + ampdu_factor = sta->deflink.ht_cap.ampdu_factor; + ampdu_density = sta->deflink.ht_cap.ampdu_density; + rtl8xxxu_set_ampdu_factor(priv, ampdu_factor); + rtl8xxxu_set_ampdu_min_space(priv, ampdu_density); + dev_dbg(dev, + "Changed HT: ampdu_factor %02x, ampdu_density %02x\n", + ampdu_factor, ampdu_density); + return IEEE80211_AMPDU_TX_START_IMMEDIATE; + case IEEE80211_AMPDU_TX_STOP_CONT: + case IEEE80211_AMPDU_TX_STOP_FLUSH: + case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: + dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_STOP\n", __func__); + rtl8xxxu_set_ampdu_factor(priv, 0); + rtl8xxxu_set_ampdu_min_space(priv, 0); + clear_bit(tid, priv->tx_aggr_started); + clear_bit(tid, priv->tid_tx_operational); + ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); + break; + case IEEE80211_AMPDU_TX_OPERATIONAL: + dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_OPERATIONAL\n", __func__); + set_bit(tid, priv->tid_tx_operational); + break; + case IEEE80211_AMPDU_RX_START: + dev_dbg(dev, "%s: IEEE80211_AMPDU_RX_START\n", __func__); + break; + case IEEE80211_AMPDU_RX_STOP: + dev_dbg(dev, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__); + break; + default: + break; + } + return 0; +} + +static void +rtl8xxxu_sta_statistics(struct ieee80211_hw *hw, struct ieee80211_vif *vif, + struct ieee80211_sta *sta, struct station_info *sinfo) +{ + struct rtl8xxxu_priv *priv = hw->priv; + + sinfo->txrate = priv->ra_report.txrate; + sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BITRATE); +} + +static u8 rtl8xxxu_signal_to_snr(int signal) +{ + if (signal < RTL8XXXU_NOISE_FLOOR_MIN) + signal = RTL8XXXU_NOISE_FLOOR_MIN; + else if (signal > 0) + signal = 0; + return (u8)(signal - RTL8XXXU_NOISE_FLOOR_MIN); +} + +static void rtl8xxxu_refresh_rate_mask(struct rtl8xxxu_priv *priv, + int signal, struct ieee80211_sta *sta, + bool force) +{ + struct rtl8xxxu_sta_info *sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv; + struct ieee80211_hw *hw = priv->hw; + u16 wireless_mode; + u8 rssi_level, ratr_idx; + u8 txbw_40mhz; + u8 snr, snr_thresh_high, snr_thresh_low; + u8 go_up_gap = 5; + u8 macid = rtl8xxxu_get_macid(priv, sta); + + rssi_level = sta_info->rssi_level; + snr = rtl8xxxu_signal_to_snr(signal); + snr_thresh_high = RTL8XXXU_SNR_THRESH_HIGH; + snr_thresh_low = RTL8XXXU_SNR_THRESH_LOW; + txbw_40mhz = (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) ? 1 : 0; + + switch (rssi_level) { + case RTL8XXXU_RATR_STA_MID: + snr_thresh_high += go_up_gap; + break; + case RTL8XXXU_RATR_STA_LOW: + snr_thresh_high += go_up_gap; + snr_thresh_low += go_up_gap; + break; + default: + break; + } + + if (snr > snr_thresh_high) + rssi_level = RTL8XXXU_RATR_STA_HIGH; + else if (snr > snr_thresh_low) + rssi_level = RTL8XXXU_RATR_STA_MID; + else + rssi_level = RTL8XXXU_RATR_STA_LOW; + + if (rssi_level != sta_info->rssi_level || force) { + int sgi = 0; + u32 rate_bitmap = 0; + + rate_bitmap = (sta->deflink.supp_rates[0] & 0xfff) | + (sta->deflink.ht_cap.mcs.rx_mask[0] << 12) | + (sta->deflink.ht_cap.mcs.rx_mask[1] << 20); + if (sta->deflink.ht_cap.cap & + (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20)) + sgi = 1; + + wireless_mode = rtl8xxxu_wireless_mode(hw, sta); + switch (wireless_mode) { + case WIRELESS_MODE_B: + ratr_idx = RATEID_IDX_B; + if (rate_bitmap & 0x0000000c) + rate_bitmap &= 0x0000000d; + else + rate_bitmap &= 0x0000000f; + break; + case WIRELESS_MODE_A: + case WIRELESS_MODE_G: + ratr_idx = RATEID_IDX_G; + if (rssi_level == RTL8XXXU_RATR_STA_HIGH) + rate_bitmap &= 0x00000f00; + else + rate_bitmap &= 0x00000ff0; + break; + case (WIRELESS_MODE_B | WIRELESS_MODE_G): + ratr_idx = RATEID_IDX_BG; + if (rssi_level == RTL8XXXU_RATR_STA_HIGH) + rate_bitmap &= 0x00000f00; + else if (rssi_level == RTL8XXXU_RATR_STA_MID) + rate_bitmap &= 0x00000ff0; + else + rate_bitmap &= 0x00000ff5; + break; + case WIRELESS_MODE_N_24G: + case WIRELESS_MODE_N_5G: + case (WIRELESS_MODE_G | WIRELESS_MODE_N_24G): + case (WIRELESS_MODE_A | WIRELESS_MODE_N_5G): + if (priv->tx_paths == 2 && priv->rx_paths == 2) + ratr_idx = RATEID_IDX_GN_N2SS; + else + ratr_idx = RATEID_IDX_GN_N1SS; + break; + case (WIRELESS_MODE_B | WIRELESS_MODE_G | WIRELESS_MODE_N_24G): + case (WIRELESS_MODE_B | WIRELESS_MODE_N_24G): + if (txbw_40mhz) { + if (priv->tx_paths == 2 && priv->rx_paths == 2) + ratr_idx = RATEID_IDX_BGN_40M_2SS; + else + ratr_idx = RATEID_IDX_BGN_40M_1SS; + } else { + if (priv->tx_paths == 2 && priv->rx_paths == 2) + ratr_idx = RATEID_IDX_BGN_20M_2SS_BN; + else + ratr_idx = RATEID_IDX_BGN_20M_1SS_BN; + } + + if (priv->tx_paths == 2 && priv->rx_paths == 2) { + if (rssi_level == RTL8XXXU_RATR_STA_HIGH) { + rate_bitmap &= 0x0f8f0000; + } else if (rssi_level == RTL8XXXU_RATR_STA_MID) { + rate_bitmap &= 0x0f8ff000; + } else { + if (txbw_40mhz) + rate_bitmap &= 0x0f8ff015; + else + rate_bitmap &= 0x0f8ff005; + } + } else { + if (rssi_level == RTL8XXXU_RATR_STA_HIGH) { + rate_bitmap &= 0x000f0000; + } else if (rssi_level == RTL8XXXU_RATR_STA_MID) { + rate_bitmap &= 0x000ff000; + } else { + if (txbw_40mhz) + rate_bitmap &= 0x000ff015; + else + rate_bitmap &= 0x000ff005; + } + } + break; + default: + ratr_idx = RATEID_IDX_BGN_40M_2SS; + rate_bitmap &= 0x0fffffff; + break; + } + + sta_info->rssi_level = rssi_level; + priv->fops->update_rate_mask(priv, rate_bitmap, ratr_idx, sgi, txbw_40mhz, macid); + } +} + +static void rtl8xxxu_set_atc_status(struct rtl8xxxu_priv *priv, bool atc_status) +{ + struct rtl8xxxu_cfo_tracking *cfo = &priv->cfo_tracking; + u32 val32; + + if (atc_status == cfo->atc_status) + return; + + cfo->atc_status = atc_status; + + val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING); + if (atc_status) + val32 |= CFO_TRACKING_ATC_STATUS; + else + val32 &= ~CFO_TRACKING_ATC_STATUS; + rtl8xxxu_write32(priv, REG_OFDM1_CFO_TRACKING, val32); +} + +/* Central frequency offset correction */ +static void rtl8xxxu_track_cfo(struct rtl8xxxu_priv *priv) +{ + struct rtl8xxxu_cfo_tracking *cfo = &priv->cfo_tracking; + int cfo_khz_a, cfo_khz_b, cfo_average; + int crystal_cap; + + if (!rtl8xxxu_is_assoc(priv)) { + /* Reset */ + cfo->adjust = true; + + if (cfo->crystal_cap > priv->default_crystal_cap) + priv->fops->set_crystal_cap(priv, cfo->crystal_cap - 1); + else if (cfo->crystal_cap < priv->default_crystal_cap) + priv->fops->set_crystal_cap(priv, cfo->crystal_cap + 1); + + rtl8xxxu_set_atc_status(priv, true); + + return; + } + + if (cfo->packet_count == cfo->packet_count_pre) + /* No new information. */ + return; + + cfo->packet_count_pre = cfo->packet_count; + + /* CFO_tail[1:0] is S(8,7), (num_subcarrier>>7) x 312.5K = CFO value(K Hz) */ + cfo_khz_a = (int)((cfo->cfo_tail[0] * 3125) / 10) >> 7; + cfo_khz_b = (int)((cfo->cfo_tail[1] * 3125) / 10) >> 7; + + if (priv->tx_paths == 1) + cfo_average = cfo_khz_a; + else + cfo_average = (cfo_khz_a + cfo_khz_b) / 2; + + dev_dbg(&priv->udev->dev, "cfo_average: %d\n", cfo_average); + + if (cfo->adjust) { + if (abs(cfo_average) < CFO_TH_XTAL_LOW) + cfo->adjust = false; + } else { + if (abs(cfo_average) > CFO_TH_XTAL_HIGH) + cfo->adjust = true; + } + + /* + * TODO: We should return here only if bluetooth is enabled. + * See the vendor drivers for how to determine that. + */ + if (priv->has_bluetooth) + return; + + if (!cfo->adjust) + return; + + crystal_cap = cfo->crystal_cap; + + if (cfo_average > CFO_TH_XTAL_LOW) + crystal_cap++; + else if (cfo_average < -CFO_TH_XTAL_LOW) + crystal_cap--; + + crystal_cap = clamp(crystal_cap, 0, 0x3f); + + priv->fops->set_crystal_cap(priv, crystal_cap); + + rtl8xxxu_set_atc_status(priv, abs(cfo_average) >= CFO_TH_ATC); +} + +static void rtl8xxxu_ra_iter(void *data, struct ieee80211_sta *sta) +{ + struct rtl8xxxu_sta_info *sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv; + struct rtl8xxxu_priv *priv = data; + int signal = -ewma_rssi_read(&sta_info->avg_rssi); + + priv->fops->report_rssi(priv, rtl8xxxu_get_macid(priv, sta), + rtl8xxxu_signal_to_snr(signal)); + rtl8xxxu_refresh_rate_mask(priv, signal, sta, false); +} + +struct rtl8xxxu_stas_entry { + struct list_head list; + struct ieee80211_sta *sta; +}; + +struct rtl8xxxu_iter_stas_data { + struct rtl8xxxu_priv *priv; + struct list_head list; +}; + +static void rtl8xxxu_collect_sta_iter(void *data, struct ieee80211_sta *sta) +{ + struct rtl8xxxu_iter_stas_data *iter_stas = data; + struct rtl8xxxu_stas_entry *stas_entry; + + stas_entry = kmalloc(sizeof(*stas_entry), GFP_ATOMIC); + if (!stas_entry) + return; + + stas_entry->sta = sta; + list_add_tail(&stas_entry->list, &iter_stas->list); +} + +static void rtl8xxxu_watchdog_callback(struct work_struct *work) +{ + + struct rtl8xxxu_iter_stas_data iter_data; + struct rtl8xxxu_stas_entry *sta_entry, *tmp; + struct rtl8xxxu_priv *priv; + + priv = container_of(work, struct rtl8xxxu_priv, ra_watchdog.work); + iter_data.priv = priv; + INIT_LIST_HEAD(&iter_data.list); + + mutex_lock(&priv->sta_mutex); + ieee80211_iterate_stations_atomic(priv->hw, rtl8xxxu_collect_sta_iter, + &iter_data); + list_for_each_entry_safe(sta_entry, tmp, &iter_data.list, list) { + list_del_init(&sta_entry->list); + rtl8xxxu_ra_iter(priv, sta_entry->sta); + kfree(sta_entry); + } + mutex_unlock(&priv->sta_mutex); + + if (priv->fops->set_crystal_cap) + rtl8xxxu_track_cfo(priv); + + schedule_delayed_work(&priv->ra_watchdog, 2 * HZ); +} + +static int rtl8xxxu_start(struct ieee80211_hw *hw) +{ + struct rtl8xxxu_priv *priv = hw->priv; + struct rtl8xxxu_rx_urb *rx_urb; + struct rtl8xxxu_tx_urb *tx_urb; + struct sk_buff *skb; + unsigned long flags; + int ret, i; + + ret = 0; + + init_usb_anchor(&priv->rx_anchor); + init_usb_anchor(&priv->tx_anchor); + init_usb_anchor(&priv->int_anchor); + + priv->fops->enable_rf(priv); + if (priv->usb_interrupts) { + ret = rtl8xxxu_submit_int_urb(hw); + if (ret) + goto exit; + } + + for (i = 0; i < RTL8XXXU_TX_URBS; i++) { + tx_urb = kmalloc(sizeof(struct rtl8xxxu_tx_urb), GFP_KERNEL); + if (!tx_urb) { + if (!i) + ret = -ENOMEM; + + goto error_out; + } + usb_init_urb(&tx_urb->urb); + INIT_LIST_HEAD(&tx_urb->list); + tx_urb->hw = hw; + list_add(&tx_urb->list, &priv->tx_urb_free_list); + priv->tx_urb_free_count++; + } + + priv->tx_stopped = false; + + spin_lock_irqsave(&priv->rx_urb_lock, flags); + priv->shutdown = false; + spin_unlock_irqrestore(&priv->rx_urb_lock, flags); + + for (i = 0; i < RTL8XXXU_RX_URBS; i++) { + rx_urb = kmalloc(sizeof(struct rtl8xxxu_rx_urb), GFP_KERNEL); + if (!rx_urb) { + if (!i) + ret = -ENOMEM; + + goto error_out; + } + usb_init_urb(&rx_urb->urb); + INIT_LIST_HEAD(&rx_urb->list); + rx_urb->hw = hw; + + ret = rtl8xxxu_submit_rx_urb(priv, rx_urb); + if (ret) { + if (ret != -ENOMEM) { + skb = (struct sk_buff *)rx_urb->urb.context; + dev_kfree_skb(skb); + } + rtl8xxxu_queue_rx_urb(priv, rx_urb); + } + } + + schedule_delayed_work(&priv->ra_watchdog, 2 * HZ); +exit: + /* + * Accept all data and mgmt frames + */ + rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff); + rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff); + + rtl8xxxu_write32_mask(priv, REG_OFDM0_XA_AGC_CORE1, + OFDM0_X_AGC_CORE1_IGI_MASK, 0x1e); + + return ret; + +error_out: + rtl8xxxu_free_tx_resources(priv); + /* + * Disable all data and mgmt frames + */ + rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000); + rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000); + + return ret; +} + +static void rtl8xxxu_stop(struct ieee80211_hw *hw) +{ + struct rtl8xxxu_priv *priv = hw->priv; + unsigned long flags; + + rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); + + rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000); + rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000); + + spin_lock_irqsave(&priv->rx_urb_lock, flags); + priv->shutdown = true; + spin_unlock_irqrestore(&priv->rx_urb_lock, flags); + + usb_kill_anchored_urbs(&priv->rx_anchor); + usb_kill_anchored_urbs(&priv->tx_anchor); + if (priv->usb_interrupts) + usb_kill_anchored_urbs(&priv->int_anchor); + + rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); + + priv->fops->disable_rf(priv); + + /* + * Disable interrupts + */ + if (priv->usb_interrupts) + rtl8xxxu_write32(priv, REG_USB_HIMR, 0); + + cancel_work_sync(&priv->c2hcmd_work); + cancel_delayed_work_sync(&priv->ra_watchdog); + cancel_delayed_work_sync(&priv->update_beacon_work); + + rtl8xxxu_free_rx_resources(priv); + rtl8xxxu_free_tx_resources(priv); +} + +static int rtl8xxxu_sta_add(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + struct ieee80211_sta *sta) +{ + struct rtl8xxxu_sta_info *sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv; + struct rtl8xxxu_vif *rtlvif = (struct rtl8xxxu_vif *)vif->drv_priv; + struct rtl8xxxu_priv *priv = hw->priv; + + mutex_lock(&priv->sta_mutex); + ewma_rssi_init(&sta_info->avg_rssi); + if (vif->type == NL80211_IFTYPE_AP) { + sta_info->rssi_level = RTL8XXXU_RATR_STA_INIT; + sta_info->macid = rtl8xxxu_acquire_macid(priv); + if (sta_info->macid >= RTL8XXXU_MAX_MAC_ID_NUM) { + mutex_unlock(&priv->sta_mutex); + return -ENOSPC; + } + + rtl8xxxu_refresh_rate_mask(priv, 0, sta, true); + priv->fops->report_connect(priv, sta_info->macid, H2C_MACID_ROLE_STA, true); + } else { + switch (rtlvif->port_num) { + case 0: + sta_info->macid = RTL8XXXU_BC_MC_MACID; + break; + case 1: + sta_info->macid = RTL8XXXU_BC_MC_MACID1; + break; + default: + break; + } + } + mutex_unlock(&priv->sta_mutex); + + return 0; +} + +static int rtl8xxxu_sta_remove(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + struct ieee80211_sta *sta) +{ + struct rtl8xxxu_sta_info *sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv; + struct rtl8xxxu_priv *priv = hw->priv; + + mutex_lock(&priv->sta_mutex); + if (vif->type == NL80211_IFTYPE_AP) + rtl8xxxu_release_macid(priv, sta_info->macid); + mutex_unlock(&priv->sta_mutex); + + return 0; +} + +static const struct ieee80211_ops rtl8xxxu_ops = { + .add_chanctx = ieee80211_emulate_add_chanctx, + .remove_chanctx = ieee80211_emulate_remove_chanctx, + .change_chanctx = ieee80211_emulate_change_chanctx, + .switch_vif_chanctx = ieee80211_emulate_switch_vif_chanctx, + .tx = rtl8xxxu_tx, + .wake_tx_queue = ieee80211_handle_wake_tx_queue, + .add_interface = rtl8xxxu_add_interface, + .remove_interface = rtl8xxxu_remove_interface, + .config = rtl8xxxu_config, + .conf_tx = rtl8xxxu_conf_tx, + .bss_info_changed = rtl8xxxu_bss_info_changed, + .start_ap = rtl8xxxu_start_ap, + .configure_filter = rtl8xxxu_configure_filter, + .set_rts_threshold = rtl8xxxu_set_rts_threshold, + .start = rtl8xxxu_start, + .stop = rtl8xxxu_stop, + .sw_scan_start = rtl8xxxu_sw_scan_start, + .sw_scan_complete = rtl8xxxu_sw_scan_complete, + .set_key = rtl8xxxu_set_key, + .ampdu_action = rtl8xxxu_ampdu_action, + .sta_statistics = rtl8xxxu_sta_statistics, + .get_antenna = rtl8xxxu_get_antenna, + .set_tim = rtl8xxxu_set_tim, + .sta_add = rtl8xxxu_sta_add, + .sta_remove = rtl8xxxu_sta_remove, +}; + +static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv, + struct usb_interface *interface) +{ + struct usb_interface_descriptor *interface_desc; + struct usb_host_interface *host_interface; + struct usb_endpoint_descriptor *endpoint; + struct device *dev = &priv->udev->dev; + int i, j = 0, endpoints; + u8 dir, xtype, num; + int ret = 0; + + host_interface = interface->cur_altsetting; + interface_desc = &host_interface->desc; + endpoints = interface_desc->bNumEndpoints; + + for (i = 0; i < endpoints; i++) { + endpoint = &host_interface->endpoint[i].desc; + + dir = endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK; + num = usb_endpoint_num(endpoint); + xtype = usb_endpoint_type(endpoint); + if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB) + dev_dbg(dev, + "%s: endpoint: dir %02x, # %02x, type %02x\n", + __func__, dir, num, xtype); + if (usb_endpoint_dir_in(endpoint) && + usb_endpoint_xfer_bulk(endpoint)) { + if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB) + dev_dbg(dev, "%s: in endpoint num %i\n", + __func__, num); + + if (priv->pipe_in) { + dev_warn(dev, + "%s: Too many IN pipes\n", __func__); + ret = -EINVAL; + goto exit; + } + + priv->pipe_in = usb_rcvbulkpipe(priv->udev, num); + } + + if (usb_endpoint_dir_in(endpoint) && + usb_endpoint_xfer_int(endpoint)) { + if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB) + dev_dbg(dev, "%s: interrupt endpoint num %i\n", + __func__, num); + + if (priv->pipe_interrupt) { + dev_warn(dev, "%s: Too many INTERRUPT pipes\n", + __func__); + ret = -EINVAL; + goto exit; + } + + priv->pipe_interrupt = usb_rcvintpipe(priv->udev, num); + } + + if (usb_endpoint_dir_out(endpoint) && + usb_endpoint_xfer_bulk(endpoint)) { + if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB) + dev_dbg(dev, "%s: out endpoint num %i\n", + __func__, num); + if (j >= RTL8XXXU_OUT_ENDPOINTS) { + dev_warn(dev, + "%s: Too many OUT pipes\n", __func__); + ret = -EINVAL; + goto exit; + } + priv->out_ep[j++] = num; + } + } +exit: + priv->nr_out_eps = j; + return ret; +} + +static void rtl8xxxu_init_led(struct rtl8xxxu_priv *priv) +{ + struct led_classdev *led = &priv->led_cdev; + + if (!priv->fops->led_classdev_brightness_set) + return; + + led->brightness_set_blocking = priv->fops->led_classdev_brightness_set; + + snprintf(priv->led_name, sizeof(priv->led_name), + "rtl8xxxu-usb%s", dev_name(&priv->udev->dev)); + led->name = priv->led_name; + led->max_brightness = RTL8XXXU_HW_LED_CONTROL; + + if (led_classdev_register(&priv->udev->dev, led)) + return; + + priv->led_registered = true; + + led->brightness = led->max_brightness; + priv->fops->led_classdev_brightness_set(led, led->brightness); +} + +static void rtl8xxxu_deinit_led(struct rtl8xxxu_priv *priv) +{ + struct led_classdev *led = &priv->led_cdev; + + if (!priv->led_registered) + return; + + priv->fops->led_classdev_brightness_set(led, LED_OFF); + led_classdev_unregister(led); +} + +static const struct ieee80211_iface_limit rtl8xxxu_limits[] = { + { .max = 2, .types = BIT(NL80211_IFTYPE_STATION), }, + { .max = 1, .types = BIT(NL80211_IFTYPE_AP), }, +}; + +static const struct ieee80211_iface_combination rtl8xxxu_combinations[] = { + { + .limits = rtl8xxxu_limits, + .n_limits = ARRAY_SIZE(rtl8xxxu_limits), + .max_interfaces = 2, + .num_different_channels = 1, + }, +}; + +static int rtl8xxxu_probe(struct usb_interface *interface, + const struct usb_device_id *id) +{ + struct rtl8xxxu_priv *priv; + struct ieee80211_hw *hw; + struct usb_device *udev; + struct ieee80211_supported_band *sband; + int ret; + int untested = 1; + + udev = usb_get_dev(interface_to_usbdev(interface)); + + switch (id->idVendor) { + case USB_VENDOR_ID_REALTEK: + switch(id->idProduct) { + case 0x1724: + case 0x8176: + case 0x8178: + case 0x817f: + case 0x818b: + case 0xf179: + case 0x8179: + case 0xb711: + case 0xf192: + case 0x2005: + untested = 0; + break; + } + break; + case 0x7392: + if (id->idProduct == 0x7811 || id->idProduct == 0xa611 || id->idProduct == 0xb811) + untested = 0; + break; + case 0x050d: + if (id->idProduct == 0x1004) + untested = 0; + break; + case 0x20f4: + if (id->idProduct == 0x648b) + untested = 0; + break; + case 0x2001: + if (id->idProduct == 0x3308) + untested = 0; + break; + case 0x2357: + if (id->idProduct == 0x0109 || id->idProduct == 0x0135) + untested = 0; + break; + case 0x0b05: + if (id->idProduct == 0x18f1) + untested = 0; + break; + default: + break; + } + + if (untested) { + rtl8xxxu_debug |= RTL8XXXU_DEBUG_EFUSE; + dev_info(&udev->dev, + "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n", + id->idVendor, id->idProduct); + dev_info(&udev->dev, + "Please report results to Jes.Sorensen@gmail.com\n"); + } + + hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops); + if (!hw) { + ret = -ENOMEM; + goto err_put_dev; + } + + priv = hw->priv; + priv->hw = hw; + priv->udev = udev; + priv->fops = (struct rtl8xxxu_fileops *)id->driver_info; + mutex_init(&priv->usb_buf_mutex); + mutex_init(&priv->syson_indirect_access_mutex); + mutex_init(&priv->h2c_mutex); + mutex_init(&priv->sta_mutex); + INIT_LIST_HEAD(&priv->tx_urb_free_list); + spin_lock_init(&priv->tx_urb_lock); + INIT_LIST_HEAD(&priv->rx_urb_pending_list); + spin_lock_init(&priv->rx_urb_lock); + INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work); + INIT_DELAYED_WORK(&priv->ra_watchdog, rtl8xxxu_watchdog_callback); + INIT_DELAYED_WORK(&priv->update_beacon_work, rtl8xxxu_update_beacon_work_callback); + skb_queue_head_init(&priv->c2hcmd_queue); + + usb_set_intfdata(interface, hw); + + ret = rtl8xxxu_parse_usb(priv, interface); + if (ret) + goto err_set_intfdata; + + ret = priv->fops->identify_chip(priv); + if (ret) { + dev_err(&udev->dev, "Fatal - failed to identify chip\n"); + goto err_set_intfdata; + } + + hw->wiphy->available_antennas_tx = BIT(priv->tx_paths) - 1; + hw->wiphy->available_antennas_rx = BIT(priv->rx_paths) - 1; + + if (priv->rtl_chip == RTL8188E) + INIT_WORK(&priv->c2hcmd_work, rtl8188e_c2hcmd_callback); + else + INIT_WORK(&priv->c2hcmd_work, rtl8xxxu_c2hcmd_callback); + + ret = priv->fops->read_efuse(priv); + if (ret) { + dev_err(&udev->dev, "Fatal - failed to read EFuse\n"); + goto err_set_intfdata; + } + + ret = priv->fops->parse_efuse(priv); + if (ret) { + dev_err(&udev->dev, "Fatal - failed to parse EFuse\n"); + goto err_set_intfdata; + } + + if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) + rtl8xxxu_dump_efuse(priv); + + rtl8xxxu_print_chipinfo(priv); + + ret = priv->fops->load_firmware(priv); + if (ret) { + dev_err(&udev->dev, "Fatal - failed to load firmware\n"); + goto err_set_intfdata; + } + + ret = rtl8xxxu_init_device(hw); + if (ret) + goto err_set_intfdata; + + hw->vif_data_size = sizeof(struct rtl8xxxu_vif); + + hw->wiphy->max_scan_ssids = 1; + hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN; + if (priv->fops->max_macid_num) + hw->wiphy->max_ap_assoc_sta = priv->fops->max_macid_num - 1; + hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION); + if (priv->fops->supports_ap) + hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_AP); + hw->queues = 4; + + hw->wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH; + + if (priv->fops->supports_concurrent) { + hw->wiphy->iface_combinations = rtl8xxxu_combinations; + hw->wiphy->n_iface_combinations = ARRAY_SIZE(rtl8xxxu_combinations); + } + + sband = &rtl8xxxu_supported_band; + sband->ht_cap.ht_supported = true; + sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; + sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16; + sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40; + memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs)); + sband->ht_cap.mcs.rx_mask[0] = 0xff; + sband->ht_cap.mcs.rx_mask[4] = 0x01; + if (priv->rf_paths > 1) { + sband->ht_cap.mcs.rx_mask[1] = 0xff; + sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40; + } + sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; + /* + * Some APs will negotiate HT20_40 in a noisy environment leading + * to miserable performance. Rather than defaulting to this, only + * enable it if explicitly requested at module load time. + */ + if (rtl8xxxu_ht40_2g) { + dev_info(&udev->dev, "Enabling HT_20_40 on the 2.4GHz band\n"); + sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40; + } + hw->wiphy->bands[NL80211_BAND_2GHZ] = sband; + + hw->wiphy->rts_threshold = 2347; + + SET_IEEE80211_DEV(priv->hw, &interface->dev); + SET_IEEE80211_PERM_ADDR(hw, priv->mac_addr); + + hw->extra_tx_headroom = priv->fops->tx_desc_size; + ieee80211_hw_set(hw, SIGNAL_DBM); + + /* + * The firmware handles rate control, except for RTL8188EU, + * where we handle the rate control in the driver. + */ + ieee80211_hw_set(hw, HAS_RATE_CONTROL); + ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); + ieee80211_hw_set(hw, AMPDU_AGGREGATION); + ieee80211_hw_set(hw, MFP_CAPABLE); + + wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST); + + ret = ieee80211_register_hw(priv->hw); + if (ret) { + dev_err(&udev->dev, "%s: Failed to register: %i\n", + __func__, ret); + goto err_set_intfdata; + } + + rtl8xxxu_init_led(priv); + + return 0; + +err_set_intfdata: + usb_set_intfdata(interface, NULL); + + kfree(priv->fw_data); + mutex_destroy(&priv->usb_buf_mutex); + mutex_destroy(&priv->syson_indirect_access_mutex); + mutex_destroy(&priv->h2c_mutex); + + ieee80211_free_hw(hw); +err_put_dev: + usb_put_dev(udev); + + return ret; +} + +static void rtl8xxxu_disconnect(struct usb_interface *interface) +{ + struct rtl8xxxu_priv *priv; + struct ieee80211_hw *hw; + + hw = usb_get_intfdata(interface); + priv = hw->priv; + + rtl8xxxu_deinit_led(priv); + + ieee80211_unregister_hw(hw); + + priv->fops->power_off(priv); + + usb_set_intfdata(interface, NULL); + + dev_info(&priv->udev->dev, "disconnecting\n"); + + kfree(priv->fw_data); + mutex_destroy(&priv->usb_buf_mutex); + mutex_destroy(&priv->syson_indirect_access_mutex); + mutex_destroy(&priv->h2c_mutex); + + if (priv->udev->state != USB_STATE_NOTATTACHED) { + dev_info(&priv->udev->dev, + "Device still attached, trying to reset\n"); + usb_reset_device(priv->udev); + } + usb_put_dev(priv->udev); + ieee80211_free_hw(hw); +} + +static const struct usb_device_id dev_table[] = { +{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8724, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8723au_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1724, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8723au_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0724, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8723au_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818b, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192eu_fops}, +/* TP-Link TL-WN822N v4 */ +{USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0108, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192eu_fops}, +/* D-Link DWA-131 rev E1, tested by David Patiño */ +{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3319, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192eu_fops}, +/* Tested by Myckel Habets */ +{USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0109, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192eu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb720, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8723bu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0xa611, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8723bu_fops}, +/* RTL8188FU */ +{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xf179, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8188fu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8179, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8188eu_fops}, +/* Tested by Hans de Goede - rtl8188etv */ +{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0179, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8188eu_fops}, +/* Sitecom rtl8188eus */ +{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0076, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8188eu_fops}, +/* D-Link USB-GO-N150 */ +{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3311, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8188eu_fops}, +/* D-Link DWA-125 REV D1 */ +{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330f, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8188eu_fops}, +/* D-Link DWA-123 REV D1 */ +{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3310, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8188eu_fops}, +/* D-Link DWA-121 rev B1 */ +{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x331b, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8188eu_fops}, +/* Abocom - Abocom */ +{USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8179, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8188eu_fops}, +/* Elecom WDC-150SU2M */ +{USB_DEVICE_AND_INTERFACE_INFO(0x056e, 0x4008, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8188eu_fops}, +/* TP-Link TL-WN722N v2 */ +{USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x010c, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8188eu_fops}, +/* TP-Link TL-WN727N v5.21 */ +{USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0111, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8188eu_fops}, +/* MERCUSYS MW150US v2 */ +{USB_DEVICE_AND_INTERFACE_INFO(0x2c4e, 0x0102, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8188eu_fops}, +/* ASUS USB-N10 Nano B1 */ +{USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x18f0, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8188eu_fops}, + /* Edimax EW-7811Un V2 */ +{USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0xb811, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8188eu_fops}, +/* Rosewill USB-N150 Nano */ +{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xffef, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8188eu_fops}, +/* RTL8710BU aka RTL8188GU (not to be confused with RTL8188GTVU) */ +{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb711, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8710bu_fops}, +/* TOTOLINK N150UA V5 / N150UA-B */ +{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2005, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8710bu_fops}, +/* Comfast CF-826F */ +{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xf192, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192fu_fops}, +/* Asus USB-N13 rev C1 */ +{USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x18f1, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192fu_fops}, +/* EDIMAX EW-7722UTn V3 */ +{USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0xb722, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192fu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x318b, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192fu_fops}, +/* TP-Link TL-WN823N V2 */ +{USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0135, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192fu_fops}, +#ifdef CONFIG_RTL8XXXU_UNTESTED +/* Still supported by rtlwifi */ +{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8178, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817f, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +/* Tested by Larry Finger */ +{USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +/* Tested by Andrea Merello */ +{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +/* Tested by Jocelyn Mayer */ +{USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +/* Tested by Stefano Bravi */ +{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +/* Currently untested 8188 series devices */ +{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x018a, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8191, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8170, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8177, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817a, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817b, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817d, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817e, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818a, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1e1e, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x5088, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +/* Currently untested 8192 series devices */ +{USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2e2e, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192cu_fops}, +/* found in rtl8192eu vendor driver */ +{USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0107, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192eu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab33, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192eu_fops}, +{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818c, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192eu_fops}, +/* D-Link DWA-131 rev C1 */ +{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3312, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192eu_fops}, +/* TP-Link TL-WN8200ND V2 */ +{USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0126, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192eu_fops}, +/* Mercusys MW300UM */ +{USB_DEVICE_AND_INTERFACE_INFO(0x2c4e, 0x0100, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192eu_fops}, +/* Mercusys MW300UH */ +{USB_DEVICE_AND_INTERFACE_INFO(0x2c4e, 0x0104, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192eu_fops}, +#endif +{ } +}; + +static struct usb_driver rtl8xxxu_driver = { + .name = DRIVER_NAME, + .probe = rtl8xxxu_probe, + .disconnect = rtl8xxxu_disconnect, + .id_table = dev_table, + .no_dynamic_id = 1, + .disable_hub_initiated_lpm = 1, +}; + +MODULE_DEVICE_TABLE(usb, dev_table); + +module_usb_driver(rtl8xxxu_driver); diff --git a/drivers/net/wireless/realtek/rtl8xxxu/regs.h b/drivers/net/wireless/realtek/rtl8xxxu/regs.h new file mode 100644 index 000000000000..61c0c0ec07b3 --- /dev/null +++ b/drivers/net/wireless/realtek/rtl8xxxu/regs.h @@ -0,0 +1,1381 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2014 - 2017 Jes Sorensen + * + * Register definitions taken from original Realtek rtl8723au driver + */ + +/* 0x0000 ~ 0x00FF System Configuration */ +#define REG_SYS_ISO_CTRL 0x0000 +#define SYS_ISO_MD2PP BIT(0) +#define SYS_ISO_ANALOG_IPS BIT(5) +#define SYS_ISO_DIOR BIT(9) +#define SYS_ISO_PWC_EV25V BIT(14) +#define SYS_ISO_PWC_EV12V BIT(15) + +#define REG_SYS_FUNC 0x0002 +#define SYS_FUNC_BBRSTB BIT(0) +#define SYS_FUNC_BB_GLB_RSTN BIT(1) +#define SYS_FUNC_USBA BIT(2) +#define SYS_FUNC_UPLL BIT(3) +#define SYS_FUNC_USBD BIT(4) +#define SYS_FUNC_DIO_PCIE BIT(5) +#define SYS_FUNC_PCIEA BIT(6) +#define SYS_FUNC_PPLL BIT(7) +#define SYS_FUNC_PCIED BIT(8) +#define SYS_FUNC_DIOE BIT(9) +#define SYS_FUNC_CPU_ENABLE BIT(10) +#define SYS_FUNC_DCORE BIT(11) +#define SYS_FUNC_ELDR BIT(12) +#define SYS_FUNC_DIO_RF BIT(13) +#define SYS_FUNC_HWPDN BIT(14) +#define SYS_FUNC_MREGEN BIT(15) + +#define REG_APS_FSMCO 0x0004 +#define APS_FSMCO_PFM_ALDN BIT(1) +#define APS_FSMCO_PFM_WOWL BIT(3) +#define APS_FSMCO_ENABLE_POWERDOWN BIT(4) +#define APS_FSMCO_MAC_ENABLE BIT(8) +#define APS_FSMCO_MAC_OFF BIT(9) +#define APS_FSMCO_SW_LPS BIT(10) +#define APS_FSMCO_HW_SUSPEND BIT(11) +#define APS_FSMCO_PCIE BIT(12) +#define APS_FSMCO_HW_POWERDOWN BIT(15) +#define APS_FSMCO_WLON_RESET BIT(16) + +#define REG_SYS_CLKR 0x0008 +#define SYS_CLK_ANAD16V_ENABLE BIT(0) +#define SYS_CLK_ANA8M BIT(1) +#define SYS_CLK_MACSLP BIT(4) +#define SYS_CLK_LOADER_ENABLE BIT(5) +#define SYS_CLK_80M_SSC_DISABLE BIT(7) +#define SYS_CLK_80M_SSC_ENABLE_HO BIT(8) +#define SYS_CLK_PHY_SSC_RSTB BIT(9) +#define SYS_CLK_SEC_CLK_ENABLE BIT(10) +#define SYS_CLK_MAC_CLK_ENABLE BIT(11) +#define SYS_CLK_ENABLE BIT(12) +#define SYS_CLK_RING_CLK_ENABLE BIT(13) + +#define REG_9346CR 0x000a +#define EEPROM_BOOT BIT(4) +#define EEPROM_ENABLE BIT(5) + +#define REG_EE_VPD 0x000c +#define REG_AFE_MISC 0x0010 +#define AFE_MISC_WL_XTAL_CTRL BIT(6) + +#define REG_SPS0_CTRL 0x0011 +#define REG_SPS_OCP_CFG 0x0018 +#define REG_8192E_LDOV12_CTRL 0x0014 +#define REG_SYS_SWR_CTRL2 0x0014 +#define REG_RSV_CTRL 0x001c +#define RSV_CTRL_WLOCK_1C BIT(5) +#define RSV_CTRL_DIS_PRST BIT(6) + +#define REG_RF_CTRL 0x001f +#define RF_ENABLE BIT(0) +#define RF_RSTB BIT(1) +#define RF_SDMRSTB BIT(2) + +#define REG_LDOA15_CTRL 0x0020 +#define LDOA15_ENABLE BIT(0) +#define LDOA15_STANDBY BIT(1) +#define LDOA15_OBUF BIT(2) +#define LDOA15_REG_VOS BIT(3) +#define LDOA15_VOADJ_SHIFT 4 + +#define REG_LDOV12D_CTRL 0x0021 +#define LDOV12D_ENABLE BIT(0) +#define LDOV12D_STANDBY BIT(1) +#define LDOV12D_VADJ_SHIFT 4 + +#define REG_LDOHCI12_CTRL 0x0022 + +#define REG_LPLDO_CTRL 0x0023 +#define LPLDO_HSM BIT(2) +#define LPLDO_LSM_DIS BIT(3) + +#define REG_AFE_XTAL_CTRL 0x0024 +#define AFE_XTAL_ENABLE BIT(0) +#define AFE_XTAL_B_SELECT BIT(1) +#define AFE_XTAL_GATE_USB BIT(8) +#define AFE_XTAL_GATE_AFE BIT(11) +#define AFE_XTAL_RF_GATE BIT(14) +#define AFE_XTAL_GATE_DIG BIT(17) +#define AFE_XTAL_BT_GATE BIT(20) + +/* + * 0x0028 is also known as REG_AFE_CTRL2 on 8723bu/8192eu + */ +#define REG_AFE_PLL_CTRL 0x0028 +#define AFE_PLL_ENABLE BIT(0) +#define AFE_PLL_320_ENABLE BIT(1) +#define APE_PLL_FREF_SELECT BIT(2) +#define AFE_PLL_EDGE_SELECT BIT(3) +#define AFE_PLL_WDOGB BIT(4) +#define AFE_PLL_LPF_ENABLE BIT(5) + +#define REG_MAC_PHY_CTRL 0x002c + +#define REG_EFUSE_CTRL 0x0030 +#define REG_EFUSE_TEST 0x0034 +#define EFUSE_TRPT BIT(7) + /* 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 */ +#define EFUSE_CELL_SEL (BIT(8) | BIT(9)) +#define EFUSE_LDOE25_ENABLE BIT(31) +#define EFUSE_SELECT_MASK 0x0300 +#define EFUSE_WIFI_SELECT 0x0000 +#define EFUSE_BT0_SELECT 0x0100 +#define EFUSE_BT1_SELECT 0x0200 +#define EFUSE_BT2_SELECT 0x0300 + +#define EFUSE_ACCESS_ENABLE 0x69 /* RTL8723 only */ +#define EFUSE_ACCESS_DISABLE 0x00 /* RTL8723 only */ + +#define REG_PWR_DATA 0x0038 +#define PWR_DATA_EEPRPAD_RFE_CTRL_EN BIT(11) + +#define REG_CAL_TIMER 0x003c +#define REG_ACLK_MON 0x003e +#define REG_GPIO_MUXCFG 0x0040 +#define GPIO_MUXCFG_IO_SEL_ENBT BIT(5) +#define REG_GPIO_IO_SEL 0x0042 +#define REG_MAC_PINMUX_CFG 0x0043 +#define REG_GPIO_PIN_CTRL 0x0044 +#define REG_GPIO_INTM 0x0048 +#define GPIO_INTM_EDGE_TRIG_IRQ BIT(9) + +#define REG_LEDCFG0 0x004c +#define LEDCFG0_LED0CM GENMASK(2, 0) +#define LEDCFG0_LED1CM GENMASK(10, 8) +#define LED_MODE_SW_CTRL 0x0 +#define LED_MODE_TX_OR_RX_EVENTS 0x3 +#define LEDCFG0_LED0SV BIT(3) +#define LEDCFG0_LED1SV BIT(11) +#define LED_SW_OFF 0x0 +#define LED_SW_ON 0x1 +#define LEDCFG0_LED0_IO_MODE BIT(7) +#define LEDCFG0_LED1_IO_MODE BIT(15) +#define LED_IO_MODE_OUTPUT 0x0 +#define LED_IO_MODE_INPUT 0x1 +#define LEDCFG0_LED2EN BIT(21) +#define LED_GPIO_DISABLE 0x0 +#define LED_GPIO_ENABLE 0x1 +#define LEDCFG0_DPDT_SELECT BIT(23) +#define REG_LEDCFG1 0x004d +#define LEDCFG1_HW_LED_CONTROL BIT(1) +#define LEDCFG1_LED_DISABLE BIT(7) +#define REG_LEDCFG2 0x004e +#define LEDCFG2_HW_LED_CONTROL BIT(1) +#define LEDCFG2_HW_LED_ENABLE BIT(5) +#define LEDCFG2_SW_LED_DISABLE BIT(3) +#define LEDCFG2_SW_LED_CONTROL BIT(5) +#define LEDCFG2_DPDT_SELECT BIT(7) +#define REG_LEDCFG3 0x004f +#define REG_LEDCFG REG_LEDCFG2 +#define REG_FSIMR 0x0050 +#define REG_FSISR 0x0054 +#define REG_HSIMR 0x0058 +#define REG_HSISR 0x005c +/* RTL8723 WIFI/BT/GPS Multi-Function GPIO Pin Control. */ +#define REG_GPIO_PIN_CTRL_2 0x0060 +/* RTL8723 WIFI/BT/GPS Multi-Function GPIO Select. */ +#define REG_GPIO_IO_SEL_2 0x0062 +#define GPIO_IO_SEL_2_GPIO09_INPUT BIT(1) +#define GPIO_IO_SEL_2_GPIO09_IRQ BIT(9) + +/* RTL8723B */ +#define REG_PAD_CTRL1 0x0064 +#define PAD_CTRL1_SW_DPDT_SEL_DATA BIT(0) + +/* RTL8723 only WIFI/BT/GPS Multi-Function control source. */ +#define REG_MULTI_FUNC_CTRL 0x0068 + +#define MULTI_FN_WIFI_HW_PWRDOWN_EN BIT(0) /* Enable GPIO[9] as WiFi HW + powerdown source */ +#define MULTI_FN_WIFI_HW_PWRDOWN_SL BIT(1) /* WiFi HW powerdown polarity + control */ +#define MULTI_WIFI_FUNC_EN BIT(2) /* WiFi function enable */ + +#define MULTI_WIFI_HW_ROF_EN BIT(3) /* Enable GPIO[9] as WiFi RF HW + powerdown source */ +#define MULTI_BT_HW_PWRDOWN_EN BIT(16) /* Enable GPIO[11] as BT HW + powerdown source */ +#define MULTI_BT_HW_PWRDOWN_SL BIT(17) /* BT HW powerdown polarity + control */ +#define MULTI_BT_FUNC_EN BIT(18) /* BT function enable */ +#define MULTI_BT_HW_ROF_EN BIT(19) /* Enable GPIO[11] as BT/GPS + RF HW powerdown source */ +#define MULTI_GPS_HW_PWRDOWN_EN BIT(20) /* Enable GPIO[10] as GPS HW + powerdown source */ +#define MULTI_GPS_HW_PWRDOWN_SL BIT(21) /* GPS HW powerdown polarity + control */ +#define MULTI_GPS_FUNC_EN BIT(22) /* GPS function enable */ + +#define REG_AFE_CTRL4 0x0078 /* 8192eu/8723bu */ +#define REG_LDO_SW_CTRL 0x007c /* 8192eu */ + +#define REG_MCU_FW_DL 0x0080 +#define MCU_FW_DL_ENABLE BIT(0) +#define MCU_FW_DL_READY BIT(1) +#define MCU_FW_DL_CSUM_REPORT BIT(2) +#define MCU_MAC_INIT_READY BIT(3) +#define MCU_BB_INIT_READY BIT(4) +#define MCU_RF_INIT_READY BIT(5) +#define MCU_WINT_INIT_READY BIT(6) +#define MCU_FW_RAM_SEL BIT(7) /* 1: RAM, 0:ROM */ +#define MCU_CP_RESET BIT(23) + +#define REG_HMBOX_EXT_0 0x0088 +#define REG_HMBOX_EXT_1 0x008a +#define REG_HMBOX_EXT_2 0x008c +#define REG_HMBOX_EXT_3 0x008e + +#define REG_RSVD_1 0x0097 + +/* Interrupt registers for 8192e/8723bu/8812 */ +#define REG_HIMR0 0x00b0 +#define IMR0_TXCCK BIT(30) /* TXRPT interrupt when CCX bit + of the packet is set */ +#define IMR0_PSTIMEOUT BIT(29) /* Power Save Time Out Int */ +#define IMR0_GTINT4 BIT(28) /* Set when GTIMER4 expires */ +#define IMR0_GTINT3 BIT(27) /* Set when GTIMER3 expires */ +#define IMR0_TBDER BIT(26) /* Transmit Beacon0 Error */ +#define IMR0_TBDOK BIT(25) /* Transmit Beacon0 OK */ +#define IMR0_TSF_BIT32_TOGGLE BIT(24) /* TSF Timer BIT32 toggle + indication interrupt */ +#define IMR0_BCNDMAINT0 BIT(20) /* Beacon DMA Interrupt 0 */ +#define IMR0_BCNDERR0 BIT(16) /* Beacon Queue DMA Error 0 */ +#define IMR0_HSISR_IND_ON_INT BIT(15) /* HSISR Indicator (HSIMR & + HSISR is true) */ +#define IMR0_BCNDMAINT_E BIT(14) /* Beacon DMA Interrupt + Extension for Win7 */ +#define IMR0_ATIMEND BIT(12) /* CTWidnow End or + ATIM Window End */ +#define IMR0_HISR1_IND_INT BIT(11) /* HISR1 Indicator + (HISR1 & HIMR1 is true) */ +#define IMR0_C2HCMD BIT(10) /* CPU to Host Command INT + Status, Write 1 to clear */ +#define IMR0_CPWM2 BIT(9) /* CPU power Mode exchange INT + Status, Write 1 to clear */ +#define IMR0_CPWM BIT(8) /* CPU power Mode exchange INT + Status, Write 1 to clear */ +#define IMR0_HIGHDOK BIT(7) /* High Queue DMA OK */ +#define IMR0_MGNTDOK BIT(6) /* Management Queue DMA OK */ +#define IMR0_BKDOK BIT(5) /* AC_BK DMA OK */ +#define IMR0_BEDOK BIT(4) /* AC_BE DMA OK */ +#define IMR0_VIDOK BIT(3) /* AC_VI DMA OK */ +#define IMR0_VODOK BIT(2) /* AC_VO DMA OK */ +#define IMR0_RDU BIT(1) /* Rx Descriptor Unavailable */ +#define IMR0_ROK BIT(0) /* Receive DMA OK */ +#define REG_HISR0 0x00b4 +#define REG_HIMR1 0x00b8 +#define IMR1_BCNDMAINT7 BIT(27) /* Beacon DMA Interrupt 7 */ +#define IMR1_BCNDMAINT6 BIT(26) /* Beacon DMA Interrupt 6 */ +#define IMR1_BCNDMAINT5 BIT(25) /* Beacon DMA Interrupt 5 */ +#define IMR1_BCNDMAINT4 BIT(24) /* Beacon DMA Interrupt 4 */ +#define IMR1_BCNDMAINT3 BIT(23) /* Beacon DMA Interrupt 3 */ +#define IMR1_BCNDMAINT2 BIT(22) /* Beacon DMA Interrupt 2 */ +#define IMR1_BCNDMAINT1 BIT(21) /* Beacon DMA Interrupt 1 */ +#define IMR1_BCNDERR7 BIT(20) /* Beacon Queue DMA Err Int 7 */ +#define IMR1_BCNDERR6 BIT(19) /* Beacon Queue DMA Err Int 6 */ +#define IMR1_BCNDERR5 BIT(18) /* Beacon Queue DMA Err Int 5 */ +#define IMR1_BCNDERR4 BIT(17) /* Beacon Queue DMA Err Int 4 */ +#define IMR1_BCNDERR3 BIT(16) /* Beacon Queue DMA Err Int 3 */ +#define IMR1_BCNDERR2 BIT(15) /* Beacon Queue DMA Err Int 2 */ +#define IMR1_BCNDERR1 BIT(14) /* Beacon Queue DMA Err Int 1 */ +#define IMR1_ATIMEND_E BIT(13) /* ATIM Window End Extension + for Win7 */ +#define IMR1_TXERR BIT(11) /* Tx Error Flag Int Status, + write 1 to clear */ +#define IMR1_RXERR BIT(10) /* Rx Error Flag Int Status, + write 1 to clear */ +#define IMR1_TXFOVW BIT(9) /* Transmit FIFO Overflow */ +#define IMR1_RXFOVW BIT(8) /* Receive FIFO Overflow */ +#define REG_HISR1 0x00bc + +/* Host suspend counter on FPGA platform */ +#define REG_HOST_SUSP_CNT 0x00bc +/* Efuse access protection for RTL8723 */ +#define REG_EFUSE_ACCESS 0x00cf +#define REG_BIST_SCAN 0x00d0 +#define REG_BIST_RPT 0x00d4 +#define REG_BIST_ROM_RPT 0x00d8 +#define REG_RSVD_4 0x00dc +#define REG_USB_SIE_INTF 0x00e0 +#define REG_PCIE_MIO_INTF 0x00e4 +#define REG_PCIE_MIO_INTD 0x00e8 +#define REG_HPON_FSM 0x00ec +#define HPON_FSM_BONDING_MASK (BIT(22) | BIT(23)) +#define HPON_FSM_BONDING_1T2R BIT(22) +#define REG_SYS_CFG 0x00f0 +#define SYS_CFG_XCLK_VLD BIT(0) +#define SYS_CFG_ACLK_VLD BIT(1) +#define SYS_CFG_UCLK_VLD BIT(2) +#define SYS_CFG_PCLK_VLD BIT(3) +#define SYS_CFG_PCIRSTB BIT(4) +#define SYS_CFG_V15_VLD BIT(5) +#define SYS_CFG_TRP_B15V_EN BIT(7) +#define SYS_CFG_SW_OFFLOAD_EN BIT(7) /* For chips with IOL support */ +#define SYS_CFG_SIC_IDLE BIT(8) +#define SYS_CFG_BD_MAC2 BIT(9) +#define SYS_CFG_BD_MAC1 BIT(10) +#define SYS_CFG_IC_MACPHY_MODE BIT(11) +#define SYS_CFG_CHIP_VER (BIT(12) | BIT(13) | BIT(14) | BIT(15)) +#define SYS_CFG_BT_FUNC BIT(16) +#define SYS_CFG_VENDOR_ID BIT(19) +#define SYS_CFG_VENDOR_EXT_MASK (BIT(18) | BIT(19)) +#define SYS_CFG_VENDOR_ID_TSMC 0 +#define SYS_CFG_VENDOR_ID_SMIC BIT(18) +#define SYS_CFG_VENDOR_ID_UMC BIT(19) +#define SYS_CFG_PAD_HWPD_IDN BIT(22) +#define SYS_CFG_TRP_VAUX_EN BIT(23) +#define SYS_CFG_TRP_BT_EN BIT(24) +#define SYS_CFG_SPS_LDO_SEL BIT(24) /* 8192eu */ +#define SYS_CFG_BD_PKG_SEL BIT(25) +#define SYS_CFG_BD_HCI_SEL BIT(26) +#define SYS_CFG_TYPE_ID BIT(27) +#define SYS_CFG_RTL_ID BIT(23) /* TestChip ID, + 1:Test(RLE); 0:MP(RL) */ +#define SYS_CFG_SPS_SEL BIT(24) /* 1:LDO regulator mode; + 0:Switching regulator mode*/ +#define SYS_CFG_CHIP_VERSION_MASK 0xf000 /* Bit 12 - 15 */ + +#define REG_GPIO_OUTSTS 0x00f4 /* For RTL8723 only. */ +#define GPIO_EFS_HCI_SEL (BIT(0) | BIT(1)) +#define GPIO_PAD_HCI_SEL (BIT(2) | BIT(3)) +#define GPIO_HCI_SEL (BIT(4) | BIT(5)) +#define GPIO_PKG_SEL_HCI BIT(6) +#define GPIO_FEN_GPS BIT(7) +#define GPIO_FEN_BT BIT(8) +#define GPIO_FEN_WL BIT(9) +#define GPIO_FEN_PCI BIT(10) +#define GPIO_FEN_USB BIT(11) +#define GPIO_BTRF_HWPDN_N BIT(12) +#define GPIO_WLRF_HWPDN_N BIT(13) +#define GPIO_PDN_BT_N BIT(14) +#define GPIO_PDN_GPS_N BIT(15) +#define GPIO_BT_CTL_HWPDN BIT(16) +#define GPIO_GPS_CTL_HWPDN BIT(17) +#define GPIO_PPHY_SUSB BIT(20) +#define GPIO_UPHY_SUSB BIT(21) +#define GPIO_PCI_SUSEN BIT(22) +#define GPIO_USB_SUSEN BIT(23) +#define GPIO_RF_RL_ID (BIT(31) | BIT(30) | BIT(29) | BIT(28)) + +#define REG_SYS_CFG2 0x00fc /* 8192eu */ + +/* 0x0100 ~ 0x01FF MACTOP General Configuration */ +#define REG_CR 0x0100 +#define CR_HCI_TXDMA_ENABLE BIT(0) +#define CR_HCI_RXDMA_ENABLE BIT(1) +#define CR_TXDMA_ENABLE BIT(2) +#define CR_RXDMA_ENABLE BIT(3) +#define CR_PROTOCOL_ENABLE BIT(4) +#define CR_SCHEDULE_ENABLE BIT(5) +#define CR_MAC_TX_ENABLE BIT(6) +#define CR_MAC_RX_ENABLE BIT(7) +#define CR_SW_BEACON_ENABLE BIT(8) +#define CR_SECURITY_ENABLE BIT(9) +#define CR_CALTIMER_ENABLE BIT(10) + +/* Media Status Register */ +#define REG_MSR 0x0102 +#define MSR_LINKTYPE_MASK 0x3 +#define MSR_LINKTYPE_NONE 0x0 +#define MSR_LINKTYPE_ADHOC 0x1 +#define MSR_LINKTYPE_STATION 0x2 +#define MSR_LINKTYPE_AP 0x3 + +#define REG_PBP 0x0104 +#define PBP_PAGE_SIZE_RX_SHIFT 0 +#define PBP_PAGE_SIZE_TX_SHIFT 4 +#define PBP_PAGE_SIZE_64 0x0 +#define PBP_PAGE_SIZE_128 0x1 +#define PBP_PAGE_SIZE_256 0x2 +#define PBP_PAGE_SIZE_512 0x3 +#define PBP_PAGE_SIZE_1024 0x4 + +/* 8188eu IOL magic */ +#define REG_PKT_BUF_ACCESS_CTRL 0x0106 +#define PKT_BUF_ACCESS_CTRL_TX 0x69 +#define PKT_BUF_ACCESS_CTRL_RX 0xa5 + +#define REG_TRXDMA_CTRL 0x010c +#define TRXDMA_CTRL_RXDMA_AGG_EN BIT(2) +#define TRXDMA_CTRL_VOQ_SHIFT 4 +#define TRXDMA_CTRL_VIQ_SHIFT 6 +#define TRXDMA_CTRL_BEQ_SHIFT 8 +#define TRXDMA_CTRL_BKQ_SHIFT 10 +#define TRXDMA_CTRL_MGQ_SHIFT 12 +#define TRXDMA_CTRL_HIQ_SHIFT 14 +#define TRXDMA_CTRL_VOQ_SHIFT_8192F 4 +#define TRXDMA_CTRL_VIQ_SHIFT_8192F 7 +#define TRXDMA_CTRL_BEQ_SHIFT_8192F 10 +#define TRXDMA_CTRL_BKQ_SHIFT_8192F 13 +#define TRXDMA_CTRL_MGQ_SHIFT_8192F 16 +#define TRXDMA_CTRL_HIQ_SHIFT_8192F 19 +#define TRXDMA_QUEUE_LOW 1 +#define TRXDMA_QUEUE_NORMAL 2 +#define TRXDMA_QUEUE_HIGH 3 + +#define REG_TRXFF_BNDY 0x0114 +#define REG_TRXFF_STATUS 0x0118 +#define REG_RXFF_PTR 0x011c +#define REG_HIMR 0x0120 +#define REG_HISR 0x0124 +#define REG_HIMRE 0x0128 +#define REG_HISRE 0x012c +#define REG_CPWM 0x012f +#define REG_FWIMR 0x0130 +#define REG_FWISR 0x0134 +#define REG_FTIMR 0x0138 +#define REG_PKTBUF_DBG_CTRL 0x0140 +#define REG_PKTBUF_DBG_DATA_L 0x0144 +#define REG_PKTBUF_DBG_DATA_H 0x0148 + +#define REG_TC0_CTRL 0x0150 +#define REG_TC1_CTRL 0x0154 +#define REG_TC2_CTRL 0x0158 +#define REG_TC3_CTRL 0x015c +#define REG_TC4_CTRL 0x0160 +#define REG_TCUNIT_BASE 0x0164 +#define REG_MBIST_START 0x0174 +#define REG_MBIST_DONE 0x0178 +#define REG_MBIST_FAIL 0x017c +/* 8188EU */ +#define REG_32K_CTRL 0x0194 +#define REG_C2HEVT_MSG_NORMAL 0x01a0 +/* 8192EU/8723BU/8812 */ +#define REG_C2HEVT_CMD_ID_8723B 0x01ae +#define REG_C2HEVT_CLEAR 0x01af +#define REG_C2HEVT_MSG_TEST 0x01b8 +#define REG_MCUTST_1 0x01c0 +#define REG_FMTHR 0x01c8 +#define REG_HMTFR 0x01cc +#define REG_HMBOX_0 0x01d0 +#define REG_HMBOX_1 0x01d4 +#define REG_HMBOX_2 0x01d8 +#define REG_HMBOX_3 0x01dc + +#define REG_LLT_INIT 0x01e0 +#define LLT_OP_INACTIVE 0x0 +#define LLT_OP_WRITE (0x1 << 30) +#define LLT_OP_READ (0x2 << 30) +#define LLT_OP_MASK (0x3 << 30) + +#define REG_BB_ACCESS_CTRL 0x01e8 +#define REG_BB_ACCESS_DATA 0x01ec + +#define REG_HMBOX_EXT0_8723B 0x01f0 +#define REG_HMBOX_EXT1_8723B 0x01f4 +#define REG_HMBOX_EXT2_8723B 0x01f8 +#define REG_HMBOX_EXT3_8723B 0x01fc + +/* 0x0200 ~ 0x027F TXDMA Configuration */ +#define REG_RQPN 0x0200 +#define RQPN_HI_PQ_SHIFT 0 +#define RQPN_LO_PQ_SHIFT 8 +#define RQPN_PUB_PQ_SHIFT 16 +#define RQPN_LOAD BIT(31) + +#define REG_FIFOPAGE 0x0204 +#define REG_TDECTRL 0x0208 +#define BIT_BCN_VALID BIT(16) + +#define REG_DWBCN0_CTRL_8188F REG_TDECTRL + +#define REG_TXDMA_OFFSET_CHK 0x020c +#define TXDMA_OFFSET_DROP_DATA_EN BIT(9) +#define REG_TXDMA_STATUS 0x0210 +#define REG_RQPN_NPQ 0x0214 +#define RQPN_NPQ_SHIFT 0 +#define RQPN_EPQ_SHIFT 16 + +#define REG_AUTO_LLT 0x0224 +#define AUTO_LLT_INIT_LLT BIT(16) + +#define REG_DWBCN1_CTRL_8723B 0x0228 +#define BIT_SW_BCN_SEL BIT(20) + +/* 0x0280 ~ 0x02FF RXDMA Configuration */ +#define REG_RXDMA_AGG_PG_TH 0x0280 /* 0-7 : USB DMA size bits + 8-14: USB DMA timeout + 15 : Aggregation enable + Only seems to be used + on 8723bu/8192eu */ +#define RXDMA_USB_AGG_ENABLE BIT(31) +#define REG_RXPKT_NUM 0x0284 +#define RXPKT_NUM_RXDMA_IDLE BIT(17) +#define RXPKT_NUM_RW_RELEASE_EN BIT(18) +#define REG_RXDMA_STATUS 0x0288 + +/* Presumably only found on newer chips such as 8723bu */ +#define REG_RX_DMA_CTRL_8723B 0x0286 +#define REG_RXDMA_PRO_8723B 0x0290 +#define RXDMA_PRO_DMA_MODE BIT(1) /* Set to 0x1. */ +#define RXDMA_PRO_DMA_BURST_CNT GENMASK(3, 2) /* Set to 0x3. */ +#define RXDMA_PRO_DMA_BURST_SIZE GENMASK(5, 4) /* Set to 0x1. */ + +#define REG_EARLY_MODE_CONTROL_8710B 0x02bc + +#define REG_RF_BB_CMD_ADDR 0x02c0 +#define REG_RF_BB_CMD_DATA 0x02c4 + +/* spec version 11 */ +/* 0x0400 ~ 0x047F Protocol Configuration */ +/* 8192c, 8192d */ +#define REG_VOQ_INFO 0x0400 +#define REG_VIQ_INFO 0x0404 +#define REG_BEQ_INFO 0x0408 +#define REG_BKQ_INFO 0x040c +/* 8188e, 8723a, 8812a, 8821a, 8192e, 8723b */ +#define REG_Q0_INFO 0x400 +#define REG_Q1_INFO 0x404 +#define REG_Q2_INFO 0x408 +#define REG_Q3_INFO 0x40c + +#define REG_MGQ_INFO 0x0410 +#define REG_HGQ_INFO 0x0414 +#define REG_BCNQ_INFO 0x0418 + +#define REG_CPU_MGQ_INFORMATION 0x041c +#define REG_FWHW_TXQ_CTRL 0x0420 +#define FWHW_TXQ_CTRL_AMPDU_RETRY BIT(7) +#define FWHW_TXQ_CTRL_XMIT_MGMT_ACK BIT(12) +#define EN_BCNQ_DL BIT(22) + +#define REG_HWSEQ_CTRL 0x0423 +#define REG_TXPKTBUF_BCNQ_BDNY 0x0424 +#define REG_TXPKTBUF_MGQ_BDNY 0x0425 +#define REG_LIFETIME_EN 0x0426 +#define REG_MULTI_BCNQ_OFFSET 0x0427 + +#define REG_SPEC_SIFS 0x0428 +#define SPEC_SIFS_CCK_MASK 0x00ff +#define SPEC_SIFS_CCK_SHIFT 0 +#define SPEC_SIFS_OFDM_MASK 0xff00 +#define SPEC_SIFS_OFDM_SHIFT 8 + +#define REG_RETRY_LIMIT 0x042a +#define RETRY_LIMIT_LONG_SHIFT 0 +#define RETRY_LIMIT_LONG_MASK 0x003f +#define RETRY_LIMIT_SHORT_SHIFT 8 +#define RETRY_LIMIT_SHORT_MASK 0x3f00 + +#define REG_DARFRC 0x0430 +#define REG_RARFRC 0x0438 +#define REG_RESPONSE_RATE_SET 0x0440 +#define RESPONSE_RATE_BITMAP_ALL 0xfffff +#define RESPONSE_RATE_RRSR_CCK_ONLY_1M 0xffff1 +#define RESPONSE_RATE_RRSR_INIT_2G 0x15f +#define RESPONSE_RATE_RRSR_INIT_5G 0x150 +#define RSR_1M BIT(0) +#define RSR_2M BIT(1) +#define RSR_5_5M BIT(2) +#define RSR_11M BIT(3) +#define RSR_6M BIT(4) +#define RSR_9M BIT(5) +#define RSR_12M BIT(6) +#define RSR_18M BIT(7) +#define RSR_24M BIT(8) +#define RSR_36M BIT(9) +#define RSR_48M BIT(10) +#define RSR_54M BIT(11) +#define RSR_MCS0 BIT(12) +#define RSR_MCS1 BIT(13) +#define RSR_MCS2 BIT(14) +#define RSR_MCS3 BIT(15) +#define RSR_MCS4 BIT(16) +#define RSR_MCS5 BIT(17) +#define RSR_MCS6 BIT(18) +#define RSR_MCS7 BIT(19) +#define RSR_RSC_LOWER_SUB_CHANNEL BIT(21) /* 0x200000 */ +#define RSR_RSC_UPPER_SUB_CHANNEL BIT(22) /* 0x400000 */ +#define RSR_RSC_BANDWIDTH_40M (RSR_RSC_UPPER_SUB_CHANNEL | \ + RSR_RSC_LOWER_SUB_CHANNEL) +#define RSR_ACK_SHORT_PREAMBLE BIT(23) + +#define REG_ARFR0 0x0444 +#define REG_ARFR1 0x0448 +#define REG_ARFR2 0x044c +#define REG_ARFR3 0x0450 +#define REG_CCK_CHECK 0x0454 +#define BIT_BCN_PORT_SEL BIT(5) +#define REG_AMPDU_MAX_TIME_8723B 0x0456 +#define REG_AGGLEN_LMT 0x0458 +#define REG_AMPDU_MIN_SPACE 0x045c +#define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045d +#define REG_FAST_EDCA_CTRL 0x0460 +#define REG_RD_RESP_PKT_TH 0x0463 +#define REG_INIRTS_RATE_SEL 0x0480 +/* 8723bu */ +#define REG_DATA_SUBCHANNEL 0x0483 +/* 8723au */ +#define REG_INIDATA_RATE_SEL 0x0484 +/* MACID_SLEEP_1/3 for 8723b, 8192e, 8812a, 8821a */ +#define REG_MACID_SLEEP_3_8732B 0x0484 +#define REG_MACID_SLEEP_1_8732B 0x0488 + +#define REG_POWER_STATUS 0x04a4 +#define REG_POWER_STAGE1 0x04b4 +#define REG_POWER_STAGE2 0x04b8 +#define REG_AMPDU_BURST_MODE_8723B 0x04bc +#define REG_PKT_VO_VI_LIFE_TIME 0x04c0 +#define REG_PKT_BE_BK_LIFE_TIME 0x04c2 +#define REG_STBC_SETTING 0x04c4 +#define REG_QUEUE_CTRL 0x04c6 +#define REG_HT_SINGLE_AMPDU_8723B 0x04c7 +#define HT_SINGLE_AMPDU_ENABLE BIT(7) +#define REG_PROT_MODE_CTRL 0x04c8 +#define REG_MAX_AGGR_NUM 0x04ca +#define REG_RTS_MAX_AGGR_NUM 0x04cb +#define REG_BAR_MODE_CTRL 0x04cc +#define REG_RA_TRY_RATE_AGG_LMT 0x04cf +/* MACID_DROP for 8723a */ +#define REG_MACID_DROP_8732A 0x04d0 +/* EARLY_MODE_CONTROL 8188e */ +#define REG_EARLY_MODE_CONTROL_8188E 0x04d0 +/* MACID_SLEEP_2 for 8723b, 8192e, 8812a, 8821a */ +#define REG_MACID_SLEEP_2_8732B 0x04d0 +#define REG_MACID_SLEEP 0x04d4 +#define REG_NQOS_SEQ 0x04dc +#define REG_QOS_SEQ 0x04de +#define REG_NEED_CPU_HANDLE 0x04e0 +#define REG_PKT_LOSE_RPT 0x04e1 +#define REG_PTCL_ERR_STATUS 0x04e2 +#define REG_TX_REPORT_CTRL 0x04ec +#define TX_REPORT_CTRL_TIMER_ENABLE BIT(1) + +#define REG_TX_REPORT_TIME 0x04f0 +#define REG_DUMMY 0x04fc + +/* 0x0500 ~ 0x05FF EDCA Configuration */ +#define REG_EDCA_VO_PARAM 0x0500 +#define REG_EDCA_VI_PARAM 0x0504 +#define REG_EDCA_BE_PARAM 0x0508 +#define REG_EDCA_BK_PARAM 0x050c +#define EDCA_PARAM_ECW_MIN_SHIFT 8 +#define EDCA_PARAM_ECW_MAX_SHIFT 12 +#define EDCA_PARAM_TXOP_SHIFT 16 +#define REG_BEACON_TCFG 0x0510 +#define REG_PIFS 0x0512 +#define REG_RDG_PIFS 0x0513 +#define REG_SIFS_CCK 0x0514 +#define REG_SIFS_OFDM 0x0516 +#define REG_TSFTR_SYN_OFFSET 0x0518 +#define REG_AGGR_BREAK_TIME 0x051a +#define REG_SLOT 0x051b +#define REG_TX_PTCL_CTRL 0x0520 +#define REG_TXPAUSE 0x0522 +#define REG_DIS_TXREQ_CLR 0x0523 +#define REG_RD_CTRL 0x0524 +#define REG_TBTT_PROHIBIT 0x0540 +#define REG_RD_NAV_NXT 0x0544 +#define REG_NAV_PROT_LEN 0x0546 + +#define REG_BEACON_CTRL 0x0550 +#define REG_BEACON_CTRL_1 0x0551 +#define BEACON_ATIM BIT(0) +#define BEACON_CTRL_MBSSID BIT(1) +#define BEACON_CTRL_TX_BEACON_RPT BIT(2) +#define BEACON_FUNCTION_ENABLE BIT(3) +#define BEACON_DISABLE_TSF_UPDATE BIT(4) + +#define REG_MBID_NUM 0x0552 +#define REG_DUAL_TSF_RST 0x0553 +#define DUAL_TSF_RESET_TSF0 BIT(0) +#define DUAL_TSF_RESET_TSF1 BIT(1) +#define DUAL_TSF_RESET_P2P BIT(4) +#define DUAL_TSF_TX_OK BIT(5) + +/* The same as REG_MBSSID_BCN_SPACE */ +#define REG_BCN_INTERVAL 0x0554 +#define REG_MBSSID_BCN_SPACE 0x0554 + +#define REG_DRIVER_EARLY_INT 0x0558 +#define DRIVER_EARLY_INT_TIME 5 + +#define REG_BEACON_DMA_TIME 0x0559 +#define BEACON_DMA_ATIME_INT_TIME 2 + +#define REG_ATIMWND 0x055a +#define REG_USTIME_TSF_8723B 0x055c +#define REG_BCN_MAX_ERR 0x055d +#define REG_RXTSF_OFFSET_CCK 0x055e +#define REG_RXTSF_OFFSET_OFDM 0x055f +#define REG_TSFTR 0x0560 +#define REG_TSFTR1 0x0568 +#define REG_INIT_TSFTR 0x0564 +#define REG_ATIMWND_1 0x0570 +#define REG_PSTIMER 0x0580 +#define REG_TIMER0 0x0584 +#define REG_TIMER1 0x0588 +#define REG_ACM_HW_CTRL 0x05c0 +#define ACM_HW_CTRL_BK BIT(0) +#define ACM_HW_CTRL_BE BIT(1) +#define ACM_HW_CTRL_VI BIT(2) +#define ACM_HW_CTRL_VO BIT(3) +#define REG_ACM_RST_CTRL 0x05c1 +#define REG_ACMAVG 0x05c2 +#define REG_VO_ADMTIME 0x05c4 +#define REG_VI_ADMTIME 0x05c6 +#define REG_BE_ADMTIME 0x05c8 +#define REG_EDCA_RANDOM_GEN 0x05cc +#define REG_SCH_TXCMD 0x05d0 + +/* define REG_FW_TSF_SYNC_CNT 0x04a0 */ +#define REG_SCH_TX_CMD 0x05f8 +#define REG_FW_RESET_TSF_CNT_1 0x05fc +#define REG_FW_RESET_TSF_CNT_0 0x05fd +#define REG_FW_BCN_DIS_CNT 0x05fe + +/* 0x0600 ~ 0x07FF WMAC Configuration */ +#define REG_APSD_CTRL 0x0600 +#define APSD_CTRL_OFF BIT(6) +#define APSD_CTRL_OFF_STATUS BIT(7) +#define REG_BW_OPMODE 0x0603 +#define BW_OPMODE_20MHZ BIT(2) +#define BW_OPMODE_5G BIT(1) +#define BW_OPMODE_11J BIT(0) + +#define REG_TCR 0x0604 + +/* Receive Configuration Register */ +#define REG_RCR 0x0608 +#define RCR_ACCEPT_AP BIT(0) /* Accept all unicast packet */ +#define RCR_ACCEPT_PHYS_MATCH BIT(1) /* Accept phys match packet */ +#define RCR_ACCEPT_MCAST BIT(2) +#define RCR_ACCEPT_BCAST BIT(3) +#define RCR_ACCEPT_ADDR3 BIT(4) /* Accept address 3 match + packet */ +#define RCR_ACCEPT_PM BIT(5) /* Accept power management + packet */ +#define RCR_CHECK_BSSID_MATCH BIT(6) /* Accept BSSID match packet */ +#define RCR_CHECK_BSSID_BEACON BIT(7) /* Accept BSSID match packet + (Rx beacon, probe rsp) */ +#define RCR_ACCEPT_CRC32 BIT(8) /* Accept CRC32 error packet */ +#define RCR_ACCEPT_ICV BIT(9) /* Accept ICV error packet */ +#define RCR_ACCEPT_DATA_FRAME BIT(11) /* Accept all data pkt or use + REG_RXFLTMAP2 */ +#define RCR_ACCEPT_CTRL_FRAME BIT(12) /* Accept all control pkt or use + REG_RXFLTMAP1 */ +#define RCR_ACCEPT_MGMT_FRAME BIT(13) /* Accept all mgmt pkt or use + REG_RXFLTMAP0 */ +#define RCR_HTC_LOC_CTRL BIT(14) /* MFC<--HTC=1 MFC-->HTC=0 */ +#define RCR_UC_DATA_PKT_INT_ENABLE BIT(16) /* Enable unicast data packet + interrupt */ +#define RCR_BM_DATA_PKT_INT_ENABLE BIT(17) /* Enable broadcast data packet + interrupt */ +#define RCR_TIM_PARSER_ENABLE BIT(18) /* Enable RX beacon TIM parser*/ +#define RCR_MFBEN BIT(22) +#define RCR_LSIG_ENABLE BIT(23) /* Enable LSIG TXOP Protection + function. Search KEYCAM for + each rx packet to check if + LSIGEN bit is set. */ +#define RCR_MULTI_BSSID_ENABLE BIT(24) /* Enable Multiple BssId */ +#define RCR_FORCE_ACK BIT(26) +#define RCR_ACCEPT_BA_SSN BIT(27) /* Accept BA SSN */ +#define RCR_APPEND_PHYSTAT BIT(28) +#define RCR_APPEND_ICV BIT(29) +#define RCR_APPEND_MIC BIT(30) +#define RCR_APPEND_FCS BIT(31) /* WMAC append FCS after */ + +#define REG_RX_PKT_LIMIT 0x060c +#define REG_RX_DLK_TIME 0x060d +#define REG_RX_DRVINFO_SZ 0x060f + +#define REG_MACID 0x0610 +#define REG_BSSID 0x0618 +#define REG_MAR 0x0620 +#define REG_MBIDCAMCFG 0x0628 + +#define REG_USTIME_EDCA 0x0638 +#define REG_MAC_SPEC_SIFS 0x063a + +/* 20100719 Joseph: Hardware register definition change. (HW datasheet v54) */ + /* [15:8]SIFS_R2T_OFDM, [7:0]SIFS_R2T_CCK */ +#define REG_R2T_SIFS 0x063c + /* [15:8]SIFS_T2T_OFDM, [7:0]SIFS_T2T_CCK */ +#define REG_T2T_SIFS 0x063e +#define REG_ACKTO 0x0640 +#define REG_CTS2TO 0x0641 +#define REG_EIFS 0x0642 + +/* WMA, BA, CCX */ +#define REG_NAV_CTRL 0x0650 +/* In units of 128us */ +#define REG_NAV_UPPER 0x0652 +#define NAV_UPPER_UNIT 128 + +#define REG_BACAMCMD 0x0654 +#define REG_BACAMCONTENT 0x0658 +#define REG_LBDLY 0x0660 +#define REG_FWDLY 0x0661 +#define REG_RXERR_RPT 0x0664 +#define REG_WMAC_TRXPTCL_CTL 0x0668 +#define WMAC_TRXPTCL_CTL_BW_MASK (BIT(7) | BIT(8)) +#define WMAC_TRXPTCL_CTL_BW_20 0 +#define WMAC_TRXPTCL_CTL_BW_40 BIT(7) +#define WMAC_TRXPTCL_CTL_BW_80 BIT(8) + +/* Security */ +#define REG_CAM_CMD 0x0670 +#define CAM_CMD_POLLING BIT(31) +#define CAM_CMD_WRITE BIT(16) +#define CAM_CMD_KEY_SHIFT 3 +#define REG_CAM_WRITE 0x0674 +#define CAM_WRITE_VALID BIT(15) +#define REG_CAM_READ 0x0678 +#define REG_CAM_DEBUG 0x067c +#define REG_SECURITY_CFG 0x0680 +#define SEC_CFG_TX_USE_DEFKEY BIT(0) +#define SEC_CFG_RX_USE_DEFKEY BIT(1) +#define SEC_CFG_TX_SEC_ENABLE BIT(2) +#define SEC_CFG_RX_SEC_ENABLE BIT(3) +#define SEC_CFG_SKBYA2 BIT(4) +#define SEC_CFG_NO_SKMC BIT(5) +#define SEC_CFG_TXBC_USE_DEFKEY BIT(6) +#define SEC_CFG_RXBC_USE_DEFKEY BIT(7) + +/* Power */ +#define REG_WOW_CTRL 0x0690 +#define REG_PSSTATUS 0x0691 +#define REG_PS_RX_INFO 0x0692 +#define REG_LPNAV_CTRL 0x0694 +#define REG_WKFMCAM_CMD 0x0698 +#define REG_WKFMCAM_RWD 0x069c + +/* + * RX Filters: each bit corresponds to the numerical value of the subtype. + * If it is set the subtype frame type is passed. The filter is only used when + * the RCR_ACCEPT_DATA_FRAME, RCR_ACCEPT_CTRL_FRAME, RCR_ACCEPT_MGMT_FRAME bit + * in the RCR are low. + * + * Example: Beacon subtype is binary 1000 which is decimal 8 so we have to set + * bit 8 (0x100) in REG_RXFLTMAP0 to enable reception. + */ +#define REG_RXFLTMAP0 0x06a0 /* Management frames */ +#define REG_RXFLTMAP1 0x06a2 /* Control frames */ +#define REG_RXFLTMAP2 0x06a4 /* Data frames */ + +#define REG_BCN_PSR_RPT 0x06a8 +#define REG_CALB32K_CTRL 0x06ac +#define REG_PKT_MON_CTRL 0x06b4 +#define REG_BT_COEX_TABLE1 0x06c0 +#define REG_BT_COEX_TABLE2 0x06c4 +#define REG_BT_COEX_TABLE3 0x06c8 +#define REG_BT_COEX_TABLE4 0x06cc +#define REG_WMAC_RESP_TXINFO 0x06d8 + +#define REG_MACID1 0x0700 +#define REG_BSSID1 0x0708 + +/* + * This seems to be 8723bu specific + */ +#define REG_BT_CONTROL_8723BU 0x0764 +#define BT_CONTROL_BT_GRANT BIT(12) + +#define REG_PORT_CONTROL_8710B 0x076d +#define REG_WLAN_ACT_CONTROL_8723B 0x076e + +#define REG_FPGA0_RF_MODE 0x0800 +#define FPGA_RF_MODE BIT(0) +#define FPGA_RF_MODE_JAPAN BIT(1) +#define FPGA_RF_MODE_CCK BIT(24) +#define FPGA_RF_MODE_OFDM BIT(25) + +#define REG_FPGA0_TX_INFO 0x0804 +#define FPGA0_TX_INFO_OFDM_PATH_A BIT(0) +#define FPGA0_TX_INFO_OFDM_PATH_B BIT(1) +#define FPGA0_TX_INFO_OFDM_PATH_C BIT(2) +#define FPGA0_TX_INFO_OFDM_PATH_D BIT(3) +#define REG_FPGA0_PSD_FUNC 0x0808 +#define REG_FPGA0_TX_GAIN 0x080c +#define REG_FPGA0_RF_TIMING1 0x0810 +#define REG_FPGA0_RF_TIMING2 0x0814 +#define REG_FPGA0_POWER_SAVE 0x0818 +#define FPGA0_PS_LOWER_CHANNEL BIT(26) +#define FPGA0_PS_UPPER_CHANNEL BIT(27) + +#define REG_FPGA0_XA_HSSI_PARM1 0x0820 /* RF 3 wire register */ +#define FPGA0_HSSI_PARM1_PI BIT(8) +#define REG_FPGA0_XA_HSSI_PARM2 0x0824 +#define REG_FPGA0_XB_HSSI_PARM1 0x0828 +#define REG_FPGA0_XB_HSSI_PARM2 0x082c +#define FPGA0_HSSI_3WIRE_DATA_LEN 0x800 +#define FPGA0_HSSI_3WIRE_ADDR_LEN 0x400 +#define FPGA0_HSSI_PARM2_ADDR_SHIFT 23 +#define FPGA0_HSSI_PARM2_ADDR_MASK 0x7f800000 /* 0xff << 23 */ +#define FPGA0_HSSI_PARM2_CCK_HIGH_PWR BIT(9) +#define FPGA0_HSSI_PARM2_EDGE_READ BIT(31) + +#define REG_TX_AGC_B_RATE18_06 0x0830 +#define REG_TX_AGC_B_RATE54_24 0x0834 +#define REG_TX_AGC_B_CCK1_55_MCS32 0x0838 +#define REG_TX_AGC_B_MCS03_MCS00 0x083c + +#define REG_FPGA0_XA_LSSI_PARM 0x0840 +#define REG_FPGA0_XB_LSSI_PARM 0x0844 +#define FPGA0_LSSI_PARM_ADDR_SHIFT 20 +#define FPGA0_LSSI_PARM_ADDR_MASK 0x0ff00000 +#define FPGA0_LSSI_PARM_DATA_MASK 0x000fffff + +#define REG_TX_AGC_B_MCS07_MCS04 0x0848 +#define REG_TX_AGC_B_MCS11_MCS08 0x084c + +#define REG_FPGA0_XCD_SWITCH_CTRL 0x085c + +#define REG_FPGA0_XA_RF_INT_OE 0x0860 /* RF Channel switch */ +#define REG_FPGA0_XB_RF_INT_OE 0x0864 +#define FPGA0_INT_OE_ANTENNA_AB_OPEN 0x000 +#define FPGA0_INT_OE_ANTENNA_A BIT(8) +#define FPGA0_INT_OE_ANTENNA_B BIT(9) +#define FPGA0_INT_OE_ANTENNA_MASK (FPGA0_INT_OE_ANTENNA_A | \ + FPGA0_INT_OE_ANTENNA_B) + +#define REG_TX_AGC_B_MCS15_MCS12 0x0868 +#define REG_TX_AGC_B_CCK11_A_CCK2_11 0x086c + +#define REG_FPGA0_XAB_RF_SW_CTRL 0x0870 +#define REG_FPGA0_XA_RF_SW_CTRL 0x0870 /* 16 bit */ +#define REG_FPGA0_XB_RF_SW_CTRL 0x0872 /* 16 bit */ +#define REG_FPGA0_XCD_RF_SW_CTRL 0x0874 +#define REG_FPGA0_XC_RF_SW_CTRL 0x0874 /* 16 bit */ +#define REG_FPGA0_XD_RF_SW_CTRL 0x0876 /* 16 bit */ +#define FPGA0_RF_3WIRE_DATA BIT(0) +#define FPGA0_RF_3WIRE_CLOC BIT(1) +#define FPGA0_RF_3WIRE_LOAD BIT(2) +#define FPGA0_RF_3WIRE_RW BIT(3) +#define FPGA0_RF_3WIRE_MASK 0xf +#define FPGA0_RF_RFENV BIT(4) +#define FPGA0_RF_TRSW BIT(5) /* Useless now */ +#define FPGA0_RF_TRSWB BIT(6) +#define FPGA0_RF_ANTSW BIT(8) +#define FPGA0_RF_ANTSWB BIT(9) +#define FPGA0_RF_PAPE BIT(10) +#define FPGA0_RF_PAPE5G BIT(11) +#define FPGA0_RF_BD_CTRL_SHIFT 16 + +#define REG_FPGA0_XAB_RF_PARM 0x0878 /* Antenna select path in ODM */ +#define REG_FPGA0_XA_RF_PARM 0x0878 /* 16 bit */ +#define REG_FPGA0_XB_RF_PARM 0x087a /* 16 bit */ +#define REG_FPGA0_XCD_RF_PARM 0x087c +#define REG_FPGA0_XC_RF_PARM 0x087c /* 16 bit */ +#define REG_FPGA0_XD_RF_PARM 0x087e /* 16 bit */ +#define FPGA0_RF_PARM_RFA_ENABLE BIT(1) +#define FPGA0_RF_PARM_RFB_ENABLE BIT(17) +#define FPGA0_RF_PARM_CLK_GATE BIT(31) + +#define REG_FPGA0_ANALOG1 0x0880 +#define REG_FPGA0_ANALOG2 0x0884 +#define FPGA0_ANALOG2_20MHZ BIT(10) +#define REG_FPGA0_ANALOG3 0x0888 +#define REG_FPGA0_ANALOG4 0x088c + +#define REG_NHM_TH9_TH10_8723B 0x0890 +#define REG_NHM_TIMER_8723B 0x0894 +#define REG_NHM_TH3_TO_TH0_8723B 0x0898 +#define REG_NHM_TH7_TO_TH4_8723B 0x089c + +#define REG_FPGA0_XA_LSSI_READBACK 0x08a0 /* Tranceiver LSSI Readback */ +#define REG_FPGA0_XB_LSSI_READBACK 0x08a4 +#define REG_FPGA0_PSD_REPORT 0x08b4 +#define REG_HSPI_XA_READBACK 0x08b8 /* Transceiver A HSPI read */ +#define REG_HSPI_XB_READBACK 0x08bc /* Transceiver B HSPI read */ + +#define REG_FPGA1_RF_MODE 0x0900 + +#define REG_FPGA1_TX_INFO 0x090c +#define FPGA1_TX_ANT_MASK 0x0000000f +#define FPGA1_TX_ANT_L_MASK 0x000000f0 +#define FPGA1_TX_ANT_NON_HT_MASK 0x00000f00 +#define FPGA1_TX_ANT_HT1_MASK 0x0000f000 +#define FPGA1_TX_ANT_HT2_MASK 0x000f0000 +#define FPGA1_TX_ANT_HT_S1_MASK 0x00f00000 +#define FPGA1_TX_ANT_NON_HT_S1_MASK 0x0f000000 +#define FPGA1_TX_OFDM_TXSC_MASK 0x30000000 + +#define REG_ANT_MAPPING1 0x0914 +#define REG_RFE_OPT 0x0920 +#define REG_DPDT_CTRL 0x092c /* 8723BU */ +#define REG_RFE_CTRL_ANTA_SRC 0x0930 /* 8723BU */ +#define REG_RFE_CTRL_ANT_SRC1 0x0934 +#define REG_RFE_CTRL_ANT_SRC2 0x0938 +#define REG_RFE_CTRL_ANT_SRC3 0x093c +#define REG_RFE_PATH_SELECT 0x0940 /* 8723BU */ +#define REG_RFE_BUFFER 0x0944 /* 8723BU */ +#define REG_S0S1_PATH_SWITCH 0x0948 /* 8723BU */ +#define REG_RX_DFIR_MOD_97F 0x0948 +#define REG_OFDM_RX_DFIR 0x954 +#define REG_RFE_OPT62 0x0968 + +#define REG_CCK0_SYSTEM 0x0a00 +#define CCK0_SIDEBAND BIT(4) + +#define REG_CCK0_AFE_SETTING 0x0a04 +#define CCK0_AFE_RX_MASK 0x0f000000 +#define CCK0_AFE_TX_MASK 0xf0000000 +#define CCK0_AFE_RX_ANT_A 0 +#define CCK0_AFE_RX_ANT_B BIT(26) +#define CCK0_AFE_RX_ANT_C BIT(27) +#define CCK0_AFE_RX_ANT_D (BIT(26) | BIT(27)) +#define CCK0_AFE_RX_ANT_OPTION_A 0 +#define CCK0_AFE_RX_ANT_OPTION_B BIT(24) +#define CCK0_AFE_RX_ANT_OPTION_C BIT(25) +#define CCK0_AFE_RX_ANT_OPTION_D (BIT(24) | BIT(25)) +#define CCK0_AFE_TX_ANT_A BIT(31) +#define CCK0_AFE_TX_ANT_B BIT(30) + +#define REG_CCK_ANTDIV_PARA2 0x0a04 +#define REG_BB_POWER_SAVE4 0x0a74 + +/* 8188eu */ +#define REG_LNA_SWITCH 0x0b2c +#define LNA_SWITCH_DISABLE_CSCG BIT(22) +#define LNA_SWITCH_OUTPUT_CG BIT(31) + +#define REG_CCK_PD_THRESH 0x0a0a +#define CCK_PD_TYPE1_LV0_TH 0x40 +#define CCK_PD_TYPE1_LV1_TH 0x83 +#define CCK_PD_TYPE1_LV2_TH 0xcd +#define CCK_PD_TYPE1_LV3_TH 0xdd +#define CCK_PD_TYPE1_LV4_TH 0xed + +#define REG_CCK0_TX_FILTER1 0x0a20 +#define REG_CCK0_TX_FILTER2 0x0a24 +#define REG_CCK0_DEBUG_PORT 0x0a28 /* debug port and Tx filter3 */ +#define REG_AGC_RPT 0xa80 +#define AGC_RPT_CCK BIT(7) +#define REG_CCK0_TX_FILTER3 0x0aac + +#define REG_CONFIG_ANT_A 0x0b68 +#define REG_CONFIG_ANT_B 0x0b6c + +#define REG_OFDM0_TRX_PATH_ENABLE 0x0c04 +#define OFDM_RF_PATH_RX_MASK 0x0f +#define OFDM_RF_PATH_RX_A BIT(0) +#define OFDM_RF_PATH_RX_B BIT(1) +#define OFDM_RF_PATH_RX_C BIT(2) +#define OFDM_RF_PATH_RX_D BIT(3) +#define OFDM_RF_PATH_TX_MASK 0xf0 +#define OFDM_RF_PATH_TX_A BIT(4) +#define OFDM_RF_PATH_TX_B BIT(5) +#define OFDM_RF_PATH_TX_C BIT(6) +#define OFDM_RF_PATH_TX_D BIT(7) + +#define REG_OFDM0_TR_MUX_PAR 0x0c08 + +#define REG_OFDM0_FA_RSTC 0x0c0c + +#define REG_DOWNSAM_FACTOR 0x0c10 + +#define REG_OFDM0_XA_RX_AFE 0x0c10 +#define REG_OFDM0_XA_RX_IQ_IMBALANCE 0x0c14 +#define REG_OFDM0_XB_RX_IQ_IMBALANCE 0x0c1c + +#define REG_OFDM0_ENERGY_CCA_THRES 0x0c4c + +#define REG_OFDM0_RX_D_SYNC_PATH 0x0c40 +#define OFDM0_SYNC_PATH_NOTCH_FILTER BIT(1) + +#define REG_OFDM0_XA_AGC_CORE1 0x0c50 +#define REG_OFDM0_XA_AGC_CORE2 0x0c54 +#define REG_OFDM0_XB_AGC_CORE1 0x0c58 +#define REG_OFDM0_XB_AGC_CORE2 0x0c5c +#define REG_OFDM0_XC_AGC_CORE1 0x0c60 +#define REG_OFDM0_XC_AGC_CORE2 0x0c64 +#define REG_OFDM0_XD_AGC_CORE1 0x0c68 +#define REG_OFDM0_XD_AGC_CORE2 0x0c6c +#define OFDM0_X_AGC_CORE1_IGI_MASK 0x0000007F + +#define REG_OFDM0_AGC_PARM1 0x0c70 + +#define REG_OFDM0_AGC_RSSI_TABLE 0x0c78 + +#define REG_OFDM0_XA_TX_IQ_IMBALANCE 0x0c80 +#define REG_OFDM0_XB_TX_IQ_IMBALANCE 0x0c88 +#define REG_OFDM0_XC_TX_IQ_IMBALANCE 0x0c90 +#define REG_OFDM0_XD_TX_IQ_IMBALANCE 0x0c98 + +#define REG_OFDM0_XC_TX_AFE 0x0c94 +#define REG_OFDM0_XD_TX_AFE 0x0c9c + +#define REG_OFDM0_RX_IQ_EXT_ANTA 0x0ca0 + +/* 8188eu */ +#define REG_ANTDIV_PARA1 0x0ca4 + +#define REG_RXIQB_EXT 0x0ca8 + +/* 8723bu */ +#define REG_OFDM0_TX_PSDO_NOISE_WEIGHT 0x0ce4 + +#define REG_OFDM1_LSTF 0x0d00 +#define OFDM_LSTF_PRIME_CH_LOW BIT(10) +#define OFDM_LSTF_PRIME_CH_HIGH BIT(11) +#define OFDM_LSTF_PRIME_CH_MASK (OFDM_LSTF_PRIME_CH_LOW | \ + OFDM_LSTF_PRIME_CH_HIGH) +#define OFDM_LSTF_CONTINUE_TX BIT(28) +#define OFDM_LSTF_SINGLE_CARRIER BIT(29) +#define OFDM_LSTF_SINGLE_TONE BIT(30) +#define OFDM_LSTF_MASK 0x70000000 + +#define REG_OFDM1_TRX_PATH_ENABLE 0x0d04 +#define REG_OFDM1_CFO_TRACKING 0x0d2c +#define CFO_TRACKING_ATC_STATUS BIT(11) +#define REG_OFDM1_CSI_FIX_MASK1 0x0d40 +#define REG_OFDM1_CSI_FIX_MASK2 0x0d44 + +#define REG_ANAPWR1 0x0d94 + +#define REG_TX_AGC_A_RATE18_06 0x0e00 +#define REG_TX_AGC_A_RATE54_24 0x0e04 +#define REG_TX_AGC_A_CCK1_MCS32 0x0e08 +#define REG_TX_AGC_A_MCS03_MCS00 0x0e10 +#define REG_TX_AGC_A_MCS07_MCS04 0x0e14 +#define REG_TX_AGC_A_MCS11_MCS08 0x0e18 +#define REG_TX_AGC_A_MCS15_MCS12 0x0e1c + +#define REG_NP_ANTA 0x0e20 + +#define REG_TAP_UPD_97F 0x0e24 + +#define REG_FPGA0_IQK 0x0e28 + +#define REG_TX_IQK_TONE_A 0x0e30 +#define REG_RX_IQK_TONE_A 0x0e34 +#define REG_TX_IQK_PI_A 0x0e38 +#define REG_RX_IQK_PI_A 0x0e3c + +#define REG_TX_IQK 0x0e40 +#define REG_RX_IQK 0x0e44 +#define REG_IQK_AGC_PTS 0x0e48 +#define REG_IQK_AGC_RSP 0x0e4c +#define REG_TX_IQK_TONE_B 0x0e50 +#define REG_RX_IQK_TONE_B 0x0e54 +#define REG_TX_IQK_PI_B 0x0e58 +#define REG_RX_IQK_PI_B 0x0e5c +#define REG_IQK_AGC_CONT 0x0e60 + +#define REG_BLUETOOTH 0x0e6c +#define REG_RX_WAIT_CCA 0x0e70 +#define REG_TX_CCK_RFON 0x0e74 +#define REG_TX_CCK_BBON 0x0e78 +#define REG_TX_OFDM_RFON 0x0e7c +#define REG_TX_OFDM_BBON 0x0e80 +#define REG_TX_TO_RX 0x0e84 +#define REG_TX_TO_TX 0x0e88 +#define REG_RX_CCK 0x0e8c + +#define REG_TX_POWER_BEFORE_IQK_A 0x0e94 +#define REG_IQK_RPT_TXA 0x0e98 +#define REG_TX_POWER_AFTER_IQK_A 0x0e9c + +#define REG_RX_POWER_BEFORE_IQK_A 0x0ea0 +#define REG_RX_POWER_BEFORE_IQK_A_2 0x0ea4 +#define REG_RX_POWER_AFTER_IQK_A 0x0ea8 +#define REG_IQK_RPT_RXA 0x0ea8 +#define REG_RX_POWER_AFTER_IQK_A_2 0x0eac + +#define REG_TX_POWER_BEFORE_IQK_B 0x0eb4 +#define REG_IQK_RPT_TXB 0x0eb8 +#define REG_TX_POWER_AFTER_IQK_B 0x0ebc + +#define REG_RX_POWER_BEFORE_IQK_B 0x0ec0 +#define REG_RX_POWER_BEFORE_IQK_B_2 0x0ec4 +#define REG_RX_POWER_AFTER_IQK_B 0x0ec8 +#define REG_IQK_RPT_RXB 0x0ec8 +#define REG_RX_POWER_AFTER_IQK_B_2 0x0ecc + +#define REG_RX_OFDM 0x0ed0 +#define REG_RX_WAIT_RIFS 0x0ed4 +#define REG_RX_TO_RX 0x0ed8 +#define REG_STANDBY 0x0edc +#define REG_SLEEP 0x0ee0 +#define REG_PMPD_ANAEN 0x0eec + +#define REG_FW_START_ADDRESS 0x1000 +#define REG_FW_START_ADDRESS_8192F 0x4000 + +#define REG_SW_GPIO_SHARE_CTRL_0 0x1038 +#define REG_SW_GPIO_SHARE_CTRL_1 0x103c +#define REG_GPIO_A0 0x1050 +#define REG_GPIO_B0 0x105b + +#define REG_USB_INFO 0xfe17 +#define REG_USB_HIMR 0xfe38 +#define USB_HIMR_TIMEOUT2 BIT(31) +#define USB_HIMR_TIMEOUT1 BIT(30) +#define USB_HIMR_PSTIMEOUT BIT(29) +#define USB_HIMR_GTINT4 BIT(28) +#define USB_HIMR_GTINT3 BIT(27) +#define USB_HIMR_TXBCNERR BIT(26) +#define USB_HIMR_TXBCNOK BIT(25) +#define USB_HIMR_TSF_BIT32_TOGGLE BIT(24) +#define USB_HIMR_BCNDMAINT3 BIT(23) +#define USB_HIMR_BCNDMAINT2 BIT(22) +#define USB_HIMR_BCNDMAINT1 BIT(21) +#define USB_HIMR_BCNDMAINT0 BIT(20) +#define USB_HIMR_BCNDOK3 BIT(19) +#define USB_HIMR_BCNDOK2 BIT(18) +#define USB_HIMR_BCNDOK1 BIT(17) +#define USB_HIMR_BCNDOK0 BIT(16) +#define USB_HIMR_HSISR_IND BIT(15) +#define USB_HIMR_BCNDMAINT_E BIT(14) +/* RSVD BIT(13) */ +#define USB_HIMR_CTW_END BIT(12) +/* RSVD BIT(11) */ +#define USB_HIMR_C2HCMD BIT(10) +#define USB_HIMR_CPWM2 BIT(9) +#define USB_HIMR_CPWM BIT(8) +#define USB_HIMR_HIGHDOK BIT(7) /* High Queue DMA OK + Interrupt */ +#define USB_HIMR_MGNTDOK BIT(6) /* Management Queue DMA OK + Interrupt */ +#define USB_HIMR_BKDOK BIT(5) /* AC_BK DMA OK Interrupt */ +#define USB_HIMR_BEDOK BIT(4) /* AC_BE DMA OK Interrupt */ +#define USB_HIMR_VIDOK BIT(3) /* AC_VI DMA OK Interrupt */ +#define USB_HIMR_VODOK BIT(2) /* AC_VO DMA Interrupt */ +#define USB_HIMR_RDU BIT(1) /* Receive Descriptor + Unavailable */ +#define USB_HIMR_ROK BIT(0) /* Receive DMA OK Interrupt */ + +#define REG_USB_ACCESS_TIMEOUT 0xfe4c + +#define REG_USB_SPECIAL_OPTION 0xfe55 +#define USB_SPEC_USB_AGG_ENABLE BIT(3) /* Enable USB aggregation */ +#define USB_SPEC_INT_BULK_SELECT BIT(4) /* Use interrupt endpoint to + deliver interrupt packet. + 0: Use int, 1: use bulk */ +#define REG_USB_HRPWM 0xfe58 +#define REG_USB_DMA_AGG_TO 0xfe5b +#define REG_USB_AGG_TIMEOUT 0xfe5c +#define REG_USB_AGG_THRESH 0xfe5d + +#define REG_NORMAL_SIE_VID 0xfe60 /* 0xfe60 - 0xfe61 */ +#define REG_NORMAL_SIE_PID 0xfe62 /* 0xfe62 - 0xfe63 */ +#define REG_NORMAL_SIE_OPTIONAL 0xfe64 +#define REG_NORMAL_SIE_EP 0xfe65 /* 0xfe65 - 0xfe67 */ +#define REG_NORMAL_SIE_EP_TX 0xfe66 +#define NORMAL_SIE_EP_TX_HIGH_MASK 0x000f +#define NORMAL_SIE_EP_TX_NORMAL_MASK 0x00f0 +#define NORMAL_SIE_EP_TX_LOW_MASK 0x0f00 + +#define REG_NORMAL_SIE_PHY 0xfe68 /* 0xfe68 - 0xfe6b */ +#define REG_NORMAL_SIE_OPTIONAL2 0xfe6c +#define REG_NORMAL_SIE_GPS_EP 0xfe6d /* RTL8723 only */ +#define REG_NORMAL_SIE_MAC_ADDR 0xfe70 /* 0xfe70 - 0xfe75 */ +#define REG_NORMAL_SIE_STRING 0xfe80 /* 0xfe80 - 0xfedf */ + +/* + * 8710B register addresses between 0x00 and 0xff must have 0x8000 + * added to them. We take care of that in the rtl8xxxu_read{8,16,32} + * and rtl8xxxu_write{8,16,32} functions. + */ +#define REG_SYS_FUNC_8710B 0x0004 +#define REG_AFE_CTRL_8710B 0x0050 +#define REG_WL_RF_PSS_8710B 0x005c +#define REG_EFUSE_INDIRECT_CTRL_8710B 0x006c +#define NORMAL_REG_READ_OFFSET 0x83000000 +#define NORMAL_REG_WRITE_OFFSET 0x84000000 +#define EFUSE_READ_OFFSET 0x85000000 +#define EFUSE_WRITE_OFFSET 0x86000000 +#define REG_HIMR0_8710B 0x0080 +#define REG_HISR0_8710B 0x0084 +/* + * 8710B uses this instead of REG_MCU_FW_DL, but at least bits + * 0-7 have the same meaning. + */ +#define REG_8051FW_CTRL_V1_8710B 0x0090 +#define REG_USB_HOST_INDIRECT_DATA_8710B 0x009c +#define REG_WL_STATUS_8710B 0x00f0 +#define REG_USB_HOST_INDIRECT_ADDR_8710B 0x00f8 + +/* + * 8710B registers which must be accessed through rtl8710b_read_syson_reg + * and rtl8710b_write_syson_reg. + */ +#define SYSON_REG_BASE_ADDR_8710B 0x40000000 +#define REG_SYS_XTAL_CTRL0_8710B 0x060 +#define REG_SYS_EEPROM_CTRL0_8710B 0x0e0 +#define REG_SYS_SYSTEM_CFG0_8710B 0x1f0 +#define REG_SYS_SYSTEM_CFG1_8710B 0x1f4 +#define REG_SYS_SYSTEM_CFG2_8710B 0x1f8 + +/* RF6052 registers */ +#define RF6052_REG_AC 0x00 +#define RF6052_REG_IQADJ_G1 0x01 +#define RF6052_REG_IQADJ_G2 0x02 +#define RF6052_REG_BS_PA_APSET_G1_G4 0x03 +#define RF6052_REG_BS_PA_APSET_G5_G8 0x04 +#define RF6052_REG_POW_TRSW 0x05 +#define RF6052_REG_GAIN_RX 0x06 +#define RF6052_REG_GAIN_TX 0x07 +#define RF6052_REG_TXM_IDAC 0x08 +#define RF6052_REG_IPA_G 0x09 +#define RF6052_REG_TXBIAS_G 0x0a +#define RF6052_REG_TXPA_AG 0x0b +#define RF6052_REG_IPA_A 0x0c +#define RF6052_REG_TXBIAS_A 0x0d +#define RF6052_REG_BS_PA_APSET_G9_G11 0x0e +#define RF6052_REG_BS_IQGEN 0x0f +#define RF6052_REG_MODE1 0x10 +#define RF6052_REG_MODE2 0x11 +#define RF6052_REG_RX_AGC_HP 0x12 +#define RF6052_REG_TX_AGC 0x13 +#define RF6052_REG_BIAS 0x14 +#define RF6052_REG_IPA 0x15 +#define RF6052_REG_TXBIAS 0x16 +#define RF6052_REG_POW_ABILITY 0x17 +#define RF6052_REG_MODE_AG 0x18 /* RF channel and BW switch */ +#define MODE_AG_CHANNEL_MASK 0x3ff +#define MODE_AG_CHANNEL_20MHZ BIT(10) +#define MODE_AG_BW_MASK (BIT(10) | BIT(11)) +#define MODE_AG_BW_20MHZ_8723B (BIT(10) | BIT(11)) +#define MODE_AG_BW_40MHZ_8723B BIT(10) +#define MODE_AG_BW_80MHZ_8723B 0 + +#define RF6052_REG_TOP 0x19 +#define RF6052_REG_RX_G1 0x1a +#define RF6052_REG_RX_G2 0x1b +#define RF6052_REG_RX_BB2 0x1c +#define RF6052_REG_RX_BB1 0x1d +#define RF6052_REG_RCK1 0x1e +#define RF6052_REG_RCK2 0x1f +#define RF6052_REG_TX_G1 0x20 +#define RF6052_REG_TX_G2 0x21 +#define RF6052_REG_TX_G3 0x22 +#define RF6052_REG_TX_BB1 0x23 +#define RF6052_REG_T_METER 0x24 +#define RF6052_REG_SYN_G1 0x25 /* RF TX Power control */ +#define RF6052_REG_SYN_G2 0x26 /* RF TX Power control */ +#define RF6052_REG_SYN_G3 0x27 /* RF TX Power control */ +#define RF6052_REG_SYN_G4 0x28 /* RF TX Power control */ +#define RF6052_REG_SYN_G5 0x29 /* RF TX Power control */ +#define RF6052_REG_SYN_G6 0x2a /* RF TX Power control */ +#define RF6052_REG_SYN_G7 0x2b /* RF TX Power control */ +#define RF6052_REG_SYN_G8 0x2c /* RF TX Power control */ + +#define RF6052_REG_RCK_OS 0x30 /* RF TX PA control */ + +#define RF6052_REG_TXPA_G1 0x31 /* RF TX PA control */ +#define RF6052_REG_TXPA_G2 0x32 /* RF TX PA control */ +#define RF6052_REG_TXPA_G3 0x33 /* RF TX PA control */ + +/* + * NextGen regs: 8723BU + */ +#define RF6052_REG_GAIN_P1 0x35 +#define RF6052_REG_T_METER_8723B 0x42 +#define RF6052_REG_UNKNOWN_43 0x43 +#define RF6052_REG_UNKNOWN_55 0x55 +#define RF6052_REG_PAD_TXG 0x56 +#define RF6052_REG_TXMOD 0x58 +#define RF6052_REG_RXG_MIX_SWBW 0x87 +#define RF6052_REG_S0S1 0xb0 +#define RF6052_REG_GAIN_CCA 0xdf +#define RF6052_REG_UNKNOWN_ED 0xed +#define RF6052_REG_WE_LUT 0xef +#define RF6052_REG_GAIN_CTRL 0xf5 diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188e.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188e.c deleted file mode 100644 index 43735ca70b7c..000000000000 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188e.c +++ /dev/null @@ -1,1897 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * RTL8XXXU mac80211 USB driver - 8188e specific subdriver - * - * Copyright (c) 2014 - 2016 Jes Sorensen - * - * Portions, notably calibration code: - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This driver was written as a replacement for the vendor provided - * rtl8723au driver. As the Realtek 8xxx chips are very similar in - * their programming interface, I have started adding support for - * additional 8xxx chips like the 8192cu, 8188cus, etc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "rtl8xxxu.h" -#include "rtl8xxxu_regs.h" - -static const struct rtl8xxxu_reg8val rtl8188e_mac_init_table[] = { - {0x026, 0x41}, {0x027, 0x35}, {0x040, 0x00}, {0x421, 0x0f}, - {0x428, 0x0a}, {0x429, 0x10}, {0x430, 0x00}, {0x431, 0x01}, - {0x432, 0x02}, {0x433, 0x04}, {0x434, 0x05}, {0x435, 0x06}, - {0x436, 0x07}, {0x437, 0x08}, {0x438, 0x00}, {0x439, 0x00}, - {0x43a, 0x01}, {0x43b, 0x02}, {0x43c, 0x04}, {0x43d, 0x05}, - {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01}, - {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f}, - {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72}, - {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x480, 0x08}, - {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff}, {0x4cd, 0xff}, - {0x4ce, 0x01}, {0x4d3, 0x01}, {0x500, 0x26}, {0x501, 0xa2}, - {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3}, - {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4}, - {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4}, - {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a}, - {0x516, 0x0a}, {0x525, 0x4f}, {0x550, 0x10}, {0x551, 0x10}, - {0x559, 0x02}, {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, - {0x609, 0x2a}, {0x620, 0xff}, {0x621, 0xff}, {0x622, 0xff}, - {0x623, 0xff}, {0x624, 0xff}, {0x625, 0xff}, {0x626, 0xff}, - {0x627, 0xff}, {0x63c, 0x08}, {0x63d, 0x08}, {0x63e, 0x0c}, - {0x63f, 0x0c}, {0x640, 0x40}, {0x652, 0x20}, {0x66e, 0x05}, - {0x700, 0x21}, {0x701, 0x43}, {0x702, 0x65}, {0x703, 0x87}, - {0x708, 0x21}, {0x709, 0x43}, {0x70a, 0x65}, {0x70b, 0x87}, - {0xffff, 0xff}, -}; - -static const struct rtl8xxxu_reg32val rtl8188eu_phy_init_table[] = { - {0x800, 0x80040000}, {0x804, 0x00000003}, - {0x808, 0x0000fc00}, {0x80c, 0x0000000a}, - {0x810, 0x10001331}, {0x814, 0x020c3d10}, - {0x818, 0x02200385}, {0x81c, 0x00000000}, - {0x820, 0x01000100}, {0x824, 0x00390204}, - {0x828, 0x00000000}, {0x82c, 0x00000000}, - {0x830, 0x00000000}, {0x834, 0x00000000}, - {0x838, 0x00000000}, {0x83c, 0x00000000}, - {0x840, 0x00010000}, {0x844, 0x00000000}, - {0x848, 0x00000000}, {0x84c, 0x00000000}, - {0x850, 0x00000000}, {0x854, 0x00000000}, - {0x858, 0x569a11a9}, {0x85c, 0x01000014}, - {0x860, 0x66f60110}, {0x864, 0x061f0649}, - {0x868, 0x00000000}, {0x86c, 0x27272700}, - {0x870, 0x07000760}, {0x874, 0x25004000}, - {0x878, 0x00000808}, {0x87c, 0x00000000}, - {0x880, 0xb0000c1c}, {0x884, 0x00000001}, - {0x888, 0x00000000}, {0x88c, 0xccc000c0}, - {0x890, 0x00000800}, {0x894, 0xfffffffe}, - {0x898, 0x40302010}, {0x89c, 0x00706050}, - {0x900, 0x00000000}, {0x904, 0x00000023}, - {0x908, 0x00000000}, {0x90c, 0x81121111}, - {0x910, 0x00000002}, {0x914, 0x00000201}, - {0xa00, 0x00d047c8}, {0xa04, 0x80ff800c}, - {0xa08, 0x8c838300}, {0xa0c, 0x2e7f120f}, - {0xa10, 0x9500bb7e}, {0xa14, 0x1114d028}, - {0xa18, 0x00881117}, {0xa1c, 0x89140f00}, - {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317}, - {0xa28, 0x00000204}, {0xa2c, 0x00d30000}, - {0xa70, 0x101fbf00}, {0xa74, 0x00000007}, - {0xa78, 0x00000900}, {0xa7c, 0x225b0606}, - {0xa80, 0x218075b1}, {0xb2c, 0x80000000}, - {0xc00, 0x48071d40}, {0xc04, 0x03a05611}, - {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c}, - {0xc10, 0x08800000}, {0xc14, 0x40000100}, - {0xc18, 0x08800000}, {0xc1c, 0x40000100}, - {0xc20, 0x00000000}, {0xc24, 0x00000000}, - {0xc28, 0x00000000}, {0xc2c, 0x00000000}, - {0xc30, 0x69e9ac47}, {0xc34, 0x469652af}, - {0xc38, 0x49795994}, {0xc3c, 0x0a97971c}, - {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7}, - {0xc48, 0xec020107}, {0xc4c, 0x007f037f}, - {0xc50, 0x69553420}, {0xc54, 0x43bc0094}, - {0xc58, 0x00013169}, {0xc5c, 0x00250492}, - {0xc60, 0x00000000}, {0xc64, 0x7112848b}, - {0xc68, 0x47c00bff}, {0xc6c, 0x00000036}, - {0xc70, 0x2c7f000d}, {0xc74, 0x020610db}, - {0xc78, 0x0000001f}, {0xc7c, 0x00b91612}, - {0xc80, 0x390000e4}, {0xc84, 0x21f60000}, - {0xc88, 0x40000100}, {0xc8c, 0x20200000}, - {0xc90, 0x00091521}, {0xc94, 0x00000000}, - {0xc98, 0x00121820}, {0xc9c, 0x00007f7f}, - {0xca0, 0x00000000}, {0xca4, 0x000300a0}, - {0xca8, 0x00000000}, {0xcac, 0x00000000}, - {0xcb0, 0x00000000}, {0xcb4, 0x00000000}, - {0xcb8, 0x00000000}, {0xcbc, 0x28000000}, - {0xcc0, 0x00000000}, {0xcc4, 0x00000000}, - {0xcc8, 0x00000000}, {0xccc, 0x00000000}, - {0xcd0, 0x00000000}, {0xcd4, 0x00000000}, - {0xcd8, 0x64b22427}, {0xcdc, 0x00766932}, - {0xce0, 0x00222222}, {0xce4, 0x00000000}, - {0xce8, 0x37644302}, {0xcec, 0x2f97d40c}, - {0xd00, 0x00000740}, {0xd04, 0x00020401}, - {0xd08, 0x0000907f}, {0xd0c, 0x20010201}, - {0xd10, 0xa0633333}, {0xd14, 0x3333bc43}, - {0xd18, 0x7a8f5b6f}, {0xd2c, 0xcc979975}, - {0xd30, 0x00000000}, {0xd34, 0x80608000}, - {0xd38, 0x00000000}, {0xd3c, 0x00127353}, - {0xd40, 0x00000000}, {0xd44, 0x00000000}, - {0xd48, 0x00000000}, {0xd4c, 0x00000000}, - {0xd50, 0x6437140a}, {0xd54, 0x00000000}, - {0xd58, 0x00000282}, {0xd5c, 0x30032064}, - {0xd60, 0x4653de68}, {0xd64, 0x04518a3c}, - {0xd68, 0x00002101}, {0xd6c, 0x2a201c16}, - {0xd70, 0x1812362e}, {0xd74, 0x322c2220}, - {0xd78, 0x000e3c24}, {0xe00, 0x2d2d2d2d}, - {0xe04, 0x2d2d2d2d}, {0xe08, 0x0390272d}, - {0xe10, 0x2d2d2d2d}, {0xe14, 0x2d2d2d2d}, - {0xe18, 0x2d2d2d2d}, {0xe1c, 0x2d2d2d2d}, - {0xe28, 0x00000000}, {0xe30, 0x1000dc1f}, - {0xe34, 0x10008c1f}, {0xe38, 0x02140102}, - {0xe3c, 0x681604c2}, {0xe40, 0x01007c00}, - {0xe44, 0x01004800}, {0xe48, 0xfb000000}, - {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f}, - {0xe54, 0x10008c1f}, {0xe58, 0x02140102}, - {0xe5c, 0x28160d05}, {0xe60, 0x00000048}, - {0xe68, 0x001b25a4}, {0xe6c, 0x00c00014}, - {0xe70, 0x00c00014}, {0xe74, 0x01000014}, - {0xe78, 0x01000014}, {0xe7c, 0x01000014}, - {0xe80, 0x01000014}, {0xe84, 0x00c00014}, - {0xe88, 0x01000014}, {0xe8c, 0x00c00014}, - {0xed0, 0x00c00014}, {0xed4, 0x00c00014}, - {0xed8, 0x00c00014}, {0xedc, 0x00000014}, - {0xee0, 0x00000014}, {0xee8, 0x21555448}, - {0xeec, 0x01c00014}, {0xf14, 0x00000003}, - {0xf4c, 0x00000000}, {0xf00, 0x00000300}, - {0xffff, 0xffffffff}, -}; - -static const struct rtl8xxxu_reg32val rtl8188e_agc_table[] = { - {0xc78, 0xfb000001}, {0xc78, 0xfb010001}, - {0xc78, 0xfb020001}, {0xc78, 0xfb030001}, - {0xc78, 0xfb040001}, {0xc78, 0xfb050001}, - {0xc78, 0xfa060001}, {0xc78, 0xf9070001}, - {0xc78, 0xf8080001}, {0xc78, 0xf7090001}, - {0xc78, 0xf60a0001}, {0xc78, 0xf50b0001}, - {0xc78, 0xf40c0001}, {0xc78, 0xf30d0001}, - {0xc78, 0xf20e0001}, {0xc78, 0xf10f0001}, - {0xc78, 0xf0100001}, {0xc78, 0xef110001}, - {0xc78, 0xee120001}, {0xc78, 0xed130001}, - {0xc78, 0xec140001}, {0xc78, 0xeb150001}, - {0xc78, 0xea160001}, {0xc78, 0xe9170001}, - {0xc78, 0xe8180001}, {0xc78, 0xe7190001}, - {0xc78, 0xe61a0001}, {0xc78, 0xe51b0001}, - {0xc78, 0xe41c0001}, {0xc78, 0xe31d0001}, - {0xc78, 0xe21e0001}, {0xc78, 0xe11f0001}, - {0xc78, 0x8a200001}, {0xc78, 0x89210001}, - {0xc78, 0x88220001}, {0xc78, 0x87230001}, - {0xc78, 0x86240001}, {0xc78, 0x85250001}, - {0xc78, 0x84260001}, {0xc78, 0x83270001}, - {0xc78, 0x82280001}, {0xc78, 0x6b290001}, - {0xc78, 0x6a2a0001}, {0xc78, 0x692b0001}, - {0xc78, 0x682c0001}, {0xc78, 0x672d0001}, - {0xc78, 0x662e0001}, {0xc78, 0x652f0001}, - {0xc78, 0x64300001}, {0xc78, 0x63310001}, - {0xc78, 0x62320001}, {0xc78, 0x61330001}, - {0xc78, 0x46340001}, {0xc78, 0x45350001}, - {0xc78, 0x44360001}, {0xc78, 0x43370001}, - {0xc78, 0x42380001}, {0xc78, 0x41390001}, - {0xc78, 0x403a0001}, {0xc78, 0x403b0001}, - {0xc78, 0x403c0001}, {0xc78, 0x403d0001}, - {0xc78, 0x403e0001}, {0xc78, 0x403f0001}, - {0xc78, 0xfb400001}, {0xc78, 0xfb410001}, - {0xc78, 0xfb420001}, {0xc78, 0xfb430001}, - {0xc78, 0xfb440001}, {0xc78, 0xfb450001}, - {0xc78, 0xfb460001}, {0xc78, 0xfb470001}, - {0xc78, 0xfb480001}, {0xc78, 0xfa490001}, - {0xc78, 0xf94a0001}, {0xc78, 0xf84b0001}, - {0xc78, 0xf74c0001}, {0xc78, 0xf64d0001}, - {0xc78, 0xf54e0001}, {0xc78, 0xf44f0001}, - {0xc78, 0xf3500001}, {0xc78, 0xf2510001}, - {0xc78, 0xf1520001}, {0xc78, 0xf0530001}, - {0xc78, 0xef540001}, {0xc78, 0xee550001}, - {0xc78, 0xed560001}, {0xc78, 0xec570001}, - {0xc78, 0xeb580001}, {0xc78, 0xea590001}, - {0xc78, 0xe95a0001}, {0xc78, 0xe85b0001}, - {0xc78, 0xe75c0001}, {0xc78, 0xe65d0001}, - {0xc78, 0xe55e0001}, {0xc78, 0xe45f0001}, - {0xc78, 0xe3600001}, {0xc78, 0xe2610001}, - {0xc78, 0xc3620001}, {0xc78, 0xc2630001}, - {0xc78, 0xc1640001}, {0xc78, 0x8b650001}, - {0xc78, 0x8a660001}, {0xc78, 0x89670001}, - {0xc78, 0x88680001}, {0xc78, 0x87690001}, - {0xc78, 0x866a0001}, {0xc78, 0x856b0001}, - {0xc78, 0x846c0001}, {0xc78, 0x676d0001}, - {0xc78, 0x666e0001}, {0xc78, 0x656f0001}, - {0xc78, 0x64700001}, {0xc78, 0x63710001}, - {0xc78, 0x62720001}, {0xc78, 0x61730001}, - {0xc78, 0x60740001}, {0xc78, 0x46750001}, - {0xc78, 0x45760001}, {0xc78, 0x44770001}, - {0xc78, 0x43780001}, {0xc78, 0x42790001}, - {0xc78, 0x417a0001}, {0xc78, 0x407b0001}, - {0xc78, 0x407c0001}, {0xc78, 0x407d0001}, - {0xc78, 0x407e0001}, {0xc78, 0x407f0001}, - {0xc50, 0x69553422}, {0xc50, 0x69553420}, - {0xffff, 0xffffffff} -}; - -static const struct rtl8xxxu_rfregval rtl8188eu_radioa_init_table[] = { - {0x00, 0x00030000}, {0x08, 0x00084000}, - {0x18, 0x00000407}, {0x19, 0x00000012}, - {0x1e, 0x00080009}, {0x1f, 0x00000880}, - {0x2f, 0x0001a060}, {0x3f, 0x00000000}, - {0x42, 0x000060c0}, {0x57, 0x000d0000}, - {0x58, 0x000be180}, {0x67, 0x00001552}, - {0x83, 0x00000000}, {0xb0, 0x000ff8fc}, - {0xb1, 0x00054400}, {0xb2, 0x000ccc19}, - {0xb4, 0x00043003}, {0xb6, 0x0004953e}, - {0xb7, 0x0001c718}, {0xb8, 0x000060ff}, - {0xb9, 0x00080001}, {0xba, 0x00040000}, - {0xbb, 0x00000400}, {0xbf, 0x000c0000}, - {0xc2, 0x00002400}, {0xc3, 0x00000009}, - {0xc4, 0x00040c91}, {0xc5, 0x00099999}, - {0xc6, 0x000000a3}, {0xc7, 0x00088820}, - {0xc8, 0x00076c06}, {0xc9, 0x00000000}, - {0xca, 0x00080000}, {0xdf, 0x00000180}, - {0xef, 0x000001a0}, {0x51, 0x0006b27d}, - {0x52, 0x0007e49d}, /* Set to 0x0007e4dd for SDIO */ - {0x53, 0x00000073}, {0x56, 0x00051ff3}, - {0x35, 0x00000086}, {0x35, 0x00000186}, - {0x35, 0x00000286}, {0x36, 0x00001c25}, - {0x36, 0x00009c25}, {0x36, 0x00011c25}, - {0x36, 0x00019c25}, {0xb6, 0x00048538}, - {0x18, 0x00000c07}, {0x5a, 0x0004bd00}, - {0x19, 0x000739d0}, {0x34, 0x0000adf3}, - {0x34, 0x00009df0}, {0x34, 0x00008ded}, - {0x34, 0x00007dea}, {0x34, 0x00006de7}, - {0x34, 0x000054ee}, {0x34, 0x000044eb}, - {0x34, 0x000034e8}, {0x34, 0x0000246b}, - {0x34, 0x00001468}, {0x34, 0x0000006d}, - {0x00, 0x00030159}, {0x84, 0x00068200}, - {0x86, 0x000000ce}, {0x87, 0x00048a00}, - {0x8e, 0x00065540}, {0x8f, 0x00088000}, - {0xef, 0x000020a0}, {0x3b, 0x000f02b0}, - {0x3b, 0x000ef7b0}, {0x3b, 0x000d4fb0}, - {0x3b, 0x000cf060}, {0x3b, 0x000b0090}, - {0x3b, 0x000a0080}, {0x3b, 0x00090080}, - {0x3b, 0x0008f780}, {0x3b, 0x000722b0}, - {0x3b, 0x0006f7b0}, {0x3b, 0x00054fb0}, - {0x3b, 0x0004f060}, {0x3b, 0x00030090}, - {0x3b, 0x00020080}, {0x3b, 0x00010080}, - {0x3b, 0x0000f780}, {0xef, 0x000000a0}, - {0x00, 0x00010159}, {0x18, 0x0000f407}, - {0xFE, 0x00000000}, {0xFE, 0x00000000}, - {0x1F, 0x00080003}, {0xFE, 0x00000000}, - {0xFE, 0x00000000}, {0x1E, 0x00000001}, - {0x1F, 0x00080000}, {0x00, 0x00033e60}, - {0xff, 0xffffffff} -}; - -#define PERENTRY 23 -#define RETRYSIZE 5 -#define RATESIZE 28 -#define TX_RPT2_ITEM_SIZE 8 - -static const u8 retry_penalty[PERENTRY][RETRYSIZE + 1] = { - {5, 4, 3, 2, 0, 3}, /* 92 , idx=0 */ - {6, 5, 4, 3, 0, 4}, /* 86 , idx=1 */ - {6, 5, 4, 2, 0, 4}, /* 81 , idx=2 */ - {8, 7, 6, 4, 0, 6}, /* 75 , idx=3 */ - {10, 9, 8, 6, 0, 8}, /* 71 , idx=4 */ - {10, 9, 8, 4, 0, 8}, /* 66 , idx=5 */ - {10, 9, 8, 2, 0, 8}, /* 62 , idx=6 */ - {10, 9, 8, 0, 0, 8}, /* 59 , idx=7 */ - {18, 17, 16, 8, 0, 16}, /* 53 , idx=8 */ - {26, 25, 24, 16, 0, 24}, /* 50 , idx=9 */ - {34, 33, 32, 24, 0, 32}, /* 47 , idx=0x0a */ - {34, 31, 28, 20, 0, 32}, /* 43 , idx=0x0b */ - {34, 31, 27, 18, 0, 32}, /* 40 , idx=0x0c */ - {34, 31, 26, 16, 0, 32}, /* 37 , idx=0x0d */ - {34, 30, 22, 16, 0, 32}, /* 32 , idx=0x0e */ - {34, 30, 24, 16, 0, 32}, /* 26 , idx=0x0f */ - {49, 46, 40, 16, 0, 48}, /* 20 , idx=0x10 */ - {49, 45, 32, 0, 0, 48}, /* 17 , idx=0x11 */ - {49, 45, 22, 18, 0, 48}, /* 15 , idx=0x12 */ - {49, 40, 24, 16, 0, 48}, /* 12 , idx=0x13 */ - {49, 32, 18, 12, 0, 48}, /* 9 , idx=0x14 */ - {49, 22, 18, 14, 0, 48}, /* 6 , idx=0x15 */ - {49, 16, 16, 0, 0, 48} /* 3, idx=0x16 */ -}; - -static const u8 pt_penalty[RETRYSIZE + 1] = {34, 31, 30, 24, 0, 32}; - -static const u8 retry_penalty_idx_normal[2][RATESIZE] = { - { /* RSSI>TH */ - 4, 4, 4, 5, - 4, 4, 5, 7, 7, 7, 8, 0x0a, - 4, 4, 4, 4, 6, 0x0a, 0x0b, 0x0d, - 5, 5, 7, 7, 8, 0x0b, 0x0d, 0x0f - }, - { /* RSSITH */ - 4, 4, 4, 5, - 4, 4, 5, 7, 7, 7, 8, 0x0a, - 4, 4, 4, 4, 6, 0x0a, 0x0b, 0x0d, - 5, 5, 7, 7, 8, 0x0b, 0x0d, 0x0f - }, - { /* RSSIudev->dev; - u32 sys_cfg, vendor; - int ret = 0; - - strscpy(priv->chip_name, "8188EU", sizeof(priv->chip_name)); - priv->rtl_chip = RTL8188E; - priv->rf_paths = 1; - priv->rx_paths = 1; - priv->tx_paths = 1; - priv->has_wifi = 1; - - sys_cfg = rtl8xxxu_read32(priv, REG_SYS_CFG); - priv->chip_cut = u32_get_bits(sys_cfg, SYS_CFG_CHIP_VERSION_MASK); - if (sys_cfg & SYS_CFG_TRP_VAUX_EN) { - dev_info(dev, "Unsupported test chip\n"); - return -EOPNOTSUPP; - } - - /* - * TODO: At a glance, I cut requires a different firmware, - * different initialisation tables, and no software rate - * control. The vendor driver is not configured to handle - * I cut chips by default. Are there any in the wild? - */ - if (priv->chip_cut == 8) { - dev_info(dev, "RTL8188EU cut I is not supported. Please complain about it at linux-wireless@vger.kernel.org.\n"); - return -EOPNOTSUPP; - } - - vendor = sys_cfg & SYS_CFG_VENDOR_ID; - rtl8xxxu_identify_vendor_1bit(priv, vendor); - - ret = rtl8xxxu_config_endpoints_no_sie(priv); - - return ret; -} - -static void rtl8188eu_config_channel(struct ieee80211_hw *hw) -{ - struct rtl8xxxu_priv *priv = hw->priv; - u32 val32, rsr; - u8 opmode; - int sec_ch_above, channel; - int i; - - opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE); - rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); - channel = hw->conf.chandef.chan->hw_value; - - switch (hw->conf.chandef.width) { - case NL80211_CHAN_WIDTH_20_NOHT: - case NL80211_CHAN_WIDTH_20: - opmode |= BW_OPMODE_20MHZ; - rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode); - - val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); - val32 &= ~FPGA_RF_MODE; - rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); - - val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); - val32 &= ~FPGA_RF_MODE; - rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); - break; - case NL80211_CHAN_WIDTH_40: - if (hw->conf.chandef.center_freq1 > - hw->conf.chandef.chan->center_freq) { - sec_ch_above = 1; - channel += 2; - } else { - sec_ch_above = 0; - channel -= 2; - } - - opmode &= ~BW_OPMODE_20MHZ; - rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode); - rsr &= ~RSR_RSC_BANDWIDTH_40M; - if (sec_ch_above) - rsr |= RSR_RSC_LOWER_SUB_CHANNEL; - else - rsr |= RSR_RSC_UPPER_SUB_CHANNEL; - rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr); - - val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); - val32 |= FPGA_RF_MODE; - rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); - - val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); - val32 |= FPGA_RF_MODE; - rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); - - /* - * Set Control channel to upper or lower. These settings - * are required only for 40MHz - */ - val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM); - val32 &= ~CCK0_SIDEBAND; - if (!sec_ch_above) - val32 |= CCK0_SIDEBAND; - rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32); - - val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF); - val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */ - if (sec_ch_above) - val32 |= OFDM_LSTF_PRIME_CH_LOW; - else - val32 |= OFDM_LSTF_PRIME_CH_HIGH; - rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); - - val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); - val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL); - if (sec_ch_above) - val32 |= FPGA0_PS_UPPER_CHANNEL; - else - val32 |= FPGA0_PS_LOWER_CHANNEL; - rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); - break; - - default: - break; - } - - for (i = RF_A; i < priv->rf_paths; i++) { - val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); - u32p_replace_bits(&val32, channel, MODE_AG_CHANNEL_MASK); - rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); - } - - for (i = RF_A; i < priv->rf_paths; i++) { - val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); - val32 &= ~MODE_AG_BW_MASK; - if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) - val32 |= MODE_AG_BW_40MHZ_8723B; - else - val32 |= MODE_AG_BW_20MHZ_8723B; - rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); - } -} - -static void rtl8188eu_init_aggregation(struct rtl8xxxu_priv *priv) -{ - u8 agg_ctrl, usb_spec; - - usb_spec = rtl8xxxu_read8(priv, REG_USB_SPECIAL_OPTION); - usb_spec &= ~USB_SPEC_USB_AGG_ENABLE; - rtl8xxxu_write8(priv, REG_USB_SPECIAL_OPTION, usb_spec); - - agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL); - agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN; - rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl); -} - -static int rtl8188eu_parse_efuse(struct rtl8xxxu_priv *priv) -{ - struct rtl8188eu_efuse *efuse = &priv->efuse_wifi.efuse8188eu; - - if (efuse->rtl_id != cpu_to_le16(0x8129)) - return -EINVAL; - - ether_addr_copy(priv->mac_addr, efuse->mac_addr); - - memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base, - sizeof(efuse->tx_power_index_A.cck_base)); - - memcpy(priv->ht40_1s_tx_power_index_A, - efuse->tx_power_index_A.ht40_base, - sizeof(efuse->tx_power_index_A.ht40_base)); - - priv->default_crystal_cap = efuse->xtal_k & 0x3f; - - return 0; -} - -static void rtl8188eu_reset_8051(struct rtl8xxxu_priv *priv) -{ - u16 sys_func; - - sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC); - sys_func &= ~SYS_FUNC_CPU_ENABLE; - rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func); - - sys_func |= SYS_FUNC_CPU_ENABLE; - rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func); -} - -static int rtl8188eu_load_firmware(struct rtl8xxxu_priv *priv) -{ - const char *fw_name; - int ret; - - fw_name = "rtlwifi/rtl8188eufw.bin"; - - ret = rtl8xxxu_load_firmware(priv, fw_name); - - return ret; -} - -static void rtl8188eu_init_phy_bb(struct rtl8xxxu_priv *priv) -{ - u8 val8; - u16 val16; - - val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); - val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB | SYS_FUNC_DIO_RF; - rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); - - /* - * Per vendor driver, run power sequence before init of RF - */ - val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB; - rtl8xxxu_write8(priv, REG_RF_CTRL, val8); - - val8 = SYS_FUNC_USBA | SYS_FUNC_USBD | - SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB; - rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); - - rtl8xxxu_init_phy_regs(priv, rtl8188eu_phy_init_table); - rtl8xxxu_init_phy_regs(priv, rtl8188e_agc_table); -} - -static int rtl8188eu_init_phy_rf(struct rtl8xxxu_priv *priv) -{ - return rtl8xxxu_init_phy_rf(priv, rtl8188eu_radioa_init_table, RF_A); -} - -static int rtl8188eu_iqk_path_a(struct rtl8xxxu_priv *priv) -{ - u32 reg_eac, reg_e94, reg_e9c; - int result = 0; - - /* Path A IQK setting */ - rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1c); - rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x30008c1c); - - rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x8214032a); - rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160000); - - /* LO calibration setting */ - rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911); - - /* One shot, path A LOK & IQK */ - rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); - rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); - - mdelay(10); - - /* Check failed */ - reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); - reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); - reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); - - if (!(reg_eac & BIT(28)) && - ((reg_e94 & 0x03ff0000) != 0x01420000) && - ((reg_e9c & 0x03ff0000) != 0x00420000)) - result |= 0x01; - - return result; -} - -static int rtl8188eu_rx_iqk_path_a(struct rtl8xxxu_priv *priv) -{ - u32 reg_ea4, reg_eac, reg_e94, reg_e9c, val32; - int result = 0; - - /* Leave IQK mode */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); - u32p_replace_bits(&val32, 0, 0xffffff00); - rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); - - /* Enable path A PA in TX IQK mode */ - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf117b); - - /* Enter IQK mode */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); - u32p_replace_bits(&val32, 0x808000, 0xffffff00); - rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); - - /* TX IQK setting */ - rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); - rtl8xxxu_write32(priv, REG_RX_IQK, 0x81004800); - - /* path-A IQK setting */ - rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1c); - rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x30008c1c); - - rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160804); - rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160000); - - /* LO calibration setting */ - rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911); - - /* One shot, path A LOK & IQK */ - rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); - rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); - - mdelay(10); - - /* Check failed */ - reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); - reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); - reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); - - if (!(reg_eac & BIT(28)) && - ((reg_e94 & 0x03ff0000) != 0x01420000) && - ((reg_e9c & 0x03ff0000) != 0x00420000)) - result |= 0x01; - else - goto out; - - val32 = 0x80007c00 | - (reg_e94 & 0x03ff0000) | ((reg_e9c >> 16) & 0x03ff); - rtl8xxxu_write32(priv, REG_TX_IQK, val32); - - /* Modify RX IQK mode table */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); - u32p_replace_bits(&val32, 0, 0xffffff00); - rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); - - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7ffa); - - /* Enter IQK mode */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); - u32p_replace_bits(&val32, 0x808000, 0xffffff00); - rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); - - /* IQK setting */ - rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); - - /* Path A IQK setting */ - rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x30008c1c); - rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1c); - - rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160c05); - rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160c05); - - /* LO calibration setting */ - rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911); - - /* One shot, path A LOK & IQK */ - rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); - rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); - - mdelay(10); - - reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); - reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); - - if (!(reg_eac & BIT(27)) && - ((reg_ea4 & 0x03ff0000) != 0x01320000) && - ((reg_eac & 0x03ff0000) != 0x00360000)) - result |= 0x02; - else - dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n", - __func__); - -out: - return result; -} - -static void rtl8188eu_phy_iqcalibrate(struct rtl8xxxu_priv *priv, - int result[][8], int t) -{ - struct device *dev = &priv->udev->dev; - u32 i, val32; - int path_a_ok; - int retry = 2; - static const u32 adda_regs[RTL8XXXU_ADDA_REGS] = { - REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH, - REG_RX_WAIT_CCA, REG_TX_CCK_RFON, - REG_TX_CCK_BBON, REG_TX_OFDM_RFON, - REG_TX_OFDM_BBON, REG_TX_TO_RX, - REG_TX_TO_TX, REG_RX_CCK, - REG_RX_OFDM, REG_RX_WAIT_RIFS, - REG_RX_TO_RX, REG_STANDBY, - REG_SLEEP, REG_PMPD_ANAEN - }; - static const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = { - REG_TXPAUSE, REG_BEACON_CTRL, - REG_BEACON_CTRL_1, REG_GPIO_MUXCFG - }; - static const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = { - REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR, - REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, - REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE, - REG_FPGA0_XB_RF_INT_OE, REG_CCK0_AFE_SETTING - }; - - /* - * Note: IQ calibration must be performed after loading - * PHY_REG.txt , and radio_a, radio_b.txt - */ - - if (t == 0) { - /* Save ADDA parameters, turn Path A ADDA on */ - rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup, - RTL8XXXU_ADDA_REGS); - rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup); - rtl8xxxu_save_regs(priv, iqk_bb_regs, - priv->bb_backup, RTL8XXXU_BB_REGS); - } - - rtl8xxxu_path_adda_on(priv, adda_regs, true); - - if (t == 0) { - val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1); - priv->pi_enabled = u32_get_bits(val32, FPGA0_HSSI_PARM1_PI); - } - - if (!priv->pi_enabled) { - /* Switch BB to PI mode to do IQ Calibration. */ - rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100); - rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100); - } - - /* MAC settings */ - rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup); - - val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING); - u32p_replace_bits(&val32, 0xf, 0x0f000000); - rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32); - - rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600); - rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4); - rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000); - - if (!priv->no_pape) { - val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL); - val32 |= (FPGA0_RF_PAPE | - (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT)); - rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32); - } - - val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE); - val32 &= ~BIT(10); - rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32); - val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE); - val32 &= ~BIT(10); - rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32); - - /* Page B init */ - rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x0f600000); - - /* IQ calibration setting */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); - u32p_replace_bits(&val32, 0x808000, 0xffffff00); - rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); - rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); - rtl8xxxu_write32(priv, REG_RX_IQK, 0x81004800); - - for (i = 0; i < retry; i++) { - path_a_ok = rtl8188eu_iqk_path_a(priv); - if (path_a_ok == 0x01) { - val32 = rtl8xxxu_read32(priv, - REG_TX_POWER_BEFORE_IQK_A); - result[t][0] = (val32 >> 16) & 0x3ff; - val32 = rtl8xxxu_read32(priv, - REG_TX_POWER_AFTER_IQK_A); - result[t][1] = (val32 >> 16) & 0x3ff; - break; - } - } - - if (!path_a_ok) - dev_dbg(dev, "%s: Path A TX IQK failed!\n", __func__); - - for (i = 0; i < retry; i++) { - path_a_ok = rtl8188eu_rx_iqk_path_a(priv); - if (path_a_ok == 0x03) { - val32 = rtl8xxxu_read32(priv, - REG_RX_POWER_BEFORE_IQK_A_2); - result[t][2] = (val32 >> 16) & 0x3ff; - val32 = rtl8xxxu_read32(priv, - REG_RX_POWER_AFTER_IQK_A_2); - result[t][3] = (val32 >> 16) & 0x3ff; - - break; - } - } - - if (!path_a_ok) - dev_dbg(dev, "%s: Path A RX IQK failed!\n", __func__); - - /* Back to BB mode, load original value */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); - u32p_replace_bits(&val32, 0, 0xffffff00); - rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); - - if (t == 0) - return; - - if (!priv->pi_enabled) { - /* Switch back BB to SI mode after finishing IQ Calibration */ - rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000000); - rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000000); - } - - /* Reload ADDA power saving parameters */ - rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup, - RTL8XXXU_ADDA_REGS); - - /* Reload MAC parameters */ - rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup); - - /* Reload BB parameters */ - rtl8xxxu_restore_regs(priv, iqk_bb_regs, - priv->bb_backup, RTL8XXXU_BB_REGS); - - /* Restore RX initial gain */ - rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3); - - /* Load 0xe30 IQC default value */ - rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00); - rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00); -} - -static void rtl8188eu_phy_iq_calibrate(struct rtl8xxxu_priv *priv) -{ - struct device *dev = &priv->udev->dev; - int result[4][8]; /* last is final result */ - int i, candidate; - bool path_a_ok; - u32 reg_e94, reg_e9c, reg_ea4, reg_eac; - u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc; - bool simu; - - memset(result, 0, sizeof(result)); - result[3][0] = 0x100; - result[3][2] = 0x100; - result[3][4] = 0x100; - result[3][6] = 0x100; - - candidate = -1; - - path_a_ok = false; - - for (i = 0; i < 3; i++) { - rtl8188eu_phy_iqcalibrate(priv, result, i); - - if (i == 1) { - simu = rtl8xxxu_simularity_compare(priv, - result, 0, 1); - if (simu) { - candidate = 0; - break; - } - } - - if (i == 2) { - simu = rtl8xxxu_simularity_compare(priv, - result, 0, 2); - if (simu) { - candidate = 0; - break; - } - - simu = rtl8xxxu_simularity_compare(priv, - result, 1, 2); - if (simu) - candidate = 1; - else - candidate = 3; - } - } - - if (candidate >= 0) { - reg_e94 = result[candidate][0]; - priv->rege94 = reg_e94; - reg_e9c = result[candidate][1]; - priv->rege9c = reg_e9c; - reg_ea4 = result[candidate][2]; - reg_eac = result[candidate][3]; - reg_eb4 = result[candidate][4]; - priv->regeb4 = reg_eb4; - reg_ebc = result[candidate][5]; - priv->regebc = reg_ebc; - reg_ec4 = result[candidate][6]; - reg_ecc = result[candidate][7]; - dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate); - dev_dbg(dev, - "%s: e94=%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x ecc=%x\n", - __func__, reg_e94, reg_e9c, reg_ea4, reg_eac, - reg_eb4, reg_ebc, reg_ec4, reg_ecc); - path_a_ok = true; - } else { - reg_e94 = 0x100; - reg_eb4 = 0x100; - priv->rege94 = 0x100; - priv->regeb4 = 0x100; - reg_e9c = 0x0; - reg_ebc = 0x0; - priv->rege9c = 0x0; - priv->regebc = 0x0; - } - - if (reg_e94 && candidate >= 0) - rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result, - candidate, (reg_ea4 == 0)); - - rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg, - priv->bb_recovery_backup, RTL8XXXU_BB_REGS); -} - -static void rtl8188e_disabled_to_emu(struct rtl8xxxu_priv *priv) -{ - u16 val16; - - val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO); - val16 &= ~(APS_FSMCO_HW_SUSPEND | APS_FSMCO_PCIE); - rtl8xxxu_write16(priv, REG_APS_FSMCO, val16); -} - -static int rtl8188e_emu_to_active(struct rtl8xxxu_priv *priv) -{ - u8 val8; - u32 val32; - u16 val16; - int count, ret = 0; - - /* wait till 0x04[17] = 1 power ready*/ - for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { - val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); - if (val32 & BIT(17)) - break; - - udelay(10); - } - - if (!count) { - ret = -EBUSY; - goto exit; - } - - /* reset baseband */ - val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); - val8 &= ~(SYS_FUNC_BBRSTB | SYS_FUNC_BB_GLB_RSTN); - rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); - - /*0x24[23] = 2b'01 schmit trigger */ - val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL); - val32 |= BIT(23); - rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32); - - /* 0x04[15] = 0 disable HWPDN (control by DRV)*/ - val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO); - val16 &= ~APS_FSMCO_HW_POWERDOWN; - rtl8xxxu_write16(priv, REG_APS_FSMCO, val16); - - /*0x04[12:11] = 2b'00 disable WL suspend*/ - val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO); - val16 &= ~(APS_FSMCO_HW_SUSPEND | APS_FSMCO_PCIE); - rtl8xxxu_write16(priv, REG_APS_FSMCO, val16); - - /* set, then poll until 0 */ - val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); - val32 |= APS_FSMCO_MAC_ENABLE; - rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); - - for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { - val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); - if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) { - ret = 0; - break; - } - udelay(10); - } - - if (!count) { - ret = -EBUSY; - goto exit; - } - - /* LDO normal mode*/ - val8 = rtl8xxxu_read8(priv, REG_LPLDO_CTRL); - val8 &= ~BIT(4); - rtl8xxxu_write8(priv, REG_LPLDO_CTRL, val8); - -exit: - return ret; -} - -static int rtl8188eu_active_to_emu(struct rtl8xxxu_priv *priv) -{ - u8 val8; - - /* Turn off RF */ - val8 = rtl8xxxu_read8(priv, REG_RF_CTRL); - val8 &= ~RF_ENABLE; - rtl8xxxu_write8(priv, REG_RF_CTRL, val8); - - /* LDO Sleep mode */ - val8 = rtl8xxxu_read8(priv, REG_LPLDO_CTRL); - val8 |= BIT(4); - rtl8xxxu_write8(priv, REG_LPLDO_CTRL, val8); - - return 0; -} - -static int rtl8188eu_emu_to_disabled(struct rtl8xxxu_priv *priv) -{ - u32 val32; - u16 val16; - u8 val8; - - val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL); - val32 |= BIT(23); - rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32); - - val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO); - val16 &= ~APS_FSMCO_PCIE; - val16 |= APS_FSMCO_HW_SUSPEND; - rtl8xxxu_write16(priv, REG_APS_FSMCO, val16); - - rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x00); - - val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG + 1); - val8 &= ~BIT(4); - rtl8xxxu_write8(priv, REG_GPIO_MUXCFG + 1, val8); - - /* Set USB suspend enable local register 0xfe10[4]=1 */ - val8 = rtl8xxxu_read8(priv, 0xfe10); - val8 |= BIT(4); - rtl8xxxu_write8(priv, 0xfe10, val8); - - return 0; -} - -static int rtl8188eu_active_to_lps(struct rtl8xxxu_priv *priv) -{ - struct device *dev = &priv->udev->dev; - u8 val8; - u16 val16; - u32 val32; - int retry, retval; - - rtl8xxxu_write8(priv, REG_TXPAUSE, 0x7f); - - retry = 100; - retval = -EBUSY; - /* Poll 32 bit wide REG_SCH_TX_CMD for 0 to ensure no TX is pending. */ - do { - val32 = rtl8xxxu_read32(priv, REG_SCH_TX_CMD); - if (!val32) { - retval = 0; - break; - } - } while (retry--); - - if (!retry) { - dev_warn(dev, "Failed to flush TX queue\n"); - retval = -EBUSY; - goto out; - } - - /* Disable CCK and OFDM, clock gated */ - val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); - val8 &= ~SYS_FUNC_BBRSTB; - rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); - - udelay(2); - - /* Reset MAC TRX */ - val16 = rtl8xxxu_read16(priv, REG_CR); - val16 |= 0xff; - val16 &= ~(CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE | CR_SECURITY_ENABLE); - rtl8xxxu_write16(priv, REG_CR, val16); - - val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST); - val8 |= DUAL_TSF_TX_OK; - rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8); - -out: - return retval; -} - -static int rtl8188eu_power_on(struct rtl8xxxu_priv *priv) -{ - u16 val16; - int ret; - - rtl8188e_disabled_to_emu(priv); - - ret = rtl8188e_emu_to_active(priv); - if (ret) - goto exit; - - /* - * Enable MAC DMA/WMAC/SCHEDULE/SEC block - * Set CR bit10 to enable 32k calibration. - * We do not set CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE here - * due to a hardware bug in the 88E, requiring those to be - * set after REG_TRXFF_BNDY is set. If not the RXFF bundary - * will get set to a larger buffer size than the real buffer - * size. - */ - val16 = (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE | - CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | - CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE | - CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE); - rtl8xxxu_write16(priv, REG_CR, val16); - -exit: - return ret; -} - -static void rtl8188eu_power_off(struct rtl8xxxu_priv *priv) -{ - u8 val8; - u16 val16; - - rtl8xxxu_flush_fifo(priv); - - val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL); - val8 &= ~TX_REPORT_CTRL_TIMER_ENABLE; - rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8); - - /* Turn off RF */ - rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00); - - rtl8188eu_active_to_lps(priv); - - /* Reset Firmware if running in RAM */ - if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL) - rtl8xxxu_firmware_self_reset(priv); - - /* Reset MCU */ - val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); - val16 &= ~SYS_FUNC_CPU_ENABLE; - rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); - - /* Reset MCU ready status */ - rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00); - - /* 32K_CTRL looks to be very 8188e specific */ - val8 = rtl8xxxu_read8(priv, REG_32K_CTRL); - val8 &= ~BIT(0); - rtl8xxxu_write8(priv, REG_32K_CTRL, val8); - - rtl8188eu_active_to_emu(priv); - rtl8188eu_emu_to_disabled(priv); - - /* Reset MCU IO Wrapper */ - val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); - val8 &= ~BIT(3); - rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); - - val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); - val8 |= BIT(3); - rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); - - /* Vendor driver refers to GPIO_IN */ - val8 = rtl8xxxu_read8(priv, REG_GPIO_PIN_CTRL); - /* Vendor driver refers to GPIO_OUT */ - rtl8xxxu_write8(priv, REG_GPIO_PIN_CTRL + 1, val8); - rtl8xxxu_write8(priv, REG_GPIO_PIN_CTRL + 2, 0xff); - - val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL); - rtl8xxxu_write8(priv, REG_GPIO_IO_SEL, val8 << 4); - val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL + 1); - rtl8xxxu_write8(priv, REG_GPIO_IO_SEL + 1, val8 | 0x0f); - - /* - * Set LNA, TRSW, EX_PA Pin to output mode - * Referred to as REG_BB_PAD_CTRL in 8188eu vendor driver - */ - rtl8xxxu_write32(priv, REG_PAD_CTRL1, 0x00080808); - - rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x00); - - rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, 0x00000000); -} - -static void rtl8188e_enable_rf(struct rtl8xxxu_priv *priv) -{ - u32 val32; - - rtl8xxxu_write8(priv, REG_RF_CTRL, RF_ENABLE | RF_RSTB | RF_SDMRSTB); - - val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); - val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK); - val32 |= OFDM_RF_PATH_RX_A | OFDM_RF_PATH_TX_A; - rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); - - rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); -} - -static void rtl8188e_disable_rf(struct rtl8xxxu_priv *priv) -{ - u32 val32; - - val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); - val32 &= ~OFDM_RF_PATH_TX_MASK; - rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); - - /* Power down RF module */ - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0); - - rtl8188eu_active_to_emu(priv); -} - -static void rtl8188e_usb_quirks(struct rtl8xxxu_priv *priv) -{ - u16 val16; - - /* - * Technically this is not a USB quirk, but a chip quirk. - * This has to be done after REG_TRXFF_BNDY is set, see - * rtl8188eu_power_on() for details. - */ - val16 = rtl8xxxu_read16(priv, REG_CR); - val16 |= (CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE); - rtl8xxxu_write16(priv, REG_CR, val16); - - rtl8xxxu_gen2_usb_quirks(priv); - - /* Pre-TX enable WEP/TKIP security */ - rtl8xxxu_write8(priv, REG_EARLY_MODE_CONTROL_8188E + 3, 0x01); -} - -static s8 rtl8188e_cck_rssi(struct rtl8xxxu_priv *priv, struct rtl8723au_phy_stats *phy_stats) -{ - /* only use lna 0/1/2/3/7 */ - static const s8 lna_gain_table_0[8] = {17, -1, -13, -29, -32, -35, -38, -41}; - /* only use lna 3/7 */ - static const s8 lna_gain_table_1[8] = {29, 20, 12, 3, -6, -15, -24, -33}; - - u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a; - s8 rx_pwr_all = 0x00; - u8 vga_idx, lna_idx; - s8 lna_gain = 0; - - lna_idx = u8_get_bits(cck_agc_rpt, CCK_AGC_RPT_LNA_IDX_MASK); - vga_idx = u8_get_bits(cck_agc_rpt, CCK_AGC_RPT_VGA_IDX_MASK); - - if (priv->chip_cut >= 8) /* cut I */ /* SMIC */ - lna_gain = lna_gain_table_0[lna_idx]; - else /* TSMC */ - lna_gain = lna_gain_table_1[lna_idx]; - - rx_pwr_all = lna_gain - (2 * vga_idx); - - return rx_pwr_all; -} - -static int rtl8188eu_led_brightness_set(struct led_classdev *led_cdev, - enum led_brightness brightness) -{ - struct rtl8xxxu_priv *priv = container_of(led_cdev, - struct rtl8xxxu_priv, - led_cdev); - u8 ledcfg = rtl8xxxu_read8(priv, REG_LEDCFG2); - - if (brightness == LED_OFF) { - ledcfg &= ~LEDCFG2_HW_LED_CONTROL; - ledcfg |= LEDCFG2_SW_LED_CONTROL | LEDCFG2_SW_LED_DISABLE; - } else if (brightness == LED_ON) { - ledcfg &= ~(LEDCFG2_HW_LED_CONTROL | LEDCFG2_SW_LED_DISABLE); - ledcfg |= LEDCFG2_SW_LED_CONTROL; - } else if (brightness == RTL8XXXU_HW_LED_CONTROL) { - ledcfg &= ~LEDCFG2_SW_LED_DISABLE; - ledcfg |= LEDCFG2_HW_LED_CONTROL | LEDCFG2_HW_LED_ENABLE; - } - - rtl8xxxu_write8(priv, REG_LEDCFG2, ledcfg); - - return 0; -} - -static void rtl8188e_set_tx_rpt_timing(struct rtl8xxxu_ra_info *ra, u8 timing) -{ - u8 idx; - - for (idx = 0; idx < 5; idx++) - if (dynamic_tx_rpt_timing[idx] == ra->rpt_time) - break; - - if (timing == DEFAULT_TIMING) { - idx = 0; /* 200ms */ - } else if (timing == INCREASE_TIMING) { - if (idx < 5) - idx++; - } else if (timing == DECREASE_TIMING) { - if (idx > 0) - idx--; - } - - ra->rpt_time = dynamic_tx_rpt_timing[idx]; -} - -static void rtl8188e_rate_down(struct rtl8xxxu_ra_info *ra) -{ - u8 rate_id = ra->pre_rate; - u8 lowest_rate = ra->lowest_rate; - u8 highest_rate = ra->highest_rate; - s8 i; - - if (rate_id > highest_rate) { - rate_id = highest_rate; - } else if (ra->rate_sgi) { - ra->rate_sgi = 0; - } else if (rate_id > lowest_rate) { - if (rate_id > 0) { - for (i = rate_id - 1; i >= lowest_rate; i--) { - if (ra->ra_use_rate & BIT(i)) { - rate_id = i; - goto rate_down_finish; - } - } - } - } else if (rate_id <= lowest_rate) { - rate_id = lowest_rate; - } - -rate_down_finish: - if (ra->ra_waiting_counter == 1) { - ra->ra_waiting_counter++; - ra->ra_pending_counter++; - } else if (ra->ra_waiting_counter > 1) { - ra->ra_waiting_counter = 0; - ra->ra_pending_counter = 0; - } - - if (ra->ra_pending_counter >= 4) - ra->ra_pending_counter = 4; - - ra->ra_drop_after_down = 1; - - ra->decision_rate = rate_id; - - rtl8188e_set_tx_rpt_timing(ra, DECREASE_TIMING); -} - -static void rtl8188e_rate_up(struct rtl8xxxu_ra_info *ra) -{ - u8 rate_id = ra->pre_rate; - u8 highest_rate = ra->highest_rate; - u8 i; - - if (ra->ra_waiting_counter == 1) { - ra->ra_waiting_counter = 0; - ra->ra_pending_counter = 0; - } else if (ra->ra_waiting_counter > 1) { - ra->pre_rssi_sta_ra = ra->rssi_sta_ra; - goto rate_up_finish; - } - - rtl8188e_set_tx_rpt_timing(ra, DEFAULT_TIMING); - - if (rate_id < highest_rate) { - for (i = rate_id + 1; i <= highest_rate; i++) { - if (ra->ra_use_rate & BIT(i)) { - rate_id = i; - goto rate_up_finish; - } - } - } else if (rate_id == highest_rate) { - if (ra->sgi_enable && !ra->rate_sgi) - ra->rate_sgi = 1; - else if (!ra->sgi_enable) - ra->rate_sgi = 0; - } else { /* rate_id > ra->highest_rate */ - rate_id = highest_rate; - } - -rate_up_finish: - if (ra->ra_waiting_counter == (4 + pending_for_rate_up_fail[ra->ra_pending_counter])) - ra->ra_waiting_counter = 0; - else - ra->ra_waiting_counter++; - - ra->decision_rate = rate_id; -} - -static void rtl8188e_reset_ra_counter(struct rtl8xxxu_ra_info *ra) -{ - u8 rate_id = ra->decision_rate; - - ra->nsc_up = (n_threshold_high[rate_id] + n_threshold_low[rate_id]) >> 1; - ra->nsc_down = (n_threshold_high[rate_id] + n_threshold_low[rate_id]) >> 1; -} - -static void rtl8188e_rate_decision(struct rtl8xxxu_ra_info *ra) -{ - struct rtl8xxxu_priv *priv = container_of(ra, struct rtl8xxxu_priv, ra_info); - const u8 *retry_penalty_idx_0; - const u8 *retry_penalty_idx_1; - const u8 *retry_penalty_up_idx; - u8 rate_id, penalty_id1, penalty_id2; - int i; - - if (ra->total == 0) - return; - - if (ra->ra_drop_after_down) { - ra->ra_drop_after_down--; - - rtl8188e_reset_ra_counter(ra); - - return; - } - - if (priv->chip_cut == 8) { /* cut I */ - retry_penalty_idx_0 = retry_penalty_idx_cut_i[0]; - retry_penalty_idx_1 = retry_penalty_idx_cut_i[1]; - retry_penalty_up_idx = retry_penalty_up_idx_cut_i; - } else { - retry_penalty_idx_0 = retry_penalty_idx_normal[0]; - retry_penalty_idx_1 = retry_penalty_idx_normal[1]; - retry_penalty_up_idx = retry_penalty_up_idx_normal; - } - - if (ra->rssi_sta_ra < (ra->pre_rssi_sta_ra - 3) || - ra->rssi_sta_ra > (ra->pre_rssi_sta_ra + 3)) { - ra->pre_rssi_sta_ra = ra->rssi_sta_ra; - ra->ra_waiting_counter = 0; - ra->ra_pending_counter = 0; - } - - /* Start RA decision */ - if (ra->pre_rate > ra->highest_rate) - rate_id = ra->highest_rate; - else - rate_id = ra->pre_rate; - - /* rate down */ - if (ra->rssi_sta_ra > rssi_threshold[rate_id]) - penalty_id1 = retry_penalty_idx_0[rate_id]; - else - penalty_id1 = retry_penalty_idx_1[rate_id]; - - for (i = 0; i < 5; i++) - ra->nsc_down += ra->retry[i] * retry_penalty[penalty_id1][i]; - - if (ra->nsc_down > (ra->total * retry_penalty[penalty_id1][5])) - ra->nsc_down -= ra->total * retry_penalty[penalty_id1][5]; - else - ra->nsc_down = 0; - - /* rate up */ - penalty_id2 = retry_penalty_up_idx[rate_id]; - - for (i = 0; i < 5; i++) - ra->nsc_up += ra->retry[i] * retry_penalty[penalty_id2][i]; - - if (ra->nsc_up > (ra->total * retry_penalty[penalty_id2][5])) - ra->nsc_up -= ra->total * retry_penalty[penalty_id2][5]; - else - ra->nsc_up = 0; - - if (ra->nsc_down < n_threshold_low[rate_id] || - ra->drop > dropping_necessary[rate_id]) { - rtl8188e_rate_down(ra); - - rtl8xxxu_update_ra_report(&priv->ra_report, ra->decision_rate, - ra->rate_sgi, priv->ra_report.txrate.bw); - } else if (ra->nsc_up > n_threshold_high[rate_id]) { - rtl8188e_rate_up(ra); - - rtl8xxxu_update_ra_report(&priv->ra_report, ra->decision_rate, - ra->rate_sgi, priv->ra_report.txrate.bw); - } - - if (ra->decision_rate == ra->pre_rate) - ra->dynamic_tx_rpt_timing_counter++; - else - ra->dynamic_tx_rpt_timing_counter = 0; - - if (ra->dynamic_tx_rpt_timing_counter >= 4) { - /* Rate didn't change 4 times, extend RPT timing */ - rtl8188e_set_tx_rpt_timing(ra, INCREASE_TIMING); - ra->dynamic_tx_rpt_timing_counter = 0; - } - - ra->pre_rate = ra->decision_rate; - - rtl8188e_reset_ra_counter(ra); -} - -static void rtl8188e_power_training_try_state(struct rtl8xxxu_ra_info *ra) -{ - ra->pt_try_state = 0; - switch (ra->pt_mode_ss) { - case 3: - if (ra->decision_rate >= DESC_RATE_MCS13) - ra->pt_try_state = 1; - break; - case 2: - if (ra->decision_rate >= DESC_RATE_MCS5) - ra->pt_try_state = 1; - break; - case 1: - if (ra->decision_rate >= DESC_RATE_48M) - ra->pt_try_state = 1; - break; - case 0: - if (ra->decision_rate >= DESC_RATE_11M) - ra->pt_try_state = 1; - break; - default: - break; - } - - if (ra->rssi_sta_ra < 48) { - ra->pt_stage = 0; - } else if (ra->pt_try_state == 1) { - if ((ra->pt_stop_count >= 10) || - (ra->pt_pre_rssi > ra->rssi_sta_ra + 5) || - (ra->pt_pre_rssi < ra->rssi_sta_ra - 5) || - (ra->decision_rate != ra->pt_pre_rate)) { - if (ra->pt_stage == 0) - ra->pt_stage = 1; - else if (ra->pt_stage == 1) - ra->pt_stage = 3; - else - ra->pt_stage = 5; - - ra->pt_pre_rssi = ra->rssi_sta_ra; - ra->pt_stop_count = 0; - } else { - ra->ra_stage = 0; - ra->pt_stop_count++; - } - } else { - ra->pt_stage = 0; - ra->ra_stage = 0; - } - - ra->pt_pre_rate = ra->decision_rate; - - /* TODO: implement the "false alarm" statistics for this */ - /* Disable power training when noisy environment */ - /* if (p_dm_odm->is_disable_power_training) { */ - if (1) { - ra->pt_stage = 0; - ra->ra_stage = 0; - ra->pt_stop_count = 0; - } -} - -static void rtl8188e_power_training_decision(struct rtl8xxxu_ra_info *ra) -{ - u8 temp_stage; - u32 numsc; - u32 num_total; - u8 stage_id; - u8 j; - - numsc = 0; - num_total = ra->total * pt_penalty[5]; - for (j = 0; j <= 4; j++) { - numsc += ra->retry[j] * pt_penalty[j]; - - if (numsc > num_total) - break; - } - - j >>= 1; - temp_stage = (ra->pt_stage + 1) >> 1; - if (temp_stage > j) - stage_id = temp_stage - j; - else - stage_id = 0; - - ra->pt_smooth_factor = (ra->pt_smooth_factor >> 1) + - (ra->pt_smooth_factor >> 2) + - stage_id * 16 + 2; - if (ra->pt_smooth_factor > 192) - ra->pt_smooth_factor = 192; - stage_id = ra->pt_smooth_factor >> 6; - temp_stage = stage_id * 2; - if (temp_stage != 0) - temp_stage--; - if (ra->drop > 3) - temp_stage = 0; - ra->pt_stage = temp_stage; -} - -void rtl8188e_handle_ra_tx_report2(struct rtl8xxxu_priv *priv, struct sk_buff *skb) -{ - u32 *_rx_desc = (u32 *)(skb->data - sizeof(struct rtl8xxxu_rxdesc16)); - struct rtl8xxxu_rxdesc16 *rx_desc = (struct rtl8xxxu_rxdesc16 *)_rx_desc; - struct device *dev = &priv->udev->dev; - struct rtl8xxxu_ra_info *ra = &priv->ra_info; - u32 tx_rpt_len = rx_desc->pktlen & 0x3ff; - u32 items = tx_rpt_len / TX_RPT2_ITEM_SIZE; - u64 macid_valid = ((u64)_rx_desc[5] << 32) | _rx_desc[4]; - u32 macid; - u8 *rpt = skb->data; - bool valid; - u16 min_rpt_time = 0x927c; - - dev_dbg(dev, "%s: len: %d items: %d\n", __func__, tx_rpt_len, items); - - /* We only use macid 0, so only the first item is relevant. - * AP mode will use more of them if it's ever implemented. - */ - if (!priv->vifs[0] || priv->vifs[0]->type == NL80211_IFTYPE_STATION) - items = 1; - - for (macid = 0; macid < items; macid++) { - valid = false; - - if (macid < 64) - valid = macid_valid & BIT(macid); - - if (valid) { - ra->retry[0] = le16_to_cpu(*(__le16 *)rpt); - ra->retry[1] = rpt[2]; - ra->retry[2] = rpt[3]; - ra->retry[3] = rpt[4]; - ra->retry[4] = rpt[5]; - ra->drop = rpt[6]; - ra->total = ra->retry[0] + ra->retry[1] + ra->retry[2] + - ra->retry[3] + ra->retry[4] + ra->drop; - - if (ra->total > 0) { - if (ra->ra_stage < 5) - rtl8188e_rate_decision(ra); - else if (ra->ra_stage == 5) - rtl8188e_power_training_try_state(ra); - else /* ra->ra_stage == 6 */ - rtl8188e_power_training_decision(ra); - - if (ra->ra_stage <= 5) - ra->ra_stage++; - else - ra->ra_stage = 0; - } - } else if (macid == 0) { - dev_warn(dev, "%s: TX report item 0 not valid\n", __func__); - } - - dev_dbg(dev, "%s: valid: %d retry: %d %d %d %d %d drop: %d\n", - __func__, valid, - ra->retry[0], ra->retry[1], ra->retry[2], - ra->retry[3], ra->retry[4], ra->drop); - - if (min_rpt_time > ra->rpt_time) - min_rpt_time = ra->rpt_time; - - rpt += TX_RPT2_ITEM_SIZE; - } - - if (min_rpt_time != ra->pre_min_rpt_time) { - rtl8xxxu_write16(priv, REG_TX_REPORT_TIME, min_rpt_time); - ra->pre_min_rpt_time = min_rpt_time; - } -} - -static void rtl8188e_arfb_refresh(struct rtl8xxxu_ra_info *ra) -{ - s8 i; - - ra->ra_use_rate = ra->rate_mask; - - /* Highest rate */ - if (ra->ra_use_rate) { - for (i = RATESIZE; i >= 0; i--) { - if (ra->ra_use_rate & BIT(i)) { - ra->highest_rate = i; - break; - } - } - } else { - ra->highest_rate = 0; - } - - /* Lowest rate */ - if (ra->ra_use_rate) { - for (i = 0; i < RATESIZE; i++) { - if (ra->ra_use_rate & BIT(i)) { - ra->lowest_rate = i; - break; - } - } - } else { - ra->lowest_rate = 0; - } - - if (ra->highest_rate > DESC_RATE_MCS7) - ra->pt_mode_ss = 3; - else if (ra->highest_rate > DESC_RATE_54M) - ra->pt_mode_ss = 2; - else if (ra->highest_rate > DESC_RATE_11M) - ra->pt_mode_ss = 1; - else - ra->pt_mode_ss = 0; -} - -static void -rtl8188e_update_rate_mask(struct rtl8xxxu_priv *priv, - u32 ramask, u8 rateid, int sgi, int txbw_40mhz, - u8 macid) -{ - struct rtl8xxxu_ra_info *ra = &priv->ra_info; - - ra->rate_id = rateid; - ra->rate_mask = ramask; - ra->sgi_enable = sgi; - - rtl8188e_arfb_refresh(ra); -} - -static void rtl8188e_ra_set_rssi(struct rtl8xxxu_priv *priv, u8 macid, u8 rssi) -{ - priv->ra_info.rssi_sta_ra = rssi; -} - -void rtl8188e_ra_info_init_all(struct rtl8xxxu_ra_info *ra) -{ - ra->decision_rate = DESC_RATE_MCS7; - ra->pre_rate = DESC_RATE_MCS7; - ra->highest_rate = DESC_RATE_MCS7; - ra->lowest_rate = 0; - ra->rate_id = 0; - ra->rate_mask = 0xfffff; - ra->rssi_sta_ra = 0; - ra->pre_rssi_sta_ra = 0; - ra->sgi_enable = 0; - ra->ra_use_rate = 0xfffff; - ra->nsc_down = (n_threshold_high[DESC_RATE_MCS7] + n_threshold_low[DESC_RATE_MCS7]) / 2; - ra->nsc_up = (n_threshold_high[DESC_RATE_MCS7] + n_threshold_low[DESC_RATE_MCS7]) / 2; - ra->rate_sgi = 0; - ra->rpt_time = 0x927c; - ra->drop = 0; - ra->retry[0] = 0; - ra->retry[1] = 0; - ra->retry[2] = 0; - ra->retry[3] = 0; - ra->retry[4] = 0; - ra->total = 0; - ra->ra_waiting_counter = 0; - ra->ra_pending_counter = 0; - ra->ra_drop_after_down = 0; - - ra->pt_try_state = 0; - ra->pt_stage = 5; - ra->pt_smooth_factor = 192; - ra->pt_stop_count = 0; - ra->pt_pre_rate = 0; - ra->pt_pre_rssi = 0; - ra->pt_mode_ss = 0; - ra->ra_stage = 0; -} - -struct rtl8xxxu_fileops rtl8188eu_fops = { - .identify_chip = rtl8188eu_identify_chip, - .parse_efuse = rtl8188eu_parse_efuse, - .load_firmware = rtl8188eu_load_firmware, - .power_on = rtl8188eu_power_on, - .power_off = rtl8188eu_power_off, - .read_efuse = rtl8xxxu_read_efuse, - .reset_8051 = rtl8188eu_reset_8051, - .llt_init = rtl8xxxu_init_llt_table, - .init_phy_bb = rtl8188eu_init_phy_bb, - .init_phy_rf = rtl8188eu_init_phy_rf, - .phy_lc_calibrate = rtl8723a_phy_lc_calibrate, - .phy_iq_calibrate = rtl8188eu_phy_iq_calibrate, - .config_channel = rtl8188eu_config_channel, - .parse_rx_desc = rtl8xxxu_parse_rxdesc16, - .parse_phystats = rtl8723au_rx_parse_phystats, - .init_aggregation = rtl8188eu_init_aggregation, - .enable_rf = rtl8188e_enable_rf, - .disable_rf = rtl8188e_disable_rf, - .usb_quirks = rtl8188e_usb_quirks, - .set_tx_power = rtl8188f_set_tx_power, - .update_rate_mask = rtl8188e_update_rate_mask, - .report_connect = rtl8xxxu_gen2_report_connect, - .report_rssi = rtl8188e_ra_set_rssi, - .fill_txdesc = rtl8xxxu_fill_txdesc_v3, - .set_crystal_cap = rtl8188f_set_crystal_cap, - .cck_rssi = rtl8188e_cck_rssi, - .led_classdev_brightness_set = rtl8188eu_led_brightness_set, - .writeN_block_size = 128, - .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc16), - .tx_desc_size = sizeof(struct rtl8xxxu_txdesc32), - .has_tx_report = 1, - .init_reg_pkt_life_time = 1, - .gen2_thermal_meter = 1, - .max_sec_cam_num = 32, - .adda_1t_init = 0x0b1b25a0, - .adda_1t_path_on = 0x0bdb25a0, - /* - * Use 9K for 8188e normal chip - * Max RX buffer = 10K - max(TxReportSize(64*8), WOLPattern(16*24)) - */ - .trxff_boundary = 0x25ff, - .pbp_rx = PBP_PAGE_SIZE_128, - .pbp_tx = PBP_PAGE_SIZE_128, - .mactable = rtl8188e_mac_init_table, - .total_page_num = TX_TOTAL_PAGE_NUM_8188E, - .page_num_hi = TX_PAGE_NUM_HI_PQ_8188E, - .page_num_lo = TX_PAGE_NUM_LO_PQ_8188E, - .page_num_norm = TX_PAGE_NUM_NORM_PQ_8188E, - .last_llt_entry = 175, -}; diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188f.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188f.c deleted file mode 100644 index 9043e548518f..000000000000 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8188f.c +++ /dev/null @@ -1,1762 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * RTL8XXXU mac80211 USB driver - 8188f specific subdriver - * - * Copyright (c) 2022 Bitterblue Smith - * - * Portions copied from existing rtl8xxxu code: - * Copyright (c) 2014 - 2017 Jes Sorensen - * - * Portions, notably calibration code: - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "rtl8xxxu.h" -#include "rtl8xxxu_regs.h" - -static const struct rtl8xxxu_reg8val rtl8188f_mac_init_table[] = { - {0x024, 0xDF}, {0x025, 0x07}, {0x02B, 0x1C}, {0x283, 0x20}, - {0x421, 0x0F}, {0x428, 0x0A}, {0x429, 0x10}, {0x430, 0x00}, - {0x431, 0x00}, {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, - {0x435, 0x05}, {0x436, 0x07}, {0x437, 0x08}, {0x43C, 0x04}, - {0x43D, 0x05}, {0x43E, 0x07}, {0x43F, 0x08}, {0x440, 0x5D}, - {0x441, 0x01}, {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, - {0x446, 0x00}, {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xF0}, - {0x44A, 0x0F}, {0x44B, 0x3E}, {0x44C, 0x10}, {0x44D, 0x00}, - {0x44E, 0x00}, {0x44F, 0x00}, {0x450, 0x00}, {0x451, 0xF0}, - {0x452, 0x0F}, {0x453, 0x00}, {0x456, 0x5E}, {0x460, 0x44}, - {0x461, 0x44}, {0x4BC, 0xC0}, {0x4C8, 0xFF}, {0x4C9, 0x08}, - {0x4CC, 0xFF}, {0x4CD, 0xFF}, {0x4CE, 0x01}, {0x500, 0x26}, - {0x501, 0xA2}, {0x502, 0x2F}, {0x503, 0x00}, {0x504, 0x28}, - {0x505, 0xA3}, {0x506, 0x5E}, {0x507, 0x00}, {0x508, 0x2B}, - {0x509, 0xA4}, {0x50A, 0x5E}, {0x50B, 0x00}, {0x50C, 0x4F}, - {0x50D, 0xA4}, {0x50E, 0x00}, {0x50F, 0x00}, {0x512, 0x1C}, - {0x514, 0x0A}, {0x516, 0x0A}, {0x525, 0x4F}, {0x550, 0x10}, - {0x551, 0x10}, {0x559, 0x02}, {0x55C, 0x28}, {0x55D, 0xFF}, - {0x605, 0x30}, {0x608, 0x0E}, {0x609, 0x2A}, {0x620, 0xFF}, - {0x621, 0xFF}, {0x622, 0xFF}, {0x623, 0xFF}, {0x624, 0xFF}, - {0x625, 0xFF}, {0x626, 0xFF}, {0x627, 0xFF}, {0x638, 0x28}, - {0x63C, 0x0A}, {0x63D, 0x0A}, {0x63E, 0x0E}, {0x63F, 0x0E}, - {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00}, {0x652, 0xC8}, - {0x66E, 0x05}, {0x700, 0x21}, {0x701, 0x43}, {0x702, 0x65}, - {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43}, {0x70A, 0x65}, - {0x70B, 0x87}, - {0xffff, 0xff}, -}; - -static const struct rtl8xxxu_reg32val rtl8188fu_phy_init_table[] = { - {0x800, 0x80045700}, {0x804, 0x00000001}, - {0x808, 0x0000FC00}, {0x80C, 0x0000000A}, - {0x810, 0x10001331}, {0x814, 0x020C3D10}, - {0x818, 0x00200385}, {0x81C, 0x00000000}, - {0x820, 0x01000100}, {0x824, 0x00390204}, - {0x828, 0x00000000}, {0x82C, 0x00000000}, - {0x830, 0x00000000}, {0x834, 0x00000000}, - {0x838, 0x00000000}, {0x83C, 0x00000000}, - {0x840, 0x00010000}, {0x844, 0x00000000}, - {0x848, 0x00000000}, {0x84C, 0x00000000}, - {0x850, 0x00030000}, {0x854, 0x00000000}, - {0x858, 0x569A569A}, {0x85C, 0x569A569A}, - {0x860, 0x00000130}, {0x864, 0x00000000}, - {0x868, 0x00000000}, {0x86C, 0x27272700}, - {0x870, 0x00000000}, {0x874, 0x25004000}, - {0x878, 0x00000808}, {0x87C, 0x004F0201}, - {0x880, 0xB0000B1E}, {0x884, 0x00000007}, - {0x888, 0x00000000}, {0x88C, 0xCCC000C0}, - {0x890, 0x00000800}, {0x894, 0xFFFFFFFE}, - {0x898, 0x40302010}, {0x89C, 0x00706050}, - {0x900, 0x00000000}, {0x904, 0x00000023}, - {0x908, 0x00000000}, {0x90C, 0x81121111}, - {0x910, 0x00000002}, {0x914, 0x00000201}, - {0x948, 0x99000000}, {0x94C, 0x00000010}, - {0x950, 0x20003000}, {0x954, 0x4A880000}, - {0x958, 0x4BC5D87A}, {0x95C, 0x04EB9B79}, - {0x96C, 0x00000003}, {0xA00, 0x00D047C8}, - {0xA04, 0x80FF800C}, {0xA08, 0x8C898300}, - {0xA0C, 0x2E7F120F}, {0xA10, 0x9500BB78}, - {0xA14, 0x1114D028}, {0xA18, 0x00881117}, - {0xA1C, 0x89140F00}, {0xA20, 0xD1D80000}, - {0xA24, 0x5A7DA0BD}, {0xA28, 0x0000223B}, - {0xA2C, 0x00D30000}, {0xA70, 0x101FBF00}, - {0xA74, 0x00000007}, {0xA78, 0x00000900}, - {0xA7C, 0x225B0606}, {0xA80, 0x218075B1}, - {0xA84, 0x00120000}, {0xA88, 0x040C0000}, - {0xA8C, 0x12345678}, {0xA90, 0xABCDEF00}, - {0xA94, 0x001B1B89}, {0xA98, 0x05100000}, - {0xA9C, 0x3F000000}, {0xAA0, 0x00000000}, - {0xB2C, 0x00000000}, {0xC00, 0x48071D40}, - {0xC04, 0x03A05611}, {0xC08, 0x000000E4}, - {0xC0C, 0x6C6C6C6C}, {0xC10, 0x18800000}, - {0xC14, 0x40000100}, {0xC18, 0x08800000}, - {0xC1C, 0x40000100}, {0xC20, 0x00000000}, - {0xC24, 0x00000000}, {0xC28, 0x00000000}, - {0xC2C, 0x00000000}, {0xC30, 0x69E9CC4A}, - {0xC34, 0x31000040}, {0xC38, 0x21688080}, - {0xC3C, 0x00001714}, {0xC40, 0x1F78403F}, - {0xC44, 0x00010036}, {0xC48, 0xEC020107}, - {0xC4C, 0x007F037F}, {0xC50, 0x69553420}, - {0xC54, 0x43BC0094}, {0xC58, 0x00013169}, - {0xC5C, 0x00250492}, {0xC60, 0x00000000}, - {0xC64, 0x7112848B}, {0xC68, 0x47C07BFF}, - {0xC6C, 0x00000036}, {0xC70, 0x2C7F000D}, - {0xC74, 0x020600DB}, {0xC78, 0x0000001F}, - {0xC7C, 0x00B91612}, {0xC80, 0x390000E4}, - {0xC84, 0x11F60000}, - {0xC88, 0x40000100}, {0xC8C, 0x20200000}, - {0xC90, 0x00091521}, {0xC94, 0x00000000}, - {0xC98, 0x00121820}, {0xC9C, 0x00007F7F}, - {0xCA0, 0x00000000}, {0xCA4, 0x000300A0}, - {0xCA8, 0x00000000}, {0xCAC, 0x00000000}, - {0xCB0, 0x00000000}, {0xCB4, 0x00000000}, - {0xCB8, 0x00000000}, {0xCBC, 0x28000000}, - {0xCC0, 0x00000000}, {0xCC4, 0x00000000}, - {0xCC8, 0x00000000}, {0xCCC, 0x00000000}, - {0xCD0, 0x00000000}, {0xCD4, 0x00000000}, - {0xCD8, 0x64B22427}, {0xCDC, 0x00766932}, - {0xCE0, 0x00222222}, {0xCE4, 0x10000000}, - {0xCE8, 0x37644302}, {0xCEC, 0x2F97D40C}, - {0xD00, 0x04030740}, {0xD04, 0x40020401}, - {0xD08, 0x0000907F}, {0xD0C, 0x20010201}, - {0xD10, 0xA0633333}, {0xD14, 0x3333BC53}, - {0xD18, 0x7A8F5B6F}, {0xD2C, 0xCB979975}, - {0xD30, 0x00000000}, {0xD34, 0x80608000}, - {0xD38, 0x98000000}, {0xD3C, 0x40127353}, - {0xD40, 0x00000000}, {0xD44, 0x00000000}, - {0xD48, 0x00000000}, {0xD4C, 0x00000000}, - {0xD50, 0x6437140A}, {0xD54, 0x00000000}, - {0xD58, 0x00000282}, {0xD5C, 0x30032064}, - {0xD60, 0x4653DE68}, {0xD64, 0x04518A3C}, - {0xD68, 0x00002101}, {0xD6C, 0x2A201C16}, - {0xD70, 0x1812362E}, {0xD74, 0x322C2220}, - {0xD78, 0x000E3C24}, {0xE00, 0x2D2D2D2D}, - {0xE04, 0x2D2D2D2D}, {0xE08, 0x0390272D}, - {0xE10, 0x2D2D2D2D}, {0xE14, 0x2D2D2D2D}, - {0xE18, 0x2D2D2D2D}, {0xE1C, 0x2D2D2D2D}, - {0xE28, 0x00000000}, {0xE30, 0x1000DC1F}, - {0xE34, 0x10008C1F}, {0xE38, 0x02140102}, - {0xE3C, 0x681604C2}, {0xE40, 0x01007C00}, - {0xE44, 0x01004800}, {0xE48, 0xFB000000}, - {0xE4C, 0x000028D1}, {0xE50, 0x1000DC1F}, - {0xE54, 0x10008C1F}, {0xE58, 0x02140102}, - {0xE5C, 0x28160D05}, {0xE60, 0x00000008}, - {0xE60, 0x021400A0}, {0xE64, 0x281600A0}, - {0xE6C, 0x01C00010}, {0xE70, 0x01C00010}, - {0xE74, 0x02000010}, {0xE78, 0x02000010}, - {0xE7C, 0x02000010}, {0xE80, 0x02000010}, - {0xE84, 0x01C00010}, {0xE88, 0x02000010}, - {0xE8C, 0x01C00010}, {0xED0, 0x01C00010}, - {0xED4, 0x01C00010}, {0xED8, 0x01C00010}, - {0xEDC, 0x00000010}, {0xEE0, 0x00000010}, - {0xEEC, 0x03C00010}, {0xF14, 0x00000003}, - {0xF4C, 0x00000000}, {0xF00, 0x00000300}, - {0xffff, 0xffffffff}, -}; - -static const struct rtl8xxxu_reg32val rtl8188f_agc_table[] = { - {0xC78, 0xFC000001}, {0xC78, 0xFB010001}, - {0xC78, 0xFA020001}, {0xC78, 0xF9030001}, - {0xC78, 0xF8040001}, {0xC78, 0xF7050001}, - {0xC78, 0xF6060001}, {0xC78, 0xF5070001}, - {0xC78, 0xF4080001}, {0xC78, 0xF3090001}, - {0xC78, 0xF20A0001}, {0xC78, 0xF10B0001}, - {0xC78, 0xF00C0001}, {0xC78, 0xEF0D0001}, - {0xC78, 0xEE0E0001}, {0xC78, 0xED0F0001}, - {0xC78, 0xEC100001}, {0xC78, 0xEB110001}, - {0xC78, 0xEA120001}, {0xC78, 0xE9130001}, - {0xC78, 0xE8140001}, {0xC78, 0xE7150001}, - {0xC78, 0xE6160001}, {0xC78, 0xE5170001}, - {0xC78, 0xE4180001}, {0xC78, 0xE3190001}, - {0xC78, 0xE21A0001}, {0xC78, 0xE11B0001}, - {0xC78, 0xE01C0001}, {0xC78, 0xC21D0001}, - {0xC78, 0xC11E0001}, {0xC78, 0xC01F0001}, - {0xC78, 0xA5200001}, {0xC78, 0xA4210001}, - {0xC78, 0xA3220001}, {0xC78, 0xA2230001}, - {0xC78, 0xA1240001}, {0xC78, 0xA0250001}, - {0xC78, 0x65260001}, {0xC78, 0x64270001}, - {0xC78, 0x63280001}, {0xC78, 0x62290001}, - {0xC78, 0x612A0001}, {0xC78, 0x442B0001}, - {0xC78, 0x432C0001}, {0xC78, 0x422D0001}, - {0xC78, 0x412E0001}, {0xC78, 0x402F0001}, - {0xC78, 0x21300001}, {0xC78, 0x20310001}, - {0xC78, 0x05320001}, {0xC78, 0x04330001}, - {0xC78, 0x03340001}, {0xC78, 0x02350001}, - {0xC78, 0x01360001}, {0xC78, 0x00370001}, - {0xC78, 0x00380001}, {0xC78, 0x00390001}, - {0xC78, 0x003A0001}, {0xC78, 0x003B0001}, - {0xC78, 0x003C0001}, {0xC78, 0x003D0001}, - {0xC78, 0x003E0001}, {0xC78, 0x003F0001}, - {0xC50, 0x69553422}, {0xC50, 0x69553420}, - {0xffff, 0xffffffff} -}; - -static const struct rtl8xxxu_rfregval rtl8188fu_radioa_init_table[] = { - {0x00, 0x00030000}, {0x08, 0x00008400}, - {0x18, 0x00000407}, {0x19, 0x00000012}, - {0x1B, 0x00001C6C}, - {0x1E, 0x00080009}, {0x1F, 0x00000880}, - {0x2F, 0x0001A060}, {0x3F, 0x00028000}, - {0x42, 0x000060C0}, {0x57, 0x000D0000}, - {0x58, 0x000C0160}, {0x67, 0x00001552}, - {0x83, 0x00000000}, {0xB0, 0x000FF9F0}, - {0xB1, 0x00022218}, {0xB2, 0x00034C00}, - {0xB4, 0x0004484B}, {0xB5, 0x0000112A}, - {0xB6, 0x0000053E}, {0xB7, 0x00010408}, - {0xB8, 0x00010200}, {0xB9, 0x00080001}, - {0xBA, 0x00040001}, {0xBB, 0x00000400}, - {0xBF, 0x000C0000}, {0xC2, 0x00002400}, - {0xC3, 0x00000009}, {0xC4, 0x00040C91}, - {0xC5, 0x00099999}, {0xC6, 0x000000A3}, - {0xC7, 0x0008F820}, {0xC8, 0x00076C06}, - {0xC9, 0x00000000}, {0xCA, 0x00080000}, - {0xDF, 0x00000180}, {0xEF, 0x000001A0}, - {0x51, 0x000E8333}, {0x52, 0x000FAC2C}, - {0x53, 0x00000103}, {0x56, 0x000517F0}, - {0x35, 0x00000099}, {0x35, 0x00000199}, - {0x35, 0x00000299}, {0x36, 0x00000064}, - {0x36, 0x00008064}, {0x36, 0x00010064}, - {0x36, 0x00018064}, {0x18, 0x00000C07}, - {0x5A, 0x00048000}, {0x19, 0x000739D0}, - {0x34, 0x0000ADD6}, {0x34, 0x00009DD3}, - {0x34, 0x00008CF4}, {0x34, 0x00007CF1}, - {0x34, 0x00006CEE}, {0x34, 0x00005CEB}, - {0x34, 0x00004CCE}, {0x34, 0x00003CCB}, - {0x34, 0x00002CC8}, {0x34, 0x00001C4B}, - {0x34, 0x00000C48}, - {0x00, 0x00030159}, {0x84, 0x00048000}, - {0x86, 0x0000002A}, {0x87, 0x00000025}, - {0x8E, 0x00065540}, {0x8F, 0x00088000}, - {0xEF, 0x000020A0}, {0x3B, 0x000F0F00}, - {0x3B, 0x000E0B00}, {0x3B, 0x000D0900}, - {0x3B, 0x000C0700}, {0x3B, 0x000B0600}, - {0x3B, 0x000A0400}, {0x3B, 0x00090200}, - {0x3B, 0x00080000}, {0x3B, 0x0007BF00}, - {0x3B, 0x00060B00}, {0x3B, 0x0005C900}, - {0x3B, 0x00040700}, {0x3B, 0x00030600}, - {0x3B, 0x0002D500}, {0x3B, 0x00010200}, - {0x3B, 0x0000E000}, {0xEF, 0x000000A0}, - {0xEF, 0x00000010}, {0x3B, 0x0000C0A8}, - {0x3B, 0x00010400}, {0xEF, 0x00000000}, - {0xEF, 0x00080000}, {0x30, 0x00010000}, - {0x31, 0x0000000F}, {0x32, 0x00007EFE}, - {0xEF, 0x00000000}, {0x00, 0x00010159}, - {0x18, 0x0000FC07}, {0xFE, 0x00000000}, - {0xFE, 0x00000000}, {0x1F, 0x00080003}, - {0xFE, 0x00000000}, {0xFE, 0x00000000}, - {0x1E, 0x00000001}, {0x1F, 0x00080000}, - {0x00, 0x00033D95}, - {0xff, 0xffffffff} -}; - -static const struct rtl8xxxu_rfregval rtl8188fu_cut_b_radioa_init_table[] = { - {0x00, 0x00030000}, {0x08, 0x00008400}, - {0x18, 0x00000407}, {0x19, 0x00000012}, - {0x1B, 0x00001C6C}, - {0x1E, 0x00080009}, {0x1F, 0x00000880}, - {0x2F, 0x0001A060}, {0x3F, 0x00028000}, - {0x42, 0x000060C0}, {0x57, 0x000D0000}, - {0x58, 0x000C0160}, {0x67, 0x00001552}, - {0x83, 0x00000000}, {0xB0, 0x000FF9F0}, - {0xB1, 0x00022218}, {0xB2, 0x00034C00}, - {0xB4, 0x0004484B}, {0xB5, 0x0000112A}, - {0xB6, 0x0000053E}, {0xB7, 0x00010408}, - {0xB8, 0x00010200}, {0xB9, 0x00080001}, - {0xBA, 0x00040001}, {0xBB, 0x00000400}, - {0xBF, 0x000C0000}, {0xC2, 0x00002400}, - {0xC3, 0x00000009}, {0xC4, 0x00040C91}, - {0xC5, 0x00099999}, {0xC6, 0x000000A3}, - {0xC7, 0x0008F820}, {0xC8, 0x00076C06}, - {0xC9, 0x00000000}, {0xCA, 0x00080000}, - {0xDF, 0x00000180}, {0xEF, 0x000001A0}, - {0x51, 0x000E8231}, {0x52, 0x000FAC2C}, - {0x53, 0x00000141}, {0x56, 0x000517F0}, - {0x35, 0x00000090}, {0x35, 0x00000190}, - {0x35, 0x00000290}, {0x36, 0x00001064}, - {0x36, 0x00009064}, {0x36, 0x00011064}, - {0x36, 0x00019064}, {0x18, 0x00000C07}, - {0x5A, 0x00048000}, {0x19, 0x000739D0}, - {0x34, 0x0000ADD2}, {0x34, 0x00009DD0}, - {0x34, 0x00008CF3}, {0x34, 0x00007CF0}, - {0x34, 0x00006CED}, {0x34, 0x00005CD2}, - {0x34, 0x00004CCF}, {0x34, 0x00003CCC}, - {0x34, 0x00002CC9}, {0x34, 0x00001C4C}, - {0x34, 0x00000C49}, - {0x00, 0x00030159}, {0x84, 0x00048000}, - {0x86, 0x0000002A}, {0x87, 0x00000025}, - {0x8E, 0x00065540}, {0x8F, 0x00088000}, - {0xEF, 0x000020A0}, {0x3B, 0x000F0F00}, - {0x3B, 0x000E0B00}, {0x3B, 0x000D0900}, - {0x3B, 0x000C0700}, {0x3B, 0x000B0600}, - {0x3B, 0x000A0400}, {0x3B, 0x00090200}, - {0x3B, 0x00080000}, {0x3B, 0x0007BF00}, - {0x3B, 0x00060B00}, {0x3B, 0x0005C900}, - {0x3B, 0x00040700}, {0x3B, 0x00030600}, - {0x3B, 0x0002D500}, {0x3B, 0x00010200}, - {0x3B, 0x0000E000}, {0xEF, 0x000000A0}, - {0xEF, 0x00000010}, {0x3B, 0x0000C0A8}, - {0x3B, 0x00010400}, {0xEF, 0x00000000}, - {0xEF, 0x00080000}, {0x30, 0x00010000}, - {0x31, 0x0000000F}, {0x32, 0x00007EFE}, - {0xEF, 0x00000000}, {0x00, 0x00010159}, - {0x18, 0x0000FC07}, {0xFE, 0x00000000}, - {0xFE, 0x00000000}, {0x1F, 0x00080003}, - {0xFE, 0x00000000}, {0xFE, 0x00000000}, - {0x1E, 0x00000001}, {0x1F, 0x00080000}, - {0x00, 0x00033D95}, - {0xff, 0xffffffff} -}; - -static int rtl8188fu_identify_chip(struct rtl8xxxu_priv *priv) -{ - struct device *dev = &priv->udev->dev; - u32 sys_cfg, vendor; - int ret = 0; - - strscpy(priv->chip_name, "8188FU", sizeof(priv->chip_name)); - priv->rtl_chip = RTL8188F; - priv->rf_paths = 1; - priv->rx_paths = 1; - priv->tx_paths = 1; - priv->has_wifi = 1; - - sys_cfg = rtl8xxxu_read32(priv, REG_SYS_CFG); - priv->chip_cut = u32_get_bits(sys_cfg, SYS_CFG_CHIP_VERSION_MASK); - if (sys_cfg & SYS_CFG_TRP_VAUX_EN) { - dev_info(dev, "Unsupported test chip\n"); - ret = -ENOTSUPP; - goto out; - } - - vendor = sys_cfg & SYS_CFG_VENDOR_EXT_MASK; - rtl8xxxu_identify_vendor_2bits(priv, vendor); - - ret = rtl8xxxu_config_endpoints_no_sie(priv); - -out: - return ret; -} - -void rtl8188f_channel_to_group(int channel, int *group, int *cck_group) -{ - if (channel < 3) - *group = 0; - else if (channel < 6) - *group = 1; - else if (channel < 9) - *group = 2; - else if (channel < 12) - *group = 3; - else - *group = 4; - - if (channel == 14) - *cck_group = 5; - else - *cck_group = *group; -} - -void -rtl8188f_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40) -{ - u32 val32, ofdm, mcs; - u8 cck, ofdmbase, mcsbase; - int group, cck_group; - - rtl8188f_channel_to_group(channel, &group, &cck_group); - - cck = priv->cck_tx_power_index_A[cck_group]; - - val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32); - val32 &= 0xffff00ff; - val32 |= (cck << 8); - rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); - - val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); - val32 &= 0xff; - val32 |= ((cck << 8) | (cck << 16) | (cck << 24)); - rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); - - ofdmbase = priv->ht40_1s_tx_power_index_A[group]; - ofdmbase += priv->ofdm_tx_power_diff[0].a; - ofdm = ofdmbase | ofdmbase << 8 | ofdmbase << 16 | ofdmbase << 24; - - rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm); - rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm); - - mcsbase = priv->ht40_1s_tx_power_index_A[group]; - if (ht40) - /* This diff is always 0 - not used in 8188FU. */ - mcsbase += priv->ht40_tx_power_diff[0].a; - else - mcsbase += priv->ht20_tx_power_diff[0].a; - mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24; - - rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs); - rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs); - rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs); - rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs); -} - -/* A workaround to eliminate the 2400MHz, 2440MHz, 2480MHz spur of 8188F. */ -static void rtl8188f_spur_calibration(struct rtl8xxxu_priv *priv, u8 channel) -{ - static const u32 frequencies[14 + 1] = { - [5] = 0xFCCD, - [6] = 0xFC4D, - [7] = 0xFFCD, - [8] = 0xFF4D, - [11] = 0xFDCD, - [13] = 0xFCCD, - [14] = 0xFF9A - }; - - static const u32 reg_d40[14 + 1] = { - [5] = 0x06000000, - [6] = 0x00000600, - [13] = 0x06000000 - }; - - static const u32 reg_d44[14 + 1] = { - [11] = 0x04000000 - }; - - static const u32 reg_d4c[14 + 1] = { - [7] = 0x06000000, - [8] = 0x00000380, - [14] = 0x00180000 - }; - - const u8 threshold = 0x16; - bool do_notch, hw_ctrl, sw_ctrl, hw_ctrl_s1 = 0, sw_ctrl_s1 = 0; - u32 val32, initial_gain, reg948; - - val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_D_SYNC_PATH); - val32 |= GENMASK(28, 24); - rtl8xxxu_write32(priv, REG_OFDM0_RX_D_SYNC_PATH, val32); - - /* enable notch filter */ - val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_D_SYNC_PATH); - val32 |= BIT(9); - rtl8xxxu_write32(priv, REG_OFDM0_RX_D_SYNC_PATH, val32); - - if (channel <= 14 && frequencies[channel] > 0) { - reg948 = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); - hw_ctrl = reg948 & BIT(6); - sw_ctrl = !hw_ctrl; - - if (hw_ctrl) { - val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE); - val32 &= GENMASK(5, 3); - hw_ctrl_s1 = val32 == BIT(3); - } else if (sw_ctrl) { - sw_ctrl_s1 = !(reg948 & BIT(9)); - } - - if (hw_ctrl_s1 || sw_ctrl_s1) { - initial_gain = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); - - /* Disable CCK block */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); - val32 &= ~FPGA_RF_MODE_CCK; - rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); - - val32 = initial_gain & ~OFDM0_X_AGC_CORE1_IGI_MASK; - val32 |= 0x30; - rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32); - - /* disable 3-wire */ - rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xccf000c0); - - /* Setup PSD */ - rtl8xxxu_write32(priv, REG_FPGA0_PSD_FUNC, frequencies[channel]); - - /* Start PSD */ - rtl8xxxu_write32(priv, REG_FPGA0_PSD_FUNC, 0x400000 | frequencies[channel]); - - msleep(30); - - do_notch = rtl8xxxu_read32(priv, REG_FPGA0_PSD_REPORT) >= threshold; - - /* turn off PSD */ - rtl8xxxu_write32(priv, REG_FPGA0_PSD_FUNC, frequencies[channel]); - - /* enable 3-wire */ - rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xccc000c0); - - /* Enable CCK block */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); - val32 |= FPGA_RF_MODE_CCK; - rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); - - rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, initial_gain); - - if (do_notch) { - rtl8xxxu_write32(priv, REG_OFDM1_CSI_FIX_MASK1, reg_d40[channel]); - rtl8xxxu_write32(priv, REG_OFDM1_CSI_FIX_MASK2, reg_d44[channel]); - rtl8xxxu_write32(priv, 0xd48, 0x0); - rtl8xxxu_write32(priv, 0xd4c, reg_d4c[channel]); - - /* enable CSI mask */ - val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING); - val32 |= BIT(28); - rtl8xxxu_write32(priv, REG_OFDM1_CFO_TRACKING, val32); - - return; - } - } - } - - /* disable CSI mask function */ - val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING); - val32 &= ~BIT(28); - rtl8xxxu_write32(priv, REG_OFDM1_CFO_TRACKING, val32); -} - -static void rtl8188fu_config_channel(struct ieee80211_hw *hw) -{ - struct rtl8xxxu_priv *priv = hw->priv; - u32 val32; - u8 channel, subchannel; - bool sec_ch_above; - - channel = (u8)hw->conf.chandef.chan->hw_value; - - /* Set channel */ - val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG); - val32 &= ~MODE_AG_CHANNEL_MASK; - val32 |= channel; - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32); - - /* Spur calibration */ - rtl8188f_spur_calibration(priv, channel); - - /* Set bandwidth mode */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); - val32 &= ~FPGA_RF_MODE; - val32 |= hw->conf.chandef.width == NL80211_CHAN_WIDTH_40; - rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); - - val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); - val32 &= ~FPGA_RF_MODE; - val32 |= hw->conf.chandef.width == NL80211_CHAN_WIDTH_40; - rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); - - /* RXADC CLK */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); - val32 |= GENMASK(10, 8); - rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); - - /* TXDAC CLK */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); - val32 |= BIT(14) | BIT(12); - val32 &= ~BIT(13); - rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); - - /* small BW */ - val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT); - val32 &= ~GENMASK(31, 30); - rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32); - - /* adc buffer clk */ - val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT); - val32 &= ~BIT(29); - val32 |= BIT(28); - rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32); - - /* adc buffer clk */ - val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_AFE); - val32 &= ~BIT(29); - val32 |= BIT(28); - rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_AFE, val32); - - val32 = rtl8xxxu_read32(priv, REG_OFDM_RX_DFIR); - val32 &= ~BIT(19); - rtl8xxxu_write32(priv, REG_OFDM_RX_DFIR, val32); - - val32 = rtl8xxxu_read32(priv, REG_OFDM_RX_DFIR); - val32 &= ~GENMASK(23, 20); - val32 |= BIT(21); - if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_20 || - hw->conf.chandef.width == NL80211_CHAN_WIDTH_20_NOHT) - val32 |= BIT(20); - else if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) - val32 |= BIT(22); - rtl8xxxu_write32(priv, REG_OFDM_RX_DFIR, val32); - - if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) { - if (hw->conf.chandef.center_freq1 > - hw->conf.chandef.chan->center_freq) { - sec_ch_above = 1; - channel += 2; - } else { - sec_ch_above = 0; - channel -= 2; - } - - /* Set Control channel to upper or lower. */ - val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM); - val32 &= ~CCK0_SIDEBAND; - if (!sec_ch_above) - val32 |= CCK0_SIDEBAND; - rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32); - - val32 = rtl8xxxu_read32(priv, REG_DATA_SUBCHANNEL); - val32 &= ~GENMASK(3, 0); - if (sec_ch_above) - subchannel = 2; - else - subchannel = 1; - val32 |= subchannel; - rtl8xxxu_write32(priv, REG_DATA_SUBCHANNEL, val32); - - val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); - val32 &= ~RSR_RSC_BANDWIDTH_40M; - rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); - } - - /* RF TRX_BW */ - val32 = channel; - if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_20 || - hw->conf.chandef.width == NL80211_CHAN_WIDTH_20_NOHT) - val32 |= MODE_AG_BW_20MHZ_8723B; - else if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) - val32 |= MODE_AG_BW_40MHZ_8723B; - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32); - - /* FILTER BW&RC Corner (ACPR) */ - if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_20 || - hw->conf.chandef.width == NL80211_CHAN_WIDTH_20_NOHT) - val32 = 0x00065; - else if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) - val32 = 0x00025; - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RXG_MIX_SWBW, val32); - - if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_20 || - hw->conf.chandef.width == NL80211_CHAN_WIDTH_20_NOHT) - val32 = 0x0; - else if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) - val32 = 0x01000; - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RX_BB2, val32); - - /* RC Corner */ - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x00140); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RX_G2, 0x01c6c); -} - -static void rtl8188fu_init_aggregation(struct rtl8xxxu_priv *priv) -{ - u8 agg_ctrl, rxdma_mode, usb_tx_agg_desc_num = 6; - u32 agg_rx, val32; - - /* TX aggregation */ - val32 = rtl8xxxu_read32(priv, REG_DWBCN0_CTRL_8188F); - val32 &= ~(0xf << 4); - val32 |= usb_tx_agg_desc_num << 4; - rtl8xxxu_write32(priv, REG_DWBCN0_CTRL_8188F, val32); - rtl8xxxu_write8(priv, REG_DWBCN1_CTRL_8723B, usb_tx_agg_desc_num << 1); - - /* RX aggregation */ - agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL); - agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN; - - agg_rx = rtl8xxxu_read32(priv, REG_RXDMA_AGG_PG_TH); - agg_rx &= ~RXDMA_USB_AGG_ENABLE; - agg_rx &= ~0xFF0F; /* reset agg size and timeout */ - - rxdma_mode = rtl8xxxu_read8(priv, REG_RXDMA_PRO_8723B); - rxdma_mode &= ~BIT(1); - - rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl); - rtl8xxxu_write32(priv, REG_RXDMA_AGG_PG_TH, agg_rx); - rtl8xxxu_write8(priv, REG_RXDMA_PRO_8723B, rxdma_mode); -} - -static void rtl8188fu_init_statistics(struct rtl8xxxu_priv *priv) -{ - u32 val32; - - /* Time duration for NHM unit: 4us, 0xc350=200ms */ - rtl8xxxu_write16(priv, REG_NHM_TIMER_8723B + 2, 0xc350); - rtl8xxxu_write16(priv, REG_NHM_TH9_TH10_8723B + 2, 0xffff); - rtl8xxxu_write32(priv, REG_NHM_TH3_TO_TH0_8723B, 0xffffff50); - rtl8xxxu_write32(priv, REG_NHM_TH7_TO_TH4_8723B, 0xffffffff); - - /* TH8 */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); - val32 |= 0xff; - rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); - - /* Enable CCK */ - val32 = rtl8xxxu_read32(priv, REG_NHM_TH9_TH10_8723B); - val32 &= ~(BIT(8) | BIT(9) | BIT(10)); - val32 |= BIT(8); - rtl8xxxu_write32(priv, REG_NHM_TH9_TH10_8723B, val32); - - /* Max power amongst all RX antennas */ - val32 = rtl8xxxu_read32(priv, REG_OFDM0_FA_RSTC); - val32 |= BIT(7); - rtl8xxxu_write32(priv, REG_OFDM0_FA_RSTC, val32); -} - -static int rtl8188fu_parse_efuse(struct rtl8xxxu_priv *priv) -{ - struct rtl8188fu_efuse *efuse = &priv->efuse_wifi.efuse8188fu; - - if (efuse->rtl_id != cpu_to_le16(0x8129)) - return -EINVAL; - - ether_addr_copy(priv->mac_addr, efuse->mac_addr); - - memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base, - sizeof(efuse->tx_power_index_A.cck_base)); - - memcpy(priv->ht40_1s_tx_power_index_A, - efuse->tx_power_index_A.ht40_base, - sizeof(efuse->tx_power_index_A.ht40_base)); - - priv->ofdm_tx_power_diff[0].a = efuse->tx_power_index_A.ht20_ofdm_1s_diff.a; - priv->ht20_tx_power_diff[0].a = efuse->tx_power_index_A.ht20_ofdm_1s_diff.b; - - priv->default_crystal_cap = efuse->xtal_k & 0x3f; - - return 0; -} - -static int rtl8188fu_load_firmware(struct rtl8xxxu_priv *priv) -{ - const char *fw_name; - int ret; - - fw_name = "rtlwifi/rtl8188fufw.bin"; - - ret = rtl8xxxu_load_firmware(priv, fw_name); - - return ret; -} - -static void rtl8188fu_init_phy_bb(struct rtl8xxxu_priv *priv) -{ - u8 val8; - u16 val16; - - /* Enable BB and RF */ - val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); - val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB | SYS_FUNC_DIO_RF; - rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); - - /* - * Per vendor driver, run power sequence before init of RF - */ - val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB; - rtl8xxxu_write8(priv, REG_RF_CTRL, val8); - - usleep_range(10, 20); - - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_IQADJ_G1, 0x780); - - val8 = SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB | SYS_FUNC_USBA | SYS_FUNC_USBD; - rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); - - rtl8xxxu_init_phy_regs(priv, rtl8188fu_phy_init_table); - rtl8xxxu_init_phy_regs(priv, rtl8188f_agc_table); -} - -static int rtl8188fu_init_phy_rf(struct rtl8xxxu_priv *priv) -{ - int ret; - - if (priv->chip_cut == 1) - ret = rtl8xxxu_init_phy_rf(priv, rtl8188fu_cut_b_radioa_init_table, RF_A); - else - ret = rtl8xxxu_init_phy_rf(priv, rtl8188fu_radioa_init_table, RF_A); - - return ret; -} - -void rtl8188f_phy_lc_calibrate(struct rtl8xxxu_priv *priv) -{ - u32 val32; - u32 rf_amode, lstf; - int i; - - /* Check continuous TX and Packet TX */ - lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF); - - if (lstf & OFDM_LSTF_MASK) { - /* Disable all continuous TX */ - val32 = lstf & ~OFDM_LSTF_MASK; - rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); - } else { - /* Deal with Packet TX case */ - /* block all queues */ - rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); - } - - /* Read original RF mode Path A */ - rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG); - - /* Start LC calibration */ - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, rf_amode | 0x08000); - - for (i = 0; i < 100; i++) { - if ((rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG) & 0x08000) == 0) - break; - msleep(10); - } - - if (i == 100) - dev_warn(&priv->udev->dev, "LC calibration timed out.\n"); - - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, rf_amode); - - /* Restore original parameters */ - if (lstf & OFDM_LSTF_MASK) - rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf); - else /* Deal with Packet TX case */ - rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); -} - -static int rtl8188fu_iqk_path_a(struct rtl8xxxu_priv *priv, u32 *lok_result) -{ - u32 reg_eac, reg_e94, reg_e9c, val32; - int result = 0; - - /* - * Leave IQK mode - */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); - val32 &= 0x000000ff; - rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); - - /* - * Enable path A PA in TX IQK mode - */ - val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); - val32 |= 0x80000; - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x20000); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0x07ff7); - - /* PA,PAD gain adjust */ - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x980); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_PAD_TXG, 0x5102a); - - /* enter IQK mode */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); - val32 &= 0x000000ff; - val32 |= 0x80800000; - rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); - - /* path-A IQK setting */ - rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); - rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); - - rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821403ff); - rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160000); - - /* LO calibration setting */ - rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911); - - /* One shot, path A LOK & IQK */ - rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); - rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); - - mdelay(25); - - /* - * Leave IQK mode - */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); - val32 &= 0x000000ff; - rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); - - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x180); - - /* save LOK result */ - *lok_result = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_TXM_IDAC); - - /* Check failed */ - reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); - reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); - reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); - - if (!(reg_eac & BIT(28)) && - ((reg_e94 & 0x03ff0000) != 0x01420000) && - ((reg_e9c & 0x03ff0000) != 0x00420000)) - result |= 0x01; - - return result; -} - -static int rtl8188fu_rx_iqk_path_a(struct rtl8xxxu_priv *priv, u32 lok_result) -{ - u32 reg_ea4, reg_eac, reg_e94, reg_e9c, val32; - int result = 0; - - /* - * Leave IQK mode - */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); - val32 &= 0x000000ff; - rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); - - /* - * Enable path A PA in TX IQK mode - */ - val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); - val32 |= 0x80000; - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf1173); - - /* PA,PAD gain adjust */ - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x980); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_PAD_TXG, 0x5102a); - - /* - * Enter IQK mode - */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); - val32 &= 0x000000ff; - val32 |= 0x80800000; - rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); - - /* - * Tx IQK setting - */ - rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); - rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); - - /* path-A IQK setting */ - rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1c); - rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x30008c1c); - - rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160fff); - rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160000); - - /* LO calibration setting */ - rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911); - - /* One shot, path A LOK & IQK */ - rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); - rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); - - mdelay(25); - - /* - * Leave IQK mode - */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); - val32 &= 0x000000ff; - rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); - - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x180); - - /* Check failed */ - reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); - reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); - reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); - - if (!(reg_eac & BIT(28)) && - ((reg_e94 & 0x03ff0000) != 0x01420000) && - ((reg_e9c & 0x03ff0000) != 0x00420000)) - result |= 0x01; - else /* If TX not OK, ignore RX */ - goto out; - - val32 = 0x80007c00 | (reg_e94 & 0x3ff0000) | - ((reg_e9c & 0x3ff0000) >> 16); - rtl8xxxu_write32(priv, REG_TX_IQK, val32); - - /* - * Modify RX IQK mode table - */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); - val32 &= 0x000000ff; - rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); - - val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); - val32 |= 0x80000; - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7ff2); - - /* - * PA, PAD setting - */ - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x980); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_PAD_TXG, 0x51000); - - /* - * Enter IQK mode - */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); - val32 &= 0x000000ff; - val32 |= 0x80800000; - rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); - - /* - * RX IQK setting - */ - rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); - - /* path-A IQK setting */ - rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x30008c1c); - rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1c); - - rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160000); - rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x281613ff); - - /* LO calibration setting */ - rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911); - - /* One shot, path A LOK & IQK */ - rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); - rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); - - mdelay(25); - - /* - * Leave IQK mode - */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); - val32 &= 0x000000ff; - rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); - - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x180); - - /* reload LOK value */ - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXM_IDAC, lok_result); - - /* Check failed */ - reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); - reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); - - if (!(reg_eac & BIT(27)) && - ((reg_ea4 & 0x03ff0000) != 0x01320000) && - ((reg_eac & 0x03ff0000) != 0x00360000)) - result |= 0x02; - -out: - return result; -} - -static void rtl8188fu_phy_iqcalibrate(struct rtl8xxxu_priv *priv, - int result[][8], int t) -{ - struct device *dev = &priv->udev->dev; - u32 i, val32, rx_initial_gain, lok_result; - u32 path_sel_bb, path_sel_rf; - int path_a_ok; - int retry = 2; - static const u32 adda_regs[RTL8XXXU_ADDA_REGS] = { - REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH, - REG_RX_WAIT_CCA, REG_TX_CCK_RFON, - REG_TX_CCK_BBON, REG_TX_OFDM_RFON, - REG_TX_OFDM_BBON, REG_TX_TO_RX, - REG_TX_TO_TX, REG_RX_CCK, - REG_RX_OFDM, REG_RX_WAIT_RIFS, - REG_RX_TO_RX, REG_STANDBY, - REG_SLEEP, REG_PMPD_ANAEN - }; - static const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = { - REG_TXPAUSE, REG_BEACON_CTRL, - REG_BEACON_CTRL_1, REG_GPIO_MUXCFG - }; - static const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = { - REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR, - REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, - REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE, - REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE - }; - - /* - * Note: IQ calibration must be performed after loading - * PHY_REG.txt , and radio_a, radio_b.txt - */ - - rx_initial_gain = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); - - if (t == 0) { - /* Save ADDA parameters, turn Path A ADDA on */ - rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup, - RTL8XXXU_ADDA_REGS); - rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup); - rtl8xxxu_save_regs(priv, iqk_bb_regs, - priv->bb_backup, RTL8XXXU_BB_REGS); - } - - rtl8xxxu_path_adda_on(priv, adda_regs, true); - - if (t == 0) { - val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1); - priv->pi_enabled = u32_get_bits(val32, FPGA0_HSSI_PARM1_PI); - } - - /* save RF path */ - path_sel_bb = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); - path_sel_rf = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_S0S1); - - /* BB setting */ - rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600); - rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4); - rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x25204000); - - /* MAC settings */ - val32 = rtl8xxxu_read32(priv, REG_TX_PTCL_CTRL); - val32 |= 0x00ff0000; - rtl8xxxu_write32(priv, REG_TX_PTCL_CTRL, val32); - - /* IQ calibration setting */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); - val32 &= 0xff; - val32 |= 0x80800000; - rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); - rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); - rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); - - for (i = 0; i < retry; i++) { - path_a_ok = rtl8188fu_iqk_path_a(priv, &lok_result); - if (path_a_ok == 0x01) { - val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); - val32 &= 0xff; - rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); - - val32 = rtl8xxxu_read32(priv, - REG_TX_POWER_BEFORE_IQK_A); - result[t][0] = (val32 >> 16) & 0x3ff; - - val32 = rtl8xxxu_read32(priv, - REG_TX_POWER_AFTER_IQK_A); - result[t][1] = (val32 >> 16) & 0x3ff; - break; - } - } - - for (i = 0; i < retry; i++) { - path_a_ok = rtl8188fu_rx_iqk_path_a(priv, lok_result); - if (path_a_ok == 0x03) { - val32 = rtl8xxxu_read32(priv, - REG_RX_POWER_BEFORE_IQK_A_2); - result[t][2] = (val32 >> 16) & 0x3ff; - - val32 = rtl8xxxu_read32(priv, - REG_RX_POWER_AFTER_IQK_A_2); - result[t][3] = (val32 >> 16) & 0x3ff; - break; - } - } - - if (!path_a_ok) - dev_dbg(dev, "%s: Path A IQK failed!\n", __func__); - - /* Back to BB mode, load original value */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); - val32 &= 0xff; - rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); - - if (t == 0) - return; - - if (!priv->pi_enabled) { - /* - * Switch back BB to SI mode after finishing - * IQ Calibration - */ - val32 = 0x01000000; - rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32); - rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32); - } - - /* Reload ADDA power saving parameters */ - rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup, - RTL8XXXU_ADDA_REGS); - - /* Reload MAC parameters */ - rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup); - - /* Reload BB parameters */ - rtl8xxxu_restore_regs(priv, iqk_bb_regs, - priv->bb_backup, RTL8XXXU_BB_REGS); - - /* Reload RF path */ - rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel_bb); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, path_sel_rf); - - /* Restore RX initial gain */ - val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); - val32 &= 0xffffff00; - val32 |= 0x50; - rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32); - val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); - val32 &= 0xffffff00; - val32 |= rx_initial_gain & 0xff; - rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32); - - /* Load 0xe30 IQC default value */ - rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00); - rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00); -} - -static void rtl8188fu_phy_iq_calibrate(struct rtl8xxxu_priv *priv) -{ - struct device *dev = &priv->udev->dev; - int result[4][8]; /* last is final result */ - int i, candidate; - bool path_a_ok; - u32 reg_e94, reg_e9c, reg_ea4, reg_eac; - u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc; - s32 reg_tmp = 0; - bool simu; - u32 path_sel_bb, path_sel_rf; - - /* Save RF path */ - path_sel_bb = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); - path_sel_rf = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_S0S1); - - memset(result, 0, sizeof(result)); - candidate = -1; - - path_a_ok = false; - - for (i = 0; i < 3; i++) { - rtl8188fu_phy_iqcalibrate(priv, result, i); - - if (i == 1) { - simu = rtl8xxxu_gen2_simularity_compare(priv, result, 0, 1); - if (simu) { - candidate = 0; - break; - } - } - - if (i == 2) { - simu = rtl8xxxu_gen2_simularity_compare(priv, result, 0, 2); - if (simu) { - candidate = 0; - break; - } - - simu = rtl8xxxu_gen2_simularity_compare(priv, result, 1, 2); - if (simu) { - candidate = 1; - } else { - for (i = 0; i < 8; i++) - reg_tmp += result[3][i]; - - if (reg_tmp) - candidate = 3; - else - candidate = -1; - } - } - } - - for (i = 0; i < 4; i++) { - reg_e94 = result[i][0]; - reg_e9c = result[i][1]; - reg_ea4 = result[i][2]; - reg_eac = result[i][3]; - reg_eb4 = result[i][4]; - reg_ebc = result[i][5]; - reg_ec4 = result[i][6]; - reg_ecc = result[i][7]; - } - - if (candidate >= 0) { - reg_e94 = result[candidate][0]; - priv->rege94 = reg_e94; - reg_e9c = result[candidate][1]; - priv->rege9c = reg_e9c; - reg_ea4 = result[candidate][2]; - reg_eac = result[candidate][3]; - reg_eb4 = result[candidate][4]; - priv->regeb4 = reg_eb4; - reg_ebc = result[candidate][5]; - priv->regebc = reg_ebc; - reg_ec4 = result[candidate][6]; - reg_ecc = result[candidate][7]; - dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate); - dev_dbg(dev, - "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x ecc=%x\n", - __func__, reg_e94, reg_e9c, - reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc); - path_a_ok = true; - } else { - reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100; - reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0; - } - - if (reg_e94 && candidate >= 0) - rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result, - candidate, (reg_ea4 == 0)); - - rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg, - priv->bb_recovery_backup, RTL8XXXU_BB_REGS); - - rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel_bb); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, path_sel_rf); -} - -static void rtl8188f_disabled_to_emu(struct rtl8xxxu_priv *priv) -{ - u16 val8; - - /* 0x04[12:11] = 2b'01enable WL suspend */ - val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); - val8 &= ~((APS_FSMCO_PCIE | APS_FSMCO_HW_SUSPEND) >> 8); - rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); - - /* 0xC4[4] <= 1, turn off USB APHY LDO under suspend mode */ - val8 = rtl8xxxu_read8(priv, 0xc4); - val8 &= ~BIT(4); - rtl8xxxu_write8(priv, 0xc4, val8); -} - -static int rtl8188f_emu_to_active(struct rtl8xxxu_priv *priv) -{ - u8 val8; - u32 val32; - int count, ret = 0; - - /* Disable SW LPS */ - val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); - val8 &= ~(APS_FSMCO_SW_LPS >> 8); - rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); - - /* wait till 0x04[17] = 1 power ready */ - for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { - val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); - if (val32 & BIT(17)) - break; - - udelay(10); - } - - if (!count) { - ret = -EBUSY; - goto exit; - } - - /* Disable HWPDN */ - val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); - val8 &= ~(APS_FSMCO_HW_POWERDOWN >> 8); - rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); - - /* Disable WL suspend */ - val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); - val8 &= ~(APS_FSMCO_HW_SUSPEND >> 8); - rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); - - /* set, then poll until 0 */ - val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); - val8 |= APS_FSMCO_MAC_ENABLE >> 8; - rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); - - for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { - val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); - if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) { - ret = 0; - break; - } - udelay(10); - } - - if (!count) { - ret = -EBUSY; - goto exit; - } - - /* 0x27<=35 to reduce RF noise */ - val8 = rtl8xxxu_write8(priv, 0x27, 0x35); -exit: - return ret; -} - -static int rtl8188fu_active_to_emu(struct rtl8xxxu_priv *priv) -{ - u8 val8; - u32 val32; - int count, ret = 0; - - /* Turn off RF */ - rtl8xxxu_write8(priv, REG_RF_CTRL, 0); - - /* 0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */ - val8 = rtl8xxxu_read8(priv, 0x4e); - val8 &= ~BIT(7); - rtl8xxxu_write8(priv, 0x4e, val8); - - /* 0x27 <= 34, xtal_qsel = 0 to xtal bring up */ - rtl8xxxu_write8(priv, 0x27, 0x34); - - /* 0x04[9] = 1 turn off MAC by HW state machine */ - val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); - val8 |= APS_FSMCO_MAC_OFF >> 8; - rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); - - for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { - val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); - if ((val32 & APS_FSMCO_MAC_OFF) == 0) { - ret = 0; - break; - } - udelay(10); - } - - if (!count) { - ret = -EBUSY; - goto exit; - } - -exit: - return ret; -} - -static int rtl8188fu_emu_to_disabled(struct rtl8xxxu_priv *priv) -{ - u8 val8; - - /* 0x04[12:11] = 2b'01 enable WL suspend */ - val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); - val8 &= ~((APS_FSMCO_PCIE | APS_FSMCO_HW_SUSPEND) >> 8); - val8 |= APS_FSMCO_HW_SUSPEND >> 8; - rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); - - /* 0xC4[4] <= 1, turn off USB APHY LDO under suspend mode */ - val8 = rtl8xxxu_read8(priv, 0xc4); - val8 |= BIT(4); - rtl8xxxu_write8(priv, 0xc4, val8); - - return 0; -} - -static int rtl8188fu_active_to_lps(struct rtl8xxxu_priv *priv) -{ - struct device *dev = &priv->udev->dev; - u8 val8; - u16 val16; - u32 val32; - int retry, retval; - - /* set RPWM IMR */ - val8 = rtl8xxxu_read8(priv, REG_FTIMR + 1); - val8 |= IMR0_CPWM >> 8; - rtl8xxxu_write8(priv, REG_FTIMR + 1, val8); - - /* Tx Pause */ - rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); - - retry = 100; - retval = -EBUSY; - - /* - * Poll 32 bit wide REG_SCH_TX_CMD for 0x00000000 to ensure no TX is pending. - */ - do { - val32 = rtl8xxxu_read32(priv, REG_SCH_TX_CMD); - if (!val32) { - retval = 0; - break; - } - } while (retry--); - - if (!retry) { - dev_warn(dev, "Failed to flush TX queue\n"); - retval = -EBUSY; - goto out; - } - - /* Disable CCK and OFDM, clock gated */ - val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); - val8 &= ~SYS_FUNC_BBRSTB; - rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); - - udelay(2); - - /* Whole BB is reset */ - val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); - val8 &= ~SYS_FUNC_BB_GLB_RSTN; - rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); - - /* Reset MAC TRX */ - val16 = rtl8xxxu_read16(priv, REG_CR); - val16 |= 0x3f; - val16 &= ~(CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE | CR_SECURITY_ENABLE); - rtl8xxxu_write16(priv, REG_CR, val16); - - /* Respond TxOK to scheduler */ - val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST); - val8 |= DUAL_TSF_TX_OK; - rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8); - -out: - return retval; -} - -static int rtl8188fu_power_on(struct rtl8xxxu_priv *priv) -{ - u16 val16; - int ret; - - rtl8188f_disabled_to_emu(priv); - - ret = rtl8188f_emu_to_active(priv); - if (ret) - goto exit; - - rtl8xxxu_write8(priv, REG_CR, 0); - - val16 = rtl8xxxu_read16(priv, REG_CR); - - val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE | - CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | - CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE | - CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE); - rtl8xxxu_write16(priv, REG_CR, val16); - -exit: - return ret; -} - -static void rtl8188fu_power_off(struct rtl8xxxu_priv *priv) -{ - u8 val8; - u16 val16; - - rtl8xxxu_flush_fifo(priv); - - val16 = rtl8xxxu_read16(priv, REG_GPIO_MUXCFG); - val16 &= ~BIT(12); - rtl8xxxu_write16(priv, REG_GPIO_MUXCFG, val16); - - rtl8xxxu_write32(priv, REG_HISR0, 0xFFFFFFFF); - rtl8xxxu_write32(priv, REG_HISR1, 0xFFFFFFFF); - - /* Stop Tx Report Timer. 0x4EC[Bit1]=b'0 */ - val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL); - val8 &= ~TX_REPORT_CTRL_TIMER_ENABLE; - rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8); - - /* Turn off RF */ - rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00); - - /* Reset Firmware if running in RAM */ - if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL) - rtl8xxxu_firmware_self_reset(priv); - - rtl8188fu_active_to_lps(priv); - - /* Reset MCU */ - val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); - val16 &= ~SYS_FUNC_CPU_ENABLE; - rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); - - /* Reset MCU ready status */ - rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00); - - rtl8188fu_active_to_emu(priv); - rtl8188fu_emu_to_disabled(priv); -} - -#define PPG_BB_GAIN_2G_TXA_OFFSET_8188F 0xee -#define PPG_BB_GAIN_2G_TX_OFFSET_MASK 0x0f - -static void rtl8188f_enable_rf(struct rtl8xxxu_priv *priv) -{ - u32 val32; - u8 pg_pwrtrim = 0xff, val8; - s8 bb_gain; - - /* Somehow this is not found in the efuse we read earlier. */ - rtl8xxxu_read_efuse8(priv, PPG_BB_GAIN_2G_TXA_OFFSET_8188F, &pg_pwrtrim); - - if (pg_pwrtrim != 0xff) { - bb_gain = pg_pwrtrim & PPG_BB_GAIN_2G_TX_OFFSET_MASK; - - if (bb_gain == PPG_BB_GAIN_2G_TX_OFFSET_MASK) - bb_gain = 0; - else if (bb_gain & 1) - bb_gain = bb_gain >> 1; - else - bb_gain = -(bb_gain >> 1); - - val8 = abs(bb_gain); - if (bb_gain > 0) - val8 |= BIT(5); - - val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_55); - val32 &= ~0xfc000; - val32 |= val8 << 14; - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_55, val32); - } - - rtl8xxxu_write8(priv, REG_RF_CTRL, RF_ENABLE | RF_RSTB | RF_SDMRSTB); - - val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); - val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK); - val32 |= OFDM_RF_PATH_RX_A | OFDM_RF_PATH_TX_A; - rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); - - rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); -} - -static void rtl8188f_disable_rf(struct rtl8xxxu_priv *priv) -{ - u32 val32; - - val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); - val32 &= ~OFDM_RF_PATH_TX_MASK; - rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); - - /* Power down RF module */ - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0); -} - -static void rtl8188f_usb_quirks(struct rtl8xxxu_priv *priv) -{ - u16 val16; - u32 val32; - - val16 = rtl8xxxu_read16(priv, REG_CR); - val16 |= (CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE); - rtl8xxxu_write16(priv, REG_CR, val16); - - val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK); - val32 |= TXDMA_OFFSET_DROP_DATA_EN; - rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32); -} - -#define XTAL1 GENMASK(22, 17) -#define XTAL0 GENMASK(16, 11) - -void rtl8188f_set_crystal_cap(struct rtl8xxxu_priv *priv, u8 crystal_cap) -{ - struct rtl8xxxu_cfo_tracking *cfo = &priv->cfo_tracking; - u32 val32; - - if (crystal_cap == cfo->crystal_cap) - return; - - val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL); - - dev_dbg(&priv->udev->dev, - "%s: Adjusting crystal cap from 0x%x (actually 0x%lx 0x%lx) to 0x%x\n", - __func__, - cfo->crystal_cap, - FIELD_GET(XTAL1, val32), - FIELD_GET(XTAL0, val32), - crystal_cap); - - val32 &= ~(XTAL1 | XTAL0); - val32 |= FIELD_PREP(XTAL1, crystal_cap) | - FIELD_PREP(XTAL0, crystal_cap); - rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32); - - cfo->crystal_cap = crystal_cap; -} - -static s8 rtl8188f_cck_rssi(struct rtl8xxxu_priv *priv, struct rtl8723au_phy_stats *phy_stats) -{ - u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a; - s8 rx_pwr_all = 0x00; - u8 vga_idx, lna_idx; - - lna_idx = u8_get_bits(cck_agc_rpt, CCK_AGC_RPT_LNA_IDX_MASK); - vga_idx = u8_get_bits(cck_agc_rpt, CCK_AGC_RPT_VGA_IDX_MASK); - - switch (lna_idx) { - case 7: - if (vga_idx <= 27) - rx_pwr_all = -100 + 2 * (27 - vga_idx); - else - rx_pwr_all = -100; - break; - case 5: - rx_pwr_all = -74 + 2 * (21 - vga_idx); - break; - case 3: - rx_pwr_all = -60 + 2 * (20 - vga_idx); - break; - case 1: - rx_pwr_all = -44 + 2 * (19 - vga_idx); - break; - default: - break; - } - - return rx_pwr_all; -} - -struct rtl8xxxu_fileops rtl8188fu_fops = { - .identify_chip = rtl8188fu_identify_chip, - .parse_efuse = rtl8188fu_parse_efuse, - .load_firmware = rtl8188fu_load_firmware, - .power_on = rtl8188fu_power_on, - .power_off = rtl8188fu_power_off, - .read_efuse = rtl8xxxu_read_efuse, - .reset_8051 = rtl8xxxu_reset_8051, - .llt_init = rtl8xxxu_auto_llt_table, - .init_phy_bb = rtl8188fu_init_phy_bb, - .init_phy_rf = rtl8188fu_init_phy_rf, - .phy_init_antenna_selection = rtl8723bu_phy_init_antenna_selection, - .phy_lc_calibrate = rtl8188f_phy_lc_calibrate, - .phy_iq_calibrate = rtl8188fu_phy_iq_calibrate, - .config_channel = rtl8188fu_config_channel, - .parse_rx_desc = rtl8xxxu_parse_rxdesc24, - .parse_phystats = rtl8723au_rx_parse_phystats, - .init_aggregation = rtl8188fu_init_aggregation, - .init_statistics = rtl8188fu_init_statistics, - .init_burst = rtl8xxxu_init_burst, - .enable_rf = rtl8188f_enable_rf, - .disable_rf = rtl8188f_disable_rf, - .usb_quirks = rtl8188f_usb_quirks, - .set_tx_power = rtl8188f_set_tx_power, - .update_rate_mask = rtl8xxxu_gen2_update_rate_mask, - .report_connect = rtl8xxxu_gen2_report_connect, - .report_rssi = rtl8xxxu_gen2_report_rssi, - .fill_txdesc = rtl8xxxu_fill_txdesc_v2, - .set_crystal_cap = rtl8188f_set_crystal_cap, - .cck_rssi = rtl8188f_cck_rssi, - .writeN_block_size = 128, - .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc24), - .tx_desc_size = sizeof(struct rtl8xxxu_txdesc40), - .has_s0s1 = 1, - .has_tx_report = 1, - .gen2_thermal_meter = 1, - .needs_full_init = 1, - .init_reg_rxfltmap = 1, - .init_reg_pkt_life_time = 1, - .init_reg_hmtfr = 1, - .ampdu_max_time = 0x70, - .ustime_tsf_edca = 0x28, - .max_aggr_num = 0x0c14, - .supports_ap = 1, - .max_macid_num = 16, - .max_sec_cam_num = 16, - .supports_concurrent = 1, - .adda_1t_init = 0x03c00014, - .adda_1t_path_on = 0x03c00014, - .trxff_boundary = 0x3f7f, - .pbp_rx = PBP_PAGE_SIZE_256, - .pbp_tx = PBP_PAGE_SIZE_256, - .mactable = rtl8188f_mac_init_table, - .total_page_num = TX_TOTAL_PAGE_NUM_8188F, - .page_num_hi = TX_PAGE_NUM_HI_PQ_8188F, - .page_num_lo = TX_PAGE_NUM_LO_PQ_8188F, - .page_num_norm = TX_PAGE_NUM_NORM_PQ_8188F, -}; diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192c.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192c.c deleted file mode 100644 index 49eb1d0a6019..000000000000 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192c.c +++ /dev/null @@ -1,673 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * RTL8XXXU mac80211 USB driver - 8188c/8188r/8192c specific subdriver - * - * Copyright (c) 2014 - 2017 Jes Sorensen - * - * Portions, notably calibration code: - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This driver was written as a replacement for the vendor provided - * rtl8723au driver. As the Realtek 8xxx chips are very similar in - * their programming interface, I have started adding support for - * additional 8xxx chips like the 8192cu, 8188cus, etc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "rtl8xxxu.h" -#include "rtl8xxxu_regs.h" - -#ifdef CONFIG_RTL8XXXU_UNTESTED -static struct rtl8xxxu_power_base rtl8192c_power_base = { - .reg_0e00 = 0x07090c0c, - .reg_0e04 = 0x01020405, - .reg_0e08 = 0x00000000, - .reg_086c = 0x00000000, - - .reg_0e10 = 0x0b0c0c0e, - .reg_0e14 = 0x01030506, - .reg_0e18 = 0x0b0c0d0e, - .reg_0e1c = 0x01030509, - - .reg_0830 = 0x07090c0c, - .reg_0834 = 0x01020405, - .reg_0838 = 0x00000000, - .reg_086c_2 = 0x00000000, - - .reg_083c = 0x0b0c0d0e, - .reg_0848 = 0x01030509, - .reg_084c = 0x0b0c0d0e, - .reg_0868 = 0x01030509, -}; - -static struct rtl8xxxu_power_base rtl8188r_power_base = { - .reg_0e00 = 0x06080808, - .reg_0e04 = 0x00040406, - .reg_0e08 = 0x00000000, - .reg_086c = 0x00000000, - - .reg_0e10 = 0x04060608, - .reg_0e14 = 0x00020204, - .reg_0e18 = 0x04060608, - .reg_0e1c = 0x00020204, - - .reg_0830 = 0x06080808, - .reg_0834 = 0x00040406, - .reg_0838 = 0x00000000, - .reg_086c_2 = 0x00000000, - - .reg_083c = 0x04060608, - .reg_0848 = 0x00020204, - .reg_084c = 0x04060608, - .reg_0868 = 0x00020204, -}; - -static const struct rtl8xxxu_reg8val rtl8192cu_mac_init_table[] = { - {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00}, - {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05}, - {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00}, - {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05}, - {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01}, - {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f}, - {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72}, - {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08}, - {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff}, - {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2}, - {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3}, - {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4}, - {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4}, - {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a}, - {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16}, - {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00}, - {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02}, - {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a}, - {0x652, 0x20}, {0x652, 0x20}, {0x63c, 0x08}, {0x63d, 0x08}, - {0x63e, 0x0c}, {0x63f, 0x0c}, {0x66e, 0x05}, {0x700, 0x21}, - {0x701, 0x43}, {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, - {0x709, 0x43}, {0x70a, 0x65}, {0x70b, 0x87}, - {0xffff, 0xff}, -}; - -static const struct rtl8xxxu_rfregval rtl8192cu_radioa_2t_init_table[] = { - {0x00, 0x00030159}, {0x01, 0x00031284}, - {0x02, 0x00098000}, {0x03, 0x00018c63}, - {0x04, 0x000210e7}, {0x09, 0x0002044f}, - {0x0a, 0x0001adb1}, {0x0b, 0x00054867}, - {0x0c, 0x0008992e}, {0x0d, 0x0000e52c}, - {0x0e, 0x00039ce7}, {0x0f, 0x00000451}, - {0x19, 0x00000000}, {0x1a, 0x00010255}, - {0x1b, 0x00060a00}, {0x1c, 0x000fc378}, - {0x1d, 0x000a1250}, {0x1e, 0x0004445f}, - {0x1f, 0x00080001}, {0x20, 0x0000b614}, - {0x21, 0x0006c000}, {0x22, 0x00000000}, - {0x23, 0x00001558}, {0x24, 0x00000060}, - {0x25, 0x00000483}, {0x26, 0x0004f000}, - {0x27, 0x000ec7d9}, {0x28, 0x000577c0}, - {0x29, 0x00004783}, {0x2a, 0x00000001}, - {0x2b, 0x00021334}, {0x2a, 0x00000000}, - {0x2b, 0x00000054}, {0x2a, 0x00000001}, - {0x2b, 0x00000808}, {0x2b, 0x00053333}, - {0x2c, 0x0000000c}, {0x2a, 0x00000002}, - {0x2b, 0x00000808}, {0x2b, 0x0005b333}, - {0x2c, 0x0000000d}, {0x2a, 0x00000003}, - {0x2b, 0x00000808}, {0x2b, 0x00063333}, - {0x2c, 0x0000000d}, {0x2a, 0x00000004}, - {0x2b, 0x00000808}, {0x2b, 0x0006b333}, - {0x2c, 0x0000000d}, {0x2a, 0x00000005}, - {0x2b, 0x00000808}, {0x2b, 0x00073333}, - {0x2c, 0x0000000d}, {0x2a, 0x00000006}, - {0x2b, 0x00000709}, {0x2b, 0x0005b333}, - {0x2c, 0x0000000d}, {0x2a, 0x00000007}, - {0x2b, 0x00000709}, {0x2b, 0x00063333}, - {0x2c, 0x0000000d}, {0x2a, 0x00000008}, - {0x2b, 0x0000060a}, {0x2b, 0x0004b333}, - {0x2c, 0x0000000d}, {0x2a, 0x00000009}, - {0x2b, 0x0000060a}, {0x2b, 0x00053333}, - {0x2c, 0x0000000d}, {0x2a, 0x0000000a}, - {0x2b, 0x0000060a}, {0x2b, 0x0005b333}, - {0x2c, 0x0000000d}, {0x2a, 0x0000000b}, - {0x2b, 0x0000060a}, {0x2b, 0x00063333}, - {0x2c, 0x0000000d}, {0x2a, 0x0000000c}, - {0x2b, 0x0000060a}, {0x2b, 0x0006b333}, - {0x2c, 0x0000000d}, {0x2a, 0x0000000d}, - {0x2b, 0x0000060a}, {0x2b, 0x00073333}, - {0x2c, 0x0000000d}, {0x2a, 0x0000000e}, - {0x2b, 0x0000050b}, {0x2b, 0x00066666}, - {0x2c, 0x0000001a}, {0x2a, 0x000e0000}, - {0x10, 0x0004000f}, {0x11, 0x000e31fc}, - {0x10, 0x0006000f}, {0x11, 0x000ff9f8}, - {0x10, 0x0002000f}, {0x11, 0x000203f9}, - {0x10, 0x0003000f}, {0x11, 0x000ff500}, - {0x10, 0x00000000}, {0x11, 0x00000000}, - {0x10, 0x0008000f}, {0x11, 0x0003f100}, - {0x10, 0x0009000f}, {0x11, 0x00023100}, - {0x12, 0x00032000}, {0x12, 0x00071000}, - {0x12, 0x000b0000}, {0x12, 0x000fc000}, - {0x13, 0x000287b3}, {0x13, 0x000244b7}, - {0x13, 0x000204ab}, {0x13, 0x0001c49f}, - {0x13, 0x00018493}, {0x13, 0x0001429b}, - {0x13, 0x00010299}, {0x13, 0x0000c29c}, - {0x13, 0x000081a0}, {0x13, 0x000040ac}, - {0x13, 0x00000020}, {0x14, 0x0001944c}, - {0x14, 0x00059444}, {0x14, 0x0009944c}, - {0x14, 0x000d9444}, {0x15, 0x0000f424}, - {0x15, 0x0004f424}, {0x15, 0x0008f424}, - {0x15, 0x000cf424}, {0x16, 0x000e0330}, - {0x16, 0x000a0330}, {0x16, 0x00060330}, - {0x16, 0x00020330}, {0x00, 0x00010159}, - {0x18, 0x0000f401}, {0xfe, 0x00000000}, - {0xfe, 0x00000000}, {0x1f, 0x00080003}, - {0xfe, 0x00000000}, {0xfe, 0x00000000}, - {0x1e, 0x00044457}, {0x1f, 0x00080000}, - {0x00, 0x00030159}, - {0xff, 0xffffffff} -}; - -static const struct rtl8xxxu_rfregval rtl8192cu_radiob_2t_init_table[] = { - {0x00, 0x00030159}, {0x01, 0x00031284}, - {0x02, 0x00098000}, {0x03, 0x00018c63}, - {0x04, 0x000210e7}, {0x09, 0x0002044f}, - {0x0a, 0x0001adb1}, {0x0b, 0x00054867}, - {0x0c, 0x0008992e}, {0x0d, 0x0000e52c}, - {0x0e, 0x00039ce7}, {0x0f, 0x00000451}, - {0x12, 0x00032000}, {0x12, 0x00071000}, - {0x12, 0x000b0000}, {0x12, 0x000fc000}, - {0x13, 0x000287af}, {0x13, 0x000244b7}, - {0x13, 0x000204ab}, {0x13, 0x0001c49f}, - {0x13, 0x00018493}, {0x13, 0x00014297}, - {0x13, 0x00010295}, {0x13, 0x0000c298}, - {0x13, 0x0000819c}, {0x13, 0x000040a8}, - {0x13, 0x0000001c}, {0x14, 0x0001944c}, - {0x14, 0x00059444}, {0x14, 0x0009944c}, - {0x14, 0x000d9444}, {0x15, 0x0000f424}, - {0x15, 0x0004f424}, {0x15, 0x0008f424}, - {0x15, 0x000cf424}, {0x16, 0x000e0330}, - {0x16, 0x000a0330}, {0x16, 0x00060330}, - {0x16, 0x00020330}, - {0xff, 0xffffffff} -}; - -static const struct rtl8xxxu_rfregval rtl8192cu_radioa_1t_init_table[] = { - {0x00, 0x00030159}, {0x01, 0x00031284}, - {0x02, 0x00098000}, {0x03, 0x00018c63}, - {0x04, 0x000210e7}, {0x09, 0x0002044f}, - {0x0a, 0x0001adb1}, {0x0b, 0x00054867}, - {0x0c, 0x0008992e}, {0x0d, 0x0000e52c}, - {0x0e, 0x00039ce7}, {0x0f, 0x00000451}, - {0x19, 0x00000000}, {0x1a, 0x00010255}, - {0x1b, 0x00060a00}, {0x1c, 0x000fc378}, - {0x1d, 0x000a1250}, {0x1e, 0x0004445f}, - {0x1f, 0x00080001}, {0x20, 0x0000b614}, - {0x21, 0x0006c000}, {0x22, 0x00000000}, - {0x23, 0x00001558}, {0x24, 0x00000060}, - {0x25, 0x00000483}, {0x26, 0x0004f000}, - {0x27, 0x000ec7d9}, {0x28, 0x000577c0}, - {0x29, 0x00004783}, {0x2a, 0x00000001}, - {0x2b, 0x00021334}, {0x2a, 0x00000000}, - {0x2b, 0x00000054}, {0x2a, 0x00000001}, - {0x2b, 0x00000808}, {0x2b, 0x00053333}, - {0x2c, 0x0000000c}, {0x2a, 0x00000002}, - {0x2b, 0x00000808}, {0x2b, 0x0005b333}, - {0x2c, 0x0000000d}, {0x2a, 0x00000003}, - {0x2b, 0x00000808}, {0x2b, 0x00063333}, - {0x2c, 0x0000000d}, {0x2a, 0x00000004}, - {0x2b, 0x00000808}, {0x2b, 0x0006b333}, - {0x2c, 0x0000000d}, {0x2a, 0x00000005}, - {0x2b, 0x00000808}, {0x2b, 0x00073333}, - {0x2c, 0x0000000d}, {0x2a, 0x00000006}, - {0x2b, 0x00000709}, {0x2b, 0x0005b333}, - {0x2c, 0x0000000d}, {0x2a, 0x00000007}, - {0x2b, 0x00000709}, {0x2b, 0x00063333}, - {0x2c, 0x0000000d}, {0x2a, 0x00000008}, - {0x2b, 0x0000060a}, {0x2b, 0x0004b333}, - {0x2c, 0x0000000d}, {0x2a, 0x00000009}, - {0x2b, 0x0000060a}, {0x2b, 0x00053333}, - {0x2c, 0x0000000d}, {0x2a, 0x0000000a}, - {0x2b, 0x0000060a}, {0x2b, 0x0005b333}, - {0x2c, 0x0000000d}, {0x2a, 0x0000000b}, - {0x2b, 0x0000060a}, {0x2b, 0x00063333}, - {0x2c, 0x0000000d}, {0x2a, 0x0000000c}, - {0x2b, 0x0000060a}, {0x2b, 0x0006b333}, - {0x2c, 0x0000000d}, {0x2a, 0x0000000d}, - {0x2b, 0x0000060a}, {0x2b, 0x00073333}, - {0x2c, 0x0000000d}, {0x2a, 0x0000000e}, - {0x2b, 0x0000050b}, {0x2b, 0x00066666}, - {0x2c, 0x0000001a}, {0x2a, 0x000e0000}, - {0x10, 0x0004000f}, {0x11, 0x000e31fc}, - {0x10, 0x0006000f}, {0x11, 0x000ff9f8}, - {0x10, 0x0002000f}, {0x11, 0x000203f9}, - {0x10, 0x0003000f}, {0x11, 0x000ff500}, - {0x10, 0x00000000}, {0x11, 0x00000000}, - {0x10, 0x0008000f}, {0x11, 0x0003f100}, - {0x10, 0x0009000f}, {0x11, 0x00023100}, - {0x12, 0x00032000}, {0x12, 0x00071000}, - {0x12, 0x000b0000}, {0x12, 0x000fc000}, - {0x13, 0x000287b3}, {0x13, 0x000244b7}, - {0x13, 0x000204ab}, {0x13, 0x0001c49f}, - {0x13, 0x00018493}, {0x13, 0x0001429b}, - {0x13, 0x00010299}, {0x13, 0x0000c29c}, - {0x13, 0x000081a0}, {0x13, 0x000040ac}, - {0x13, 0x00000020}, {0x14, 0x0001944c}, - {0x14, 0x00059444}, {0x14, 0x0009944c}, - {0x14, 0x000d9444}, {0x15, 0x0000f405}, - {0x15, 0x0004f405}, {0x15, 0x0008f405}, - {0x15, 0x000cf405}, {0x16, 0x000e0330}, - {0x16, 0x000a0330}, {0x16, 0x00060330}, - {0x16, 0x00020330}, {0x00, 0x00010159}, - {0x18, 0x0000f401}, {0xfe, 0x00000000}, - {0xfe, 0x00000000}, {0x1f, 0x00080003}, - {0xfe, 0x00000000}, {0xfe, 0x00000000}, - {0x1e, 0x00044457}, {0x1f, 0x00080000}, - {0x00, 0x00030159}, - {0xff, 0xffffffff} -}; - -static const struct rtl8xxxu_rfregval rtl8188ru_radioa_1t_highpa_table[] = { - {0x00, 0x00030159}, {0x01, 0x00031284}, - {0x02, 0x00098000}, {0x03, 0x00018c63}, - {0x04, 0x000210e7}, {0x09, 0x0002044f}, - {0x0a, 0x0001adb0}, {0x0b, 0x00054867}, - {0x0c, 0x0008992e}, {0x0d, 0x0000e529}, - {0x0e, 0x00039ce7}, {0x0f, 0x00000451}, - {0x19, 0x00000000}, {0x1a, 0x00000255}, - {0x1b, 0x00060a00}, {0x1c, 0x000fc378}, - {0x1d, 0x000a1250}, {0x1e, 0x0004445f}, - {0x1f, 0x00080001}, {0x20, 0x0000b614}, - {0x21, 0x0006c000}, {0x22, 0x0000083c}, - {0x23, 0x00001558}, {0x24, 0x00000060}, - {0x25, 0x00000483}, {0x26, 0x0004f000}, - {0x27, 0x000ec7d9}, {0x28, 0x000977c0}, - {0x29, 0x00004783}, {0x2a, 0x00000001}, - {0x2b, 0x00021334}, {0x2a, 0x00000000}, - {0x2b, 0x00000054}, {0x2a, 0x00000001}, - {0x2b, 0x00000808}, {0x2b, 0x00053333}, - {0x2c, 0x0000000c}, {0x2a, 0x00000002}, - {0x2b, 0x00000808}, {0x2b, 0x0005b333}, - {0x2c, 0x0000000d}, {0x2a, 0x00000003}, - {0x2b, 0x00000808}, {0x2b, 0x00063333}, - {0x2c, 0x0000000d}, {0x2a, 0x00000004}, - {0x2b, 0x00000808}, {0x2b, 0x0006b333}, - {0x2c, 0x0000000d}, {0x2a, 0x00000005}, - {0x2b, 0x00000808}, {0x2b, 0x00073333}, - {0x2c, 0x0000000d}, {0x2a, 0x00000006}, - {0x2b, 0x00000709}, {0x2b, 0x0005b333}, - {0x2c, 0x0000000d}, {0x2a, 0x00000007}, - {0x2b, 0x00000709}, {0x2b, 0x00063333}, - {0x2c, 0x0000000d}, {0x2a, 0x00000008}, - {0x2b, 0x0000060a}, {0x2b, 0x0004b333}, - {0x2c, 0x0000000d}, {0x2a, 0x00000009}, - {0x2b, 0x0000060a}, {0x2b, 0x00053333}, - {0x2c, 0x0000000d}, {0x2a, 0x0000000a}, - {0x2b, 0x0000060a}, {0x2b, 0x0005b333}, - {0x2c, 0x0000000d}, {0x2a, 0x0000000b}, - {0x2b, 0x0000060a}, {0x2b, 0x00063333}, - {0x2c, 0x0000000d}, {0x2a, 0x0000000c}, - {0x2b, 0x0000060a}, {0x2b, 0x0006b333}, - {0x2c, 0x0000000d}, {0x2a, 0x0000000d}, - {0x2b, 0x0000060a}, {0x2b, 0x00073333}, - {0x2c, 0x0000000d}, {0x2a, 0x0000000e}, - {0x2b, 0x0000050b}, {0x2b, 0x00066666}, - {0x2c, 0x0000001a}, {0x2a, 0x000e0000}, - {0x10, 0x0004000f}, {0x11, 0x000e31fc}, - {0x10, 0x0006000f}, {0x11, 0x000ff9f8}, - {0x10, 0x0002000f}, {0x11, 0x000203f9}, - {0x10, 0x0003000f}, {0x11, 0x000ff500}, - {0x10, 0x00000000}, {0x11, 0x00000000}, - {0x10, 0x0008000f}, {0x11, 0x0003f100}, - {0x10, 0x0009000f}, {0x11, 0x00023100}, - {0x12, 0x000d8000}, {0x12, 0x00090000}, - {0x12, 0x00051000}, {0x12, 0x00012000}, - {0x13, 0x00028fb4}, {0x13, 0x00024fa8}, - {0x13, 0x000207a4}, {0x13, 0x0001c3b0}, - {0x13, 0x000183a4}, {0x13, 0x00014398}, - {0x13, 0x000101a4}, {0x13, 0x0000c198}, - {0x13, 0x000080a4}, {0x13, 0x00004098}, - {0x13, 0x00000000}, {0x14, 0x0001944c}, - {0x14, 0x00059444}, {0x14, 0x0009944c}, - {0x14, 0x000d9444}, {0x15, 0x0000f405}, - {0x15, 0x0004f405}, {0x15, 0x0008f405}, - {0x15, 0x000cf405}, {0x16, 0x000e0330}, - {0x16, 0x000a0330}, {0x16, 0x00060330}, - {0x16, 0x00020330}, {0x00, 0x00010159}, - {0x18, 0x0000f401}, {0xfe, 0x00000000}, - {0xfe, 0x00000000}, {0x1f, 0x00080003}, - {0xfe, 0x00000000}, {0xfe, 0x00000000}, - {0x1e, 0x00044457}, {0x1f, 0x00080000}, - {0x00, 0x00030159}, - {0xff, 0xffffffff} -}; - -static int rtl8192cu_identify_chip(struct rtl8xxxu_priv *priv) -{ - struct device *dev = &priv->udev->dev; - u32 val32, bonding, sys_cfg, vendor; - int ret = 0; - - sys_cfg = rtl8xxxu_read32(priv, REG_SYS_CFG); - priv->chip_cut = u32_get_bits(sys_cfg, SYS_CFG_CHIP_VERSION_MASK); - if (sys_cfg & SYS_CFG_TRP_VAUX_EN) { - dev_info(dev, "Unsupported test chip\n"); - ret = -ENOTSUPP; - goto out; - } - - if (sys_cfg & SYS_CFG_TYPE_ID) { - bonding = rtl8xxxu_read32(priv, REG_HPON_FSM); - bonding &= HPON_FSM_BONDING_MASK; - if (bonding == HPON_FSM_BONDING_1T2R) { - strscpy(priv->chip_name, "8191CU", sizeof(priv->chip_name)); - priv->tx_paths = 1; - priv->usb_interrupts = 1; - priv->rtl_chip = RTL8191C; - } else { - strscpy(priv->chip_name, "8192CU", sizeof(priv->chip_name)); - priv->tx_paths = 2; - priv->usb_interrupts = 0; - priv->rtl_chip = RTL8192C; - } - priv->rf_paths = 2; - priv->rx_paths = 2; - } else { - strscpy(priv->chip_name, "8188CU", sizeof(priv->chip_name)); - priv->rf_paths = 1; - priv->rx_paths = 1; - priv->tx_paths = 1; - priv->rtl_chip = RTL8188C; - priv->usb_interrupts = 0; - } - priv->has_wifi = 1; - - vendor = sys_cfg & SYS_CFG_VENDOR_ID; - rtl8xxxu_identify_vendor_1bit(priv, vendor); - - val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS); - priv->rom_rev = u32_get_bits(val32, GPIO_RF_RL_ID); - - rtl8xxxu_config_endpoints_sie(priv); - - /* - * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX - */ - if (!priv->ep_tx_count) - ret = rtl8xxxu_config_endpoints_no_sie(priv); - -out: - return ret; -} - -static int rtl8192cu_load_firmware(struct rtl8xxxu_priv *priv) -{ - const char *fw_name; - int ret; - - if (!priv->vendor_umc) - fw_name = "rtlwifi/rtl8192cufw_TMSC.bin"; - else if (priv->chip_cut || priv->rtl_chip == RTL8192C) - fw_name = "rtlwifi/rtl8192cufw_B.bin"; - else - fw_name = "rtlwifi/rtl8192cufw_A.bin"; - - ret = rtl8xxxu_load_firmware(priv, fw_name); - - return ret; -} - -static int rtl8192cu_parse_efuse(struct rtl8xxxu_priv *priv) -{ - struct rtl8192cu_efuse *efuse = &priv->efuse_wifi.efuse8192; - - if (efuse->rtl_id != cpu_to_le16(0x8129)) - return -EINVAL; - - ether_addr_copy(priv->mac_addr, efuse->mac_addr); - - memcpy(priv->cck_tx_power_index_A, - efuse->cck_tx_power_index_A, - sizeof(efuse->cck_tx_power_index_A)); - memcpy(priv->cck_tx_power_index_B, - efuse->cck_tx_power_index_B, - sizeof(efuse->cck_tx_power_index_B)); - - memcpy(priv->ht40_1s_tx_power_index_A, - efuse->ht40_1s_tx_power_index_A, - sizeof(efuse->ht40_1s_tx_power_index_A)); - memcpy(priv->ht40_1s_tx_power_index_B, - efuse->ht40_1s_tx_power_index_B, - sizeof(efuse->ht40_1s_tx_power_index_B)); - memcpy(priv->ht40_2s_tx_power_index_diff, - efuse->ht40_2s_tx_power_index_diff, - sizeof(efuse->ht40_2s_tx_power_index_diff)); - - memcpy(priv->ht20_tx_power_index_diff, - efuse->ht20_tx_power_index_diff, - sizeof(efuse->ht20_tx_power_index_diff)); - memcpy(priv->ofdm_tx_power_index_diff, - efuse->ofdm_tx_power_index_diff, - sizeof(efuse->ofdm_tx_power_index_diff)); - - memcpy(priv->ht40_max_power_offset, - efuse->ht40_max_power_offset, - sizeof(efuse->ht40_max_power_offset)); - memcpy(priv->ht20_max_power_offset, - efuse->ht20_max_power_offset, - sizeof(efuse->ht20_max_power_offset)); - - priv->power_base = &rtl8192c_power_base; - - if (efuse->rf_regulatory & 0x20) { - strscpy(priv->chip_name, "8188RU", sizeof(priv->chip_name)); - priv->rtl_chip = RTL8188R; - priv->hi_pa = 1; - priv->no_pape = 1; - priv->power_base = &rtl8188r_power_base; - } - - return 0; -} - -static int rtl8192cu_init_phy_rf(struct rtl8xxxu_priv *priv) -{ - const struct rtl8xxxu_rfregval *rftable; - int ret; - - if (priv->rtl_chip == RTL8188R) { - rftable = rtl8188ru_radioa_1t_highpa_table; - ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A); - } else if (priv->rf_paths == 1) { - rftable = rtl8192cu_radioa_1t_init_table; - ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A); - } else { - rftable = rtl8192cu_radioa_2t_init_table; - ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A); - if (ret) - goto exit; - rftable = rtl8192cu_radiob_2t_init_table; - ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_B); - } - -exit: - return ret; -} - -static int rtl8192cu_power_on(struct rtl8xxxu_priv *priv) -{ - u8 val8; - u16 val16; - u32 val32; - int i; - - for (i = 100; i; i--) { - val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO); - if (val8 & APS_FSMCO_PFM_ALDN) - break; - } - - if (!i) { - pr_info("%s: Poll failed\n", __func__); - return -ENODEV; - } - - /* - * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register - */ - rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0); - rtl8xxxu_write8(priv, REG_SPS0_CTRL, 0x2b); - udelay(100); - - val8 = rtl8xxxu_read8(priv, REG_LDOV12D_CTRL); - if (!(val8 & LDOV12D_ENABLE)) { - pr_info("%s: Enabling LDOV12D (%02x)\n", __func__, val8); - val8 |= LDOV12D_ENABLE; - rtl8xxxu_write8(priv, REG_LDOV12D_CTRL, val8); - - udelay(100); - - val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL); - val8 &= ~SYS_ISO_MD2PP; - rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8); - } - - /* - * Auto enable WLAN - */ - val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO); - val16 |= APS_FSMCO_MAC_ENABLE; - rtl8xxxu_write16(priv, REG_APS_FSMCO, val16); - - for (i = 1000; i; i--) { - val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO); - if (!(val16 & APS_FSMCO_MAC_ENABLE)) - break; - } - if (!i) { - pr_info("%s: FSMCO_MAC_ENABLE poll failed\n", __func__); - return -EBUSY; - } - - /* - * Enable radio, GPIO, LED - */ - val16 = APS_FSMCO_HW_SUSPEND | APS_FSMCO_ENABLE_POWERDOWN | - APS_FSMCO_PFM_ALDN; - rtl8xxxu_write16(priv, REG_APS_FSMCO, val16); - - /* - * Release RF digital isolation - */ - val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL); - val16 &= ~SYS_ISO_DIOR; - rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16); - - val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL); - val8 &= ~APSD_CTRL_OFF; - rtl8xxxu_write8(priv, REG_APSD_CTRL, val8); - for (i = 200; i; i--) { - val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL); - if (!(val8 & APSD_CTRL_OFF_STATUS)) - break; - } - - if (!i) { - pr_info("%s: APSD_CTRL poll failed\n", __func__); - return -EBUSY; - } - - /* - * Enable MAC DMA/WMAC/SCHEDULE/SEC block - */ - val16 = rtl8xxxu_read16(priv, REG_CR); - val16 |= CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE | - CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | CR_PROTOCOL_ENABLE | - CR_SCHEDULE_ENABLE | CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE; - rtl8xxxu_write16(priv, REG_CR, val16); - - rtl8xxxu_write8(priv, 0xfe10, 0x19); - - /* - * Workaround for 8188RU LNA power leakage problem. - */ - if (priv->rtl_chip == RTL8188R) { - val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM); - val32 &= ~BIT(1); - rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32); - } - return 0; -} - -static int rtl8192cu_led_brightness_set(struct led_classdev *led_cdev, - enum led_brightness brightness) -{ - struct rtl8xxxu_priv *priv = container_of(led_cdev, - struct rtl8xxxu_priv, - led_cdev); - u8 ledcfg = rtl8xxxu_read8(priv, REG_LEDCFG0); - - if (brightness == LED_OFF) - ledcfg = LEDCFG2_SW_LED_CONTROL | LEDCFG2_SW_LED_DISABLE; - else if (brightness == LED_ON) - ledcfg = LEDCFG2_SW_LED_CONTROL; - else if (brightness == RTL8XXXU_HW_LED_CONTROL) - ledcfg = LEDCFG2_HW_LED_CONTROL | LEDCFG2_HW_LED_ENABLE; - - rtl8xxxu_write8(priv, REG_LEDCFG0, ledcfg); - - return 0; -} - -struct rtl8xxxu_fileops rtl8192cu_fops = { - .identify_chip = rtl8192cu_identify_chip, - .parse_efuse = rtl8192cu_parse_efuse, - .load_firmware = rtl8192cu_load_firmware, - .power_on = rtl8192cu_power_on, - .power_off = rtl8xxxu_power_off, - .read_efuse = rtl8xxxu_read_efuse, - .reset_8051 = rtl8xxxu_reset_8051, - .llt_init = rtl8xxxu_init_llt_table, - .init_phy_bb = rtl8xxxu_gen1_init_phy_bb, - .init_phy_rf = rtl8192cu_init_phy_rf, - .phy_lc_calibrate = rtl8723a_phy_lc_calibrate, - .phy_iq_calibrate = rtl8xxxu_gen1_phy_iq_calibrate, - .config_channel = rtl8xxxu_gen1_config_channel, - .parse_rx_desc = rtl8xxxu_parse_rxdesc16, - .parse_phystats = rtl8723au_rx_parse_phystats, - .init_aggregation = rtl8xxxu_gen1_init_aggregation, - .enable_rf = rtl8xxxu_gen1_enable_rf, - .disable_rf = rtl8xxxu_gen1_disable_rf, - .usb_quirks = rtl8xxxu_gen1_usb_quirks, - .set_tx_power = rtl8xxxu_gen1_set_tx_power, - .update_rate_mask = rtl8xxxu_update_rate_mask, - .report_connect = rtl8xxxu_gen1_report_connect, - .report_rssi = rtl8xxxu_gen1_report_rssi, - .fill_txdesc = rtl8xxxu_fill_txdesc_v1, - .cck_rssi = rtl8723a_cck_rssi, - .led_classdev_brightness_set = rtl8192cu_led_brightness_set, - .writeN_block_size = 128, - .rx_agg_buf_size = 16000, - .tx_desc_size = sizeof(struct rtl8xxxu_txdesc32), - .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc16), - .max_sec_cam_num = 32, - .adda_1t_init = 0x0b1b25a0, - .adda_1t_path_on = 0x0bdb25a0, - .adda_2t_path_on_a = 0x04db25a4, - .adda_2t_path_on_b = 0x0b1b25a4, - .trxff_boundary = 0x27ff, - .pbp_rx = PBP_PAGE_SIZE_128, - .pbp_tx = PBP_PAGE_SIZE_128, - .mactable = rtl8192cu_mac_init_table, - .total_page_num = TX_TOTAL_PAGE_NUM, - .page_num_hi = TX_PAGE_NUM_HI_PQ, - .page_num_lo = TX_PAGE_NUM_LO_PQ, - .page_num_norm = TX_PAGE_NUM_NORM_PQ, -}; -#endif diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c deleted file mode 100644 index 26132b6b9331..000000000000 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c +++ /dev/null @@ -1,1779 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * RTL8XXXU mac80211 USB driver - 8192e specific subdriver - * - * Copyright (c) 2014 - 2017 Jes Sorensen - * - * Portions, notably calibration code: - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This driver was written as a replacement for the vendor provided - * rtl8723au driver. As the Realtek 8xxx chips are very similar in - * their programming interface, I have started adding support for - * additional 8xxx chips like the 8192cu, 8188cus, etc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "rtl8xxxu.h" -#include "rtl8xxxu_regs.h" - -static const struct rtl8xxxu_reg8val rtl8192e_mac_init_table[] = { - {0x011, 0xeb}, {0x012, 0x07}, {0x014, 0x75}, {0x303, 0xa7}, - {0x428, 0x0a}, {0x429, 0x10}, {0x430, 0x00}, {0x431, 0x00}, - {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05}, - {0x436, 0x07}, {0x437, 0x08}, {0x43c, 0x04}, {0x43d, 0x05}, - {0x43e, 0x07}, {0x43f, 0x08}, {0x440, 0x5d}, {0x441, 0x01}, - {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, {0x446, 0x00}, - {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xf0}, {0x44a, 0x0f}, - {0x44b, 0x3e}, {0x44c, 0x10}, {0x44d, 0x00}, {0x44e, 0x00}, - {0x44f, 0x00}, {0x450, 0x00}, {0x451, 0xf0}, {0x452, 0x0f}, - {0x453, 0x00}, {0x456, 0x5e}, {0x460, 0x66}, {0x461, 0x66}, - {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff}, {0x4cd, 0xff}, - {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2}, {0x502, 0x2f}, - {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3}, {0x506, 0x5e}, - {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4}, {0x50a, 0x5e}, - {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4}, {0x50e, 0x00}, - {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a}, {0x516, 0x0a}, - {0x525, 0x4f}, {0x540, 0x12}, {0x541, 0x64}, {0x550, 0x10}, - {0x551, 0x10}, {0x559, 0x02}, {0x55c, 0x50}, {0x55d, 0xff}, - {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a}, {0x620, 0xff}, - {0x621, 0xff}, {0x622, 0xff}, {0x623, 0xff}, {0x624, 0xff}, - {0x625, 0xff}, {0x626, 0xff}, {0x627, 0xff}, {0x638, 0x50}, - {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e}, {0x63f, 0x0e}, - {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00}, {0x652, 0xc8}, - {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43}, {0x702, 0x65}, - {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43}, {0x70a, 0x65}, - {0x70b, 0x87}, - {0xffff, 0xff}, -}; - -static const struct rtl8xxxu_reg32val rtl8192eu_phy_init_table[] = { - {0x800, 0x80040000}, {0x804, 0x00000003}, - {0x808, 0x0000fc00}, {0x80c, 0x0000000a}, - {0x810, 0x10001331}, {0x814, 0x020c3d10}, - {0x818, 0x02220385}, {0x81c, 0x00000000}, - {0x820, 0x01000100}, {0x824, 0x00390204}, - {0x828, 0x01000100}, {0x82c, 0x00390204}, - {0x830, 0x32323232}, {0x834, 0x30303030}, - {0x838, 0x30303030}, {0x83c, 0x30303030}, - {0x840, 0x00010000}, {0x844, 0x00010000}, - {0x848, 0x28282828}, {0x84c, 0x28282828}, - {0x850, 0x00000000}, {0x854, 0x00000000}, - {0x858, 0x009a009a}, {0x85c, 0x01000014}, - {0x860, 0x66f60000}, {0x864, 0x061f0000}, - {0x868, 0x30303030}, {0x86c, 0x30303030}, - {0x870, 0x00000000}, {0x874, 0x55004200}, - {0x878, 0x08080808}, {0x87c, 0x00000000}, - {0x880, 0xb0000c1c}, {0x884, 0x00000001}, - {0x888, 0x00000000}, {0x88c, 0xcc0000c0}, - {0x890, 0x00000800}, {0x894, 0xfffffffe}, - {0x898, 0x40302010}, {0x900, 0x00000000}, - {0x904, 0x00000023}, {0x908, 0x00000000}, - {0x90c, 0x81121313}, {0x910, 0x806c0001}, - {0x914, 0x00000001}, {0x918, 0x00000000}, - {0x91c, 0x00010000}, {0x924, 0x00000001}, - {0x928, 0x00000000}, {0x92c, 0x00000000}, - {0x930, 0x00000000}, {0x934, 0x00000000}, - {0x938, 0x00000000}, {0x93c, 0x00000000}, - {0x940, 0x00000000}, {0x944, 0x00000000}, - {0x94c, 0x00000008}, {0xa00, 0x00d0c7c8}, - {0xa04, 0x81ff000c}, {0xa08, 0x8c838300}, - {0xa0c, 0x2e68120f}, {0xa10, 0x95009b78}, - {0xa14, 0x1114d028}, {0xa18, 0x00881117}, - {0xa1c, 0x89140f00}, {0xa20, 0x1a1b0000}, - {0xa24, 0x090e1317}, {0xa28, 0x00000204}, - {0xa2c, 0x00d30000}, {0xa70, 0x101fff00}, - {0xa74, 0x00000007}, {0xa78, 0x00000900}, - {0xa7c, 0x225b0606}, {0xa80, 0x218075b1}, - {0xb38, 0x00000000}, {0xc00, 0x48071d40}, - {0xc04, 0x03a05633}, {0xc08, 0x000000e4}, - {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000}, - {0xc14, 0x40000100}, {0xc18, 0x08800000}, - {0xc1c, 0x40000100}, {0xc20, 0x00000000}, - {0xc24, 0x00000000}, {0xc28, 0x00000000}, - {0xc2c, 0x00000000}, {0xc30, 0x69e9ac47}, - {0xc34, 0x469652af}, {0xc38, 0x49795994}, - {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f}, - {0xc44, 0x000100b7}, {0xc48, 0xec020107}, - {0xc4c, 0x007f037f}, -#ifdef EXT_PA_8192EU - /* External PA or external LNA */ - {0xc50, 0x00340220}, -#else - {0xc50, 0x00340020}, -#endif - {0xc54, 0x0080801f}, -#ifdef EXT_PA_8192EU - /* External PA or external LNA */ - {0xc58, 0x00000220}, -#else - {0xc58, 0x00000020}, -#endif - {0xc5c, 0x00248492}, {0xc60, 0x00000000}, - {0xc64, 0x7112848b}, {0xc68, 0x47c00bff}, - {0xc6c, 0x00000036}, {0xc70, 0x00000600}, - {0xc74, 0x02013169}, {0xc78, 0x0000001f}, - {0xc7c, 0x00b91612}, -#ifdef EXT_PA_8192EU - /* External PA or external LNA */ - {0xc80, 0x2d4000b5}, -#else - {0xc80, 0x40000100}, -#endif - {0xc84, 0x21f60000}, -#ifdef EXT_PA_8192EU - /* External PA or external LNA */ - {0xc88, 0x2d4000b5}, -#else - {0xc88, 0x40000100}, -#endif - {0xc8c, 0xa0e40000}, {0xc90, 0x00121820}, - {0xc94, 0x00000000}, {0xc98, 0x00121820}, - {0xc9c, 0x00007f7f}, {0xca0, 0x00000000}, - {0xca4, 0x000300a0}, {0xca8, 0x00000000}, - {0xcac, 0x00000000}, {0xcb0, 0x00000000}, - {0xcb4, 0x00000000}, {0xcb8, 0x00000000}, - {0xcbc, 0x28000000}, {0xcc0, 0x00000000}, - {0xcc4, 0x00000000}, {0xcc8, 0x00000000}, - {0xccc, 0x00000000}, {0xcd0, 0x00000000}, - {0xcd4, 0x00000000}, {0xcd8, 0x64b22427}, - {0xcdc, 0x00766932}, {0xce0, 0x00222222}, - {0xce4, 0x00040000}, {0xce8, 0x77644302}, - {0xcec, 0x2f97d40c}, {0xd00, 0x00080740}, - {0xd04, 0x00020403}, {0xd08, 0x0000907f}, - {0xd0c, 0x20010201}, {0xd10, 0xa0633333}, - {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b}, - {0xd1c, 0x0000007f}, {0xd2c, 0xcc979975}, - {0xd30, 0x00000000}, {0xd34, 0x80608000}, - {0xd38, 0x00000000}, {0xd3c, 0x00127353}, - {0xd40, 0x00000000}, {0xd44, 0x00000000}, - {0xd48, 0x00000000}, {0xd4c, 0x00000000}, - {0xd50, 0x6437140a}, {0xd54, 0x00000000}, - {0xd58, 0x00000282}, {0xd5c, 0x30032064}, - {0xd60, 0x4653de68}, {0xd64, 0x04518a3c}, - {0xd68, 0x00002101}, {0xd6c, 0x2a201c16}, - {0xd70, 0x1812362e}, {0xd74, 0x322c2220}, - {0xd78, 0x000e3c24}, {0xd80, 0x01081008}, - {0xd84, 0x00000800}, {0xd88, 0xf0b50000}, - {0xe00, 0x30303030}, {0xe04, 0x30303030}, - {0xe08, 0x03903030}, {0xe10, 0x30303030}, - {0xe14, 0x30303030}, {0xe18, 0x30303030}, - {0xe1c, 0x30303030}, {0xe28, 0x00000000}, - {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f}, - {0xe38, 0x02140102}, {0xe3c, 0x681604c2}, - {0xe40, 0x01007c00}, {0xe44, 0x01004800}, - {0xe48, 0xfb000000}, {0xe4c, 0x000028d1}, - {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f}, - {0xe58, 0x02140102}, {0xe5c, 0x28160d05}, - {0xe60, 0x00000008}, {0xe68, 0x0fc05656}, - {0xe6c, 0x03c09696}, {0xe70, 0x03c09696}, - {0xe74, 0x0c005656}, {0xe78, 0x0c005656}, - {0xe7c, 0x0c005656}, {0xe80, 0x0c005656}, - {0xe84, 0x03c09696}, {0xe88, 0x0c005656}, - {0xe8c, 0x03c09696}, {0xed0, 0x03c09696}, - {0xed4, 0x03c09696}, {0xed8, 0x03c09696}, - {0xedc, 0x0000d6d6}, {0xee0, 0x0000d6d6}, - {0xeec, 0x0fc01616}, {0xee4, 0xb0000c1c}, - {0xee8, 0x00000001}, {0xf14, 0x00000003}, - {0xf4c, 0x00000000}, {0xf00, 0x00000300}, - {0xffff, 0xffffffff}, -}; - -static const struct rtl8xxxu_reg32val rtl8xxx_agc_8192eu_std_table[] = { - {0xc78, 0xfb000001}, {0xc78, 0xfb010001}, - {0xc78, 0xfb020001}, {0xc78, 0xfb030001}, - {0xc78, 0xfb040001}, {0xc78, 0xfb050001}, - {0xc78, 0xfa060001}, {0xc78, 0xf9070001}, - {0xc78, 0xf8080001}, {0xc78, 0xf7090001}, - {0xc78, 0xf60a0001}, {0xc78, 0xf50b0001}, - {0xc78, 0xf40c0001}, {0xc78, 0xf30d0001}, - {0xc78, 0xf20e0001}, {0xc78, 0xf10f0001}, - {0xc78, 0xf0100001}, {0xc78, 0xef110001}, - {0xc78, 0xee120001}, {0xc78, 0xed130001}, - {0xc78, 0xec140001}, {0xc78, 0xeb150001}, - {0xc78, 0xea160001}, {0xc78, 0xe9170001}, - {0xc78, 0xe8180001}, {0xc78, 0xe7190001}, - {0xc78, 0xc81a0001}, {0xc78, 0xc71b0001}, - {0xc78, 0xc61c0001}, {0xc78, 0x071d0001}, - {0xc78, 0x061e0001}, {0xc78, 0x051f0001}, - {0xc78, 0x04200001}, {0xc78, 0x03210001}, - {0xc78, 0xaa220001}, {0xc78, 0xa9230001}, - {0xc78, 0xa8240001}, {0xc78, 0xa7250001}, - {0xc78, 0xa6260001}, {0xc78, 0x85270001}, - {0xc78, 0x84280001}, {0xc78, 0x83290001}, - {0xc78, 0x252a0001}, {0xc78, 0x242b0001}, - {0xc78, 0x232c0001}, {0xc78, 0x222d0001}, - {0xc78, 0x672e0001}, {0xc78, 0x662f0001}, - {0xc78, 0x65300001}, {0xc78, 0x64310001}, - {0xc78, 0x63320001}, {0xc78, 0x62330001}, - {0xc78, 0x61340001}, {0xc78, 0x45350001}, - {0xc78, 0x44360001}, {0xc78, 0x43370001}, - {0xc78, 0x42380001}, {0xc78, 0x41390001}, - {0xc78, 0x403a0001}, {0xc78, 0x403b0001}, - {0xc78, 0x403c0001}, {0xc78, 0x403d0001}, - {0xc78, 0x403e0001}, {0xc78, 0x403f0001}, - {0xc78, 0xfb400001}, {0xc78, 0xfb410001}, - {0xc78, 0xfb420001}, {0xc78, 0xfb430001}, - {0xc78, 0xfb440001}, {0xc78, 0xfb450001}, - {0xc78, 0xfa460001}, {0xc78, 0xf9470001}, - {0xc78, 0xf8480001}, {0xc78, 0xf7490001}, - {0xc78, 0xf64a0001}, {0xc78, 0xf54b0001}, - {0xc78, 0xf44c0001}, {0xc78, 0xf34d0001}, - {0xc78, 0xf24e0001}, {0xc78, 0xf14f0001}, - {0xc78, 0xf0500001}, {0xc78, 0xef510001}, - {0xc78, 0xee520001}, {0xc78, 0xed530001}, - {0xc78, 0xec540001}, {0xc78, 0xeb550001}, - {0xc78, 0xea560001}, {0xc78, 0xe9570001}, - {0xc78, 0xe8580001}, {0xc78, 0xe7590001}, - {0xc78, 0xe65a0001}, {0xc78, 0xe55b0001}, - {0xc78, 0xe45c0001}, {0xc78, 0xe35d0001}, - {0xc78, 0xe25e0001}, {0xc78, 0xe15f0001}, - {0xc78, 0x8a600001}, {0xc78, 0x89610001}, - {0xc78, 0x88620001}, {0xc78, 0x87630001}, - {0xc78, 0x86640001}, {0xc78, 0x85650001}, - {0xc78, 0x84660001}, {0xc78, 0x83670001}, - {0xc78, 0x82680001}, {0xc78, 0x6b690001}, - {0xc78, 0x6a6a0001}, {0xc78, 0x696b0001}, - {0xc78, 0x686c0001}, {0xc78, 0x676d0001}, - {0xc78, 0x666e0001}, {0xc78, 0x656f0001}, - {0xc78, 0x64700001}, {0xc78, 0x63710001}, - {0xc78, 0x62720001}, {0xc78, 0x61730001}, - {0xc78, 0x49740001}, {0xc78, 0x48750001}, - {0xc78, 0x47760001}, {0xc78, 0x46770001}, - {0xc78, 0x45780001}, {0xc78, 0x44790001}, - {0xc78, 0x437a0001}, {0xc78, 0x427b0001}, - {0xc78, 0x417c0001}, {0xc78, 0x407d0001}, - {0xc78, 0x407e0001}, {0xc78, 0x407f0001}, - {0xc50, 0x00040022}, {0xc50, 0x00040020}, - {0xffff, 0xffffffff} -}; - -static const struct rtl8xxxu_reg32val rtl8xxx_agc_8192eu_highpa_table[] = { - {0xc78, 0xfa000001}, {0xc78, 0xf9010001}, - {0xc78, 0xf8020001}, {0xc78, 0xf7030001}, - {0xc78, 0xf6040001}, {0xc78, 0xf5050001}, - {0xc78, 0xf4060001}, {0xc78, 0xf3070001}, - {0xc78, 0xf2080001}, {0xc78, 0xf1090001}, - {0xc78, 0xf00a0001}, {0xc78, 0xef0b0001}, - {0xc78, 0xee0c0001}, {0xc78, 0xed0d0001}, - {0xc78, 0xec0e0001}, {0xc78, 0xeb0f0001}, - {0xc78, 0xea100001}, {0xc78, 0xe9110001}, - {0xc78, 0xe8120001}, {0xc78, 0xe7130001}, - {0xc78, 0xe6140001}, {0xc78, 0xe5150001}, - {0xc78, 0xe4160001}, {0xc78, 0xe3170001}, - {0xc78, 0xe2180001}, {0xc78, 0xe1190001}, - {0xc78, 0x8a1a0001}, {0xc78, 0x891b0001}, - {0xc78, 0x881c0001}, {0xc78, 0x871d0001}, - {0xc78, 0x861e0001}, {0xc78, 0x851f0001}, - {0xc78, 0x84200001}, {0xc78, 0x83210001}, - {0xc78, 0x82220001}, {0xc78, 0x6a230001}, - {0xc78, 0x69240001}, {0xc78, 0x68250001}, - {0xc78, 0x67260001}, {0xc78, 0x66270001}, - {0xc78, 0x65280001}, {0xc78, 0x64290001}, - {0xc78, 0x632a0001}, {0xc78, 0x622b0001}, - {0xc78, 0x612c0001}, {0xc78, 0x602d0001}, - {0xc78, 0x472e0001}, {0xc78, 0x462f0001}, - {0xc78, 0x45300001}, {0xc78, 0x44310001}, - {0xc78, 0x43320001}, {0xc78, 0x42330001}, - {0xc78, 0x41340001}, {0xc78, 0x40350001}, - {0xc78, 0x40360001}, {0xc78, 0x40370001}, - {0xc78, 0x40380001}, {0xc78, 0x40390001}, - {0xc78, 0x403a0001}, {0xc78, 0x403b0001}, - {0xc78, 0x403c0001}, {0xc78, 0x403d0001}, - {0xc78, 0x403e0001}, {0xc78, 0x403f0001}, - {0xc78, 0xfa400001}, {0xc78, 0xf9410001}, - {0xc78, 0xf8420001}, {0xc78, 0xf7430001}, - {0xc78, 0xf6440001}, {0xc78, 0xf5450001}, - {0xc78, 0xf4460001}, {0xc78, 0xf3470001}, - {0xc78, 0xf2480001}, {0xc78, 0xf1490001}, - {0xc78, 0xf04a0001}, {0xc78, 0xef4b0001}, - {0xc78, 0xee4c0001}, {0xc78, 0xed4d0001}, - {0xc78, 0xec4e0001}, {0xc78, 0xeb4f0001}, - {0xc78, 0xea500001}, {0xc78, 0xe9510001}, - {0xc78, 0xe8520001}, {0xc78, 0xe7530001}, - {0xc78, 0xe6540001}, {0xc78, 0xe5550001}, - {0xc78, 0xe4560001}, {0xc78, 0xe3570001}, - {0xc78, 0xe2580001}, {0xc78, 0xe1590001}, - {0xc78, 0x8a5a0001}, {0xc78, 0x895b0001}, - {0xc78, 0x885c0001}, {0xc78, 0x875d0001}, - {0xc78, 0x865e0001}, {0xc78, 0x855f0001}, - {0xc78, 0x84600001}, {0xc78, 0x83610001}, - {0xc78, 0x82620001}, {0xc78, 0x6a630001}, - {0xc78, 0x69640001}, {0xc78, 0x68650001}, - {0xc78, 0x67660001}, {0xc78, 0x66670001}, - {0xc78, 0x65680001}, {0xc78, 0x64690001}, - {0xc78, 0x636a0001}, {0xc78, 0x626b0001}, - {0xc78, 0x616c0001}, {0xc78, 0x606d0001}, - {0xc78, 0x476e0001}, {0xc78, 0x466f0001}, - {0xc78, 0x45700001}, {0xc78, 0x44710001}, - {0xc78, 0x43720001}, {0xc78, 0x42730001}, - {0xc78, 0x41740001}, {0xc78, 0x40750001}, - {0xc78, 0x40760001}, {0xc78, 0x40770001}, - {0xc78, 0x40780001}, {0xc78, 0x40790001}, - {0xc78, 0x407a0001}, {0xc78, 0x407b0001}, - {0xc78, 0x407c0001}, {0xc78, 0x407d0001}, - {0xc78, 0x407e0001}, {0xc78, 0x407f0001}, - {0xc50, 0x00040222}, {0xc50, 0x00040220}, - {0xffff, 0xffffffff} -}; - -static const struct rtl8xxxu_rfregval rtl8192eu_radioa_init_table[] = { - {0x7f, 0x00000082}, {0x81, 0x0003fc00}, - {0x00, 0x00030000}, {0x08, 0x00008400}, - {0x18, 0x00000407}, {0x19, 0x00000012}, - {0x1b, 0x00000064}, {0x1e, 0x00080009}, - {0x1f, 0x00000880}, {0x2f, 0x0001a060}, - {0x3f, 0x00000000}, {0x42, 0x000060c0}, - {0x57, 0x000d0000}, {0x58, 0x000be180}, - {0x67, 0x00001552}, {0x83, 0x00000000}, - {0xb0, 0x000ff9f1}, {0xb1, 0x00055418}, - {0xb2, 0x0008cc00}, {0xb4, 0x00043083}, - {0xb5, 0x00008166}, {0xb6, 0x0000803e}, - {0xb7, 0x0001c69f}, {0xb8, 0x0000407f}, - {0xb9, 0x00080001}, {0xba, 0x00040001}, - {0xbb, 0x00000400}, {0xbf, 0x000c0000}, - {0xc2, 0x00002400}, {0xc3, 0x00000009}, - {0xc4, 0x00040c91}, {0xc5, 0x00099999}, - {0xc6, 0x000000a3}, {0xc7, 0x00088820}, - {0xc8, 0x00076c06}, {0xc9, 0x00000000}, - {0xca, 0x00080000}, {0xdf, 0x00000180}, - {0xef, 0x000001a0}, {0x51, 0x00069545}, - {0x52, 0x0007e45e}, {0x53, 0x00000071}, - {0x56, 0x00051ff3}, {0x35, 0x000000a8}, - {0x35, 0x000001e2}, {0x35, 0x000002a8}, - {0x36, 0x00001c24}, {0x36, 0x00009c24}, - {0x36, 0x00011c24}, {0x36, 0x00019c24}, - {0x18, 0x00000c07}, {0x5a, 0x00048000}, - {0x19, 0x000739d0}, -#ifdef EXT_PA_8192EU - /* External PA or external LNA */ - {0x34, 0x0000a093}, {0x34, 0x0000908f}, - {0x34, 0x0000808c}, {0x34, 0x0000704d}, - {0x34, 0x0000604a}, {0x34, 0x00005047}, - {0x34, 0x0000400a}, {0x34, 0x00003007}, - {0x34, 0x00002004}, {0x34, 0x00001001}, - {0x34, 0x00000000}, -#else - /* Regular */ - {0x34, 0x0000add7}, {0x34, 0x00009dd4}, - {0x34, 0x00008dd1}, {0x34, 0x00007dce}, - {0x34, 0x00006dcb}, {0x34, 0x00005dc8}, - {0x34, 0x00004dc5}, {0x34, 0x000034cc}, - {0x34, 0x0000244f}, {0x34, 0x0000144c}, - {0x34, 0x00000014}, -#endif - {0x00, 0x00030159}, - {0x84, 0x00068180}, - {0x86, 0x0000014e}, - {0x87, 0x00048e00}, - {0x8e, 0x00065540}, - {0x8f, 0x00088000}, - {0xef, 0x000020a0}, -#ifdef EXT_PA_8192EU - /* External PA or external LNA */ - {0x3b, 0x000f07b0}, -#else - {0x3b, 0x000f02b0}, -#endif - {0x3b, 0x000ef7b0}, {0x3b, 0x000d4fb0}, - {0x3b, 0x000cf060}, {0x3b, 0x000b0090}, - {0x3b, 0x000a0080}, {0x3b, 0x00090080}, - {0x3b, 0x0008f780}, -#ifdef EXT_PA_8192EU - /* External PA or external LNA */ - {0x3b, 0x000787b0}, -#else - {0x3b, 0x00078730}, -#endif - {0x3b, 0x00060fb0}, {0x3b, 0x0005ffa0}, - {0x3b, 0x00040620}, {0x3b, 0x00037090}, - {0x3b, 0x00020080}, {0x3b, 0x0001f060}, - {0x3b, 0x0000ffb0}, {0xef, 0x000000a0}, - {0xfe, 0x00000000}, {0x18, 0x0000fc07}, - {0xfe, 0x00000000}, {0xfe, 0x00000000}, - {0xfe, 0x00000000}, {0xfe, 0x00000000}, - {0x1e, 0x00000001}, {0x1f, 0x00080000}, - {0x00, 0x00033e70}, - {0xff, 0xffffffff} -}; - -static const struct rtl8xxxu_rfregval rtl8192eu_radiob_init_table[] = { - {0x7f, 0x00000082}, {0x81, 0x0003fc00}, - {0x00, 0x00030000}, {0x08, 0x00008400}, - {0x18, 0x00000407}, {0x19, 0x00000012}, - {0x1b, 0x00000064}, {0x1e, 0x00080009}, - {0x1f, 0x00000880}, {0x2f, 0x0001a060}, - {0x3f, 0x00000000}, {0x42, 0x000060c0}, - {0x57, 0x000d0000}, {0x58, 0x000be180}, - {0x67, 0x00001552}, {0x7f, 0x00000082}, - {0x81, 0x0003f000}, {0x83, 0x00000000}, - {0xdf, 0x00000180}, {0xef, 0x000001a0}, - {0x51, 0x00069545}, {0x52, 0x0007e42e}, - {0x53, 0x00000071}, {0x56, 0x00051ff3}, - {0x35, 0x000000a8}, {0x35, 0x000001e0}, - {0x35, 0x000002a8}, {0x36, 0x00001ca8}, - {0x36, 0x00009c24}, {0x36, 0x00011c24}, - {0x36, 0x00019c24}, {0x18, 0x00000c07}, - {0x5a, 0x00048000}, {0x19, 0x000739d0}, -#ifdef EXT_PA_8192EU - /* External PA or external LNA */ - {0x34, 0x0000a093}, {0x34, 0x0000908f}, - {0x34, 0x0000808c}, {0x34, 0x0000704d}, - {0x34, 0x0000604a}, {0x34, 0x00005047}, - {0x34, 0x0000400a}, {0x34, 0x00003007}, - {0x34, 0x00002004}, {0x34, 0x00001001}, - {0x34, 0x00000000}, -#else - {0x34, 0x0000add7}, {0x34, 0x00009dd4}, - {0x34, 0x00008dd1}, {0x34, 0x00007dce}, - {0x34, 0x00006dcb}, {0x34, 0x00005dc8}, - {0x34, 0x00004dc5}, {0x34, 0x000034cc}, - {0x34, 0x0000244f}, {0x34, 0x0000144c}, - {0x34, 0x00000014}, -#endif - {0x00, 0x00030159}, {0x84, 0x00068180}, - {0x86, 0x000000ce}, {0x87, 0x00048a00}, - {0x8e, 0x00065540}, {0x8f, 0x00088000}, - {0xef, 0x000020a0}, -#ifdef EXT_PA_8192EU - /* External PA or external LNA */ - {0x3b, 0x000f07b0}, -#else - {0x3b, 0x000f02b0}, -#endif - - {0x3b, 0x000ef7b0}, {0x3b, 0x000d4fb0}, - {0x3b, 0x000cf060}, {0x3b, 0x000b0090}, - {0x3b, 0x000a0080}, {0x3b, 0x00090080}, - {0x3b, 0x0008f780}, -#ifdef EXT_PA_8192EU - /* External PA or external LNA */ - {0x3b, 0x000787b0}, -#else - {0x3b, 0x00078730}, -#endif - {0x3b, 0x00060fb0}, {0x3b, 0x0005ffa0}, - {0x3b, 0x00040620}, {0x3b, 0x00037090}, - {0x3b, 0x00020080}, {0x3b, 0x0001f060}, - {0x3b, 0x0000ffb0}, {0xef, 0x000000a0}, - {0x00, 0x00010159}, {0xfe, 0x00000000}, - {0xfe, 0x00000000}, {0xfe, 0x00000000}, - {0xfe, 0x00000000}, {0x1e, 0x00000001}, - {0x1f, 0x00080000}, {0x00, 0x00033e70}, - {0xff, 0xffffffff} -}; - -static int rtl8192eu_identify_chip(struct rtl8xxxu_priv *priv) -{ - struct device *dev = &priv->udev->dev; - u32 val32, bonding, sys_cfg, vendor; - int ret = 0; - - sys_cfg = rtl8xxxu_read32(priv, REG_SYS_CFG); - priv->chip_cut = u32_get_bits(sys_cfg, SYS_CFG_CHIP_VERSION_MASK); - if (sys_cfg & SYS_CFG_TRP_VAUX_EN) { - dev_info(dev, "Unsupported test chip\n"); - ret = -ENOTSUPP; - goto out; - } - - bonding = rtl8xxxu_read32(priv, REG_HPON_FSM); - bonding &= HPON_FSM_BONDING_MASK; - if (bonding == HPON_FSM_BONDING_1T2R) { - strscpy(priv->chip_name, "8191EU", sizeof(priv->chip_name)); - priv->tx_paths = 1; - priv->rtl_chip = RTL8191E; - } else { - strscpy(priv->chip_name, "8192EU", sizeof(priv->chip_name)); - priv->tx_paths = 2; - priv->rtl_chip = RTL8192E; - } - priv->rf_paths = 2; - priv->rx_paths = 2; - priv->has_wifi = 1; - - vendor = sys_cfg & SYS_CFG_VENDOR_EXT_MASK; - rtl8xxxu_identify_vendor_2bits(priv, vendor); - - val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS); - priv->rom_rev = u32_get_bits(val32, GPIO_RF_RL_ID); - - rtl8xxxu_config_endpoints_sie(priv); - - /* - * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX - */ - if (!priv->ep_tx_count) - ret = rtl8xxxu_config_endpoints_no_sie(priv); - -out: - return ret; -} - -static void -rtl8192e_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40) -{ - u32 val32, ofdm, mcs; - u8 cck, ofdmbase, mcsbase; - int group, tx_idx; - - tx_idx = 0; - group = rtl8xxxu_gen2_channel_to_group(channel); - - cck = priv->cck_tx_power_index_A[group]; - - val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32); - val32 &= 0xffff00ff; - val32 |= (cck << 8); - rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); - - val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); - val32 &= 0xff; - val32 |= ((cck << 8) | (cck << 16) | (cck << 24)); - rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); - - ofdmbase = priv->ht40_1s_tx_power_index_A[group]; - ofdmbase += priv->ofdm_tx_power_diff[tx_idx].a; - ofdm = ofdmbase | ofdmbase << 8 | ofdmbase << 16 | ofdmbase << 24; - - rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm); - rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm); - - mcsbase = priv->ht40_1s_tx_power_index_A[group]; - if (ht40) - mcsbase += priv->ht40_tx_power_diff[tx_idx++].a; - else - mcsbase += priv->ht20_tx_power_diff[tx_idx++].a; - mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24; - - rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs); - rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs); - rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs); - rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs); - - if (priv->tx_paths > 1) { - cck = priv->cck_tx_power_index_B[group]; - - val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32); - val32 &= 0xff; - val32 |= ((cck << 8) | (cck << 16) | (cck << 24)); - rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32); - - val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); - val32 &= 0xffffff00; - val32 |= cck; - rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); - - ofdmbase = priv->ht40_1s_tx_power_index_B[group]; - ofdmbase += priv->ofdm_tx_power_diff[tx_idx].b; - ofdm = ofdmbase | ofdmbase << 8 | - ofdmbase << 16 | ofdmbase << 24; - - rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, ofdm); - rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, ofdm); - - mcsbase = priv->ht40_1s_tx_power_index_B[group]; - if (ht40) - mcsbase += priv->ht40_tx_power_diff[tx_idx++].b; - else - mcsbase += priv->ht20_tx_power_diff[tx_idx++].b; - mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24; - - rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, mcs); - rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, mcs); - rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, mcs); - rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, mcs); - } -} - -static int rtl8192eu_parse_efuse(struct rtl8xxxu_priv *priv) -{ - struct rtl8192eu_efuse *efuse = &priv->efuse_wifi.efuse8192eu; - int i; - - if (efuse->rtl_id != cpu_to_le16(0x8129)) - return -EINVAL; - - ether_addr_copy(priv->mac_addr, efuse->mac_addr); - - memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base, - sizeof(efuse->tx_power_index_A.cck_base)); - memcpy(priv->cck_tx_power_index_B, efuse->tx_power_index_B.cck_base, - sizeof(efuse->tx_power_index_B.cck_base)); - - memcpy(priv->ht40_1s_tx_power_index_A, - efuse->tx_power_index_A.ht40_base, - sizeof(efuse->tx_power_index_A.ht40_base)); - memcpy(priv->ht40_1s_tx_power_index_B, - efuse->tx_power_index_B.ht40_base, - sizeof(efuse->tx_power_index_B.ht40_base)); - - priv->ht20_tx_power_diff[0].a = - efuse->tx_power_index_A.ht20_ofdm_1s_diff.b; - priv->ht20_tx_power_diff[0].b = - efuse->tx_power_index_B.ht20_ofdm_1s_diff.b; - - priv->ht40_tx_power_diff[0].a = 0; - priv->ht40_tx_power_diff[0].b = 0; - - for (i = 1; i < RTL8723B_TX_COUNT; i++) { - priv->ofdm_tx_power_diff[i].a = - efuse->tx_power_index_A.pwr_diff[i - 1].ofdm; - priv->ofdm_tx_power_diff[i].b = - efuse->tx_power_index_B.pwr_diff[i - 1].ofdm; - - priv->ht20_tx_power_diff[i].a = - efuse->tx_power_index_A.pwr_diff[i - 1].ht20; - priv->ht20_tx_power_diff[i].b = - efuse->tx_power_index_B.pwr_diff[i - 1].ht20; - - priv->ht40_tx_power_diff[i].a = - efuse->tx_power_index_A.pwr_diff[i - 1].ht40; - priv->ht40_tx_power_diff[i].b = - efuse->tx_power_index_B.pwr_diff[i - 1].ht40; - } - - priv->default_crystal_cap = priv->efuse_wifi.efuse8192eu.xtal_k & 0x3f; - - return 0; -} - -static int rtl8192eu_load_firmware(struct rtl8xxxu_priv *priv) -{ - const char *fw_name; - int ret; - - fw_name = "rtlwifi/rtl8192eu_nic.bin"; - - ret = rtl8xxxu_load_firmware(priv, fw_name); - - return ret; -} - -static void rtl8192eu_init_phy_bb(struct rtl8xxxu_priv *priv) -{ - u8 val8; - u16 val16; - - val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); - val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB | SYS_FUNC_DIO_RF; - rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); - - /* 6. 0x1f[7:0] = 0x07 */ - val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB; - rtl8xxxu_write8(priv, REG_RF_CTRL, val8); - - val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); - val16 |= (SYS_FUNC_USBA | SYS_FUNC_USBD | SYS_FUNC_DIO_RF | - SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB); - rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); - val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB; - rtl8xxxu_write8(priv, REG_RF_CTRL, val8); - rtl8xxxu_init_phy_regs(priv, rtl8192eu_phy_init_table); - - if (priv->hi_pa) - rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8192eu_highpa_table); - else - rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8192eu_std_table); -} - -static int rtl8192eu_init_phy_rf(struct rtl8xxxu_priv *priv) -{ - int ret; - - ret = rtl8xxxu_init_phy_rf(priv, rtl8192eu_radioa_init_table, RF_A); - if (ret) - goto exit; - - ret = rtl8xxxu_init_phy_rf(priv, rtl8192eu_radiob_init_table, RF_B); - -exit: - return ret; -} - -static int rtl8192eu_iqk_path_a(struct rtl8xxxu_priv *priv) -{ - u32 reg_eac, reg_e94, reg_e9c; - int result = 0; - - /* - * TX IQK - * PA/PAD controlled by 0x0 - */ - rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x00180); - - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x20000); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0x07f77); - - rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); - - /* Path A IQK setting */ - rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); - rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); - rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); - rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); - - rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140303); - rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x68160000); - - /* LO calibration setting */ - rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911); - - /* One shot, path A LOK & IQK */ - rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); - rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); - - mdelay(10); - - /* Check failed */ - reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); - reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); - reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); - - if (!(reg_eac & BIT(28)) && - ((reg_e94 & 0x03ff0000) != 0x01420000) && - ((reg_e9c & 0x03ff0000) != 0x00420000)) - result |= 0x01; - - return result; -} - -static int rtl8192eu_rx_iqk_path_a(struct rtl8xxxu_priv *priv) -{ - u32 reg_ea4, reg_eac, reg_e94, reg_e9c, val32; - int result = 0; - - /* Leave IQK mode */ - rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00); - - /* Enable path A PA in TX IQK mode */ - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf1173); - - rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0); - rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000); - rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f); - rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf1173); - - /* PA/PAD control by 0x56, and set = 0x0 */ - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x00980); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_PAD_TXG, 0x511e0); - - /* Enter IQK mode */ - rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); - - /* TX IQK setting */ - rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); - rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); - - /* path-A IQK setting */ - rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); - rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); - rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); - rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); - - rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x8216031f); - rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x6816031f); - - /* LO calibration setting */ - rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911); - - /* One shot, path A LOK & IQK */ - rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); - rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); - - mdelay(10); - - /* Check failed */ - reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); - reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); - reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); - - if (!(reg_eac & BIT(28)) && - ((reg_e94 & 0x03ff0000) != 0x01420000) && - ((reg_e9c & 0x03ff0000) != 0x00420000)) { - result |= 0x01; - } else { - /* PA/PAD controlled by 0x0 */ - rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x180); - goto out; - } - - val32 = 0x80007c00 | - (reg_e94 & 0x03ff0000) | ((reg_e9c >> 16) & 0x03ff); - rtl8xxxu_write32(priv, REG_TX_IQK, val32); - - /* Modify RX IQK mode table */ - rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); - - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7ff2); - - rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0); - rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000); - rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f); - rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf7ff2); - - /* PA/PAD control by 0x56, and set = 0x0 */ - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x00980); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_PAD_TXG, 0x510e0); - - /* Enter IQK mode */ - rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); - - /* IQK setting */ - rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); - - /* Path A IQK setting */ - rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); - rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c); - rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); - rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); - - rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821608ff); - rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x281608ff); - - /* LO calibration setting */ - rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a891); - - /* One shot, path A LOK & IQK */ - rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); - rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); - - mdelay(10); - - reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); - reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); - - rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x180); - - if (!(reg_eac & BIT(27)) && - ((reg_ea4 & 0x03ff0000) != 0x01320000) && - ((reg_eac & 0x03ff0000) != 0x00360000)) - result |= 0x02; - else - dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n", - __func__); - -out: - return result; -} - -static int rtl8192eu_iqk_path_b(struct rtl8xxxu_priv *priv) -{ - u32 reg_eac, reg_eb4, reg_ebc; - int result = 0; - - rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); - rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_CCA, 0x00180); - - rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0); - rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x20000); - rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f); - rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0x07f77); - - rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); - - /* Path B IQK setting */ - rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); - rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); - rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x18008c1c); - rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); - - rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140303); - rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x68160000); - - /* LO calibration setting */ - rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911); - - /* One shot, path A LOK & IQK */ - rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000); - rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); - - mdelay(1); - - /* Check failed */ - reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); - reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); - reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); - - if (!(reg_eac & BIT(31)) && - ((reg_eb4 & 0x03ff0000) != 0x01420000) && - ((reg_ebc & 0x03ff0000) != 0x00420000)) - result |= 0x01; - else - dev_warn(&priv->udev->dev, "%s: Path B IQK failed!\n", - __func__); - - return result; -} - -static int rtl8192eu_rx_iqk_path_b(struct rtl8xxxu_priv *priv) -{ - u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc, val32; - int result = 0; - - /* Leave IQK mode */ - rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); - - /* Enable path A PA in TX IQK mode */ - rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0); - rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000); - rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f); - rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf1173); - - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf1173); - - /* PA/PAD control by 0x56, and set = 0x0 */ - rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_CCA, 0x00980); - rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_PAD_TXG, 0x511e0); - - /* Enter IQK mode */ - rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); - - /* TX IQK setting */ - rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); - rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); - - /* path-A IQK setting */ - rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); - rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); - rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x18008c1c); - rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); - - rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x8216031f); - rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x6816031f); - - /* LO calibration setting */ - rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911); - - /* One shot, path A LOK & IQK */ - rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000); - rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); - - mdelay(10); - - /* Check failed */ - reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); - reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); - reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); - - if (!(reg_eac & BIT(31)) && - ((reg_eb4 & 0x03ff0000) != 0x01420000) && - ((reg_ebc & 0x03ff0000) != 0x00420000)) { - result |= 0x01; - } else { - /* - * PA/PAD controlled by 0x0 - * Vendor driver restores RF_A here which I believe is a bug - */ - rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); - rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_CCA, 0x180); - goto out; - } - - val32 = 0x80007c00 | - (reg_eb4 & 0x03ff0000) | ((reg_ebc >> 16) & 0x03ff); - rtl8xxxu_write32(priv, REG_TX_IQK, val32); - - /* Modify RX IQK mode table */ - rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); - - rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0); - rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000); - rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f); - rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf7ff2); - - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7ff2); - - /* PA/PAD control by 0x56, and set = 0x0 */ - rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_CCA, 0x00980); - rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_PAD_TXG, 0x510e0); - - /* Enter IQK mode */ - rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); - - /* IQK setting */ - rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); - - /* Path A IQK setting */ - rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); - rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); - rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); - rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x18008c1c); - - rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821608ff); - rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x281608ff); - - /* LO calibration setting */ - rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a891); - - /* One shot, path A LOK & IQK */ - rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000); - rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); - - mdelay(10); - - reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); - reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2); - reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2); - - rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); - rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_CCA, 0x180); - - if (!(reg_eac & BIT(30)) && - ((reg_ec4 & 0x03ff0000) != 0x01320000) && - ((reg_ecc & 0x03ff0000) != 0x00360000)) - result |= 0x02; - else - dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n", - __func__); - -out: - return result; -} - -static void rtl8192eu_phy_iqcalibrate(struct rtl8xxxu_priv *priv, - int result[][8], int t) -{ - struct device *dev = &priv->udev->dev; - u32 i, val32; - int path_a_ok, path_b_ok; - int retry = 2; - static const u32 adda_regs[RTL8XXXU_ADDA_REGS] = { - REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH, - REG_RX_WAIT_CCA, REG_TX_CCK_RFON, - REG_TX_CCK_BBON, REG_TX_OFDM_RFON, - REG_TX_OFDM_BBON, REG_TX_TO_RX, - REG_TX_TO_TX, REG_RX_CCK, - REG_RX_OFDM, REG_RX_WAIT_RIFS, - REG_RX_TO_RX, REG_STANDBY, - REG_SLEEP, REG_PMPD_ANAEN - }; - static const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = { - REG_TXPAUSE, REG_BEACON_CTRL, - REG_BEACON_CTRL_1, REG_GPIO_MUXCFG - }; - static const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = { - REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR, - REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, - REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE, - REG_FPGA0_XB_RF_INT_OE, REG_CCK0_AFE_SETTING - }; - u8 xa_agc = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1) & 0xff; - u8 xb_agc = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1) & 0xff; - - /* - * Note: IQ calibration must be performed after loading - * PHY_REG.txt , and radio_a, radio_b.txt - */ - - if (t == 0) { - /* Save ADDA parameters, turn Path A ADDA on */ - rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup, - RTL8XXXU_ADDA_REGS); - rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup); - rtl8xxxu_save_regs(priv, iqk_bb_regs, - priv->bb_backup, RTL8XXXU_BB_REGS); - } - - rtl8xxxu_path_adda_on(priv, adda_regs, true); - - /* MAC settings */ - rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup); - - val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING); - val32 |= 0x0f000000; - rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32); - - rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600); - rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4); - rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22208200); - - val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL); - val32 |= (FPGA0_RF_PAPE | (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT)); - rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32); - - val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE); - val32 |= BIT(10); - rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32); - val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE); - val32 |= BIT(10); - rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32); - - rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); - rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); - rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); - - for (i = 0; i < retry; i++) { - path_a_ok = rtl8192eu_iqk_path_a(priv); - if (path_a_ok == 0x01) { - val32 = rtl8xxxu_read32(priv, - REG_TX_POWER_BEFORE_IQK_A); - result[t][0] = (val32 >> 16) & 0x3ff; - val32 = rtl8xxxu_read32(priv, - REG_TX_POWER_AFTER_IQK_A); - result[t][1] = (val32 >> 16) & 0x3ff; - - break; - } - } - - if (!path_a_ok) - dev_dbg(dev, "%s: Path A TX IQK failed!\n", __func__); - - for (i = 0; i < retry; i++) { - path_a_ok = rtl8192eu_rx_iqk_path_a(priv); - if (path_a_ok == 0x03) { - val32 = rtl8xxxu_read32(priv, - REG_RX_POWER_BEFORE_IQK_A_2); - result[t][2] = (val32 >> 16) & 0x3ff; - val32 = rtl8xxxu_read32(priv, - REG_RX_POWER_AFTER_IQK_A_2); - result[t][3] = (val32 >> 16) & 0x3ff; - - break; - } - } - - if (!path_a_ok) - dev_dbg(dev, "%s: Path A RX IQK failed!\n", __func__); - - if (priv->rf_paths > 1) { - /* Path A into standby */ - rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x10000); - rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); - - /* Turn Path B ADDA on */ - rtl8xxxu_path_adda_on(priv, adda_regs, false); - - rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); - rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); - rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); - - for (i = 0; i < retry; i++) { - path_b_ok = rtl8192eu_iqk_path_b(priv); - if (path_b_ok == 0x01) { - val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); - result[t][4] = (val32 >> 16) & 0x3ff; - val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); - result[t][5] = (val32 >> 16) & 0x3ff; - break; - } - } - - if (!path_b_ok) - dev_dbg(dev, "%s: Path B IQK failed!\n", __func__); - - for (i = 0; i < retry; i++) { - path_b_ok = rtl8192eu_rx_iqk_path_b(priv); - if (path_b_ok == 0x03) { - val32 = rtl8xxxu_read32(priv, - REG_RX_POWER_BEFORE_IQK_B_2); - result[t][6] = (val32 >> 16) & 0x3ff; - val32 = rtl8xxxu_read32(priv, - REG_RX_POWER_AFTER_IQK_B_2); - result[t][7] = (val32 >> 16) & 0x3ff; - break; - } - } - - if (!path_b_ok) - dev_dbg(dev, "%s: Path B RX IQK failed!\n", __func__); - } - - /* Back to BB mode, load original value */ - rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); - - if (t) { - /* Reload ADDA power saving parameters */ - rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup, - RTL8XXXU_ADDA_REGS); - - /* Reload MAC parameters */ - rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup); - - /* Reload BB parameters */ - rtl8xxxu_restore_regs(priv, iqk_bb_regs, - priv->bb_backup, RTL8XXXU_BB_REGS); - - /* Restore RX initial gain */ - val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); - val32 &= 0xffffff00; - rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | 0x50); - rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | xa_agc); - - if (priv->rf_paths > 1) { - val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1); - val32 &= 0xffffff00; - rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1, - val32 | 0x50); - rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1, - val32 | xb_agc); - } - - /* Load 0xe30 IQC default value */ - rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00); - rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00); - } -} - -static void rtl8192eu_phy_iq_calibrate(struct rtl8xxxu_priv *priv) -{ - struct device *dev = &priv->udev->dev; - int result[4][8]; /* last is final result */ - int i, candidate; - bool path_a_ok, path_b_ok; - u32 reg_e94, reg_e9c, reg_ea4, reg_eac; - u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc; - bool simu; - - memset(result, 0, sizeof(result)); - candidate = -1; - - path_a_ok = false; - path_b_ok = false; - - for (i = 0; i < 3; i++) { - rtl8192eu_phy_iqcalibrate(priv, result, i); - - if (i == 1) { - simu = rtl8xxxu_gen2_simularity_compare(priv, - result, 0, 1); - if (simu) { - candidate = 0; - break; - } - } - - if (i == 2) { - simu = rtl8xxxu_gen2_simularity_compare(priv, - result, 0, 2); - if (simu) { - candidate = 0; - break; - } - - simu = rtl8xxxu_gen2_simularity_compare(priv, - result, 1, 2); - if (simu) - candidate = 1; - else - candidate = 3; - } - } - - for (i = 0; i < 4; i++) { - reg_e94 = result[i][0]; - reg_e9c = result[i][1]; - reg_ea4 = result[i][2]; - reg_eb4 = result[i][4]; - reg_ebc = result[i][5]; - reg_ec4 = result[i][6]; - } - - if (candidate >= 0) { - reg_e94 = result[candidate][0]; - priv->rege94 = reg_e94; - reg_e9c = result[candidate][1]; - priv->rege9c = reg_e9c; - reg_ea4 = result[candidate][2]; - reg_eac = result[candidate][3]; - reg_eb4 = result[candidate][4]; - priv->regeb4 = reg_eb4; - reg_ebc = result[candidate][5]; - priv->regebc = reg_ebc; - reg_ec4 = result[candidate][6]; - reg_ecc = result[candidate][7]; - dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate); - dev_dbg(dev, - "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x ecc=%x\n", - __func__, reg_e94, reg_e9c, - reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc); - path_a_ok = true; - path_b_ok = true; - } else { - reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100; - reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0; - } - - if (reg_e94 && candidate >= 0) - rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result, - candidate, (reg_ea4 == 0)); - - if (priv->rf_paths > 1) - rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result, - candidate, (reg_ec4 == 0)); - - rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg, - priv->bb_recovery_backup, RTL8XXXU_BB_REGS); -} - -/* - * This is needed for 8723bu as well, presumable - */ -static void rtl8192e_crystal_afe_adjust(struct rtl8xxxu_priv *priv) -{ - u8 val8; - u32 val32; - - /* - * 40Mhz crystal source, MAC 0x28[2]=0 - */ - val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL); - val8 &= 0xfb; - rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8); - - val32 = rtl8xxxu_read32(priv, REG_AFE_CTRL4); - val32 &= 0xfffffc7f; - rtl8xxxu_write32(priv, REG_AFE_CTRL4, val32); - - /* - * 92e AFE parameter - * AFE PLL KVCO selection, MAC 0x28[6]=1 - */ - val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL); - val8 &= 0xbf; - rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8); - - /* - * AFE PLL KVCO selection, MAC 0x78[21]=0 - */ - val32 = rtl8xxxu_read32(priv, REG_AFE_CTRL4); - val32 &= 0xffdfffff; - rtl8xxxu_write32(priv, REG_AFE_CTRL4, val32); -} - -static void rtl8192e_disabled_to_emu(struct rtl8xxxu_priv *priv) -{ - u8 val8; - - /* Clear suspend enable and power down enable*/ - val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); - val8 &= ~(BIT(3) | BIT(4)); - rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); -} - -static int rtl8192e_emu_to_active(struct rtl8xxxu_priv *priv) -{ - u8 val8; - u32 val32; - int count, ret = 0; - - /* disable HWPDN 0x04[15]=0*/ - val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); - val8 &= ~BIT(7); - rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); - - /* disable SW LPS 0x04[10]= 0 */ - val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); - val8 &= ~BIT(2); - rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); - - /* disable WL suspend*/ - val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); - val8 &= ~(BIT(3) | BIT(4)); - rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); - - /* wait till 0x04[17] = 1 power ready*/ - for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { - val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); - if (val32 & BIT(17)) - break; - - udelay(10); - } - - if (!count) { - ret = -EBUSY; - goto exit; - } - - /* We should be able to optimize the following three entries into one */ - - /* release WLON reset 0x04[16]= 1*/ - val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2); - val8 |= BIT(0); - rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8); - - /* set, then poll until 0 */ - val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); - val32 |= APS_FSMCO_MAC_ENABLE; - rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); - - for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { - val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); - if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) { - ret = 0; - break; - } - udelay(10); - } - - if (!count) { - ret = -EBUSY; - goto exit; - } - -exit: - return ret; -} - -static int rtl8192eu_active_to_lps(struct rtl8xxxu_priv *priv) -{ - struct device *dev = &priv->udev->dev; - u8 val8; - u16 val16; - u32 val32; - int retry, retval; - - rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); - - retry = 100; - retval = -EBUSY; - /* - * Poll 32 bit wide 0x05f8 for 0x00000000 to ensure no TX is pending. - */ - do { - val32 = rtl8xxxu_read32(priv, REG_SCH_TX_CMD); - if (!val32) { - retval = 0; - break; - } - } while (retry--); - - if (!retry) { - dev_warn(dev, "Failed to flush TX queue\n"); - retval = -EBUSY; - goto out; - } - - /* Disable CCK and OFDM, clock gated */ - val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); - val8 &= ~SYS_FUNC_BBRSTB; - rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); - - udelay(2); - - /* Reset whole BB */ - val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); - val8 &= ~SYS_FUNC_BB_GLB_RSTN; - rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); - - /* Reset MAC TRX */ - val16 = rtl8xxxu_read16(priv, REG_CR); - val16 &= 0xff00; - val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE); - rtl8xxxu_write16(priv, REG_CR, val16); - - val16 = rtl8xxxu_read16(priv, REG_CR); - val16 &= ~CR_SECURITY_ENABLE; - rtl8xxxu_write16(priv, REG_CR, val16); - - val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST); - val8 |= DUAL_TSF_TX_OK; - rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8); - -out: - return retval; -} - -static int rtl8192eu_active_to_emu(struct rtl8xxxu_priv *priv) -{ - u8 val8; - int count, ret = 0; - - /* Turn off RF */ - val8 = rtl8xxxu_read8(priv, REG_RF_CTRL); - val8 &= ~RF_ENABLE; - rtl8xxxu_write8(priv, REG_RF_CTRL, val8); - - /* Switch DPDT_SEL_P output from register 0x65[2] */ - val8 = rtl8xxxu_read8(priv, REG_LEDCFG2); - val8 &= ~LEDCFG2_DPDT_SELECT; - rtl8xxxu_write8(priv, REG_LEDCFG2, val8); - - /* 0x0005[1] = 1 turn off MAC by HW state machine*/ - val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); - val8 |= BIT(1); - rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); - - for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { - val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); - if ((val8 & BIT(1)) == 0) - break; - udelay(10); - } - - if (!count) { - dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n", - __func__); - ret = -EBUSY; - goto exit; - } - -exit: - return ret; -} - -static int rtl8192eu_emu_to_disabled(struct rtl8xxxu_priv *priv) -{ - u8 val8; - - /* 0x04[12:11] = 01 enable WL suspend */ - val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); - val8 &= ~(BIT(3) | BIT(4)); - val8 |= BIT(3); - rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); - - return 0; -} - -static int rtl8192eu_power_on(struct rtl8xxxu_priv *priv) -{ - u16 val16; - u32 val32; - int ret; - - val32 = rtl8xxxu_read32(priv, REG_SYS_CFG); - if (val32 & SYS_CFG_SPS_LDO_SEL) { - rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0xc3); - } else { - /* - * Raise 1.2V voltage - */ - val32 = rtl8xxxu_read32(priv, REG_8192E_LDOV12_CTRL); - val32 &= 0xff0fffff; - val32 |= 0x00500000; - rtl8xxxu_write32(priv, REG_8192E_LDOV12_CTRL, val32); - rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0x83); - } - - /* - * Adjust AFE before enabling PLL - */ - rtl8192e_crystal_afe_adjust(priv); - rtl8192e_disabled_to_emu(priv); - - ret = rtl8192e_emu_to_active(priv); - if (ret) - goto exit; - - rtl8xxxu_write16(priv, REG_CR, 0x0000); - - /* - * Enable MAC DMA/WMAC/SCHEDULE/SEC block - * Set CR bit10 to enable 32k calibration. - */ - val16 = rtl8xxxu_read16(priv, REG_CR); - val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE | - CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | - CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE | - CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE | - CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE); - rtl8xxxu_write16(priv, REG_CR, val16); - -exit: - return ret; -} - -static void rtl8192eu_power_off(struct rtl8xxxu_priv *priv) -{ - u8 val8; - u16 val16; - - rtl8xxxu_flush_fifo(priv); - - val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL); - val8 &= ~TX_REPORT_CTRL_TIMER_ENABLE; - rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8); - - /* Turn off RF */ - rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00); - - rtl8192eu_active_to_lps(priv); - - /* Reset Firmware if running in RAM */ - if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL) - rtl8xxxu_firmware_self_reset(priv); - - /* Reset MCU */ - val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); - val16 &= ~SYS_FUNC_CPU_ENABLE; - rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); - - /* Reset MCU ready status */ - rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00); - - rtl8xxxu_reset_8051(priv); - - rtl8192eu_active_to_emu(priv); - rtl8192eu_emu_to_disabled(priv); -} - -static void rtl8192e_enable_rf(struct rtl8xxxu_priv *priv) -{ - u32 val32; - u8 val8; - - val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA); - val32 |= (BIT(22) | BIT(23)); - rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32); - - val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG); - val8 |= BIT(5); - rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8); - - /* - * WLAN action by PTA - */ - rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04); - - val32 = rtl8xxxu_read32(priv, REG_PWR_DATA); - val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN; - rtl8xxxu_write32(priv, REG_PWR_DATA, val32); - - val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER); - val32 |= (BIT(0) | BIT(1)); - rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32); - - rtl8xxxu_write8(priv, REG_RFE_CTRL_ANTA_SRC, 0x77); - - val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); - val32 &= ~BIT(24); - val32 |= BIT(23); - rtl8xxxu_write32(priv, REG_LEDCFG0, val32); - - /* - * Fix external switch Main->S1, Aux->S0 - */ - val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1); - val8 &= ~BIT(0); - rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8); - - /* - * Fix transmission failure of rtl8192e. - */ - rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); -} - -static s8 rtl8192e_cck_rssi(struct rtl8xxxu_priv *priv, struct rtl8723au_phy_stats *phy_stats) -{ - static const s8 lna_gain_table_0[8] = {15, 9, -10, -21, -23, -27, -43, -44}; - static const s8 lna_gain_table_1[8] = {24, 18, 13, -4, -11, -18, -31, -36}; - - u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a; - s8 rx_pwr_all = 0x00; - u8 vga_idx, lna_idx; - s8 lna_gain = 0; - - lna_idx = u8_get_bits(cck_agc_rpt, CCK_AGC_RPT_LNA_IDX_MASK); - vga_idx = u8_get_bits(cck_agc_rpt, CCK_AGC_RPT_VGA_IDX_MASK); - - if (priv->cck_agc_report_type == 0) - lna_gain = lna_gain_table_0[lna_idx]; - else - lna_gain = lna_gain_table_1[lna_idx]; - - rx_pwr_all = lna_gain - (2 * vga_idx); - - return rx_pwr_all; -} - -static int rtl8192eu_led_brightness_set(struct led_classdev *led_cdev, - enum led_brightness brightness) -{ - struct rtl8xxxu_priv *priv = container_of(led_cdev, - struct rtl8xxxu_priv, - led_cdev); - u8 ledcfg = rtl8xxxu_read8(priv, REG_LEDCFG1); - - if (brightness == LED_OFF) { - ledcfg &= ~LEDCFG1_HW_LED_CONTROL; - ledcfg |= LEDCFG1_LED_DISABLE; - } else if (brightness == LED_ON) { - ledcfg &= ~(LEDCFG1_HW_LED_CONTROL | LEDCFG1_LED_DISABLE); - } else if (brightness == RTL8XXXU_HW_LED_CONTROL) { - ledcfg &= ~LEDCFG1_LED_DISABLE; - ledcfg |= LEDCFG1_HW_LED_CONTROL; - } - - rtl8xxxu_write8(priv, REG_LEDCFG1, ledcfg); - - return 0; -} - -struct rtl8xxxu_fileops rtl8192eu_fops = { - .identify_chip = rtl8192eu_identify_chip, - .parse_efuse = rtl8192eu_parse_efuse, - .load_firmware = rtl8192eu_load_firmware, - .power_on = rtl8192eu_power_on, - .power_off = rtl8192eu_power_off, - .read_efuse = rtl8xxxu_read_efuse, - .reset_8051 = rtl8xxxu_reset_8051, - .llt_init = rtl8xxxu_auto_llt_table, - .init_phy_bb = rtl8192eu_init_phy_bb, - .init_phy_rf = rtl8192eu_init_phy_rf, - .phy_lc_calibrate = rtl8723a_phy_lc_calibrate, - .phy_iq_calibrate = rtl8192eu_phy_iq_calibrate, - .config_channel = rtl8xxxu_gen2_config_channel, - .parse_rx_desc = rtl8xxxu_parse_rxdesc24, - .parse_phystats = rtl8723au_rx_parse_phystats, - .enable_rf = rtl8192e_enable_rf, - .disable_rf = rtl8xxxu_gen2_disable_rf, - .usb_quirks = rtl8xxxu_gen2_usb_quirks, - .set_tx_power = rtl8192e_set_tx_power, - .update_rate_mask = rtl8xxxu_gen2_update_rate_mask, - .report_connect = rtl8xxxu_gen2_report_connect, - .report_rssi = rtl8xxxu_gen2_report_rssi, - .fill_txdesc = rtl8xxxu_fill_txdesc_v2, - .set_crystal_cap = rtl8723a_set_crystal_cap, - .cck_rssi = rtl8192e_cck_rssi, - .led_classdev_brightness_set = rtl8192eu_led_brightness_set, - .writeN_block_size = 128, - .tx_desc_size = sizeof(struct rtl8xxxu_txdesc40), - .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc24), - .has_s0s1 = 0, - .gen2_thermal_meter = 1, - .needs_full_init = 1, - .supports_ap = 1, - .max_macid_num = 128, - .max_sec_cam_num = 64, - .adda_1t_init = 0x0fc01616, - .adda_1t_path_on = 0x0fc01616, - .adda_2t_path_on_a = 0x0fc01616, - .adda_2t_path_on_b = 0x0fc01616, - .trxff_boundary = 0x3cff, - .mactable = rtl8192e_mac_init_table, - .total_page_num = TX_TOTAL_PAGE_NUM_8192E, - .page_num_hi = TX_PAGE_NUM_HI_PQ_8192E, - .page_num_lo = TX_PAGE_NUM_LO_PQ_8192E, - .page_num_norm = TX_PAGE_NUM_NORM_PQ_8192E, -}; diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192f.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192f.c deleted file mode 100644 index 9f1d4a6ee210..000000000000 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192f.c +++ /dev/null @@ -1,2103 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * RTL8XXXU mac80211 USB driver - 8192fu specific subdriver - * - * Copyright (c) 2023 Bitterblue Smith - * - * Portions copied from existing rtl8xxxu code: - * Copyright (c) 2014 - 2017 Jes Sorensen - * - * Portions, notably calibration code: - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "rtl8xxxu.h" -#include "rtl8xxxu_regs.h" - -static const struct rtl8xxxu_reg8val rtl8192f_mac_init_table[] = { - {0x420, 0x00}, {0x422, 0x78}, {0x428, 0x0a}, {0x429, 0x10}, - {0x430, 0x00}, {0x431, 0x00}, {0x432, 0x00}, {0x433, 0x01}, - {0x434, 0x04}, {0x435, 0x05}, {0x436, 0x07}, {0x437, 0x08}, - {0x43c, 0x04}, {0x43d, 0x05}, {0x43e, 0x07}, {0x43f, 0x08}, - {0x440, 0x5d}, {0x441, 0x01}, {0x442, 0x00}, {0x444, 0x10}, - {0x445, 0xf0}, {0x446, 0x0e}, {0x447, 0x1f}, {0x448, 0x00}, - {0x449, 0x00}, {0x44a, 0x00}, {0x44b, 0x00}, {0x44c, 0x10}, - {0x44d, 0xf0}, {0x44e, 0x0e}, {0x44f, 0x00}, {0x450, 0x00}, - {0x451, 0x00}, {0x452, 0x00}, {0x453, 0x00}, {0x480, 0x20}, - {0x49c, 0x30}, {0x49d, 0xf0}, {0x49e, 0x03}, {0x49f, 0x3e}, - {0x4a0, 0x00}, {0x4a1, 0x00}, {0x4a2, 0x00}, {0x4a3, 0x00}, - {0x4a4, 0x15}, {0x4a5, 0xf0}, {0x4a6, 0x01}, {0x4a7, 0x0e}, - {0x4a8, 0xe0}, {0x4a9, 0x00}, {0x4aa, 0x00}, {0x4ab, 0x00}, - {0x2448, 0x06}, {0x244a, 0x06}, {0x244c, 0x06}, {0x244e, 0x06}, - {0x4c7, 0x80}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4ca, 0x3c}, - {0x4cb, 0x3c}, {0x4cc, 0xff}, {0x4cd, 0xff}, {0x4ce, 0x01}, - {0x500, 0x26}, {0x501, 0xa2}, {0x502, 0x2f}, {0x503, 0x00}, - {0x504, 0x28}, {0x505, 0xa3}, {0x506, 0x5e}, {0x507, 0x00}, - {0x508, 0x2b}, {0x509, 0xa4}, {0x50a, 0x5e}, {0x50b, 0x00}, - {0x50c, 0x4f}, {0x50d, 0xa4}, {0x50e, 0x00}, {0x50f, 0x00}, - {0x512, 0x1c}, {0x514, 0x0a}, {0x516, 0x0a}, {0x521, 0x2f}, - {0x525, 0x0f}, {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, - {0x55c, 0x50}, {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, - {0x609, 0x2a}, {0x60c, 0x18}, {0x620, 0xff}, {0x621, 0xff}, - {0x622, 0xff}, {0x623, 0xff}, {0x624, 0xff}, {0x625, 0xff}, - {0x626, 0xff}, {0x627, 0xff}, {0x638, 0x50}, {0x63c, 0x0a}, - {0x63d, 0x0a}, {0x63e, 0x0e}, {0x63f, 0x0e}, {0x640, 0x40}, - {0x642, 0x40}, {0x643, 0x00}, {0x652, 0xc8}, {0x66e, 0x05}, - {0x6a0, 0xff}, {0x6a1, 0xff}, {0x6a2, 0xff}, {0x6a3, 0xff}, - {0x6a4, 0xff}, {0x6a5, 0xff}, {0x6de, 0x84}, {0x700, 0x21}, - {0x701, 0x43}, {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, - {0x709, 0x43}, {0x70a, 0x65}, {0x70b, 0x87}, {0x718, 0x40}, - {0x7c0, 0x38}, {0x7c2, 0x0f}, {0x7c3, 0xc0}, {0x073, 0x04}, - {0x7c4, 0x77}, {0x024, 0xc7}, {0x7ec, 0xff}, {0x7ed, 0xff}, - {0x7ee, 0xff}, {0x7ef, 0xff}, - {0xffff, 0xff}, -}; - -/* If updating the phy init table, also update rtl8192f_revise_cck_tx_psf(). */ -static const struct rtl8xxxu_reg32val rtl8192fu_phy_init_table[] = { - {0x800, 0x80006C00}, {0x804, 0x00004001}, - {0x808, 0x0000FC00}, {0x80C, 0x00000000}, - {0x810, 0x20200322}, {0x814, 0x020C3910}, - {0x818, 0x00000385}, {0x81C, 0x07000000}, - {0x820, 0x01000100}, {0x824, 0x00390204}, - {0x828, 0x01000100}, {0x82C, 0x00390204}, - {0x830, 0x25252525}, {0x834, 0x25252525}, - {0x838, 0x25252525}, {0x83C, 0x25252525}, - {0x840, 0x00010000}, {0x844, 0x00010000}, - {0x848, 0x25252525}, {0x84C, 0x25252525}, - {0x850, 0x00031FE0}, {0x854, 0x00000000}, - {0x858, 0x569A569A}, {0x85C, 0x00400040}, - {0x860, 0x66F60000}, {0x864, 0x061F0000}, - {0x868, 0x25252525}, {0x86C, 0x25252525}, - {0x870, 0x00000300}, {0x874, 0x04003400}, - {0x878, 0x08080808}, {0x87C, 0x004F0201}, - {0x880, 0xD8001402}, {0x884, 0xC0000120}, - {0x888, 0x00000000}, {0x88C, 0xCC0000C0}, - {0x890, 0x00000000}, {0x894, 0xFFFFFFFE}, - {0x898, 0x40302010}, {0x89C, 0x00706050}, - {0x900, 0x00000000}, {0x904, 0x00000023}, - {0x908, 0x00000F00}, {0x90C, 0x81121313}, - {0x910, 0x024C0000}, {0x914, 0x00000000}, - {0x918, 0x00000000}, {0x91C, 0x00000000}, - {0x920, 0x00000000}, {0x924, 0x00000000}, - {0x928, 0x00000000}, {0x92C, 0x00000000}, - {0x930, 0x88000000}, {0x934, 0x00000245}, - {0x938, 0x00024588}, {0x93C, 0x00000000}, - {0x940, 0x000007FF}, {0x944, 0x3F3F0000}, - {0x948, 0x000001A3}, {0x94C, 0x20200008}, - {0x950, 0x00338A98}, {0x954, 0x00000000}, - {0x958, 0xCBCAD87A}, {0x95C, 0x06EB5735}, - {0x960, 0x00000000}, {0x964, 0x00000000}, - {0x968, 0x00000000}, {0x96C, 0x00000003}, - {0x970, 0x00000000}, {0x974, 0x00000000}, - {0x978, 0x00000000}, {0x97C, 0x10030000}, - {0x980, 0x00000000}, {0x984, 0x02800280}, - {0x988, 0x020A5704}, {0x98C, 0x1461C826}, - {0x990, 0x0001469E}, {0x994, 0x008858D1}, - {0x998, 0x400086C9}, {0x99C, 0x44444242}, - {0x9A0, 0x00000000}, {0x9A4, 0x00000000}, - {0x9A8, 0x00000000}, {0x9AC, 0xC0000000}, - {0xA00, 0x00D047C8}, {0xA04, 0xC1FF0008}, - {0xA08, 0x88838300}, {0xA0C, 0x2E20100F}, - {0xA10, 0x9500BB78}, {0xA14, 0x11144028}, - {0xA18, 0x00881117}, {0xA1C, 0x89140F00}, - {0xA20, 0xE82C0001}, {0xA24, 0x64B80C1C}, - {0xA28, 0x00158810}, {0xA2C, 0x10BB8000}, - {0xA70, 0x00008000}, {0xA74, 0x80800100}, - {0xA78, 0x000089F0}, {0xA7C, 0x225B0606}, - {0xA80, 0x20803210}, {0xA84, 0x00200200}, - {0xA88, 0x00000000}, {0xA8C, 0x00000000}, - {0xA90, 0x00000000}, {0xA94, 0x00000000}, - {0xA98, 0x00000000}, {0xA9C, 0x00460000}, - {0xAA0, 0x00000000}, {0xAA4, 0x00020014}, - {0xAA8, 0xBA0A0008}, {0xAAC, 0x01235667}, - {0xAB0, 0x00000000}, {0xAB4, 0x00201402}, - {0xAB8, 0x0000001C}, {0xABC, 0x0000F7FF}, - {0xAC0, 0xD4C0A742}, {0xAC4, 0x00000000}, - {0xAC8, 0x00000F08}, {0xACC, 0x00000F07}, - {0xAD0, 0xA1052A10}, {0xAD4, 0x0D9D8452}, - {0xAD8, 0x9E024024}, {0xADC, 0x0023C001}, - {0xAE0, 0x00000391}, {0xB2C, 0x00000000}, - {0xC00, 0x00000080}, {0xC04, 0x6F005433}, - {0xC08, 0x000004E4}, {0xC0C, 0x6C6C6C6C}, - {0xC10, 0x22000000}, {0xC14, 0x40000100}, - {0xC18, 0x22000000}, {0xC1C, 0x40000100}, - {0xC20, 0x00000000}, {0xC24, 0x40000100}, - {0xC28, 0x00000000}, {0xC2C, 0x40000100}, - {0xC30, 0x0401E809}, {0xC34, 0x30000020}, - {0xC38, 0x23808080}, {0xC3C, 0x00002F44}, - {0xC40, 0x1CF8403F}, {0xC44, 0x000100C7}, - {0xC48, 0xEC060106}, {0xC4C, 0x007F037F}, - {0xC50, 0x00E48020}, {0xC54, 0x04008017}, - {0xC58, 0x00000020}, {0xC5C, 0x00708492}, - {0xC60, 0x09280200}, {0xC64, 0x5014838B}, - {0xC68, 0x47C006C7}, {0xC6C, 0x00000035}, - {0xC70, 0x00001007}, {0xC74, 0x02815269}, - {0xC78, 0x0FE07F1F}, {0xC7C, 0x00B91612}, - {0xC80, 0x40000100}, {0xC84, 0x32000000}, - {0xC88, 0x40000100}, {0xC8C, 0xA0240000}, - {0xC90, 0x400E161E}, {0xC94, 0x00000F00}, - {0xC98, 0x400E161E}, {0xC9C, 0x0000BDC8}, - {0xCA0, 0x00000000}, {0xCA4, 0x098300A0}, - {0xCA8, 0x00006B00}, {0xCAC, 0x87F45B1A}, - {0xCB0, 0x0000002D}, {0xCB4, 0x00000000}, - {0xCB8, 0x00000000}, {0xCBC, 0x28100200}, - {0xCC0, 0x0010A3D0}, {0xCC4, 0x00000F7D}, - {0xCC8, 0x00000000}, {0xCCC, 0x00000000}, - {0xCD0, 0x593659AD}, {0xCD4, 0xB7545121}, - {0xCD8, 0x64B22427}, {0xCDC, 0x00766932}, - {0xCE0, 0x40201000}, {0xCE4, 0x00000000}, - {0xCE8, 0x40E04407}, {0xCEC, 0x2E572000}, - {0xD00, 0x000D8780}, {0xD04, 0x40020403}, - {0xD08, 0x0002907F}, {0xD0C, 0x20010201}, - {0xD10, 0x06288888}, {0xD14, 0x8888367B}, - {0xD18, 0x7D806DB3}, {0xD1C, 0x0000007F}, - {0xD20, 0x567600B8}, {0xD24, 0x0000018B}, - {0xD28, 0xD513FF7D}, {0xD2C, 0xCC979975}, - {0xD30, 0x04928000}, {0xD34, 0x40608000}, - {0xD38, 0x88DDA000}, {0xD3C, 0x00026EE2}, - {0xD50, 0x67270001}, {0xD54, 0x20500000}, - {0xD58, 0x16161616}, {0xD5C, 0x71F20064}, - {0xD60, 0x4653DA60}, {0xD64, 0x3E718A3C}, - {0xD68, 0x00000183}, {0xD7C, 0x00000000}, - {0xD80, 0x50000000}, {0xD84, 0x31310400}, - {0xD88, 0xF5B50000}, {0xD8C, 0x00000000}, - {0xD90, 0x00000000}, {0xD94, 0x44BBBB44}, - {0xD98, 0x44BB44FF}, {0xD9C, 0x06033688}, - {0xE00, 0x25252525}, {0xE04, 0x25252525}, - {0xE08, 0x25252525}, {0xE10, 0x25252525}, - {0xE14, 0x25252525}, {0xE18, 0x25252525}, - {0xE1C, 0x25252525}, {0xE20, 0x00000000}, - {0xE24, 0x00200000}, {0xE28, 0x00000000}, - {0xE2C, 0x00000000}, {0xE30, 0x01007C00}, - {0xE34, 0x01004800}, {0xE38, 0x10008C0F}, - {0xE3C, 0x3C008C0F}, {0xE40, 0x01007C00}, - {0xE44, 0x00000000}, {0xE48, 0x00000000}, - {0xE4C, 0x00000000}, {0xE50, 0x01007C00}, - {0xE54, 0x01004800}, {0xE58, 0x10008C0F}, - {0xE5C, 0x3C008C0F}, {0xE60, 0x02100000}, - {0xE64, 0xBBBBBBBB}, {0xE68, 0x40404040}, - {0xE6C, 0x80408040}, {0xE70, 0x80408040}, - {0xE74, 0x40404040}, {0xE78, 0x00400040}, - {0xE7C, 0x40404040}, {0xE80, 0x00FF0000}, - {0xE84, 0x80408040}, {0xE88, 0x40404040}, - {0xE8C, 0x80408040}, {0xED0, 0x80408040}, - {0xED4, 0x80408040}, {0xED8, 0x80408040}, - {0xEDC, 0xC040C040}, {0xEE0, 0xC040C040}, - {0xEE4, 0x00400040}, {0xEE8, 0xD8001402}, - {0xEEC, 0xC0000120}, {0xEF0, 0x02000B09}, - {0xEF4, 0x00000001}, {0xEF8, 0x00000000}, - {0xF00, 0x00000300}, {0xF04, 0x00000002}, - {0xF08, 0x00007D0C}, {0xF0C, 0x0000A907}, - {0xF10, 0x00005807}, {0xF14, 0x00000003}, - {0xF18, 0x07D003E8}, {0xF1C, 0x8000001F}, - {0xF20, 0x00000000}, {0xF24, 0x00000000}, - {0xF28, 0x00000000}, {0xF2C, 0x00000000}, - {0xF30, 0x00000000}, {0xF34, 0x00000000}, - {0xF38, 0x00030055}, {0xF3C, 0x0000003A}, - {0xF40, 0x00000002}, {0xF44, 0x00000000}, - {0xF48, 0x00000000}, {0xF4C, 0x0B000000}, - {0xF50, 0x00000000}, - {0xffff, 0xffffffff}, -}; - -static const struct rtl8xxxu_reg32val rtl8192f_agc_table[] = { - {0xC78, 0x0FA0001F}, {0xC78, 0x0FA0011F}, - {0xC78, 0x0FA0021F}, {0xC78, 0x0FA0031F}, - {0xC78, 0x0FA0041F}, {0xC78, 0x0FA0051F}, - {0xC78, 0x0F90061F}, {0xC78, 0x0F80071F}, - {0xC78, 0x0F70081F}, {0xC78, 0x0F60091F}, - {0xC78, 0x0F500A1F}, {0xC78, 0x0F400B1F}, - {0xC78, 0x0F300C1F}, {0xC78, 0x0F200D1F}, - {0xC78, 0x0F100E1F}, {0xC78, 0x0F000F1F}, - {0xC78, 0x0EF0101F}, {0xC78, 0x0EE0111F}, - {0xC78, 0x0ED0121F}, {0xC78, 0x0EC0131F}, - {0xC78, 0x0EB0141F}, {0xC78, 0x0EA0151F}, - {0xC78, 0x0E90161F}, {0xC78, 0x0E80171F}, - {0xC78, 0x0E70181F}, {0xC78, 0x0E60191F}, - {0xC78, 0x0E501A1F}, {0xC78, 0x0E401B1F}, - {0xC78, 0x0E301C1F}, {0xC78, 0x0C701D1F}, - {0xC78, 0x0C601E1F}, {0xC78, 0x0C501F1F}, - {0xC78, 0x0C40201F}, {0xC78, 0x0C30211F}, - {0xC78, 0x0A60221F}, {0xC78, 0x0A50231F}, - {0xC78, 0x0A40241F}, {0xC78, 0x0A30251F}, - {0xC78, 0x0860261F}, {0xC78, 0x0850271F}, - {0xC78, 0x0840281F}, {0xC78, 0x0830291F}, - {0xC78, 0x06702A1F}, {0xC78, 0x06602B1F}, - {0xC78, 0x06502C1F}, {0xC78, 0x06402D1F}, - {0xC78, 0x06302E1F}, {0xC78, 0x04602F1F}, - {0xC78, 0x0450301F}, {0xC78, 0x0440311F}, - {0xC78, 0x0430321F}, {0xC78, 0x0260331F}, - {0xC78, 0x0250341F}, {0xC78, 0x0240351F}, - {0xC78, 0x0230361F}, {0xC78, 0x0050371F}, - {0xC78, 0x0040381F}, {0xC78, 0x0030391F}, - {0xC78, 0x00203A1F}, {0xC78, 0x00103B1F}, - {0xC78, 0x00003C1F}, {0xC78, 0x00003D1F}, - {0xC78, 0x00003E1F}, {0xC78, 0x00003F1F}, - - {0xC78, 0x0FA0401F}, {0xC78, 0x0FA0411F}, - {0xC78, 0x0FA0421F}, {0xC78, 0x0FA0431F}, - {0xC78, 0x0F90441F}, {0xC78, 0x0F80451F}, - {0xC78, 0x0F70461F}, {0xC78, 0x0F60471F}, - {0xC78, 0x0F50481F}, {0xC78, 0x0F40491F}, - {0xC78, 0x0F304A1F}, {0xC78, 0x0F204B1F}, - {0xC78, 0x0F104C1F}, {0xC78, 0x0F004D1F}, - {0xC78, 0x0EF04E1F}, {0xC78, 0x0EE04F1F}, - {0xC78, 0x0ED0501F}, {0xC78, 0x0EC0511F}, - {0xC78, 0x0EB0521F}, {0xC78, 0x0EA0531F}, - {0xC78, 0x0E90541F}, {0xC78, 0x0E80551F}, - {0xC78, 0x0E70561F}, {0xC78, 0x0E60571F}, - {0xC78, 0x0E50581F}, {0xC78, 0x0E40591F}, - {0xC78, 0x0E305A1F}, {0xC78, 0x0E205B1F}, - {0xC78, 0x0E105C1F}, {0xC78, 0x0C505D1F}, - {0xC78, 0x0C405E1F}, {0xC78, 0x0C305F1F}, - {0xC78, 0x0C20601F}, {0xC78, 0x0C10611F}, - {0xC78, 0x0A40621F}, {0xC78, 0x0A30631F}, - {0xC78, 0x0A20641F}, {0xC78, 0x0A10651F}, - {0xC78, 0x0840661F}, {0xC78, 0x0830671F}, - {0xC78, 0x0820681F}, {0xC78, 0x0810691F}, - {0xC78, 0x06506A1F}, {0xC78, 0x06406B1F}, - {0xC78, 0x06306C1F}, {0xC78, 0x06206D1F}, - {0xC78, 0x06106E1F}, {0xC78, 0x04406F1F}, - {0xC78, 0x0430701F}, {0xC78, 0x0420711F}, - {0xC78, 0x0410721F}, {0xC78, 0x0240731F}, - {0xC78, 0x0230741F}, {0xC78, 0x0220751F}, - {0xC78, 0x0210761F}, {0xC78, 0x0030771F}, - {0xC78, 0x0020781F}, {0xC78, 0x0010791F}, - {0xC78, 0x00007A1F}, {0xC78, 0x00007B1F}, - {0xC78, 0x00007C1F}, {0xC78, 0x00007D1F}, - {0xC78, 0x00007E1F}, {0xC78, 0x00007F1F}, - - {0xC78, 0x0FA0801F}, {0xC78, 0x0FA0811F}, - {0xC78, 0x0FA0821F}, {0xC78, 0x0FA0831F}, - {0xC78, 0x0FA0841F}, {0xC78, 0x0FA0851F}, - {0xC78, 0x0F90861F}, {0xC78, 0x0F80871F}, - {0xC78, 0x0F70881F}, {0xC78, 0x0F60891F}, - {0xC78, 0x0F508A1F}, {0xC78, 0x0F408B1F}, - {0xC78, 0x0F308C1F}, {0xC78, 0x0F208D1F}, - {0xC78, 0x0F108E1F}, {0xC78, 0x0B908F1F}, - {0xC78, 0x0B80901F}, {0xC78, 0x0B70911F}, - {0xC78, 0x0B60921F}, {0xC78, 0x0B50931F}, - {0xC78, 0x0B40941F}, {0xC78, 0x0B30951F}, - {0xC78, 0x0B20961F}, {0xC78, 0x0B10971F}, - {0xC78, 0x0B00981F}, {0xC78, 0x0AF0991F}, - {0xC78, 0x0AE09A1F}, {0xC78, 0x0AD09B1F}, - {0xC78, 0x0AC09C1F}, {0xC78, 0x0AB09D1F}, - {0xC78, 0x0AA09E1F}, {0xC78, 0x0A909F1F}, - {0xC78, 0x0A80A01F}, {0xC78, 0x0A70A11F}, - {0xC78, 0x0A60A21F}, {0xC78, 0x0A50A31F}, - {0xC78, 0x0A40A41F}, {0xC78, 0x0A30A51F}, - {0xC78, 0x0A20A61F}, {0xC78, 0x0A10A71F}, - {0xC78, 0x0A00A81F}, {0xC78, 0x0830A91F}, - {0xC78, 0x0820AA1F}, {0xC78, 0x0810AB1F}, - {0xC78, 0x0800AC1F}, {0xC78, 0x0640AD1F}, - {0xC78, 0x0630AE1F}, {0xC78, 0x0620AF1F}, - {0xC78, 0x0610B01F}, {0xC78, 0x0600B11F}, - {0xC78, 0x0430B21F}, {0xC78, 0x0420B31F}, - {0xC78, 0x0410B41F}, {0xC78, 0x0400B51F}, - {0xC78, 0x0230B61F}, {0xC78, 0x0220B71F}, - {0xC78, 0x0210B81F}, {0xC78, 0x0200B91F}, - {0xC78, 0x0000BA1F}, {0xC78, 0x0000BB1F}, - {0xC78, 0x0000BC1F}, {0xC78, 0x0000BD1F}, - {0xC78, 0x0000BE1F}, {0xC78, 0x0000BF1F}, - {0xC50, 0x00E48024}, {0xC50, 0x00E48020}, - {0xffff, 0xffffffff} -}; - -static const struct rtl8xxxu_rfregval rtl8192fu_radioa_init_table[] = { - {0x00, 0x30000}, {0x18, 0x0FC07}, {0x81, 0x0FC00}, {0x82, 0x003C0}, - {0x84, 0x00005}, {0x86, 0xA33A5}, {0x87, 0x00000}, {0x88, 0x58010}, - {0x8E, 0x64540}, {0x8F, 0x282D8}, {0x51, 0x02C06}, {0x52, 0x7A007}, - {0x53, 0x10061}, {0x54, 0x60018}, {0x55, 0x82020}, {0x56, 0x08CC6}, - {0x57, 0x2CC00}, {0x58, 0x00000}, {0x5A, 0x50000}, {0x5B, 0x00006}, - {0x5C, 0x00015}, {0x65, 0x20000}, {0x6E, 0x38319}, {0xF5, 0x43180}, - {0xEF, 0x00002}, {0x33, 0x00301}, {0x33, 0x1032A}, {0x33, 0x2032A}, - {0xEF, 0x00000}, {0xDF, 0x00002}, {0x35, 0x00000}, {0xF0, 0x08008}, - {0xEF, 0x00800}, {0x33, 0x0040E}, {0x33, 0x04845}, {0x33, 0x08848}, - {0x33, 0x0C84B}, {0x33, 0x1088A}, {0x33, 0x14C50}, {0x33, 0x18C8E}, - {0x33, 0x1CCCD}, {0x33, 0x20CD0}, {0x33, 0x24CD3}, {0x33, 0x28CD6}, - {0x33, 0x4002B}, {0x33, 0x4402E}, {0x33, 0x48846}, {0x33, 0x4C849}, - {0x33, 0x50888}, {0x33, 0x54CC6}, {0x33, 0x58CC9}, {0x33, 0x5CCCC}, - {0x33, 0x60CCF}, {0x33, 0x64CD2}, {0x33, 0x68CD5}, {0xEF, 0x00000}, - {0xEF, 0x00400}, {0x33, 0x01C23}, {0x33, 0x05C23}, {0x33, 0x09D23}, - {0x33, 0x0DD23}, {0x33, 0x11FA3}, {0x33, 0x15FA3}, {0x33, 0x19FAB}, - {0x33, 0x1DFAB}, {0xEF, 0x00000}, {0xEF, 0x00200}, {0x33, 0x00030}, - {0x33, 0x04030}, {0x33, 0x08030}, {0x33, 0x0C030}, {0x33, 0x10030}, - {0x33, 0x14030}, {0x33, 0x18030}, {0x33, 0x1C030}, {0x33, 0x20030}, - {0x33, 0x24030}, {0x33, 0x28030}, {0x33, 0x2C030}, {0x33, 0x30030}, - {0x33, 0x34030}, {0x33, 0x38030}, {0x33, 0x3C030}, {0xEF, 0x00000}, - {0xEF, 0x00100}, {0x33, 0x44001}, {0x33, 0x48001}, {0x33, 0x4C001}, - {0x33, 0x50001}, {0x33, 0x54001}, {0x33, 0x58001}, {0x33, 0x5C001}, - {0x33, 0x60001}, {0x33, 0x64001}, {0x33, 0x68001}, {0x33, 0x6C001}, - {0x33, 0x70001}, {0x33, 0x74001}, {0x33, 0x78001}, {0x33, 0x04000}, - {0x33, 0x08000}, {0x33, 0x0C000}, {0x33, 0x10000}, {0x33, 0x14000}, - {0x33, 0x18001}, {0x33, 0x1C002}, {0x33, 0x20002}, {0x33, 0x24002}, - {0x33, 0x28002}, {0x33, 0x2C002}, {0x33, 0x30002}, {0x33, 0x34002}, - {0x33, 0x38002}, {0xEF, 0x00000}, {0x84, 0x00000}, {0xEF, 0x80010}, - {0x30, 0x20000}, {0x31, 0x0006F}, {0x32, 0x01FF7}, {0xEF, 0x00000}, - {0x84, 0x00000}, {0xEF, 0x80000}, {0x30, 0x30000}, {0x31, 0x0006F}, - {0x32, 0xF1DF3}, {0xEF, 0x00000}, {0x84, 0x00000}, {0xEF, 0x80000}, - {0x30, 0x38000}, {0x31, 0x0006F}, {0x32, 0xF1FF2}, {0xEF, 0x00000}, - {0x1B, 0x746CE}, {0xEF, 0x20000}, {0x33, 0x30000}, {0x33, 0x38000}, - {0x33, 0x70000}, {0x33, 0x78000}, {0xEF, 0x00000}, {0xDF, 0x08000}, - {0xB0, 0xFFBCB}, {0xB3, 0x06000}, {0xB7, 0x18DF0}, {0xB8, 0x38FF0}, - {0xC9, 0x00600}, {0xDF, 0x00000}, {0xB1, 0x33B8F}, {0xB2, 0x33762}, - {0xB4, 0x141F0}, {0xB5, 0x14080}, {0xB6, 0x12425}, {0xB9, 0xC0008}, - {0xBA, 0x40005}, {0xC2, 0x02C01}, {0xC3, 0x0000B}, {0xC4, 0x81E2F}, - {0xC5, 0x5C28F}, {0xC6, 0x000A0}, {0xCA, 0x02000}, {0xFE, 0x00000}, - {0x18, 0x08C07}, {0xFE, 0x00000}, {0xFE, 0x00000}, {0xFE, 0x00000}, - {0x00, 0x31DD5}, - {0xff, 0xffffffff} -}; - -static const struct rtl8xxxu_rfregval rtl8192fu_radiob_init_table[] = { - {0x00, 0x30000}, {0x81, 0x0FC00}, {0x82, 0x003C0}, {0x84, 0x00005}, - {0x86, 0xA33A5}, {0x87, 0x00000}, {0x88, 0x58010}, {0x8E, 0x64540}, - {0x8F, 0x282D8}, {0x51, 0x02C06}, {0x52, 0x7A007}, {0x53, 0x10061}, - {0x54, 0x60018}, {0x55, 0x82020}, {0x56, 0x08CC6}, {0x57, 0x2CC00}, - {0x58, 0x00000}, {0x5A, 0x50000}, {0x5B, 0x00006}, {0x5C, 0x00015}, - {0x65, 0x20000}, {0x6E, 0x38319}, {0xF5, 0x43180}, {0xEF, 0x00002}, - {0x33, 0x00301}, {0x33, 0x1032A}, {0x33, 0x2032A}, {0xEF, 0x00000}, - {0xDF, 0x00002}, {0x35, 0x00000}, {0xF0, 0x08008}, {0xEF, 0x00800}, - {0x33, 0x0040E}, {0x33, 0x04845}, {0x33, 0x08848}, {0x33, 0x0C84B}, - {0x33, 0x1088A}, {0x33, 0x14CC8}, {0x33, 0x18CCB}, {0x33, 0x1CCCE}, - {0x33, 0x20CD1}, {0x33, 0x24CD4}, {0x33, 0x28CD7}, {0x33, 0x4002B}, - {0x33, 0x4402E}, {0x33, 0x48846}, {0x33, 0x4C849}, {0x33, 0x50888}, - {0x33, 0x54CC6}, {0x33, 0x58CC9}, {0x33, 0x5CCCC}, {0x33, 0x60CCF}, - {0x33, 0x64CD2}, {0x33, 0x68CD5}, {0xEF, 0x00000}, {0xEF, 0x00400}, - {0x33, 0x01D23}, {0x33, 0x05D23}, {0x33, 0x09FA3}, {0x33, 0x0DFA3}, - {0x33, 0x11D2B}, {0x33, 0x15D2B}, {0x33, 0x19FAB}, {0x33, 0x1DFAB}, - {0xEF, 0x00000}, {0xEF, 0x00200}, {0x33, 0x00030}, {0x33, 0x04030}, - {0x33, 0x08030}, {0x33, 0x0C030}, {0x33, 0x10030}, {0x33, 0x14030}, - {0x33, 0x18030}, {0x33, 0x1C030}, {0x33, 0x20030}, {0x33, 0x24030}, - {0x33, 0x28030}, {0x33, 0x2C030}, {0x33, 0x30030}, {0x33, 0x34030}, - {0x33, 0x38030}, {0x33, 0x3C030}, {0xEF, 0x00000}, {0xEF, 0x00100}, - {0x33, 0x44000}, {0x33, 0x48000}, {0x33, 0x4C000}, {0x33, 0x50000}, - {0x33, 0x54000}, {0x33, 0x58000}, {0x33, 0x5C000}, {0x33, 0x60000}, - {0x33, 0x64000}, {0x33, 0x68000}, {0x33, 0x6C000}, {0x33, 0x70000}, - {0x33, 0x74000}, {0x33, 0x78000}, {0x33, 0x04000}, {0x33, 0x08000}, - {0x33, 0x0C000}, {0x33, 0x10000}, {0x33, 0x14000}, {0x33, 0x18000}, - {0x33, 0x1C001}, {0x33, 0x20001}, {0x33, 0x24001}, {0x33, 0x28001}, - {0x33, 0x2C001}, {0x33, 0x30001}, {0x33, 0x34001}, {0x33, 0x38001}, - {0xEF, 0x00000}, {0x84, 0x00000}, {0xEF, 0x80010}, {0x30, 0x20000}, - {0x31, 0x0006F}, {0x32, 0x01FF7}, {0xEF, 0x00000}, {0x84, 0x00000}, - {0xEF, 0x80000}, {0x30, 0x30000}, {0x31, 0x0006F}, {0x32, 0xF1DF3}, - {0xEF, 0x00000}, {0x84, 0x00000}, {0xEF, 0x80000}, {0x30, 0x38000}, - {0x31, 0x0006F}, {0x32, 0xF1FF2}, {0xEF, 0x00000}, {0x1B, 0x746CE}, - {0xEF, 0x20000}, {0x33, 0x30000}, {0x33, 0x38000}, {0x33, 0x70000}, - {0x33, 0x78000}, {0xEF, 0x00000}, {0x00, 0x31DD5}, - {0xff, 0xffffffff} -}; - -static int rtl8192fu_identify_chip(struct rtl8xxxu_priv *priv) -{ - struct device *dev = &priv->udev->dev; - u32 sys_cfg, vendor, val32; - - strscpy(priv->chip_name, "8192FU", sizeof(priv->chip_name)); - priv->rtl_chip = RTL8192F; - priv->rf_paths = 2; - priv->rx_paths = 2; - priv->tx_paths = 2; - - sys_cfg = rtl8xxxu_read32(priv, REG_SYS_CFG); - priv->chip_cut = u32_get_bits(sys_cfg, SYS_CFG_CHIP_VERSION_MASK); - if (sys_cfg & SYS_CFG_TRP_VAUX_EN) { - dev_info(dev, "Unsupported test chip\n"); - return -EOPNOTSUPP; - } - - val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL); - priv->has_wifi = u32_get_bits(val32, MULTI_WIFI_FUNC_EN); - priv->has_bluetooth = u32_get_bits(val32, MULTI_BT_FUNC_EN); - priv->has_gps = u32_get_bits(val32, MULTI_GPS_FUNC_EN); - priv->is_multi_func = 1; - - vendor = sys_cfg & SYS_CFG_VENDOR_ID; - rtl8xxxu_identify_vendor_1bit(priv, vendor); - - val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS); - priv->rom_rev = u32_get_bits(val32, GPIO_RF_RL_ID); - - return rtl8xxxu_config_endpoints_no_sie(priv); -} - -static void -rtl8192f_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40) -{ - u8 cck, ofdmbase, mcsbase; - u32 val32, ofdm, mcs; - int group, cck_group; - - rtl8188f_channel_to_group(channel, &group, &cck_group); - - cck = priv->cck_tx_power_index_A[cck_group]; - - rtl8xxxu_write32_mask(priv, REG_TX_AGC_A_CCK1_MCS32, 0x00007f00, cck); - - val32 = (cck << 16) | (cck << 8) | cck; - rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, - 0x7f7f7f00, val32); - - ofdmbase = priv->ht40_1s_tx_power_index_A[group]; - ofdmbase += priv->ofdm_tx_power_diff[RF_A].a; - ofdm = ofdmbase | ofdmbase << 8 | ofdmbase << 16 | ofdmbase << 24; - - rtl8xxxu_write32_mask(priv, REG_TX_AGC_A_RATE18_06, 0x7f7f7f7f, ofdm); - rtl8xxxu_write32_mask(priv, REG_TX_AGC_A_RATE54_24, 0x7f7f7f7f, ofdm); - - mcsbase = priv->ht40_1s_tx_power_index_A[group]; - if (ht40) - mcsbase += priv->ht40_tx_power_diff[RF_A].a; - else - mcsbase += priv->ht20_tx_power_diff[RF_A].a; - mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24; - - rtl8xxxu_write32_mask(priv, REG_TX_AGC_A_MCS03_MCS00, 0x7f7f7f7f, mcs); - rtl8xxxu_write32_mask(priv, REG_TX_AGC_A_MCS07_MCS04, 0x7f7f7f7f, mcs); - rtl8xxxu_write32_mask(priv, REG_TX_AGC_A_MCS11_MCS08, 0x7f7f7f7f, mcs); - rtl8xxxu_write32_mask(priv, REG_TX_AGC_A_MCS15_MCS12, 0x7f7f7f7f, mcs); - - if (priv->tx_paths == 1) - return; - - cck = priv->cck_tx_power_index_B[cck_group]; - - val32 = (cck << 16) | (cck << 8) | cck; - rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_CCK1_55_MCS32, - 0x7f7f7f00, val32); - - rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, - 0x0000007f, cck); - - ofdmbase = priv->ht40_1s_tx_power_index_B[group]; - ofdmbase += priv->ofdm_tx_power_diff[RF_B].b; - ofdm = ofdmbase | ofdmbase << 8 | ofdmbase << 16 | ofdmbase << 24; - - rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_RATE18_06, 0x7f7f7f7f, ofdm); - rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_RATE54_24, 0x7f7f7f7f, ofdm); - - mcsbase = priv->ht40_1s_tx_power_index_B[group]; - if (ht40) - mcsbase += priv->ht40_tx_power_diff[RF_B].b; - else - mcsbase += priv->ht20_tx_power_diff[RF_B].b; - mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24; - - rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_MCS03_MCS00, 0x7f7f7f7f, mcs); - rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_MCS07_MCS04, 0x7f7f7f7f, mcs); - rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_MCS11_MCS08, 0x7f7f7f7f, mcs); - rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_MCS15_MCS12, 0x7f7f7f7f, mcs); -} - -static void rtl8192f_revise_cck_tx_psf(struct rtl8xxxu_priv *priv, u8 channel) -{ - if (channel == 13) { - /* Special value for channel 13 */ - rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER1, 0xf8fe0001); - /* Normal values */ - rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER2, 0x64B80C1C); - rtl8xxxu_write16(priv, REG_CCK0_DEBUG_PORT, 0x8810); - rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER3, 0x01235667); - } else if (channel == 14) { - /* Normal value */ - rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER1, 0xE82C0001); - /* Special values for channel 14 */ - rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER2, 0x0000B81C); - rtl8xxxu_write16(priv, REG_CCK0_DEBUG_PORT, 0x0000); - rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER3, 0x00003667); - } else { - /* Restore normal values from the phy init table */ - rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER1, 0xE82C0001); - rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER2, 0x64B80C1C); - rtl8xxxu_write16(priv, REG_CCK0_DEBUG_PORT, 0x8810); - rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER3, 0x01235667); - } -} - -static void rtl8192fu_config_kfree(struct rtl8xxxu_priv *priv, u8 channel) -{ - u8 bb_gain[3] = { EFUSE_UNDEFINED, EFUSE_UNDEFINED, EFUSE_UNDEFINED }; - u8 bb_gain_path_mask[2] = { 0x0f, 0xf0 }; - enum rtl8xxxu_rfpath rfpath; - u8 bb_gain_for_path; - u8 channel_idx = 0; - - if (channel >= 1 && channel <= 3) - channel_idx = 0; - if (channel >= 4 && channel <= 9) - channel_idx = 1; - if (channel >= 10 && channel <= 14) - channel_idx = 2; - - rtl8xxxu_read_efuse8(priv, 0x1ee, &bb_gain[1]); - rtl8xxxu_read_efuse8(priv, 0x1ec, &bb_gain[0]); - rtl8xxxu_read_efuse8(priv, 0x1ea, &bb_gain[2]); - - if (bb_gain[1] == EFUSE_UNDEFINED) - return; - - if (bb_gain[0] == EFUSE_UNDEFINED) - bb_gain[0] = bb_gain[1]; - - if (bb_gain[2] == EFUSE_UNDEFINED) - bb_gain[2] = bb_gain[1]; - - for (rfpath = RF_A; rfpath < priv->rf_paths; rfpath++) { - /* power_trim based on 55[19:14] */ - rtl8xxxu_write_rfreg_mask(priv, rfpath, RF6052_REG_UNKNOWN_55, - BIT(5), 1); - - /* enable 55[14] for 0.5db step */ - rtl8xxxu_write_rfreg_mask(priv, rfpath, RF6052_REG_GAIN_CTRL, - BIT(18), 1); - - /* enter power_trim debug mode */ - rtl8xxxu_write_rfreg_mask(priv, rfpath, RF6052_REG_GAIN_CCA, - BIT(7), 1); - - /* write enable */ - rtl8xxxu_write_rfreg_mask(priv, rfpath, RF6052_REG_WE_LUT, BIT(7), 1); - - bb_gain_for_path = (bb_gain[channel_idx] & bb_gain_path_mask[rfpath]); - bb_gain_for_path >>= __ffs(bb_gain_path_mask[rfpath]); - - rtl8xxxu_write_rfreg_mask(priv, rfpath, RF6052_REG_TXPA_G3, - 0x70000, channel_idx * 2); - rtl8xxxu_write_rfreg_mask(priv, rfpath, RF6052_REG_TXPA_G3, - 0x3f, bb_gain_for_path); - - rtl8xxxu_write_rfreg_mask(priv, rfpath, RF6052_REG_TXPA_G3, - 0x70000, channel_idx * 2 + 1); - rtl8xxxu_write_rfreg_mask(priv, rfpath, RF6052_REG_TXPA_G3, - 0x3f, bb_gain_for_path); - - /* leave power_trim debug mode */ - rtl8xxxu_write_rfreg_mask(priv, rfpath, RF6052_REG_GAIN_CCA, - BIT(7), 0); - - /* write disable */ - rtl8xxxu_write_rfreg_mask(priv, rfpath, RF6052_REG_WE_LUT, BIT(7), 0); - } -} - -static void rtl8192fu_config_channel(struct ieee80211_hw *hw) -{ - struct rtl8xxxu_priv *priv = hw->priv; - bool ht40 = conf_is_ht40(&hw->conf); - u8 channel, subchannel = 0; - bool sec_ch_above = 0; - u32 val32; - - channel = (u8)hw->conf.chandef.chan->hw_value; - - if (conf_is_ht40_plus(&hw->conf)) { - sec_ch_above = 1; - channel += 2; - subchannel = 2; - } else if (conf_is_ht40_minus(&hw->conf)) { - sec_ch_above = 0; - channel -= 2; - subchannel = 1; - } - - val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG); - - rtl8192f_revise_cck_tx_psf(priv, channel); - - /* Set channel */ - val32 &= ~(BIT(18) | BIT(17)); /* select the 2.4G band(?) */ - u32p_replace_bits(&val32, channel, 0xff); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32); - if (priv->rf_paths > 1) - rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_MODE_AG, val32); - - rtl8192fu_config_kfree(priv, channel); - - rtl8xxxu_write8(priv, REG_DATA_SUBCHANNEL, subchannel); - - /* small BW */ - rtl8xxxu_write32_clear(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, GENMASK(31, 30)); - - rtl8xxxu_write32_mask(priv, REG_FPGA0_RF_MODE, FPGA_RF_MODE, ht40); - rtl8xxxu_write32_mask(priv, REG_FPGA1_RF_MODE, FPGA_RF_MODE, ht40); - - /* ADC clock = 160M */ - rtl8xxxu_write32_mask(priv, REG_FPGA0_RF_MODE, GENMASK(10, 8), 4); - - /* DAC clock = 80M */ - rtl8xxxu_write32_mask(priv, REG_FPGA0_RF_MODE, BIT(13) | BIT(12), 2); - - /* ADC buffer clk */ - rtl8xxxu_write32_mask(priv, REG_ANTDIV_PARA1, BIT(27) | BIT(26), 2); - - if (ht40) - /* Set Control channel to upper or lower. */ - rtl8xxxu_write32_mask(priv, REG_CCK0_SYSTEM, - CCK0_SIDEBAND, !sec_ch_above); - - /* Enable CCK */ - rtl8xxxu_write32_set(priv, REG_FPGA0_RF_MODE, FPGA_RF_MODE_CCK); - - /* RF TRX_BW */ - val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG); - val32 &= ~MODE_AG_BW_MASK; - if (ht40) - val32 |= MODE_AG_BW_40MHZ_8723B; - else - val32 |= MODE_AG_BW_20MHZ_8723B; - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32); - if (priv->rf_paths > 1) - rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_MODE_AG, val32); - - /* Modify RX DFIR parameters */ - rtl8xxxu_write32_mask(priv, REG_TAP_UPD_97F, BIT(21) | BIT(20), 2); - - rtl8xxxu_write32_mask(priv, REG_DOWNSAM_FACTOR, BIT(29) | BIT(28), 2); - - if (ht40) - val32 = 0x3; - else - val32 = 0x1a3; - rtl8xxxu_write32_mask(priv, REG_RX_DFIR_MOD_97F, 0x1ff, val32); -} - -static void rtl8192fu_init_aggregation(struct rtl8xxxu_priv *priv) -{ - u32 agg_rx; - u8 agg_ctrl; - - /* RX aggregation */ - agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL); - agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN; - - agg_rx = rtl8xxxu_read32(priv, REG_RXDMA_AGG_PG_TH); - agg_rx &= ~RXDMA_USB_AGG_ENABLE; - agg_rx &= ~0xFF0F; /* reset agg size and timeout */ - - rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl); - rtl8xxxu_write32(priv, REG_RXDMA_AGG_PG_TH, agg_rx); -} - -static int rtl8192fu_parse_efuse(struct rtl8xxxu_priv *priv) -{ - struct rtl8192fu_efuse *efuse = &priv->efuse_wifi.efuse8192fu; - int i; - - if (efuse->rtl_id != cpu_to_le16(0x8129)) - return -EINVAL; - - ether_addr_copy(priv->mac_addr, efuse->mac_addr); - - memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base, - sizeof(efuse->tx_power_index_A.cck_base)); - memcpy(priv->cck_tx_power_index_B, efuse->tx_power_index_B.cck_base, - sizeof(efuse->tx_power_index_B.cck_base)); - - memcpy(priv->ht40_1s_tx_power_index_A, - efuse->tx_power_index_A.ht40_base, - sizeof(efuse->tx_power_index_A.ht40_base)); - memcpy(priv->ht40_1s_tx_power_index_B, - efuse->tx_power_index_B.ht40_base, - sizeof(efuse->tx_power_index_B.ht40_base)); - - priv->ht20_tx_power_diff[0].a = - efuse->tx_power_index_A.ht20_ofdm_1s_diff.b; - priv->ht20_tx_power_diff[0].b = - efuse->tx_power_index_B.ht20_ofdm_1s_diff.b; - - priv->ht40_tx_power_diff[0].a = 0; - priv->ht40_tx_power_diff[0].b = 0; - - for (i = 1; i < RTL8723B_TX_COUNT; i++) { - priv->ofdm_tx_power_diff[i].a = - efuse->tx_power_index_A.pwr_diff[i - 1].ofdm; - priv->ofdm_tx_power_diff[i].b = - efuse->tx_power_index_B.pwr_diff[i - 1].ofdm; - - priv->ht20_tx_power_diff[i].a = - efuse->tx_power_index_A.pwr_diff[i - 1].ht20; - priv->ht20_tx_power_diff[i].b = - efuse->tx_power_index_B.pwr_diff[i - 1].ht20; - - priv->ht40_tx_power_diff[i].a = - efuse->tx_power_index_A.pwr_diff[i - 1].ht40; - priv->ht40_tx_power_diff[i].b = - efuse->tx_power_index_B.pwr_diff[i - 1].ht40; - } - - priv->default_crystal_cap = efuse->xtal_k & 0x3f; - - priv->rfe_type = efuse->rfe_option & 0x1f; - - if (priv->rfe_type != 5 && priv->rfe_type != 1) - dev_warn(&priv->udev->dev, - "%s: RFE type %d was not tested. Please send an email to linux-wireless@vger.kernel.org about this.\n", - __func__, priv->rfe_type); - - return 0; -} - -static int rtl8192fu_load_firmware(struct rtl8xxxu_priv *priv) -{ - return rtl8xxxu_load_firmware(priv, "rtlwifi/rtl8192fufw.bin"); -} - -static void rtl8192fu_init_phy_bb(struct rtl8xxxu_priv *priv) -{ - /* Enable BB and RF */ - rtl8xxxu_write16_set(priv, REG_SYS_FUNC, - SYS_FUNC_BBRSTB | SYS_FUNC_BB_GLB_RSTN); - - rtl8xxxu_write8(priv, REG_RF_CTRL, RF_ENABLE | RF_RSTB | RF_SDMRSTB); - - /* To Fix MAC loopback mode fail. */ - rtl8xxxu_write8(priv, REG_LDOHCI12_CTRL, 0xf); - rtl8xxxu_write8(priv, REG_SYS_SWR_CTRL2 + 1, 0xe9); - - rtl8xxxu_init_phy_regs(priv, rtl8192fu_phy_init_table); - - rtl8xxxu_init_phy_regs(priv, rtl8192f_agc_table); -} - -static int rtl8192fu_init_phy_rf(struct rtl8xxxu_priv *priv) -{ - int ret; - - ret = rtl8xxxu_init_phy_rf(priv, rtl8192fu_radioa_init_table, RF_A); - if (ret) - return ret; - - return rtl8xxxu_init_phy_rf(priv, rtl8192fu_radiob_init_table, RF_B); -} - -static void rtl8192f_phy_lc_calibrate(struct rtl8xxxu_priv *priv) -{ - u32 backup_mask = BIT(31) | BIT(30); - u32 backup; - u32 val32; - - /* Aries's NarrowBand */ - val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT); - backup = u32_get_bits(val32, backup_mask); - - u32p_replace_bits(&val32, 0, backup_mask); - rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32); - - rtl8188f_phy_lc_calibrate(priv); - - /* Aries's NarrowBand */ - val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT); - u32p_replace_bits(&val32, backup, backup_mask); - rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32); - - /* reset OFDM state */ - rtl8xxxu_write32_clear(priv, REG_FPGA0_RF_MODE, FPGA_RF_MODE_OFDM); - rtl8xxxu_write32_set(priv, REG_FPGA0_RF_MODE, FPGA_RF_MODE_OFDM); -} - -static int rtl8192fu_iqk_path_a(struct rtl8xxxu_priv *priv) -{ - u32 reg_eac, reg_e94, reg_e9c, val32; - u32 rf_0x58_i, rf_0x58_q; - u8 rfe = priv->rfe_type; - int result = 0; - int ktime, i; - - /* Leave IQK mode */ - rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); - - rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xccf000c0); - rtl8xxxu_write32(priv, REG_ANAPWR1, 0x44ffbb44); - rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00400040); - rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x6f005403); - rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000804e4); - rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x04203400); - rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100); - - rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_GAIN_CCA, BIT(4), 1); - rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_GAIN_CCA, BIT(11), 1); - if (rfe == 7 || rfe == 8 || rfe == 9 || rfe == 12) - val32 = 0x30; - else - val32 = 0xe9; - rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_PAD_TXG, 0x003ff, val32); - - rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000); - - /* path-A IQK setting */ - rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); - rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); - rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); - rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); - - rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x8214000f); - rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28140000); - - rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); - rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); - - /* LO calibration setting */ - rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00e62911); - - /* One shot, path A LOK & IQK */ - rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa005800); - rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8005800); - - mdelay(15); - - ktime = 0; - while (rtl8xxxu_read32(priv, REG_IQK_RPT_TXA) == 0 && ktime < 21) { - mdelay(5); - ktime += 5; - } - - /* Check failed */ - reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); - reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); - reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); - - /* reload 0xdf and CCK_IND off */ - rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); - - rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_WE_LUT, BIT(4), 1); - - val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_TXMOD); - rf_0x58_i = u32_get_bits(val32, 0xfc000); - rf_0x58_q = u32_get_bits(val32, 0x003f0); - - for (i = 0; i < 8; i++) { - rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_TXPA_G3, - 0x1c000, i); - rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_TXPA_G3, - 0x00fc0, rf_0x58_i); - rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_TXPA_G3, - 0x0003f, rf_0x58_q); - } - - rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_AC, BIT(14), 0); - rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_WE_LUT, BIT(4), 0); - rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_GAIN_CCA, 0x00810, 0); - - if (!(reg_eac & BIT(28)) && - ((reg_e94 & 0x03ff0000) != 0x01420000) && - ((reg_e9c & 0x03ff0000) != 0x00420000)) - result |= 0x01; - - return result; -} - -static int rtl8192fu_rx_iqk_path_a(struct rtl8xxxu_priv *priv) -{ - u32 reg_ea4, reg_eac, reg_e94, reg_e9c, val32; - int result = 0; - int ktime; - - /* Leave IQK mode */ - rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); - - /* PA/PAD control by 0x56, and set = 0x0 */ - rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_GAIN_CCA, BIT(1), 1); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_P1, 0); - rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_GAIN_CCA, BIT(11), 1); - rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_PAD_TXG, 0x003ff, 0x27); - - /* Enter IQK mode */ - rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000); - - /* path-A IQK setting */ - rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); - rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); - rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); - rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); - - rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160027); - rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160000); - - /* Tx IQK setting */ - rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); - rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); - - /* LO calibration setting */ - rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0086a911); - - /* One shot, path A LOK & IQK */ - rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa005800); - rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8005800); - - mdelay(15); - - ktime = 0; - while (rtl8xxxu_read32(priv, REG_IQK_RPT_TXA) == 0 && ktime < 21) { - mdelay(5); - ktime += 5; - } - - /* Check failed */ - reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); - reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); - reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); - - if (!(reg_eac & BIT(28)) && - ((reg_e94 & 0x03ff0000) != 0x01420000) && - ((reg_e9c & 0x03ff0000) != 0x00420000)) { - result |= 0x01; - } else { /* If TX not OK, ignore RX */ - /* PA/PAD controlled by 0x0 */ - rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); - - rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_GAIN_CCA, - BIT(11), 0); - - return result; - } - - val32 = 0x80007c00 | (reg_e94 & 0x3ff0000) | ((reg_e9c & 0x3ff0000) >> 16); - rtl8xxxu_write32(priv, REG_TX_IQK, val32); - - /* Modify RX IQK mode table */ - rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); - - /* PA/PAD control by 0x56, and set = 0x0 */ - rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_GAIN_CCA, BIT(1), 1); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_P1, 0); - rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_GAIN_CCA, BIT(11), 1); - rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_PAD_TXG, 0x003ff, 0x1e0); - - rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xccf000c0); - rtl8xxxu_write32(priv, REG_ANAPWR1, 0x44ffbb44); - rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00400040); - rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x6f005403); - rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000804e4); - rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x04203400); - rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100); - - /* Enter IQK mode */ - rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000); - - /* path-A IQK setting */ - rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); - rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c); - rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); - rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); - - rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82170000); - rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28170000); - - /* RX IQK setting */ - rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); - - /* LO calibration setting */ - rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a8d1); - - /* One shot, path A LOK & IQK */ - rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa005800); - rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8005800); - - mdelay(15); - - ktime = 0; - while (rtl8xxxu_read32(priv, REG_IQK_RPT_RXA) == 0 && ktime < 21) { - mdelay(5); - ktime += 5; - } - - /* Check failed */ - reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); - reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); - - /* Leave IQK mode */ - rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); - - rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_GAIN_CCA, BIT(11), 0); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_P1, 0x02000); - - if (!(reg_eac & BIT(27)) && - ((reg_ea4 & 0x03ff0000) != 0x01320000) && - ((reg_eac & 0x03ff0000) != 0x00360000)) - result |= 0x02; - - return result; -} - -static int rtl8192fu_iqk_path_b(struct rtl8xxxu_priv *priv) -{ - u32 reg_eac, reg_eb4, reg_ebc, val32; - u32 rf_0x58_i, rf_0x58_q; - u8 rfe = priv->rfe_type; - int result = 0; - int ktime, i; - - /* PA/PAD controlled by 0x0 */ - rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); - - rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xccf000c0); - rtl8xxxu_write32(priv, REG_ANAPWR1, 0x44ffbb44); - rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00400040); - rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x6f005403); - rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000804e4); - rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x04203400); - rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000000); - - rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_GAIN_CCA, BIT(4), 1); - rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_GAIN_CCA, BIT(11), 1); - if (rfe == 7 || rfe == 8 || rfe == 9 || rfe == 12) - rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_PAD_TXG, - 0x003ff, 0x30); - else - rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_PAD_TXG, - 0x00fff, 0xe9); - - rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000); - - /* Path B IQK setting */ - rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); - rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); - rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x18008c1c); - rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); - - rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x8214000F); - rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28140000); - - rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); - rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); - - /* LO calibration setting */ - rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00e62911); - - /* One shot, path B LOK & IQK */ - rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa005800); - rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8005800); - - mdelay(15); - - ktime = 0; - while (rtl8xxxu_read32(priv, REG_IQK_RPT_TXB) == 0 && ktime < 21) { - mdelay(5); - ktime += 5; - } - - /* Check failed */ - reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); - reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); - reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); - - /* reload 0xdf and CCK_IND off */ - rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); - - rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_WE_LUT, BIT(4), 1); - - val32 = rtl8xxxu_read_rfreg(priv, RF_B, RF6052_REG_TXMOD); - rf_0x58_i = u32_get_bits(val32, 0xfc000); - rf_0x58_q = u32_get_bits(val32, 0x003f0); - - for (i = 0; i < 8; i++) { - rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_TXPA_G3, - 0x1c000, i); - rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_TXPA_G3, - 0x00fc0, rf_0x58_i); - rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_TXPA_G3, - 0x0003f, rf_0x58_q); - } - - rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_AC, BIT(14), 0); - rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_WE_LUT, BIT(4), 0); - rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_GAIN_CCA, 0x00810, 0); - - if (!(reg_eac & BIT(31)) && - ((reg_eb4 & 0x03ff0000) != 0x01420000) && - ((reg_ebc & 0x03ff0000) != 0x00420000)) - result |= 0x01; - else - dev_warn(&priv->udev->dev, "%s: Path B IQK failed!\n", - __func__); - - return result; -} - -static int rtl8192fu_rx_iqk_path_b(struct rtl8xxxu_priv *priv) -{ - u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc, val32; - int result = 0; - int ktime; - - /* Leave IQK mode */ - rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); - - rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_GAIN_CCA, BIT(1), 1); - rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_P1, 0); - rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_GAIN_CCA, BIT(11), 1); - rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_PAD_TXG, 0x003ff, 0x67); - - rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xccf000c0); - rtl8xxxu_write32(priv, REG_ANAPWR1, 0x44ffbb44); - rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00400040); - rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x6f005403); - rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000804e4); - rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x04203400); - rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000000); - - rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000); - - /* path-B IQK setting */ - rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); - rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); - rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x18008c1c); - rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); - - rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82160027); - rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160000); - - /* LO calibration setting */ - rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0086a911); - - /* One shot, path A LOK & IQK */ - rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa005800); - rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8005800); - - mdelay(15); - - ktime = 0; - while (rtl8xxxu_read32(priv, REG_IQK_RPT_TXB) == 0 && ktime < 21) { - mdelay(5); - ktime += 5; - } - - /* Check failed */ - reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); - reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); - reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); - - if (!(reg_eac & BIT(31)) && - ((reg_eb4 & 0x03ff0000) != 0x01420000) && - ((reg_ebc & 0x03ff0000) != 0x00420000)) { - result |= 0x01; - } else { - /* PA/PAD controlled by 0x0 */ - rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); - - rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_GAIN_CCA, - BIT(11), 0); - - return result; - } - - val32 = 0x80007c00 | (reg_eb4 & 0x03ff0000) | ((reg_ebc >> 16) & 0x03ff); - rtl8xxxu_write32(priv, REG_TX_IQK, val32); - - /* Modify RX IQK mode table */ - rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); - - rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_GAIN_CCA, BIT(1), 1); - rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_P1, 0); - rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_GAIN_CCA, BIT(11), 1); - rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_PAD_TXG, 0x003ff, 0x1e0); - - rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xccf000c0); - rtl8xxxu_write32(priv, REG_ANAPWR1, 0x44ffbb44); - rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00400040); - rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x6f005403); - rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000804e4); - rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x04203400); - rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000000); - - rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000); - - /* Path B IQK setting */ - rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); - rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); - rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); - rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x18008c1c); - - rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82170000); - rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28170000); - - /* IQK setting */ - rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); - - /* LO calibration setting */ - rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911); - - /* One shot, path A LOK & IQK */ - rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa005800); - rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8005800); - - mdelay(15); - - ktime = 0; - while (rtl8xxxu_read32(priv, REG_IQK_RPT_RXB) == 0 && ktime < 21) { - mdelay(5); - ktime += 5; - } - - reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); - reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2); - reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2); - - rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); - rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100); - - rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_GAIN_CCA, BIT(11), 0); - rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_GAIN_CCA, BIT(1), 0); - rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_P1, 0x02000); - - if (!(reg_eac & BIT(30)) && - ((reg_ec4 & 0x03ff0000) != 0x01320000) && - ((reg_ecc & 0x03ff0000) != 0x00360000)) - result |= 0x02; - else - dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n", - __func__); - - return result; -} - -static void rtl8192fu_phy_iqcalibrate(struct rtl8xxxu_priv *priv, - int result[][8], int t) -{ - static const u32 adda_regs[2] = { - REG_ANAPWR1, REG_RX_WAIT_CCA - }; - static const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = { - REG_TXPAUSE, REG_BEACON_CTRL, - REG_BEACON_CTRL_1, REG_GPIO_MUXCFG - }; - static const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = { - REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR, - REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, - REG_DPDT_CTRL, REG_RFE_CTRL_ANTA_SRC, - REG_RFE_CTRL_ANT_SRC2, REG_CCK0_AFE_SETTING - }; - u32 rx_initial_gain_a, rx_initial_gain_b; - struct device *dev = &priv->udev->dev; - int path_a_ok, path_b_ok; - u8 rfe = priv->rfe_type; - int retry = 2; - u32 i, val32; - - /* - * Note: IQ calibration must be performed after loading - * PHY_REG.txt , and radio_a, radio_b.txt - */ - - rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); - - rx_initial_gain_a = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); - rx_initial_gain_b = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1); - - if (t == 0) { - /* Save ADDA parameters, turn Path A ADDA on */ - rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup, - ARRAY_SIZE(adda_regs)); - rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup); - rtl8xxxu_save_regs(priv, iqk_bb_regs, - priv->bb_backup, RTL8XXXU_BB_REGS); - } - - /* Instead of rtl8xxxu_path_adda_on */ - rtl8xxxu_write32_set(priv, REG_FPGA0_XCD_RF_PARM, BIT(31)); - - /* MAC settings */ - rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); - rtl8xxxu_write8_clear(priv, REG_GPIO_MUXCFG, GPIO_MUXCFG_IO_SEL_ENBT); - - if (rfe == 7 || rfe == 8 || rfe == 9 || rfe == 12) { - /* in ePA IQK, rfe_func_config & SW both pull down */ - /* path A */ - rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANTA_SRC, 0xF, 0x7); - rtl8xxxu_write32_mask(priv, REG_DPDT_CTRL, 0x1, 0x0); - - rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANTA_SRC, 0xF00, 0x7); - rtl8xxxu_write32_mask(priv, REG_DPDT_CTRL, 0x4, 0x0); - - rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANTA_SRC, 0xF000, 0x7); - rtl8xxxu_write32_mask(priv, REG_DPDT_CTRL, 0x8, 0x0); - - /* path B */ - rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC2, 0xF0, 0x7); - rtl8xxxu_write32_mask(priv, REG_DPDT_CTRL, 0x20000, 0x0); - - rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC2, 0xF0000, 0x7); - rtl8xxxu_write32_mask(priv, REG_DPDT_CTRL, 0x100000, 0x0); - - rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC3, 0xF000, 0x7); - rtl8xxxu_write32_mask(priv, REG_DPDT_CTRL, 0x8000000, 0x0); - } - - if (priv->rf_paths > 1) { - /* path B standby */ - rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x000000); - rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x10000); - rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000); - } - - for (i = 0; i < retry; i++) { - path_a_ok = rtl8192fu_iqk_path_a(priv); - - if (path_a_ok == 0x01) { - val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); - result[t][0] = (val32 >> 16) & 0x3ff; - - val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); - result[t][1] = (val32 >> 16) & 0x3ff; - break; - } else { - result[t][0] = 0x100; - result[t][1] = 0x0; - } - } - - for (i = 0; i < retry; i++) { - path_a_ok = rtl8192fu_rx_iqk_path_a(priv); - - if (path_a_ok == 0x03) { - val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); - result[t][2] = (val32 >> 16) & 0x3ff; - - val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); - result[t][3] = (val32 >> 16) & 0x3ff; - break; - } else { - result[t][2] = 0x100; - result[t][3] = 0x0; - } - } - - if (!path_a_ok) - dev_warn(dev, "%s: Path A IQK failed!\n", __func__); - - if (priv->rf_paths > 1) { - for (i = 0; i < retry; i++) { - path_b_ok = rtl8192fu_iqk_path_b(priv); - - if (path_b_ok == 0x01) { - val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); - result[t][4] = (val32 >> 16) & 0x3ff; - - val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); - result[t][5] = (val32 >> 16) & 0x3ff; - break; - } else { - result[t][4] = 0x100; - result[t][5] = 0x0; - } - } - - for (i = 0; i < retry; i++) { - path_b_ok = rtl8192fu_rx_iqk_path_b(priv); - - if (path_b_ok == 0x03) { - val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2); - result[t][6] = (val32 >> 16) & 0x3ff; - - val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2); - result[t][7] = (val32 >> 16) & 0x3ff; - break; - } else { - result[t][6] = 0x100; - result[t][7] = 0x0; - } - } - - if (!path_b_ok) - dev_warn(dev, "%s: Path B IQK failed!\n", __func__); - } - - /* Back to BB mode, load original value */ - rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); - - rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xcc0000c0); - - rtl8xxxu_write32(priv, REG_ANAPWR1, 0x44bbbb44); - rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x80408040); - rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x6f005433); - rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000004e4); - rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x04003400); - rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100); - - /* Reload ADDA power saving parameters */ - rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup, - ARRAY_SIZE(adda_regs)); - - /* Reload MAC parameters */ - rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup); - - /* Reload BB parameters */ - rtl8xxxu_restore_regs(priv, iqk_bb_regs, priv->bb_backup, RTL8XXXU_BB_REGS); - - rtl8xxxu_write32_clear(priv, REG_FPGA0_XCD_RF_PARM, BIT(31)); - - /* Restore RX initial gain */ - rtl8xxxu_write32_mask(priv, REG_OFDM0_XA_AGC_CORE1, 0xff, 0x50); - rtl8xxxu_write32_mask(priv, REG_OFDM0_XA_AGC_CORE1, 0xff, - rx_initial_gain_a & 0xff); - if (priv->rf_paths > 1) { - rtl8xxxu_write32_mask(priv, REG_OFDM0_XB_AGC_CORE1, 0xff, 0x50); - rtl8xxxu_write32_mask(priv, REG_OFDM0_XB_AGC_CORE1, 0xff, - rx_initial_gain_b & 0xff); - } -} - -static void rtl8192fu_phy_iq_calibrate(struct rtl8xxxu_priv *priv) -{ - s32 reg_e94, reg_e9c, reg_ea4, reg_eac; - s32 reg_eb4, reg_ebc, reg_ec4, reg_ecc; - struct device *dev = &priv->udev->dev; - u32 path_a_0xdf, path_a_0x35; - u32 path_b_0xdf, path_b_0x35; - bool path_a_ok, path_b_ok; - u8 rfe = priv->rfe_type; - u32 rfe_path_select; - int result[4][8]; /* last is final result */ - int i, candidate; - s32 reg_tmp = 0; - bool simu; - u32 val32; - - rfe_path_select = rtl8xxxu_read32(priv, REG_RFE_PATH_SELECT); - - path_a_0xdf = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA); - path_a_0x35 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_GAIN_P1); - path_b_0xdf = rtl8xxxu_read_rfreg(priv, RF_B, RF6052_REG_GAIN_CCA); - path_b_0x35 = rtl8xxxu_read_rfreg(priv, RF_B, RF6052_REG_GAIN_P1); - - memset(result, 0, sizeof(result)); - candidate = -1; - - path_a_ok = false; - path_b_ok = false; - - for (i = 0; i < 3; i++) { - rtl8192fu_phy_iqcalibrate(priv, result, i); - - if (i == 1) { - simu = rtl8xxxu_gen2_simularity_compare(priv, result, 0, 1); - if (simu) { - candidate = 0; - break; - } - } - - if (i == 2) { - simu = rtl8xxxu_gen2_simularity_compare(priv, result, 0, 2); - if (simu) { - candidate = 0; - break; - } - - simu = rtl8xxxu_gen2_simularity_compare(priv, result, 1, 2); - if (simu) { - candidate = 1; - } else { - for (i = 0; i < 8; i++) - reg_tmp += result[3][i]; - - if (reg_tmp) - candidate = 3; - else - candidate = -1; - } - } - } - - if (candidate >= 0) { - reg_e94 = result[candidate][0]; - reg_e9c = result[candidate][1]; - reg_ea4 = result[candidate][2]; - reg_eac = result[candidate][3]; - reg_eb4 = result[candidate][4]; - reg_ebc = result[candidate][5]; - reg_ec4 = result[candidate][6]; - reg_ecc = result[candidate][7]; - - dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate); - dev_dbg(dev, "%s: e94=%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x ecc=%c\n", - __func__, reg_e94, reg_e9c, reg_ea4, reg_eac, - reg_eb4, reg_ebc, reg_ec4, reg_ecc); - - path_a_ok = true; - path_b_ok = true; - } - - rtl8xxxu_write32_mask(priv, REG_TX_IQK_TONE_A, 0x3ff00000, 0x100); - rtl8xxxu_write32_mask(priv, REG_NP_ANTA, 0x3ff, 0); - rtl8xxxu_write32_mask(priv, REG_TX_IQK_TONE_B, 0x3ff00000, 0x100); - rtl8xxxu_write32_mask(priv, REG_TAP_UPD_97F, 0x3ff, 0); - - if (candidate >= 0) { - if (reg_e94) - rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result, - candidate, (reg_ea4 == 0)); - - if (reg_eb4) - rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result, - candidate, (reg_ec4 == 0)); - } - - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, path_a_0xdf); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_P1, path_a_0x35); - rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_CCA, path_b_0xdf); - rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_P1, path_b_0x35); - - if (rfe == 7 || rfe == 8 || rfe == 9 || rfe == 12) { - rtl8xxxu_write32_set(priv, REG_SW_GPIO_SHARE_CTRL_1, 0x70000); - rtl8xxxu_write32_clear(priv, REG_LEDCFG0, 0x6c00000); - rtl8xxxu_write32_set(priv, REG_PAD_CTRL1, BIT(29) | BIT(28)); - rtl8xxxu_write32_clear(priv, REG_SW_GPIO_SHARE_CTRL_0, - 0x600000 | BIT(4)); - - /* - * Originally: - * odm_set_bb_reg(dm, R_0x944, BIT(11) | 0x1F, 0x3F); - * - * It clears bit 11 and sets bits 0..4. The mask doesn't cover - * bit 5 so it's not modified. Is that what it's supposed to - * accomplish? - */ - val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER); - val32 &= ~BIT(11); - val32 |= 0x1f; - rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32); - - if (rfe == 7) { - rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANTA_SRC, - 0xfffff, 0x23200); - rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC2, - 0xfffff, 0x23200); - rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC1, - 0xf000, 0x3); - rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC3, - 0xf000, 0x3); - } else { - rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANTA_SRC, - 0xfffff, 0x22200); - rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC2, - 0xfffff, 0x22200); - rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC1, - 0xf000, 0x2); - rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC3, - 0xf000, 0x2); - } - - rtl8xxxu_write32_clear(priv, REG_RFE_OPT62, BIT(2)); - - if (rfe == 7) - rtl8xxxu_write32(priv, REG_RFE_OPT, 0x03000003); - - rtl8xxxu_write32(priv, REG_RFE_PATH_SELECT, rfe_path_select); - } -} - -static void rtl8192fu_disabled_to_emu(struct rtl8xxxu_priv *priv) -{ - rtl8xxxu_write16_clear(priv, REG_APS_FSMCO, - APS_FSMCO_HW_POWERDOWN | APS_FSMCO_HW_SUSPEND); - - rtl8xxxu_write32_clear(priv, REG_GPIO_INTM, BIT(16)); - - rtl8xxxu_write16_clear(priv, REG_APS_FSMCO, - APS_FSMCO_PCIE | APS_FSMCO_HW_SUSPEND); -} - -static int rtl8192fu_emu_to_active(struct rtl8xxxu_priv *priv) -{ - u32 val32; - u16 val16; - int count; - - /* enable LDOA12 MACRO block for all interface */ - rtl8xxxu_write8_set(priv, REG_LDOA15_CTRL, LDOA15_ENABLE); - - /* disable BT_GPS_SEL pins */ - rtl8xxxu_write32_clear(priv, REG_PAD_CTRL1, BIT(28)); - - mdelay(1); - - /* release analog Ips to digital */ - rtl8xxxu_write8_clear(priv, REG_SYS_ISO_CTRL, SYS_ISO_ANALOG_IPS); - - val16 = APS_FSMCO_PCIE | APS_FSMCO_HW_SUSPEND | APS_FSMCO_SW_LPS; - rtl8xxxu_write16_clear(priv, REG_APS_FSMCO, val16); - - /* wait till 0x04[17] = 1 power ready */ - for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { - val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); - if (val32 & BIT(17)) - break; - - udelay(10); - } - - if (!count) - return -EBUSY; - - rtl8xxxu_write32_set(priv, REG_APS_FSMCO, APS_FSMCO_WLON_RESET); - - for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { - val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); - if ((val32 & (APS_FSMCO_MAC_ENABLE | APS_FSMCO_MAC_OFF)) == 0) - break; - - udelay(10); - } - - if (!count) - return -EBUSY; - - /* SWR OCP enable */ - rtl8xxxu_write32_set(priv, REG_AFE_MISC, BIT(18)); - - rtl8xxxu_write16_clear(priv, REG_APS_FSMCO, APS_FSMCO_HW_POWERDOWN); - - rtl8xxxu_write16_clear(priv, REG_APS_FSMCO, - APS_FSMCO_PCIE | APS_FSMCO_HW_SUSPEND); - - /* 0x7c[31]=1, LDO has max output capability */ - rtl8xxxu_write32_set(priv, REG_LDO_SW_CTRL, BIT(31)); - - rtl8xxxu_write16_set(priv, REG_APS_FSMCO, APS_FSMCO_MAC_ENABLE); - - for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { - val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); - if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) - break; - - udelay(10); - } - - if (!count) - return -EBUSY; - - /* Enable WL control XTAL setting */ - rtl8xxxu_write8_set(priv, REG_AFE_MISC, AFE_MISC_WL_XTAL_CTRL); - - /* Enable falling edge triggering interrupt */ - rtl8xxxu_write16_set(priv, REG_GPIO_INTM, GPIO_INTM_EDGE_TRIG_IRQ); - - /* Enable GPIO9 data mode */ - rtl8xxxu_write16_clear(priv, REG_GPIO_IO_SEL_2, GPIO_IO_SEL_2_GPIO09_IRQ); - - /* Enable GPIO9 input mode */ - rtl8xxxu_write16_clear(priv, REG_GPIO_IO_SEL_2, GPIO_IO_SEL_2_GPIO09_INPUT); - - /* Enable HSISR GPIO[C:0] interrupt */ - rtl8xxxu_write8_set(priv, REG_HSIMR, BIT(0)); - - /* RF HW ON/OFF Enable */ - rtl8xxxu_write8_clear(priv, REG_MULTI_FUNC_CTRL, MULTI_WIFI_HW_ROF_EN); - - /* Register Lock Disable */ - rtl8xxxu_write8_set(priv, REG_RSV_CTRL, BIT(7)); - - /* For GPIO9 internal pull high setting */ - rtl8xxxu_write16_set(priv, REG_MULTI_FUNC_CTRL, BIT(14)); - - /* reset RF path S1 */ - rtl8xxxu_write8(priv, REG_RF_CTRL, 0); - - /* reset RF path S0 */ - rtl8xxxu_write8(priv, REG_AFE_CTRL4 + 3, 0); - - /* enable RF path S1 */ - rtl8xxxu_write8(priv, REG_RF_CTRL, RF_SDMRSTB | RF_RSTB | RF_ENABLE); - - /* enable RF path S0 */ - rtl8xxxu_write8(priv, REG_AFE_CTRL4 + 3, RF_SDMRSTB | RF_RSTB | RF_ENABLE); - - /* AFE_Ctrl */ - rtl8xxxu_write8_set(priv, REG_RSVD_1, BIT(5)); - - /* AFE_Ctrl */ - rtl8xxxu_write8(priv, REG_RSVD_4, 0xcc); - - /* AFE_Ctrl 0x24[4:3]=00 for xtal gmn */ - rtl8xxxu_write8_clear(priv, REG_AFE_XTAL_CTRL, BIT(4) | BIT(3)); - - /* GPIO_A[31:0] Pull down software register */ - rtl8xxxu_write32(priv, REG_GPIO_A0, 0xffffffff); - - /* GPIO_B[7:0] Pull down software register */ - rtl8xxxu_write8(priv, REG_GPIO_B0, 0xff); - - /* Register Lock Enable */ - rtl8xxxu_write8_clear(priv, REG_RSV_CTRL, BIT(7)); - - return 0; -} - -static int rtl8192fu_active_to_emu(struct rtl8xxxu_priv *priv) -{ - u32 val32; - int count; - - /* Reset BB, RF enter Power Down mode */ - rtl8xxxu_write8_clear(priv, REG_SYS_FUNC, SYS_FUNC_BBRSTB); - - /* Enable rising edge triggering interrupt */ - rtl8xxxu_write16_clear(priv, REG_GPIO_INTM, GPIO_INTM_EDGE_TRIG_IRQ); - - /* release WLON reset */ - rtl8xxxu_write32_set(priv, REG_APS_FSMCO, APS_FSMCO_WLON_RESET); - - /* turn off MAC by HW state machine */ - rtl8xxxu_write16_set(priv, REG_APS_FSMCO, APS_FSMCO_MAC_OFF); - - for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { - val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); - if ((val32 & APS_FSMCO_MAC_OFF) == 0) - break; - - udelay(10); - } - - if (!count) - return -EBUSY; - - /* analog Ips to digital, 1:isolation */ - rtl8xxxu_write8_set(priv, REG_SYS_ISO_CTRL, SYS_ISO_ANALOG_IPS); - - /* disable LDOA12 MACRO block */ - rtl8xxxu_write8_clear(priv, REG_LDOA15_CTRL, LDOA15_ENABLE); - - return 0; -} - -static int rtl8192fu_emu_to_disabled(struct rtl8xxxu_priv *priv) -{ - u16 val16; - - /* SOP option to disable BG/MB */ - rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20); - - /* 0x04[12:11] = 2b'01 enable WL suspend */ - val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO); - val16 &= ~APS_FSMCO_PCIE; - val16 |= APS_FSMCO_HW_SUSPEND; - rtl8xxxu_write16(priv, REG_APS_FSMCO, val16); - - /* enable GPIO9 as EXT WAKEUP */ - rtl8xxxu_write32_set(priv, REG_GPIO_INTM, BIT(16)); - - return 0; -} - -static int rtl8192fu_active_to_lps(struct rtl8xxxu_priv *priv) -{ - struct device *dev = &priv->udev->dev; - u16 val16; - u32 val32; - int retry; - - /* Tx Pause */ - rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); - - retry = 100; - - /* Poll 32 bit wide REG_SCH_TX_CMD for 0 to ensure no TX is pending. */ - do { - val32 = rtl8xxxu_read32(priv, REG_SCH_TX_CMD); - if (!val32) - break; - - udelay(10); - } while (retry--); - - if (!retry) { - dev_warn(dev, "%s: Failed to flush TX queue\n", __func__); - return -EBUSY; - } - - /* Disable CCK and OFDM, clock gated */ - rtl8xxxu_write8_clear(priv, REG_SYS_FUNC, SYS_FUNC_BBRSTB); - - udelay(2); - - /* Whole BB is reset */ - rtl8xxxu_write8_clear(priv, REG_SYS_FUNC, SYS_FUNC_BB_GLB_RSTN); - - /* Reset MAC TRX */ - val16 = rtl8xxxu_read16(priv, REG_CR); - val16 &= 0xff00; - val16 |= CR_HCI_RXDMA_ENABLE | CR_HCI_TXDMA_ENABLE; - val16 &= ~CR_SECURITY_ENABLE; - rtl8xxxu_write16(priv, REG_CR, val16); - - /* Respond TxOK to scheduler */ - rtl8xxxu_write8_set(priv, REG_DUAL_TSF_RST, DUAL_TSF_TX_OK); - - return 0; -} - -static int rtl8192fu_power_on(struct rtl8xxxu_priv *priv) -{ - u16 val16; - int ret; - - rtl8xxxu_write8(priv, REG_USB_ACCESS_TIMEOUT, 0x80); - - rtl8192fu_disabled_to_emu(priv); - - ret = rtl8192fu_emu_to_active(priv); - if (ret) - return ret; - - rtl8xxxu_write16(priv, REG_CR, 0); - - val16 = rtl8xxxu_read16(priv, REG_CR); - - val16 |= CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE | - CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | - CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE | - CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE; - rtl8xxxu_write16(priv, REG_CR, val16); - - return 0; -} - -static void rtl8192fu_power_off(struct rtl8xxxu_priv *priv) -{ - rtl8xxxu_flush_fifo(priv); - - /* Stop Tx Report Timer. 0x4EC[Bit1]=b'0 */ - rtl8xxxu_write8_clear(priv, REG_TX_REPORT_CTRL, - TX_REPORT_CTRL_TIMER_ENABLE); - - /* stop rx */ - rtl8xxxu_write8(priv, REG_CR, 0x00); - - rtl8192fu_active_to_lps(priv); - - /* Reset Firmware if running in RAM */ - if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL) - rtl8xxxu_firmware_self_reset(priv); - - /* Reset MCU */ - rtl8xxxu_write16_clear(priv, REG_SYS_FUNC, SYS_FUNC_CPU_ENABLE); - - /* Reset MCU ready status */ - rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00); - - rtl8192fu_active_to_emu(priv); - rtl8192fu_emu_to_disabled(priv); -} - -static void rtl8192f_reset_8051(struct rtl8xxxu_priv *priv) -{ - rtl8xxxu_write8_clear(priv, REG_RSV_CTRL, BIT(1)); - - rtl8xxxu_write8_clear(priv, REG_RSV_CTRL + 1, BIT(0)); - - rtl8xxxu_write16_clear(priv, REG_SYS_FUNC, SYS_FUNC_CPU_ENABLE); - - rtl8xxxu_write8_clear(priv, REG_RSV_CTRL, BIT(1)); - - rtl8xxxu_write8_set(priv, REG_RSV_CTRL + 1, BIT(0)); - - rtl8xxxu_write16_set(priv, REG_SYS_FUNC, SYS_FUNC_CPU_ENABLE); -} - -static void rtl8192f_enable_rf(struct rtl8xxxu_priv *priv) -{ - u32 val32; - - rtl8xxxu_write8(priv, REG_RF_CTRL, RF_ENABLE | RF_RSTB | RF_SDMRSTB); - - val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); - val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK); - val32 |= OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B | - OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B; - rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); - - rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); -} - -static void rtl8192f_disable_rf(struct rtl8xxxu_priv *priv) -{ - u32 val32; - - val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); - val32 &= ~OFDM_RF_PATH_TX_MASK; - rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); - - /* Power down RF module */ - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0); -} - -static void rtl8192f_usb_quirks(struct rtl8xxxu_priv *priv) -{ - u16 val16; - - rtl8xxxu_gen2_usb_quirks(priv); - - val16 = rtl8xxxu_read16(priv, REG_CR); - val16 |= (CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE); - rtl8xxxu_write16(priv, REG_CR, val16); -} - -#define XTAL1 GENMASK(6, 1) -#define XTAL0 GENMASK(30, 25) - -static void rtl8192f_set_crystal_cap(struct rtl8xxxu_priv *priv, u8 crystal_cap) -{ - struct rtl8xxxu_cfo_tracking *cfo = &priv->cfo_tracking; - u32 xtal1, xtal0; - - if (crystal_cap == cfo->crystal_cap) - return; - - xtal1 = rtl8xxxu_read32(priv, REG_AFE_PLL_CTRL); - xtal0 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL); - - dev_dbg(&priv->udev->dev, - "%s: Adjusting crystal cap from 0x%x (actually 0x%x 0x%x) to 0x%x\n", - __func__, - cfo->crystal_cap, - u32_get_bits(xtal1, XTAL1), - u32_get_bits(xtal0, XTAL0), - crystal_cap); - - u32p_replace_bits(&xtal1, crystal_cap, XTAL1); - u32p_replace_bits(&xtal0, crystal_cap, XTAL0); - rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, xtal1); - rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, xtal0); - - cfo->crystal_cap = crystal_cap; -} - -static s8 rtl8192f_cck_rssi(struct rtl8xxxu_priv *priv, struct rtl8723au_phy_stats *phy_stats) -{ - struct jaguar2_phy_stats_type0 *phy_stats0 = (struct jaguar2_phy_stats_type0 *)phy_stats; - u8 lna_idx = (phy_stats0->lna_h << 3) | phy_stats0->lna_l; - u8 vga_idx = phy_stats0->vga; - s8 rx_pwr_all; - - switch (lna_idx) { - case 7: - rx_pwr_all = -44 - (2 * vga_idx); - break; - case 5: - rx_pwr_all = -28 - (2 * vga_idx); - break; - case 3: - rx_pwr_all = -10 - (2 * vga_idx); - break; - case 0: - rx_pwr_all = 14 - (2 * vga_idx); - break; - default: - rx_pwr_all = 0; - break; - } - - return rx_pwr_all; -} - -static int rtl8192fu_led_brightness_set(struct led_classdev *led_cdev, - enum led_brightness brightness) -{ - struct rtl8xxxu_priv *priv = container_of(led_cdev, - struct rtl8xxxu_priv, - led_cdev); - u32 ledcfg; - - /* Values obtained by observing the USB traffic from the Windows driver. */ - rtl8xxxu_write32(priv, REG_SW_GPIO_SHARE_CTRL_0, 0x20080); - rtl8xxxu_write32(priv, REG_SW_GPIO_SHARE_CTRL_1, 0x1b0000); - - ledcfg = rtl8xxxu_read32(priv, REG_LEDCFG0); - - /* Comfast CF-826F uses LED1. Asus USB-N13 C1 uses LED0. Set both. */ - - u32p_replace_bits(&ledcfg, LED_GPIO_ENABLE, LEDCFG0_LED2EN); - u32p_replace_bits(&ledcfg, LED_IO_MODE_OUTPUT, LEDCFG0_LED0_IO_MODE); - u32p_replace_bits(&ledcfg, LED_IO_MODE_OUTPUT, LEDCFG0_LED1_IO_MODE); - - if (brightness == LED_OFF) { - u32p_replace_bits(&ledcfg, LED_MODE_SW_CTRL, LEDCFG0_LED0CM); - u32p_replace_bits(&ledcfg, LED_SW_OFF, LEDCFG0_LED0SV); - u32p_replace_bits(&ledcfg, LED_MODE_SW_CTRL, LEDCFG0_LED1CM); - u32p_replace_bits(&ledcfg, LED_SW_OFF, LEDCFG0_LED1SV); - } else if (brightness == LED_ON) { - u32p_replace_bits(&ledcfg, LED_MODE_SW_CTRL, LEDCFG0_LED0CM); - u32p_replace_bits(&ledcfg, LED_SW_ON, LEDCFG0_LED0SV); - u32p_replace_bits(&ledcfg, LED_MODE_SW_CTRL, LEDCFG0_LED1CM); - u32p_replace_bits(&ledcfg, LED_SW_ON, LEDCFG0_LED1SV); - } else if (brightness == RTL8XXXU_HW_LED_CONTROL) { - u32p_replace_bits(&ledcfg, LED_MODE_TX_OR_RX_EVENTS, - LEDCFG0_LED0CM); - u32p_replace_bits(&ledcfg, LED_SW_OFF, LEDCFG0_LED0SV); - u32p_replace_bits(&ledcfg, LED_MODE_TX_OR_RX_EVENTS, - LEDCFG0_LED1CM); - u32p_replace_bits(&ledcfg, LED_SW_OFF, LEDCFG0_LED1SV); - } - - rtl8xxxu_write32(priv, REG_LEDCFG0, ledcfg); - - return 0; -} - -struct rtl8xxxu_fileops rtl8192fu_fops = { - .identify_chip = rtl8192fu_identify_chip, - .parse_efuse = rtl8192fu_parse_efuse, - .load_firmware = rtl8192fu_load_firmware, - .power_on = rtl8192fu_power_on, - .power_off = rtl8192fu_power_off, - .read_efuse = rtl8xxxu_read_efuse, - .reset_8051 = rtl8192f_reset_8051, - .llt_init = rtl8xxxu_auto_llt_table, - .init_phy_bb = rtl8192fu_init_phy_bb, - .init_phy_rf = rtl8192fu_init_phy_rf, - .phy_lc_calibrate = rtl8192f_phy_lc_calibrate, - .phy_iq_calibrate = rtl8192fu_phy_iq_calibrate, - .config_channel = rtl8192fu_config_channel, - .parse_rx_desc = rtl8xxxu_parse_rxdesc24, - .parse_phystats = jaguar2_rx_parse_phystats, - .init_aggregation = rtl8192fu_init_aggregation, - .init_burst = rtl8xxxu_init_burst, - .enable_rf = rtl8192f_enable_rf, - .disable_rf = rtl8192f_disable_rf, - .usb_quirks = rtl8192f_usb_quirks, - .set_tx_power = rtl8192f_set_tx_power, - .update_rate_mask = rtl8xxxu_gen2_update_rate_mask, - .report_connect = rtl8xxxu_gen2_report_connect, - .report_rssi = rtl8xxxu_gen2_report_rssi, - .fill_txdesc = rtl8xxxu_fill_txdesc_v2, - .set_crystal_cap = rtl8192f_set_crystal_cap, - .cck_rssi = rtl8192f_cck_rssi, - .led_classdev_brightness_set = rtl8192fu_led_brightness_set, - .writeN_block_size = 254, - .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc24), - .tx_desc_size = sizeof(struct rtl8xxxu_txdesc40), - .has_tx_report = 1, - .gen2_thermal_meter = 1, - .needs_full_init = 1, - .init_reg_rxfltmap = 1, - .init_reg_pkt_life_time = 1, - .init_reg_hmtfr = 1, - .ampdu_max_time = 0x5e, - .ustime_tsf_edca = 0x50, - .max_aggr_num = 0x1f1f, - .supports_ap = 1, - .max_macid_num = 128, - .max_sec_cam_num = 64, - .trxff_boundary = 0x3f3f, - .pbp_rx = PBP_PAGE_SIZE_256, - .pbp_tx = PBP_PAGE_SIZE_256, - .mactable = rtl8192f_mac_init_table, - .total_page_num = TX_TOTAL_PAGE_NUM_8192F, - .page_num_hi = TX_PAGE_NUM_HI_PQ_8192F, - .page_num_lo = TX_PAGE_NUM_LO_PQ_8192F, - .page_num_norm = TX_PAGE_NUM_NORM_PQ_8192F, -}; diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8710b.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8710b.c deleted file mode 100644 index aa27ac4f828b..000000000000 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8710b.c +++ /dev/null @@ -1,1887 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * RTL8XXXU mac80211 USB driver - 8710bu aka 8188gu specific subdriver - * - * Copyright (c) 2023 Bitterblue Smith - * - * Portions copied from existing rtl8xxxu code: - * Copyright (c) 2014 - 2017 Jes Sorensen - * - * Portions, notably calibration code: - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "rtl8xxxu.h" -#include "rtl8xxxu_regs.h" - -static const struct rtl8xxxu_reg8val rtl8710b_mac_init_table[] = { - {0x421, 0x0F}, {0x428, 0x0A}, {0x429, 0x10}, {0x430, 0x00}, - {0x431, 0x00}, {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, - {0x435, 0x05}, {0x436, 0x07}, {0x437, 0x08}, {0x43C, 0x04}, - {0x43D, 0x05}, {0x43E, 0x07}, {0x43F, 0x08}, {0x440, 0x5D}, - {0x441, 0x01}, {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, - {0x446, 0x00}, {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xF0}, - {0x44A, 0x0F}, {0x44B, 0x3E}, {0x44C, 0x10}, {0x44D, 0x00}, - {0x44E, 0x00}, {0x44F, 0x00}, {0x450, 0x00}, {0x451, 0xF0}, - {0x452, 0x0F}, {0x453, 0x00}, {0x456, 0x5E}, {0x460, 0x66}, - {0x461, 0x66}, {0x4C8, 0xFF}, {0x4C9, 0x08}, {0x4CC, 0xFF}, - {0x4CD, 0xFF}, {0x4CE, 0x01}, {0x500, 0x26}, {0x501, 0xA2}, - {0x502, 0x2F}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xA3}, - {0x506, 0x5E}, {0x507, 0x00}, {0x508, 0x2B}, {0x509, 0xA4}, - {0x50A, 0x5E}, {0x50B, 0x00}, {0x50C, 0x4F}, {0x50D, 0xA4}, - {0x50E, 0x00}, {0x50F, 0x00}, {0x512, 0x1C}, {0x514, 0x0A}, - {0x516, 0x0A}, {0x525, 0x4F}, {0x550, 0x10}, {0x551, 0x10}, - {0x559, 0x02}, {0x55C, 0x28}, {0x55D, 0xFF}, {0x605, 0x30}, - {0x608, 0x0E}, {0x609, 0x2A}, {0x620, 0xFF}, {0x621, 0xFF}, - {0x622, 0xFF}, {0x623, 0xFF}, {0x624, 0xFF}, {0x625, 0xFF}, - {0x626, 0xFF}, {0x627, 0xFF}, {0x638, 0x28}, {0x63C, 0x0A}, - {0x63D, 0x0A}, {0x63E, 0x0C}, {0x63F, 0x0C}, {0x640, 0x40}, - {0x642, 0x40}, {0x643, 0x00}, {0x652, 0xC8}, {0x66A, 0xB0}, - {0x66E, 0x05}, {0x700, 0x21}, {0x701, 0x43}, {0x702, 0x65}, - {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43}, {0x70A, 0x65}, - {0x70B, 0x87}, - {0xffff, 0xff}, -}; - -/* If updating the phy init tables, also update rtl8710b_revise_cck_tx_psf(). */ -static const struct rtl8xxxu_reg32val rtl8710bu_qfn48m_u_phy_init_table[] = { - {0x800, 0x80045700}, {0x804, 0x00000001}, - {0x808, 0x00FC8000}, {0x80C, 0x0000000A}, - {0x810, 0x10001331}, {0x814, 0x020C3D10}, - {0x818, 0x00200385}, {0x81C, 0x00000000}, - {0x820, 0x01000100}, {0x824, 0x00390204}, - {0x828, 0x00000000}, {0x82C, 0x00000000}, - {0x830, 0x00000000}, {0x834, 0x00000000}, - {0x838, 0x00000000}, {0x83C, 0x00000000}, - {0x840, 0x00010000}, {0x844, 0x00000000}, - {0x848, 0x00000000}, {0x84C, 0x00000000}, - {0x850, 0x00030000}, {0x854, 0x00000000}, - {0x858, 0x7E1A569A}, {0x85C, 0x569A569A}, - {0x860, 0x00000130}, {0x864, 0x20000000}, - {0x868, 0x00000000}, {0x86C, 0x27272700}, - {0x870, 0x00050000}, {0x874, 0x25005000}, - {0x878, 0x00000808}, {0x87C, 0x004F0201}, - {0x880, 0xB0000B1E}, {0x884, 0x00000007}, - {0x888, 0x00000000}, {0x88C, 0xCCC400C0}, - {0x890, 0x00000800}, {0x894, 0xFFFFFFFE}, - {0x898, 0x40302010}, {0x89C, 0x00706050}, - {0x900, 0x00000000}, {0x904, 0x00000023}, - {0x908, 0x00000000}, {0x90C, 0x81121111}, - {0x910, 0x00000402}, {0x914, 0x00000201}, - {0x920, 0x18C6318C}, {0x924, 0x0000018C}, - {0x948, 0x99000000}, {0x94C, 0x00000010}, - {0x950, 0x00003000}, {0x954, 0x5A880000}, - {0x958, 0x4BC6D87A}, {0x95C, 0x04EB9B79}, - {0x96C, 0x00000003}, {0x970, 0x00000000}, - {0x974, 0x00000000}, {0x978, 0x00000000}, - {0x97C, 0x13000000}, {0x980, 0x00000000}, - {0xA00, 0x00D046C8}, {0xA04, 0x80FF800C}, - {0xA08, 0x84838300}, {0xA0C, 0x2E20100F}, - {0xA10, 0x9500BB78}, {0xA14, 0x1114D028}, - {0xA18, 0x00881117}, {0xA1C, 0x89140F00}, - {0xA20, 0xE82C0001}, {0xA24, 0x64B80C1C}, - {0xA28, 0x00008810}, {0xA2C, 0x00D30000}, - {0xA70, 0x101FBF00}, {0xA74, 0x00000007}, - {0xA78, 0x00000900}, {0xA7C, 0x225B0606}, - {0xA80, 0x218075B1}, {0xA84, 0x00200000}, - {0xA88, 0x040C0000}, {0xA8C, 0x12345678}, - {0xA90, 0xABCDEF00}, {0xA94, 0x001B1B89}, - {0xA98, 0x00000000}, {0xA9C, 0x80020000}, - {0xAA0, 0x00000000}, {0xAA4, 0x0000000C}, - {0xAA8, 0xCA110058}, {0xAAC, 0x01235667}, - {0xAB0, 0x00000000}, {0xAB4, 0x20201402}, - {0xB2C, 0x00000000}, {0xC00, 0x48071D40}, - {0xC04, 0x03A05611}, {0xC08, 0x000000E4}, - {0xC0C, 0x6C6C6C6C}, {0xC10, 0x18800000}, - {0xC14, 0x40000100}, {0xC18, 0x08800000}, - {0xC1C, 0x40000100}, {0xC20, 0x00000000}, - {0xC24, 0x00000000}, {0xC28, 0x00000000}, - {0xC2C, 0x00000000}, {0xC30, 0x69E9AC4A}, - {0xC34, 0x31000040}, {0xC38, 0x21688080}, - {0xC3C, 0x0000170C}, {0xC40, 0x1F78403F}, - {0xC44, 0x00010036}, {0xC48, 0xEC020107}, - {0xC4C, 0x007F037F}, {0xC50, 0x69553420}, - {0xC54, 0x43BC0094}, {0xC58, 0x00013169}, - {0xC5C, 0x00250492}, {0xC60, 0x00280A00}, - {0xC64, 0x7112848B}, {0xC68, 0x47C074FF}, - {0xC6C, 0x00000036}, {0xC70, 0x2C7F000D}, - {0xC74, 0x020600DB}, {0xC78, 0x0000001F}, - {0xC7C, 0x00B91612}, {0xC80, 0x390000E4}, - {0xC84, 0x11F60000}, {0xC88, 0x1051B75F}, - {0xC8C, 0x20200109}, {0xC90, 0x00091521}, - {0xC94, 0x00000000}, {0xC98, 0x00121820}, - {0xC9C, 0x00007F7F}, {0xCA0, 0x00011000}, - {0xCA4, 0x800000A0}, {0xCA8, 0x84E6C606}, - {0xCAC, 0x00000060}, {0xCB0, 0x00000000}, - {0xCB4, 0x00000000}, {0xCB8, 0x00000000}, - {0xCBC, 0x28000000}, {0xCC0, 0x1051B75F}, - {0xCC4, 0x00000109}, {0xCC8, 0x000442D6}, - {0xCCC, 0x00000000}, {0xCD0, 0x000001C8}, - {0xCD4, 0x001C8000}, {0xCD8, 0x00000100}, - {0xCDC, 0x40100000}, {0xCE0, 0x00222220}, - {0xCE4, 0x10000000}, {0xCE8, 0x37644302}, - {0xCEC, 0x2F97D40C}, {0xD00, 0x04030740}, - {0xD04, 0x40020401}, {0xD08, 0x0000907F}, - {0xD0C, 0x20010201}, {0xD10, 0xA0633333}, - {0xD14, 0x3333BC53}, {0xD18, 0x7A8F5B6F}, - {0xD2C, 0xCB979975}, {0xD30, 0x00000000}, - {0xD34, 0x40608000}, {0xD38, 0x88000000}, - {0xD3C, 0xC0127353}, {0xD40, 0x00000000}, - {0xD44, 0x00000000}, {0xD48, 0x00000000}, - {0xD4C, 0x00000000}, {0xD50, 0x00006528}, - {0xD54, 0x00000000}, {0xD58, 0x00000282}, - {0xD5C, 0x30032064}, {0xD60, 0x4653DE68}, - {0xD64, 0x04518A3C}, {0xD68, 0x00002101}, - {0xE00, 0x2D2D2D2D}, {0xE04, 0x2D2D2D2D}, - {0xE08, 0x0390272D}, {0xE10, 0x2D2D2D2D}, - {0xE14, 0x2D2D2D2D}, {0xE18, 0x2D2D2D2D}, - {0xE1C, 0x2D2D2D2D}, {0xE28, 0x00000000}, - {0xE30, 0x1000DC1F}, {0xE34, 0x10008C1F}, - {0xE38, 0x02140102}, {0xE3C, 0x681604C2}, - {0xE40, 0x01007C00}, {0xE44, 0x01004800}, - {0xE48, 0xFB000000}, {0xE4C, 0x000028D1}, - {0xE50, 0x1000DC1F}, {0xE54, 0x10008C1F}, - {0xE58, 0x02140102}, {0xE5C, 0x28160D05}, - {0xE60, 0x0000C008}, {0xE68, 0x001B25A4}, - {0xE64, 0x281600A0}, {0xE6C, 0x01C00010}, - {0xE70, 0x01C00010}, {0xE74, 0x02000010}, - {0xE78, 0x02000010}, {0xE7C, 0x02000010}, - {0xE80, 0x02000010}, {0xE84, 0x01C00010}, - {0xE88, 0x02000010}, {0xE8C, 0x01C00010}, - {0xED0, 0x01C00010}, {0xED4, 0x01C00010}, - {0xED8, 0x01C00010}, {0xEDC, 0x00000010}, - {0xEE0, 0x00000010}, {0xEEC, 0x03C00010}, - {0xF14, 0x00000003}, {0xF00, 0x00100300}, - {0xF08, 0x0000800B}, {0xF0C, 0x0000F007}, - {0xF10, 0x0000A487}, {0xF1C, 0x80000064}, - {0xF38, 0x00030155}, {0xF3C, 0x0000003A}, - {0xF4C, 0x13000000}, {0xF50, 0x00000000}, - {0xF18, 0x00000000}, - {0xffff, 0xffffffff}, -}; - -/* If updating the phy init tables, also update rtl8710b_revise_cck_tx_psf(). */ -static const struct rtl8xxxu_reg32val rtl8710bu_qfn48m_s_phy_init_table[] = { - {0x800, 0x80045700}, {0x804, 0x00000001}, - {0x808, 0x00FC8000}, {0x80C, 0x0000000A}, - {0x810, 0x10001331}, {0x814, 0x020C3D10}, - {0x818, 0x00200385}, {0x81C, 0x00000000}, - {0x820, 0x01000100}, {0x824, 0x00390204}, - {0x828, 0x00000000}, {0x82C, 0x00000000}, - {0x830, 0x00000000}, {0x834, 0x00000000}, - {0x838, 0x00000000}, {0x83C, 0x00000000}, - {0x840, 0x00010000}, {0x844, 0x00000000}, - {0x848, 0x00000000}, {0x84C, 0x00000000}, - {0x850, 0x00030000}, {0x854, 0x00000000}, - {0x858, 0x7E1A569A}, {0x85C, 0x569A569A}, - {0x860, 0x00000130}, {0x864, 0x20000000}, - {0x868, 0x00000000}, {0x86C, 0x27272700}, - {0x870, 0x00050000}, {0x874, 0x25005000}, - {0x878, 0x00000808}, {0x87C, 0x004F0201}, - {0x880, 0xB0000B1E}, {0x884, 0x00000007}, - {0x888, 0x00000000}, {0x88C, 0xCCC400C0}, - {0x890, 0x00000800}, {0x894, 0xFFFFFFFE}, - {0x898, 0x40302010}, {0x89C, 0x00706050}, - {0x900, 0x00000000}, {0x904, 0x00000023}, - {0x908, 0x00000000}, {0x90C, 0x81121111}, - {0x910, 0x00000402}, {0x914, 0x00000201}, - {0x920, 0x18C6318C}, {0x924, 0x0000018C}, - {0x948, 0x99000000}, {0x94C, 0x00000010}, - {0x950, 0x00003000}, {0x954, 0x5A880000}, - {0x958, 0x4BC6D87A}, {0x95C, 0x04EB9B79}, - {0x96C, 0x00000003}, {0x970, 0x00000000}, - {0x974, 0x00000000}, {0x978, 0x00000000}, - {0x97C, 0x13000000}, {0x980, 0x00000000}, - {0xA00, 0x00D046C8}, {0xA04, 0x80FF800C}, - {0xA08, 0x84838300}, {0xA0C, 0x2A20100F}, - {0xA10, 0x9500BB78}, {0xA14, 0x1114D028}, - {0xA18, 0x00881117}, {0xA1C, 0x89140F00}, - {0xA20, 0xE82C0001}, {0xA24, 0x64B80C1C}, - {0xA28, 0x00008810}, {0xA2C, 0x00D30000}, - {0xA70, 0x101FBF00}, {0xA74, 0x00000007}, - {0xA78, 0x00000900}, {0xA7C, 0x225B0606}, - {0xA80, 0x218075B1}, {0xA84, 0x00200000}, - {0xA88, 0x040C0000}, {0xA8C, 0x12345678}, - {0xA90, 0xABCDEF00}, {0xA94, 0x001B1B89}, - {0xA98, 0x00000000}, {0xA9C, 0x80020000}, - {0xAA0, 0x00000000}, {0xAA4, 0x0000000C}, - {0xAA8, 0xCA110058}, {0xAAC, 0x01235667}, - {0xAB0, 0x00000000}, {0xAB4, 0x20201402}, - {0xB2C, 0x00000000}, {0xC00, 0x48071D40}, - {0xC04, 0x03A05611}, {0xC08, 0x000000E4}, - {0xC0C, 0x6C6C6C6C}, {0xC10, 0x18800000}, - {0xC14, 0x40000100}, {0xC18, 0x08800000}, - {0xC1C, 0x40000100}, {0xC20, 0x00000000}, - {0xC24, 0x00000000}, {0xC28, 0x00000000}, - {0xC2C, 0x00000000}, {0xC30, 0x69E9AC4A}, - {0xC34, 0x31000040}, {0xC38, 0x21688080}, - {0xC3C, 0x0000170C}, {0xC40, 0x1F78403F}, - {0xC44, 0x00010036}, {0xC48, 0xEC020107}, - {0xC4C, 0x007F037F}, {0xC50, 0x69553420}, - {0xC54, 0x43BC0094}, {0xC58, 0x00013169}, - {0xC5C, 0x00250492}, {0xC60, 0x00280A00}, - {0xC64, 0x7112848B}, {0xC68, 0x47C074FF}, - {0xC6C, 0x00000036}, {0xC70, 0x2C7F000D}, - {0xC74, 0x020600DB}, {0xC78, 0x0000001F}, - {0xC7C, 0x00B91612}, {0xC80, 0x390000E4}, - {0xC84, 0x11F60000}, {0xC88, 0x1051B75F}, - {0xC8C, 0x20200109}, {0xC90, 0x00091521}, - {0xC94, 0x00000000}, {0xC98, 0x00121820}, - {0xC9C, 0x00007F7F}, {0xCA0, 0x00011000}, - {0xCA4, 0x800000A0}, {0xCA8, 0x84E6C606}, - {0xCAC, 0x00000060}, {0xCB0, 0x00000000}, - {0xCB4, 0x00000000}, {0xCB8, 0x00000000}, - {0xCBC, 0x28000000}, {0xCC0, 0x1051B75F}, - {0xCC4, 0x00000109}, {0xCC8, 0x000442D6}, - {0xCCC, 0x00000000}, {0xCD0, 0x000001C8}, - {0xCD4, 0x001C8000}, {0xCD8, 0x00000100}, - {0xCDC, 0x40100000}, {0xCE0, 0x00222220}, - {0xCE4, 0x10000000}, {0xCE8, 0x37644302}, - {0xCEC, 0x2F97D40C}, {0xD00, 0x04030740}, - {0xD04, 0x40020401}, {0xD08, 0x0000907F}, - {0xD0C, 0x20010201}, {0xD10, 0xA0633333}, - {0xD14, 0x3333BC53}, {0xD18, 0x7A8F5B6F}, - {0xD2C, 0xCB979975}, {0xD30, 0x00000000}, - {0xD34, 0x40608000}, {0xD38, 0x88000000}, - {0xD3C, 0xC0127353}, {0xD40, 0x00000000}, - {0xD44, 0x00000000}, {0xD48, 0x00000000}, - {0xD4C, 0x00000000}, {0xD50, 0x00006528}, - {0xD54, 0x00000000}, {0xD58, 0x00000282}, - {0xD5C, 0x30032064}, {0xD60, 0x4653DE68}, - {0xD64, 0x04518A3C}, {0xD68, 0x00002101}, - {0xE00, 0x2D2D2D2D}, {0xE04, 0x2D2D2D2D}, - {0xE08, 0x0390272D}, {0xE10, 0x2D2D2D2D}, - {0xE14, 0x2D2D2D2D}, {0xE18, 0x2D2D2D2D}, - {0xE1C, 0x2D2D2D2D}, {0xE28, 0x00000000}, - {0xE30, 0x1000DC1F}, {0xE34, 0x10008C1F}, - {0xE38, 0x02140102}, {0xE3C, 0x681604C2}, - {0xE40, 0x01007C00}, {0xE44, 0x01004800}, - {0xE48, 0xFB000000}, {0xE4C, 0x000028D1}, - {0xE50, 0x1000DC1F}, {0xE54, 0x10008C1F}, - {0xE58, 0x02140102}, {0xE5C, 0x28160D05}, - {0xE60, 0x0000C008}, {0xE68, 0x001B25A4}, - {0xE64, 0x281600A0}, {0xE6C, 0x01C00010}, - {0xE70, 0x01C00010}, {0xE74, 0x02000010}, - {0xE78, 0x02000010}, {0xE7C, 0x02000010}, - {0xE80, 0x02000010}, {0xE84, 0x01C00010}, - {0xE88, 0x02000010}, {0xE8C, 0x01C00010}, - {0xED0, 0x01C00010}, {0xED4, 0x01C00010}, - {0xED8, 0x01C00010}, {0xEDC, 0x00000010}, - {0xEE0, 0x00000010}, {0xEEC, 0x03C00010}, - {0xF14, 0x00000003}, {0xF00, 0x00100300}, - {0xF08, 0x0000800B}, {0xF0C, 0x0000F007}, - {0xF10, 0x0000A487}, {0xF1C, 0x80000064}, - {0xF38, 0x00030155}, {0xF3C, 0x0000003A}, - {0xF4C, 0x13000000}, {0xF50, 0x00000000}, - {0xF18, 0x00000000}, - {0xffff, 0xffffffff}, -}; - -static const struct rtl8xxxu_reg32val rtl8710b_agc_table[] = { - {0xC78, 0xFC000001}, {0xC78, 0xFB010001}, - {0xC78, 0xFA020001}, {0xC78, 0xF9030001}, - {0xC78, 0xF8040001}, {0xC78, 0xF7050001}, - {0xC78, 0xF6060001}, {0xC78, 0xF5070001}, - {0xC78, 0xF4080001}, {0xC78, 0xF3090001}, - {0xC78, 0xF20A0001}, {0xC78, 0xF10B0001}, - {0xC78, 0xF00C0001}, {0xC78, 0xEF0D0001}, - {0xC78, 0xEE0E0001}, {0xC78, 0xED0F0001}, - {0xC78, 0xEC100001}, {0xC78, 0xEB110001}, - {0xC78, 0xEA120001}, {0xC78, 0xE9130001}, - {0xC78, 0xE8140001}, {0xC78, 0xE7150001}, - {0xC78, 0xE6160001}, {0xC78, 0xE5170001}, - {0xC78, 0xE4180001}, {0xC78, 0xE3190001}, - {0xC78, 0xE21A0001}, {0xC78, 0xE11B0001}, - {0xC78, 0xE01C0001}, {0xC78, 0xC31D0001}, - {0xC78, 0xC21E0001}, {0xC78, 0xC11F0001}, - {0xC78, 0xC0200001}, {0xC78, 0xA3210001}, - {0xC78, 0xA2220001}, {0xC78, 0xA1230001}, - {0xC78, 0xA0240001}, {0xC78, 0x86250001}, - {0xC78, 0x85260001}, {0xC78, 0x84270001}, - {0xC78, 0x83280001}, {0xC78, 0x82290001}, - {0xC78, 0x812A0001}, {0xC78, 0x802B0001}, - {0xC78, 0x632C0001}, {0xC78, 0x622D0001}, - {0xC78, 0x612E0001}, {0xC78, 0x602F0001}, - {0xC78, 0x42300001}, {0xC78, 0x41310001}, - {0xC78, 0x40320001}, {0xC78, 0x23330001}, - {0xC78, 0x22340001}, {0xC78, 0x21350001}, - {0xC78, 0x20360001}, {0xC78, 0x02370001}, - {0xC78, 0x01380001}, {0xC78, 0x00390001}, - {0xC78, 0x003A0001}, {0xC78, 0x003B0001}, - {0xC78, 0x003C0001}, {0xC78, 0x003D0001}, - {0xC78, 0x003E0001}, {0xC78, 0x003F0001}, - {0xC78, 0xF7400001}, {0xC78, 0xF7410001}, - {0xC78, 0xF7420001}, {0xC78, 0xF7430001}, - {0xC78, 0xF7440001}, {0xC78, 0xF7450001}, - {0xC78, 0xF7460001}, {0xC78, 0xF7470001}, - {0xC78, 0xF7480001}, {0xC78, 0xF6490001}, - {0xC78, 0xF34A0001}, {0xC78, 0xF24B0001}, - {0xC78, 0xF14C0001}, {0xC78, 0xF04D0001}, - {0xC78, 0xD14E0001}, {0xC78, 0xD04F0001}, - {0xC78, 0xB5500001}, {0xC78, 0xB4510001}, - {0xC78, 0xB3520001}, {0xC78, 0xB2530001}, - {0xC78, 0xB1540001}, {0xC78, 0xB0550001}, - {0xC78, 0xAF560001}, {0xC78, 0xAE570001}, - {0xC78, 0xAD580001}, {0xC78, 0xAC590001}, - {0xC78, 0xAB5A0001}, {0xC78, 0xAA5B0001}, - {0xC78, 0xA95C0001}, {0xC78, 0xA85D0001}, - {0xC78, 0xA75E0001}, {0xC78, 0xA65F0001}, - {0xC78, 0xA5600001}, {0xC78, 0xA4610001}, - {0xC78, 0xA3620001}, {0xC78, 0xA2630001}, - {0xC78, 0xA1640001}, {0xC78, 0xA0650001}, - {0xC78, 0x87660001}, {0xC78, 0x86670001}, - {0xC78, 0x85680001}, {0xC78, 0x84690001}, - {0xC78, 0x836A0001}, {0xC78, 0x826B0001}, - {0xC78, 0x816C0001}, {0xC78, 0x806D0001}, - {0xC78, 0x636E0001}, {0xC78, 0x626F0001}, - {0xC78, 0x61700001}, {0xC78, 0x60710001}, - {0xC78, 0x42720001}, {0xC78, 0x41730001}, - {0xC78, 0x40740001}, {0xC78, 0x23750001}, - {0xC78, 0x22760001}, {0xC78, 0x21770001}, - {0xC78, 0x20780001}, {0xC78, 0x03790001}, - {0xC78, 0x027A0001}, {0xC78, 0x017B0001}, - {0xC78, 0x007C0001}, {0xC78, 0x007D0001}, - {0xC78, 0x007E0001}, {0xC78, 0x007F0001}, - {0xC50, 0x69553422}, {0xC50, 0x69553420}, - {0xffff, 0xffffffff} -}; - -static const struct rtl8xxxu_rfregval rtl8710bu_qfn48m_u_radioa_init_table[] = { - {0x00, 0x00030000}, {0x08, 0x00008400}, - {0x17, 0x00000000}, {0x18, 0x00000C01}, - {0x19, 0x000739D2}, {0x1C, 0x00000C4C}, - {0x1B, 0x00000C6C}, {0x1E, 0x00080009}, - {0x1F, 0x00000880}, {0x2F, 0x0001A060}, - {0x3F, 0x00015000}, {0x42, 0x000060C0}, - {0x57, 0x000D0000}, {0x58, 0x000C0160}, - {0x67, 0x00001552}, {0x83, 0x00000000}, - {0xB0, 0x000FF9F0}, {0xB1, 0x00010018}, - {0xB2, 0x00054C00}, {0xB4, 0x0004486B}, - {0xB5, 0x0000112A}, {0xB6, 0x0000053E}, - {0xB7, 0x00014408}, {0xB8, 0x00010200}, - {0xB9, 0x00080801}, {0xBA, 0x00040001}, - {0xBB, 0x00000400}, {0xBF, 0x000C0000}, - {0xC2, 0x00002400}, {0xC3, 0x00000009}, - {0xC4, 0x00040C91}, {0xC5, 0x00099999}, - {0xC6, 0x000000A3}, {0xC7, 0x00088820}, - {0xC8, 0x00076C06}, {0xC9, 0x00000000}, - {0xCA, 0x00080000}, {0xDF, 0x00000180}, - {0xEF, 0x000001A8}, {0x3D, 0x00000003}, - {0x3D, 0x00080003}, {0x51, 0x000F1E69}, - {0x52, 0x000FBF6C}, {0x53, 0x0000032F}, - {0x54, 0x00055007}, {0x56, 0x000517F0}, - {0x35, 0x000000F4}, {0x35, 0x00000179}, - {0x35, 0x000002F4}, {0x36, 0x00000BF8}, - {0x36, 0x00008BF8}, {0x36, 0x00010BF8}, - {0x36, 0x00018BF8}, {0x18, 0x00000C01}, - {0x5A, 0x00048000}, {0x5A, 0x00048000}, - {0x34, 0x0000ADF5}, {0x34, 0x00009DF2}, - {0x34, 0x00008DEF}, {0x34, 0x00007DEC}, - {0x34, 0x00006DE9}, {0x34, 0x00005CEC}, - {0x34, 0x00004CE9}, {0x34, 0x00003C6C}, - {0x34, 0x00002C69}, {0x34, 0x0000106E}, - {0x34, 0x0000006B}, {0x84, 0x00048000}, - {0x87, 0x00000065}, {0x8E, 0x00065540}, - {0xDF, 0x00000110}, {0x86, 0x0000002A}, - {0x8F, 0x00088000}, {0x81, 0x0003FD80}, - {0xEF, 0x00082000}, {0x3B, 0x000F0F00}, - {0x3B, 0x000E0E00}, {0x3B, 0x000DFE00}, - {0x3B, 0x000C0D00}, {0x3B, 0x000B0C00}, - {0x3B, 0x000A0500}, {0x3B, 0x00090400}, - {0x3B, 0x00080000}, {0x3B, 0x00070F00}, - {0x3B, 0x00060E00}, {0x3B, 0x00050A00}, - {0x3B, 0x00040D00}, {0x3B, 0x00030C00}, - {0x3B, 0x00020500}, {0x3B, 0x00010400}, - {0x3B, 0x00000000}, {0xEF, 0x00080000}, - {0xEF, 0x00088000}, {0x3B, 0x00000170}, - {0x3B, 0x000C0030}, {0xEF, 0x00080000}, - {0xEF, 0x00080000}, {0x30, 0x00010000}, - {0x31, 0x0000000F}, {0x32, 0x00047EFE}, - {0xEF, 0x00000000}, {0x00, 0x00010159}, - {0x18, 0x0000FC01}, {0xFE, 0x00000000}, - {0x00, 0x00033D95}, - {0xff, 0xffffffff} -}; - -static const struct rtl8xxxu_rfregval rtl8710bu_qfn48m_s_radioa_init_table[] = { - {0x00, 0x00030000}, {0x08, 0x00008400}, - {0x17, 0x00000000}, {0x18, 0x00000C01}, - {0x19, 0x000739D2}, {0x1C, 0x00000C4C}, - {0x1B, 0x00000C6C}, {0x1E, 0x00080009}, - {0x1F, 0x00000880}, {0x2F, 0x0001A060}, - {0x3F, 0x00015000}, {0x42, 0x000060C0}, - {0x57, 0x000D0000}, {0x58, 0x000C0160}, - {0x67, 0x00001552}, {0x83, 0x00000000}, - {0xB0, 0x000FF9F0}, {0xB1, 0x00010018}, - {0xB2, 0x00054C00}, {0xB4, 0x0004486B}, - {0xB5, 0x0000112A}, {0xB6, 0x0000053E}, - {0xB7, 0x00014408}, {0xB8, 0x00010200}, - {0xB9, 0x00080801}, {0xBA, 0x00040001}, - {0xBB, 0x00000400}, {0xBF, 0x000C0000}, - {0xC2, 0x00002400}, {0xC3, 0x00000009}, - {0xC4, 0x00040C91}, {0xC5, 0x00099999}, - {0xC6, 0x000000A3}, {0xC7, 0x00088820}, - {0xC8, 0x00076C06}, {0xC9, 0x00000000}, - {0xCA, 0x00080000}, {0xDF, 0x00000180}, - {0xEF, 0x000001A8}, {0x3D, 0x00000003}, - {0x3D, 0x00080003}, {0x51, 0x000F1E69}, - {0x52, 0x000FBF6C}, {0x53, 0x0000032F}, - {0x54, 0x00055007}, {0x56, 0x000517F0}, - {0x35, 0x000000F4}, {0x35, 0x00000179}, - {0x35, 0x000002F4}, {0x36, 0x00000BF8}, - {0x36, 0x00008BF8}, {0x36, 0x00010BF8}, - {0x36, 0x00018BF8}, {0x18, 0x00000C01}, - {0x5A, 0x00048000}, {0x5A, 0x00048000}, - {0x34, 0x0000ADF5}, {0x34, 0x00009DF2}, - {0x34, 0x00008DEF}, {0x34, 0x00007DEC}, - {0x34, 0x00006DE9}, {0x34, 0x00005CEC}, - {0x34, 0x00004CE9}, {0x34, 0x00003C6C}, - {0x34, 0x00002C69}, {0x34, 0x0000106E}, - {0x34, 0x0000006B}, {0x84, 0x00048000}, - {0x87, 0x00000065}, {0x8E, 0x00065540}, - {0xDF, 0x00000110}, {0x86, 0x0000002A}, - {0x8F, 0x00088000}, {0x81, 0x0003FD80}, - {0xEF, 0x00082000}, {0x3B, 0x000F0F00}, - {0x3B, 0x000E0E00}, {0x3B, 0x000DFE00}, - {0x3B, 0x000C0D00}, {0x3B, 0x000B0C00}, - {0x3B, 0x000A0500}, {0x3B, 0x00090400}, - {0x3B, 0x00080000}, {0x3B, 0x00070F00}, - {0x3B, 0x00060E00}, {0x3B, 0x00050A00}, - {0x3B, 0x00040D00}, {0x3B, 0x00030C00}, - {0x3B, 0x00020500}, {0x3B, 0x00010400}, - {0x3B, 0x00000000}, {0xEF, 0x00080000}, - {0xEF, 0x00088000}, {0x3B, 0x000000B0}, - {0x3B, 0x000C0030}, {0xEF, 0x00080000}, - {0xEF, 0x00080000}, {0x30, 0x00010000}, - {0x31, 0x0000000F}, {0x32, 0x00047EFE}, - {0xEF, 0x00000000}, {0x00, 0x00010159}, - {0x18, 0x0000FC01}, {0xFE, 0x00000000}, - {0x00, 0x00033D95}, - {0xff, 0xffffffff} -}; - -static u32 rtl8710b_indirect_read32(struct rtl8xxxu_priv *priv, u32 addr) -{ - struct device *dev = &priv->udev->dev; - u32 val32, value = 0xffffffff; - u8 polling_count = 0xff; - - if (!IS_ALIGNED(addr, 4)) { - dev_warn(dev, "%s: Aborting because 0x%x is not a multiple of 4.\n", - __func__, addr); - return value; - } - - mutex_lock(&priv->syson_indirect_access_mutex); - - rtl8xxxu_write32(priv, REG_USB_HOST_INDIRECT_ADDR_8710B, addr); - rtl8xxxu_write32(priv, REG_EFUSE_INDIRECT_CTRL_8710B, NORMAL_REG_READ_OFFSET); - - do - val32 = rtl8xxxu_read32(priv, REG_EFUSE_INDIRECT_CTRL_8710B); - while ((val32 & BIT(31)) && (--polling_count > 0)); - - if (polling_count == 0) - dev_warn(dev, "%s: Failed to read from 0x%x, 0x806c = 0x%x\n", - __func__, addr, val32); - else - value = rtl8xxxu_read32(priv, REG_USB_HOST_INDIRECT_DATA_8710B); - - mutex_unlock(&priv->syson_indirect_access_mutex); - - if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ) - dev_info(dev, "%s(%04x) = 0x%08x\n", __func__, addr, value); - - return value; -} - -static void rtl8710b_indirect_write32(struct rtl8xxxu_priv *priv, u32 addr, u32 val) -{ - struct device *dev = &priv->udev->dev; - u8 polling_count = 0xff; - u32 val32; - - if (!IS_ALIGNED(addr, 4)) { - dev_warn(dev, "%s: Aborting because 0x%x is not a multiple of 4.\n", - __func__, addr); - return; - } - - mutex_lock(&priv->syson_indirect_access_mutex); - - rtl8xxxu_write32(priv, REG_USB_HOST_INDIRECT_ADDR_8710B, addr); - rtl8xxxu_write32(priv, REG_USB_HOST_INDIRECT_DATA_8710B, val); - rtl8xxxu_write32(priv, REG_EFUSE_INDIRECT_CTRL_8710B, NORMAL_REG_WRITE_OFFSET); - - do - val32 = rtl8xxxu_read32(priv, REG_EFUSE_INDIRECT_CTRL_8710B); - while ((val32 & BIT(31)) && (--polling_count > 0)); - - if (polling_count == 0) - dev_warn(dev, "%s: Failed to write 0x%x to 0x%x, 0x806c = 0x%x\n", - __func__, val, addr, val32); - - mutex_unlock(&priv->syson_indirect_access_mutex); - - if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE) - dev_info(dev, "%s(%04x) = 0x%08x\n", __func__, addr, val); -} - -static u32 rtl8710b_read_syson_reg(struct rtl8xxxu_priv *priv, u32 addr) -{ - return rtl8710b_indirect_read32(priv, addr | SYSON_REG_BASE_ADDR_8710B); -} - -static void rtl8710b_write_syson_reg(struct rtl8xxxu_priv *priv, u32 addr, u32 val) -{ - rtl8710b_indirect_write32(priv, addr | SYSON_REG_BASE_ADDR_8710B, val); -} - -static int rtl8710b_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data) -{ - u32 val32; - int i; - - /* Write Address */ - rtl8xxxu_write32(priv, REG_USB_HOST_INDIRECT_ADDR_8710B, offset); - - rtl8xxxu_write32(priv, REG_EFUSE_INDIRECT_CTRL_8710B, EFUSE_READ_OFFSET); - - /* Poll for data read */ - val32 = rtl8xxxu_read32(priv, REG_EFUSE_INDIRECT_CTRL_8710B); - for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) { - val32 = rtl8xxxu_read32(priv, REG_EFUSE_INDIRECT_CTRL_8710B); - if (!(val32 & BIT(31))) - break; - } - - if (i == RTL8XXXU_MAX_REG_POLL) - return -EIO; - - val32 = rtl8xxxu_read32(priv, REG_USB_HOST_INDIRECT_DATA_8710B); - - *data = val32 & 0xff; - return 0; -} - -#define EEPROM_PACKAGE_TYPE_8710B 0xF8 -#define PACKAGE_QFN48M_U 0xee -#define PACKAGE_QFN48M_S 0xfe - -static int rtl8710bu_identify_chip(struct rtl8xxxu_priv *priv) -{ - struct device *dev = &priv->udev->dev; - u32 cfg0, cfg2, vendor; - u8 package_type = 0x7; /* a nonsense value */ - - sprintf(priv->chip_name, "8710BU"); - priv->rtl_chip = RTL8710B; - priv->rf_paths = 1; - priv->rx_paths = 1; - priv->tx_paths = 1; - priv->has_wifi = 1; - - cfg0 = rtl8710b_read_syson_reg(priv, REG_SYS_SYSTEM_CFG0_8710B); - priv->chip_cut = cfg0 & 0xf; - - if (cfg0 & BIT(16)) { - dev_info(dev, "%s: Unsupported test chip\n", __func__); - return -EOPNOTSUPP; - } - - vendor = u32_get_bits(cfg0, 0xc0); - - /* SMIC and TSMC are swapped compared to rtl8xxxu_identify_vendor_2bits */ - switch (vendor) { - case 0: - sprintf(priv->chip_vendor, "SMIC"); - priv->vendor_smic = 1; - break; - case 1: - sprintf(priv->chip_vendor, "TSMC"); - break; - case 2: - sprintf(priv->chip_vendor, "UMC"); - priv->vendor_umc = 1; - break; - default: - sprintf(priv->chip_vendor, "unknown"); - break; - } - - rtl8710b_read_efuse8(priv, EEPROM_PACKAGE_TYPE_8710B, &package_type); - - if (package_type == 0xff) { - dev_warn(dev, "Package type is undefined. Assuming it based on the vendor.\n"); - - if (priv->vendor_umc) { - package_type = PACKAGE_QFN48M_U; - } else if (priv->vendor_smic) { - package_type = PACKAGE_QFN48M_S; - } else { - dev_warn(dev, "The vendor is neither UMC nor SMIC. Assuming the package type is QFN48M_U.\n"); - - /* - * In this case the vendor driver doesn't set - * the package type to anything, which is the - * same as setting it to PACKAGE_DEFAULT (0). - */ - package_type = PACKAGE_QFN48M_U; - } - } else if (package_type != PACKAGE_QFN48M_S && - package_type != PACKAGE_QFN48M_U) { - dev_warn(dev, "Failed to read the package type. Assuming it's the default QFN48M_U.\n"); - - /* - * In this case the vendor driver actually sets it to - * PACKAGE_DEFAULT, but that selects the same values - * from the init tables as PACKAGE_QFN48M_U. - */ - package_type = PACKAGE_QFN48M_U; - } - - priv->package_type = package_type; - - dev_dbg(dev, "Package type: 0x%x\n", package_type); - - cfg2 = rtl8710b_read_syson_reg(priv, REG_SYS_SYSTEM_CFG2_8710B); - priv->rom_rev = cfg2 & 0xf; - - return rtl8xxxu_config_endpoints_no_sie(priv); -} - -static void rtl8710b_revise_cck_tx_psf(struct rtl8xxxu_priv *priv, u8 channel) -{ - if (channel == 13) { - /* Normal values */ - rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER2, 0x64B80C1C); - rtl8xxxu_write32(priv, REG_CCK0_DEBUG_PORT, 0x00008810); - rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER3, 0x01235667); - /* Special value for channel 13 */ - rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER1, 0xd1d80001); - } else if (channel == 14) { - /* Special values for channel 14 */ - rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER2, 0x0000B81C); - rtl8xxxu_write32(priv, REG_CCK0_DEBUG_PORT, 0x00000000); - rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER3, 0x00003667); - /* Normal value */ - rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER1, 0xE82C0001); - } else { - /* Restore normal values from the phy init table */ - rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER2, 0x64B80C1C); - rtl8xxxu_write32(priv, REG_CCK0_DEBUG_PORT, 0x00008810); - rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER3, 0x01235667); - rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER1, 0xE82C0001); - } -} - -static void rtl8710bu_config_channel(struct ieee80211_hw *hw) -{ - struct rtl8xxxu_priv *priv = hw->priv; - bool ht40 = conf_is_ht40(&hw->conf); - u8 channel, subchannel = 0; - bool sec_ch_above = 0; - u32 val32; - u16 val16; - - channel = (u8)hw->conf.chandef.chan->hw_value; - - if (conf_is_ht40_plus(&hw->conf)) { - sec_ch_above = 1; - channel += 2; - subchannel = 2; - } else if (conf_is_ht40_minus(&hw->conf)) { - sec_ch_above = 0; - channel -= 2; - subchannel = 1; - } - - /* Set channel */ - val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG); - u32p_replace_bits(&val32, channel, MODE_AG_CHANNEL_MASK); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32); - - rtl8710b_revise_cck_tx_psf(priv, channel); - - /* Set bandwidth mode */ - val16 = rtl8xxxu_read16(priv, REG_WMAC_TRXPTCL_CTL); - val16 &= ~WMAC_TRXPTCL_CTL_BW_MASK; - if (ht40) - val16 |= WMAC_TRXPTCL_CTL_BW_40; - rtl8xxxu_write16(priv, REG_WMAC_TRXPTCL_CTL, val16); - - rtl8xxxu_write8(priv, REG_DATA_SUBCHANNEL, subchannel); - - val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); - u32p_replace_bits(&val32, ht40, FPGA_RF_MODE); - rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); - - val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); - u32p_replace_bits(&val32, ht40, FPGA_RF_MODE); - rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); - - if (ht40) { - /* Set Control channel to upper or lower. */ - val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM); - u32p_replace_bits(&val32, !sec_ch_above, CCK0_SIDEBAND); - rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32); - } - - /* RXADC CLK */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); - val32 |= GENMASK(10, 8); - rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); - - /* TXDAC CLK */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); - val32 |= BIT(14) | BIT(12); - val32 &= ~BIT(13); - rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); - - /* small BW */ - val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT); - val32 &= ~GENMASK(31, 30); - rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32); - - /* adc buffer clk */ - val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT); - val32 &= ~BIT(29); - val32 |= BIT(28); - rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32); - - /* adc buffer clk */ - val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_AFE); - val32 &= ~BIT(29); - val32 |= BIT(28); - rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_AFE, val32); - - val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE); - val32 &= ~BIT(30); - val32 |= BIT(29); - rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32); - - if (ht40) { - val32 = rtl8xxxu_read32(priv, REG_OFDM_RX_DFIR); - val32 &= ~BIT(19); - rtl8xxxu_write32(priv, REG_OFDM_RX_DFIR, val32); - - val32 = rtl8xxxu_read32(priv, REG_OFDM_RX_DFIR); - val32 &= ~GENMASK(23, 20); - rtl8xxxu_write32(priv, REG_OFDM_RX_DFIR, val32); - - val32 = rtl8xxxu_read32(priv, REG_OFDM_RX_DFIR); - val32 &= ~GENMASK(27, 24); - rtl8xxxu_write32(priv, REG_OFDM_RX_DFIR, val32); - - /* RF TRX_BW */ - val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG); - val32 &= ~MODE_AG_BW_MASK; - val32 |= MODE_AG_BW_40MHZ_8723B; - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32); - } else { - val32 = rtl8xxxu_read32(priv, REG_OFDM_RX_DFIR); - val32 |= BIT(19); - rtl8xxxu_write32(priv, REG_OFDM_RX_DFIR, val32); - - val32 = rtl8xxxu_read32(priv, REG_OFDM_RX_DFIR); - val32 &= ~GENMASK(23, 20); - val32 |= BIT(23); - rtl8xxxu_write32(priv, REG_OFDM_RX_DFIR, val32); - - val32 = rtl8xxxu_read32(priv, REG_OFDM_RX_DFIR); - val32 &= ~GENMASK(27, 24); - val32 |= BIT(27) | BIT(25); - rtl8xxxu_write32(priv, REG_OFDM_RX_DFIR, val32); - - /* RF TRX_BW */ - val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG); - val32 &= ~MODE_AG_BW_MASK; - val32 |= MODE_AG_BW_20MHZ_8723B; - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32); - } -} - -static void rtl8710bu_init_aggregation(struct rtl8xxxu_priv *priv) -{ - u32 agg_rx; - u8 agg_ctrl; - - /* RX aggregation */ - agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL); - agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN; - - agg_rx = rtl8xxxu_read32(priv, REG_RXDMA_AGG_PG_TH); - agg_rx &= ~RXDMA_USB_AGG_ENABLE; - agg_rx &= ~0xFF0F; /* reset agg size and timeout */ - - rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl); - rtl8xxxu_write32(priv, REG_RXDMA_AGG_PG_TH, agg_rx); -} - -static void rtl8710bu_init_statistics(struct rtl8xxxu_priv *priv) -{ - u32 val32; - - /* Time duration for NHM unit: 4us, 0xc350=200ms */ - rtl8xxxu_write16(priv, REG_NHM_TIMER_8723B + 2, 0xc350); - rtl8xxxu_write16(priv, REG_NHM_TH9_TH10_8723B + 2, 0xffff); - rtl8xxxu_write32(priv, REG_NHM_TH3_TO_TH0_8723B, 0xffffff50); - rtl8xxxu_write32(priv, REG_NHM_TH7_TO_TH4_8723B, 0xffffffff); - - /* TH8 */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); - val32 |= 0xff; - rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); - - /* Enable CCK */ - val32 = rtl8xxxu_read32(priv, REG_NHM_TH9_TH10_8723B); - val32 &= ~(BIT(8) | BIT(9) | BIT(10)); - val32 |= BIT(8); - rtl8xxxu_write32(priv, REG_NHM_TH9_TH10_8723B, val32); - - /* Max power amongst all RX antennas */ - val32 = rtl8xxxu_read32(priv, REG_OFDM0_FA_RSTC); - val32 |= BIT(7); - rtl8xxxu_write32(priv, REG_OFDM0_FA_RSTC, val32); -} - -static int rtl8710b_read_efuse(struct rtl8xxxu_priv *priv) -{ - struct device *dev = &priv->udev->dev; - u8 val8, word_mask, header, extheader; - u16 efuse_addr, offset; - int i, ret = 0; - u32 val32; - - val32 = rtl8710b_read_syson_reg(priv, REG_SYS_EEPROM_CTRL0_8710B); - priv->boot_eeprom = u32_get_bits(val32, EEPROM_BOOT); - priv->has_eeprom = u32_get_bits(val32, EEPROM_ENABLE); - - /* Default value is 0xff */ - memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN); - - efuse_addr = 0; - while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) { - u16 map_addr; - - ret = rtl8710b_read_efuse8(priv, efuse_addr++, &header); - if (ret || header == 0xff) - goto exit; - - if ((header & 0x1f) == 0x0f) { /* extended header */ - offset = (header & 0xe0) >> 5; - - ret = rtl8710b_read_efuse8(priv, efuse_addr++, &extheader); - if (ret) - goto exit; - - /* All words disabled */ - if ((extheader & 0x0f) == 0x0f) - continue; - - offset |= ((extheader & 0xf0) >> 1); - word_mask = extheader & 0x0f; - } else { - offset = (header >> 4) & 0x0f; - word_mask = header & 0x0f; - } - - /* Get word enable value from PG header */ - - /* We have 8 bits to indicate validity */ - map_addr = offset * 8; - for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) { - /* Check word enable condition in the section */ - if (word_mask & BIT(i)) { - map_addr += 2; - continue; - } - - ret = rtl8710b_read_efuse8(priv, efuse_addr++, &val8); - if (ret) - goto exit; - if (map_addr >= EFUSE_MAP_LEN - 1) { - dev_warn(dev, "%s: Illegal map_addr (%04x), efuse corrupt!\n", - __func__, map_addr); - ret = -EINVAL; - goto exit; - } - priv->efuse_wifi.raw[map_addr++] = val8; - - ret = rtl8710b_read_efuse8(priv, efuse_addr++, &val8); - if (ret) - goto exit; - priv->efuse_wifi.raw[map_addr++] = val8; - } - } - -exit: - - return ret; -} - -static int rtl8710bu_parse_efuse(struct rtl8xxxu_priv *priv) -{ - struct rtl8710bu_efuse *efuse = &priv->efuse_wifi.efuse8710bu; - - if (efuse->rtl_id != cpu_to_le16(0x8195)) - return -EINVAL; - - ether_addr_copy(priv->mac_addr, efuse->mac_addr); - - memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base, - sizeof(efuse->tx_power_index_A.cck_base)); - - memcpy(priv->ht40_1s_tx_power_index_A, - efuse->tx_power_index_A.ht40_base, - sizeof(efuse->tx_power_index_A.ht40_base)); - - priv->ofdm_tx_power_diff[0].a = efuse->tx_power_index_A.ht20_ofdm_1s_diff.a; - priv->ht20_tx_power_diff[0].a = efuse->tx_power_index_A.ht20_ofdm_1s_diff.b; - - priv->default_crystal_cap = efuse->xtal_k & 0x3f; - - return 0; -} - -static int rtl8710bu_load_firmware(struct rtl8xxxu_priv *priv) -{ - if (priv->vendor_smic) { - return rtl8xxxu_load_firmware(priv, "rtlwifi/rtl8710bufw_SMIC.bin"); - } else if (priv->vendor_umc) { - return rtl8xxxu_load_firmware(priv, "rtlwifi/rtl8710bufw_UMC.bin"); - } else { - dev_err(&priv->udev->dev, "We have no suitable firmware for this chip.\n"); - return -1; - } -} - -static void rtl8710bu_init_phy_bb(struct rtl8xxxu_priv *priv) -{ - const struct rtl8xxxu_reg32val *phy_init_table; - u32 val32; - - /* Enable BB and RF */ - val32 = rtl8xxxu_read32(priv, REG_SYS_FUNC_8710B); - val32 |= GENMASK(17, 16) | GENMASK(26, 24); - rtl8xxxu_write32(priv, REG_SYS_FUNC_8710B, val32); - - if (priv->package_type == PACKAGE_QFN48M_U) - phy_init_table = rtl8710bu_qfn48m_u_phy_init_table; - else - phy_init_table = rtl8710bu_qfn48m_s_phy_init_table; - - rtl8xxxu_init_phy_regs(priv, phy_init_table); - - rtl8xxxu_init_phy_regs(priv, rtl8710b_agc_table); -} - -static int rtl8710bu_init_phy_rf(struct rtl8xxxu_priv *priv) -{ - const struct rtl8xxxu_rfregval *radioa_init_table; - - if (priv->package_type == PACKAGE_QFN48M_U) - radioa_init_table = rtl8710bu_qfn48m_u_radioa_init_table; - else - radioa_init_table = rtl8710bu_qfn48m_s_radioa_init_table; - - return rtl8xxxu_init_phy_rf(priv, radioa_init_table, RF_A); -} - -static int rtl8710bu_iqk_path_a(struct rtl8xxxu_priv *priv, u32 *lok_result) -{ - u32 reg_eac, reg_e94, reg_e9c, val32, path_sel_bb; - int result = 0; - - path_sel_bb = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); - - rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x99000000); - - /* - * Leave IQK mode - */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); - u32p_replace_bits(&val32, 0, 0xffffff00); - rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); - - /* - * Enable path A PA in TX IQK mode - */ - val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); - val32 |= 0x80000; - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x20000); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0x07ff7); - - /* PA,PAD gain adjust */ - val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA); - val32 |= BIT(11); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, val32); - val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_PAD_TXG); - u32p_replace_bits(&val32, 0x1ed, 0x00fff); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_PAD_TXG, val32); - - /* enter IQK mode */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); - u32p_replace_bits(&val32, 0x808000, 0xffffff00); - rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); - - /* path-A IQK setting */ - rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); - rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); - - rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821403ff); - rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160c06); - - /* LO calibration setting */ - rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x02002911); - - /* One shot, path A LOK & IQK */ - rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000); - rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); - - mdelay(10); - - rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel_bb); - - /* - * Leave IQK mode - */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); - u32p_replace_bits(&val32, 0, 0xffffff00); - rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); - - val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA); - val32 &= ~BIT(11); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, val32); - - /* save LOK result */ - *lok_result = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_TXM_IDAC); - - /* Check failed */ - reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); - reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); - reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); - - if (!(reg_eac & BIT(28)) && - ((reg_e94 & 0x03ff0000) != 0x01420000) && - ((reg_e9c & 0x03ff0000) != 0x00420000)) - result |= 0x01; - - return result; -} - -static int rtl8710bu_rx_iqk_path_a(struct rtl8xxxu_priv *priv, u32 lok_result) -{ - u32 reg_ea4, reg_eac, reg_e94, reg_e9c, val32, path_sel_bb, tmp; - int result = 0; - - path_sel_bb = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); - - rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x99000000); - - /* - * Leave IQK mode - */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); - u32p_replace_bits(&val32, 0, 0xffffff00); - rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); - - /* modify RXIQK mode table */ - val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); - val32 |= 0x80000; - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf1173); - - /* PA,PAD gain adjust */ - val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA); - val32 |= BIT(11); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, val32); - val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_PAD_TXG); - u32p_replace_bits(&val32, 0xf, 0x003e0); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_PAD_TXG, val32); - - /* - * Enter IQK mode - */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); - u32p_replace_bits(&val32, 0x808000, 0xffffff00); - rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); - - /* path-A IQK setting */ - rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); - rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); - - rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x8216129f); - rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160c00); - - /* - * Tx IQK setting - */ - rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); - rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); - - /* LO calibration setting */ - rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911); - - /* One shot, path A LOK & IQK */ - rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); - rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); - - mdelay(10); - - /* Check failed */ - reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); - reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); - reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); - - if (!(reg_eac & BIT(28)) && - ((reg_e94 & 0x03ff0000) != 0x01420000) && - ((reg_e9c & 0x03ff0000) != 0x00420000)) { - result |= 0x01; - } else { /* If TX not OK, ignore RX */ - - /* reload RF path */ - rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel_bb); - - /* - * Leave IQK mode - */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); - u32p_replace_bits(&val32, 0, 0xffffff00); - rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); - - val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA); - val32 &= ~BIT(11); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, val32); - - return result; - } - - val32 = 0x80007c00 | (reg_e94 & 0x3ff0000) | ((reg_e9c & 0x3ff0000) >> 16); - rtl8xxxu_write32(priv, REG_TX_IQK, val32); - - /* - * Modify RX IQK mode table - */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); - u32p_replace_bits(&val32, 0, 0xffffff00); - rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); - - val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); - val32 |= 0x80000; - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7ff2); - - /* - * PA, PAD setting - */ - val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA); - val32 |= BIT(11); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, val32); - val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_PAD_TXG); - u32p_replace_bits(&val32, 0x2a, 0x00fff); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_PAD_TXG, val32); - - /* - * Enter IQK mode - */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); - u32p_replace_bits(&val32, 0x808000, 0xffffff00); - rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); - - /* - * RX IQK setting - */ - rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); - - /* path-A IQK setting */ - rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); - rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c); - - rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x2816169f); - - /* LO calibration setting */ - rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911); - - /* One shot, path A LOK & IQK */ - rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); - rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); - - mdelay(10); - - /* reload RF path */ - rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel_bb); - - /* - * Leave IQK mode - */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); - u32p_replace_bits(&val32, 0, 0xffffff00); - rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); - - val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA); - val32 &= ~BIT(11); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, val32); - - /* reload LOK value */ - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXM_IDAC, lok_result); - - /* Check failed */ - reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); - reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); - - tmp = (reg_eac & 0x03ff0000) >> 16; - if ((tmp & 0x200) > 0) - tmp = 0x400 - tmp; - - if (!(reg_eac & BIT(27)) && - ((reg_ea4 & 0x03ff0000) != 0x01320000) && - ((reg_eac & 0x03ff0000) != 0x00360000) && - (((reg_ea4 & 0x03ff0000) >> 16) < 0x11a) && - (((reg_ea4 & 0x03ff0000) >> 16) > 0xe6) && - (tmp < 0x1a)) - result |= 0x02; - - return result; -} - -static void rtl8710bu_phy_iqcalibrate(struct rtl8xxxu_priv *priv, - int result[][8], int t) -{ - struct device *dev = &priv->udev->dev; - u32 i, val32, rx_initial_gain, lok_result; - u32 path_sel_bb, path_sel_rf; - int path_a_ok; - int retry = 2; - static const u32 adda_regs[RTL8XXXU_ADDA_REGS] = { - REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH, - REG_RX_WAIT_CCA, REG_TX_CCK_RFON, - REG_TX_CCK_BBON, REG_TX_OFDM_RFON, - REG_TX_OFDM_BBON, REG_TX_TO_RX, - REG_TX_TO_TX, REG_RX_CCK, - REG_RX_OFDM, REG_RX_WAIT_RIFS, - REG_RX_TO_RX, REG_STANDBY, - REG_SLEEP, REG_PMPD_ANAEN - }; - static const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = { - REG_TXPAUSE, REG_BEACON_CTRL, - REG_BEACON_CTRL_1, REG_GPIO_MUXCFG - }; - static const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = { - REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR, - REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, - REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE, - REG_FPGA0_XB_RF_INT_OE, REG_CCK0_AFE_SETTING - }; - - /* - * Note: IQ calibration must be performed after loading - * PHY_REG.txt , and radio_a, radio_b.txt - */ - - rx_initial_gain = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); - - if (t == 0) { - /* Save ADDA parameters, turn Path A ADDA on */ - rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup, - RTL8XXXU_ADDA_REGS); - rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup); - rtl8xxxu_save_regs(priv, iqk_bb_regs, - priv->bb_backup, RTL8XXXU_BB_REGS); - } - - rtl8xxxu_path_adda_on(priv, adda_regs, true); - - if (t == 0) { - val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1); - priv->pi_enabled = u32_get_bits(val32, FPGA0_HSSI_PARM1_PI); - } - - if (!priv->pi_enabled) { - /* Switch BB to PI mode to do IQ Calibration */ - rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100); - rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100); - } - - /* MAC settings */ - val32 = rtl8xxxu_read32(priv, REG_TX_PTCL_CTRL); - val32 |= 0x00ff0000; - rtl8xxxu_write32(priv, REG_TX_PTCL_CTRL, val32); - - /* save RF path */ - path_sel_bb = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); - path_sel_rf = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_S0S1); - - /* BB setting */ - val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING); - val32 |= 0x0f000000; - rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32); - rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x03c00010); - rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05601); - rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4); - rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x25204000); - - /* IQ calibration setting */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); - u32p_replace_bits(&val32, 0x808000, 0xffffff00); - rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); - rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); - rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); - - for (i = 0; i < retry; i++) { - path_a_ok = rtl8710bu_iqk_path_a(priv, &lok_result); - - if (path_a_ok == 0x01) { - val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); - result[t][0] = (val32 >> 16) & 0x3ff; - - val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); - result[t][1] = (val32 >> 16) & 0x3ff; - break; - } else { - result[t][0] = 0x100; - result[t][1] = 0x0; - } - } - - for (i = 0; i < retry; i++) { - path_a_ok = rtl8710bu_rx_iqk_path_a(priv, lok_result); - - if (path_a_ok == 0x03) { - val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); - result[t][2] = (val32 >> 16) & 0x3ff; - - val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); - result[t][3] = (val32 >> 16) & 0x3ff; - break; - } else { - result[t][2] = 0x100; - result[t][3] = 0x0; - } - } - - if (!path_a_ok) - dev_warn(dev, "%s: Path A IQK failed!\n", __func__); - - /* Back to BB mode, load original value */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); - u32p_replace_bits(&val32, 0, 0xffffff00); - rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); - - if (t == 0) - return; - - /* Reload ADDA power saving parameters */ - rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup, RTL8XXXU_ADDA_REGS); - - /* Reload MAC parameters */ - rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup); - - /* Reload BB parameters */ - rtl8xxxu_restore_regs(priv, iqk_bb_regs, priv->bb_backup, RTL8XXXU_BB_REGS); - - /* Reload RF path */ - rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel_bb); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, path_sel_rf); - - /* Restore RX initial gain */ - val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); - u32p_replace_bits(&val32, 0x50, 0x000000ff); - rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32); - val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); - u32p_replace_bits(&val32, rx_initial_gain & 0xff, 0x000000ff); - rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32); - - /* Load 0xe30 IQC default value */ - rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00); - rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00); -} - -static void rtl8710bu_phy_iq_calibrate(struct rtl8xxxu_priv *priv) -{ - struct device *dev = &priv->udev->dev; - int result[4][8]; /* last is final result */ - int i, candidate; - bool path_a_ok; - s32 reg_e94, reg_e9c, reg_ea4, reg_eac; - s32 reg_tmp = 0; - bool simu; - u32 path_sel_bb; - - /* Save RF path */ - path_sel_bb = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); - - memset(result, 0, sizeof(result)); - candidate = -1; - - path_a_ok = false; - - for (i = 0; i < 3; i++) { - rtl8710bu_phy_iqcalibrate(priv, result, i); - - if (i == 1) { - simu = rtl8xxxu_gen2_simularity_compare(priv, result, 0, 1); - if (simu) { - candidate = 0; - break; - } - } - - if (i == 2) { - simu = rtl8xxxu_gen2_simularity_compare(priv, result, 0, 2); - if (simu) { - candidate = 0; - break; - } - - simu = rtl8xxxu_gen2_simularity_compare(priv, result, 1, 2); - if (simu) { - candidate = 1; - } else { - for (i = 0; i < 8; i++) - reg_tmp += result[3][i]; - - if (reg_tmp) - candidate = 3; - else - candidate = -1; - } - } - } - - if (candidate >= 0) { - reg_e94 = result[candidate][0]; - reg_e9c = result[candidate][1]; - reg_ea4 = result[candidate][2]; - reg_eac = result[candidate][3]; - - dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate); - dev_dbg(dev, "%s: e94=%x e9c=%x ea4=%x eac=%x\n", - __func__, reg_e94, reg_e9c, reg_ea4, reg_eac); - - path_a_ok = true; - - if (reg_e94) - rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result, - candidate, (reg_ea4 == 0)); - } - - rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg, - priv->bb_recovery_backup, RTL8XXXU_BB_REGS); - - rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel_bb); -} - -static int rtl8710b_emu_to_active(struct rtl8xxxu_priv *priv) -{ - u8 val8; - int count, ret = 0; - - /* AFE power mode selection: 1: LDO mode, 0: Power-cut mode */ - val8 = rtl8xxxu_read8(priv, 0x5d); - val8 &= ~BIT(0); - rtl8xxxu_write8(priv, 0x5d, val8); - - val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC_8710B); - val8 |= BIT(0); - rtl8xxxu_write8(priv, REG_SYS_FUNC_8710B, val8); - - rtl8xxxu_write8(priv, 0x56, 0x0e); - - val8 = rtl8xxxu_read8(priv, 0x20); - val8 |= BIT(0); - rtl8xxxu_write8(priv, 0x20, val8); - - for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { - val8 = rtl8xxxu_read8(priv, 0x20); - if (!(val8 & BIT(0))) - break; - - udelay(10); - } - - if (!count) - ret = -EBUSY; - - return ret; -} - -static int rtl8710bu_active_to_emu(struct rtl8xxxu_priv *priv) -{ - u8 val8; - u32 val32; - int count, ret = 0; - - /* Turn off RF */ - val32 = rtl8xxxu_read32(priv, REG_SYS_FUNC_8710B); - val32 &= ~GENMASK(26, 24); - rtl8xxxu_write32(priv, REG_SYS_FUNC_8710B, val32); - - /* BB reset */ - val32 = rtl8xxxu_read32(priv, REG_SYS_FUNC_8710B); - val32 &= ~GENMASK(17, 16); - rtl8xxxu_write32(priv, REG_SYS_FUNC_8710B, val32); - - /* Turn off MAC by HW state machine */ - val8 = rtl8xxxu_read8(priv, 0x20); - val8 |= BIT(1); - rtl8xxxu_write8(priv, 0x20, val8); - - for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { - val8 = rtl8xxxu_read8(priv, 0x20); - if ((val8 & BIT(1)) == 0) { - ret = 0; - break; - } - udelay(10); - } - - if (!count) - ret = -EBUSY; - - return ret; -} - -static int rtl8710bu_active_to_lps(struct rtl8xxxu_priv *priv) -{ - struct device *dev = &priv->udev->dev; - u8 val8; - u16 val16; - u32 val32; - int retry, retval; - - /* Tx Pause */ - rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); - - retry = 100; - retval = -EBUSY; - /* - * Poll 32 bit wide REG_SCH_TX_CMD for 0x00000000 to ensure no TX is pending. - */ - do { - val32 = rtl8xxxu_read32(priv, REG_SCH_TX_CMD); - if (!val32) { - retval = 0; - break; - } - udelay(10); - } while (retry--); - - if (!retry) { - dev_warn(dev, "Failed to flush TX queue\n"); - retval = -EBUSY; - return retval; - } - - /* Disable CCK and OFDM, clock gated */ - val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); - val8 &= ~SYS_FUNC_BBRSTB; - rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); - - udelay(2); - - /* Whole BB is reset */ - val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); - val8 &= ~SYS_FUNC_BB_GLB_RSTN; - rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); - - /* Reset MAC TRX */ - val16 = rtl8xxxu_read16(priv, REG_CR); - val16 &= 0xff00; - val16 |= CR_HCI_RXDMA_ENABLE | CR_HCI_TXDMA_ENABLE; - val16 &= ~CR_SECURITY_ENABLE; - rtl8xxxu_write16(priv, REG_CR, val16); - - /* Respond TxOK to scheduler */ - val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST); - val8 |= DUAL_TSF_TX_OK; - rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8); - - return retval; -} - -static int rtl8710bu_power_on(struct rtl8xxxu_priv *priv) -{ - u32 val32; - u16 val16; - u8 val8; - int ret; - - rtl8xxxu_write8(priv, REG_USB_ACCESS_TIMEOUT, 0x80); - - val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL); - val8 &= ~BIT(5); - rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8); - - val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC_8710B); - val8 |= BIT(0); - rtl8xxxu_write8(priv, REG_SYS_FUNC_8710B, val8); - - val8 = rtl8xxxu_read8(priv, 0x20); - val8 |= BIT(0); - rtl8xxxu_write8(priv, 0x20, val8); - - rtl8xxxu_write8(priv, REG_AFE_CTRL_8710B, 0); - - val8 = rtl8xxxu_read8(priv, REG_WL_STATUS_8710B); - val8 |= BIT(1); - rtl8xxxu_write8(priv, REG_WL_STATUS_8710B, val8); - - ret = rtl8710b_emu_to_active(priv); - if (ret) - return ret; - - rtl8xxxu_write16(priv, REG_CR, 0); - - val16 = rtl8xxxu_read16(priv, REG_CR); - - val16 |= CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE | - CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | - CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE | - CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE; - rtl8xxxu_write16(priv, REG_CR, val16); - - /* Enable hardware sequence number. */ - val8 = rtl8xxxu_read8(priv, REG_HWSEQ_CTRL); - val8 |= 0x7f; - rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, val8); - - udelay(2); - - /* - * Technically the rest was in the rtl8710bu_hal_init function, - * not the power_on function, but it's fine because we only - * call power_on from init_device. - */ - - val8 = rtl8xxxu_read8(priv, 0xfef9); - val8 &= ~BIT(0); - rtl8xxxu_write8(priv, 0xfef9, val8); - - /* Clear the 0x40000138[5] to prevent CM4 Suspend */ - val32 = rtl8710b_read_syson_reg(priv, 0x138); - val32 &= ~BIT(5); - rtl8710b_write_syson_reg(priv, 0x138, val32); - - return ret; -} - -static void rtl8710bu_power_off(struct rtl8xxxu_priv *priv) -{ - u32 val32; - u8 val8; - - rtl8xxxu_flush_fifo(priv); - - rtl8xxxu_write32(priv, REG_HISR0_8710B, 0xffffffff); - rtl8xxxu_write32(priv, REG_HIMR0_8710B, 0x0); - - /* Set the 0x40000138[5] to allow CM4 Suspend */ - val32 = rtl8710b_read_syson_reg(priv, 0x138); - val32 |= BIT(5); - rtl8710b_write_syson_reg(priv, 0x138, val32); - - /* Stop rx */ - rtl8xxxu_write8(priv, REG_CR, 0x00); - - rtl8710bu_active_to_lps(priv); - - /* Reset MCU ? */ - val8 = rtl8xxxu_read8(priv, REG_8051FW_CTRL_V1_8710B + 3); - val8 &= ~BIT(0); - rtl8xxxu_write8(priv, REG_8051FW_CTRL_V1_8710B + 3, val8); - - /* Reset MCU ready status */ - rtl8xxxu_write8(priv, REG_8051FW_CTRL_V1_8710B, 0x00); - - rtl8710bu_active_to_emu(priv); -} - -static void rtl8710b_reset_8051(struct rtl8xxxu_priv *priv) -{ - u8 val8; - - val8 = rtl8xxxu_read8(priv, REG_8051FW_CTRL_V1_8710B + 3); - val8 &= ~BIT(0); - rtl8xxxu_write8(priv, REG_8051FW_CTRL_V1_8710B + 3, val8); - - udelay(50); - - val8 = rtl8xxxu_read8(priv, REG_8051FW_CTRL_V1_8710B + 3); - val8 |= BIT(0); - rtl8xxxu_write8(priv, REG_8051FW_CTRL_V1_8710B + 3, val8); -} - -static void rtl8710b_enable_rf(struct rtl8xxxu_priv *priv) -{ - u32 val32; - - rtl8xxxu_write8(priv, REG_RF_CTRL, RF_ENABLE | RF_RSTB | RF_SDMRSTB); - - val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); - val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK); - val32 |= OFDM_RF_PATH_RX_A | OFDM_RF_PATH_TX_A; - rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); - - rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); -} - -static void rtl8710b_disable_rf(struct rtl8xxxu_priv *priv) -{ - u32 val32; - - val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); - val32 &= ~OFDM_RF_PATH_TX_MASK; - rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); - - /* Power down RF module */ - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0); -} - -static void rtl8710b_usb_quirks(struct rtl8xxxu_priv *priv) -{ - u16 val16; - - rtl8xxxu_gen2_usb_quirks(priv); - - val16 = rtl8xxxu_read16(priv, REG_CR); - val16 |= (CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE); - rtl8xxxu_write16(priv, REG_CR, val16); -} - -#define XTAL1 GENMASK(29, 24) -#define XTAL0 GENMASK(23, 18) - -static void rtl8710b_set_crystal_cap(struct rtl8xxxu_priv *priv, u8 crystal_cap) -{ - struct rtl8xxxu_cfo_tracking *cfo = &priv->cfo_tracking; - u32 val32; - - if (crystal_cap == cfo->crystal_cap) - return; - - val32 = rtl8710b_read_syson_reg(priv, REG_SYS_XTAL_CTRL0_8710B); - - dev_dbg(&priv->udev->dev, - "%s: Adjusting crystal cap from 0x%x (actually 0x%x 0x%x) to 0x%x\n", - __func__, - cfo->crystal_cap, - u32_get_bits(val32, XTAL1), - u32_get_bits(val32, XTAL0), - crystal_cap); - - u32p_replace_bits(&val32, crystal_cap, XTAL1); - u32p_replace_bits(&val32, crystal_cap, XTAL0); - rtl8710b_write_syson_reg(priv, REG_SYS_XTAL_CTRL0_8710B, val32); - - cfo->crystal_cap = crystal_cap; -} - -static s8 rtl8710b_cck_rssi(struct rtl8xxxu_priv *priv, struct rtl8723au_phy_stats *phy_stats) -{ - struct jaguar2_phy_stats_type0 *phy_stats0 = (struct jaguar2_phy_stats_type0 *)phy_stats; - u8 lna_idx = (phy_stats0->lna_h << 3) | phy_stats0->lna_l; - u8 vga_idx = phy_stats0->vga; - s8 rx_pwr_all = 0x00; - - switch (lna_idx) { - case 7: - rx_pwr_all = -52 - (2 * vga_idx); - break; - case 6: - rx_pwr_all = -42 - (2 * vga_idx); - break; - case 5: - rx_pwr_all = -36 - (2 * vga_idx); - break; - case 3: - rx_pwr_all = -12 - (2 * vga_idx); - break; - case 2: - rx_pwr_all = 0 - (2 * vga_idx); - break; - default: - rx_pwr_all = 0; - break; - } - - return rx_pwr_all; -} - -struct rtl8xxxu_fileops rtl8710bu_fops = { - .identify_chip = rtl8710bu_identify_chip, - .parse_efuse = rtl8710bu_parse_efuse, - .load_firmware = rtl8710bu_load_firmware, - .power_on = rtl8710bu_power_on, - .power_off = rtl8710bu_power_off, - .read_efuse = rtl8710b_read_efuse, - .reset_8051 = rtl8710b_reset_8051, - .llt_init = rtl8xxxu_auto_llt_table, - .init_phy_bb = rtl8710bu_init_phy_bb, - .init_phy_rf = rtl8710bu_init_phy_rf, - .phy_lc_calibrate = rtl8188f_phy_lc_calibrate, - .phy_iq_calibrate = rtl8710bu_phy_iq_calibrate, - .config_channel = rtl8710bu_config_channel, - .parse_rx_desc = rtl8xxxu_parse_rxdesc24, - .parse_phystats = jaguar2_rx_parse_phystats, - .init_aggregation = rtl8710bu_init_aggregation, - .init_statistics = rtl8710bu_init_statistics, - .init_burst = rtl8xxxu_init_burst, - .enable_rf = rtl8710b_enable_rf, - .disable_rf = rtl8710b_disable_rf, - .usb_quirks = rtl8710b_usb_quirks, - .set_tx_power = rtl8188f_set_tx_power, - .update_rate_mask = rtl8xxxu_gen2_update_rate_mask, - .report_connect = rtl8xxxu_gen2_report_connect, - .report_rssi = rtl8xxxu_gen2_report_rssi, - .fill_txdesc = rtl8xxxu_fill_txdesc_v2, - .set_crystal_cap = rtl8710b_set_crystal_cap, - .cck_rssi = rtl8710b_cck_rssi, - .writeN_block_size = 4, - .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc24), - .tx_desc_size = sizeof(struct rtl8xxxu_txdesc40), - .has_tx_report = 1, - .gen2_thermal_meter = 1, - .needs_full_init = 1, - .init_reg_rxfltmap = 1, - .init_reg_pkt_life_time = 1, - .init_reg_hmtfr = 1, - .ampdu_max_time = 0x5e, - /* - * The RTL8710BU vendor driver uses 0x50 here and it works fine, - * but in rtl8xxxu 0x50 causes slow upload and random packet loss. Why? - */ - .ustime_tsf_edca = 0x28, - .max_aggr_num = 0x0c14, - .supports_ap = 1, - .max_macid_num = 16, - .max_sec_cam_num = 32, - .adda_1t_init = 0x03c00016, - .adda_1t_path_on = 0x03c00016, - .trxff_boundary = 0x3f7f, - .pbp_rx = PBP_PAGE_SIZE_256, - .pbp_tx = PBP_PAGE_SIZE_256, - .mactable = rtl8710b_mac_init_table, - .total_page_num = TX_TOTAL_PAGE_NUM_8723B, - .page_num_hi = TX_PAGE_NUM_HI_PQ_8723B, - .page_num_lo = TX_PAGE_NUM_LO_PQ_8723B, - .page_num_norm = TX_PAGE_NUM_NORM_PQ_8723B, -}; diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723a.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723a.c deleted file mode 100644 index 965c8c3662a6..000000000000 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723a.c +++ /dev/null @@ -1,547 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * RTL8XXXU mac80211 USB driver - 8723a specific subdriver - * - * Copyright (c) 2014 - 2017 Jes Sorensen - * - * Portions, notably calibration code: - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This driver was written as a replacement for the vendor provided - * rtl8723au driver. As the Realtek 8xxx chips are very similar in - * their programming interface, I have started adding support for - * additional 8xxx chips like the 8192cu, 8188cus, etc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "rtl8xxxu.h" -#include "rtl8xxxu_regs.h" - -static struct rtl8xxxu_power_base rtl8723a_power_base = { - .reg_0e00 = 0x0a0c0c0c, - .reg_0e04 = 0x02040608, - .reg_0e08 = 0x00000000, - .reg_086c = 0x00000000, - - .reg_0e10 = 0x0a0c0d0e, - .reg_0e14 = 0x02040608, - .reg_0e18 = 0x0a0c0d0e, - .reg_0e1c = 0x02040608, - - .reg_0830 = 0x0a0c0c0c, - .reg_0834 = 0x02040608, - .reg_0838 = 0x00000000, - .reg_086c_2 = 0x00000000, - - .reg_083c = 0x0a0c0d0e, - .reg_0848 = 0x02040608, - .reg_084c = 0x0a0c0d0e, - .reg_0868 = 0x02040608, -}; - -static const struct rtl8xxxu_reg8val rtl8723au_mac_init_table[] = { - {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00}, - {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05}, - {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00}, - {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05}, - {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01}, - {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f}, - {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72}, - {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08}, - {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff}, - {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2}, - {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3}, - {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4}, - {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4}, - {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a}, - {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16}, - {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00}, - {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02}, - {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a}, - {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e}, - {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43}, - {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43}, - {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff}, -}; - -static const struct rtl8xxxu_rfregval rtl8723au_radioa_1t_init_table[] = { - {0x00, 0x00030159}, {0x01, 0x00031284}, - {0x02, 0x00098000}, {0x03, 0x00039c63}, - {0x04, 0x000210e7}, {0x09, 0x0002044f}, - {0x0a, 0x0001a3f1}, {0x0b, 0x00014787}, - {0x0c, 0x000896fe}, {0x0d, 0x0000e02c}, - {0x0e, 0x00039ce7}, {0x0f, 0x00000451}, - {0x19, 0x00000000}, {0x1a, 0x00030355}, - {0x1b, 0x00060a00}, {0x1c, 0x000fc378}, - {0x1d, 0x000a1250}, {0x1e, 0x0000024f}, - {0x1f, 0x00000000}, {0x20, 0x0000b614}, - {0x21, 0x0006c000}, {0x22, 0x00000000}, - {0x23, 0x00001558}, {0x24, 0x00000060}, - {0x25, 0x00000483}, {0x26, 0x0004f000}, - {0x27, 0x000ec7d9}, {0x28, 0x00057730}, - {0x29, 0x00004783}, {0x2a, 0x00000001}, - {0x2b, 0x00021334}, {0x2a, 0x00000000}, - {0x2b, 0x00000054}, {0x2a, 0x00000001}, - {0x2b, 0x00000808}, {0x2b, 0x00053333}, - {0x2c, 0x0000000c}, {0x2a, 0x00000002}, - {0x2b, 0x00000808}, {0x2b, 0x0005b333}, - {0x2c, 0x0000000d}, {0x2a, 0x00000003}, - {0x2b, 0x00000808}, {0x2b, 0x00063333}, - {0x2c, 0x0000000d}, {0x2a, 0x00000004}, - {0x2b, 0x00000808}, {0x2b, 0x0006b333}, - {0x2c, 0x0000000d}, {0x2a, 0x00000005}, - {0x2b, 0x00000808}, {0x2b, 0x00073333}, - {0x2c, 0x0000000d}, {0x2a, 0x00000006}, - {0x2b, 0x00000709}, {0x2b, 0x0005b333}, - {0x2c, 0x0000000d}, {0x2a, 0x00000007}, - {0x2b, 0x00000709}, {0x2b, 0x00063333}, - {0x2c, 0x0000000d}, {0x2a, 0x00000008}, - {0x2b, 0x0000060a}, {0x2b, 0x0004b333}, - {0x2c, 0x0000000d}, {0x2a, 0x00000009}, - {0x2b, 0x0000060a}, {0x2b, 0x00053333}, - {0x2c, 0x0000000d}, {0x2a, 0x0000000a}, - {0x2b, 0x0000060a}, {0x2b, 0x0005b333}, - {0x2c, 0x0000000d}, {0x2a, 0x0000000b}, - {0x2b, 0x0000060a}, {0x2b, 0x00063333}, - {0x2c, 0x0000000d}, {0x2a, 0x0000000c}, - {0x2b, 0x0000060a}, {0x2b, 0x0006b333}, - {0x2c, 0x0000000d}, {0x2a, 0x0000000d}, - {0x2b, 0x0000060a}, {0x2b, 0x00073333}, - {0x2c, 0x0000000d}, {0x2a, 0x0000000e}, - {0x2b, 0x0000050b}, {0x2b, 0x00066666}, - {0x2c, 0x0000001a}, {0x2a, 0x000e0000}, - {0x10, 0x0004000f}, {0x11, 0x000e31fc}, - {0x10, 0x0006000f}, {0x11, 0x000ff9f8}, - {0x10, 0x0002000f}, {0x11, 0x000203f9}, - {0x10, 0x0003000f}, {0x11, 0x000ff500}, - {0x10, 0x00000000}, {0x11, 0x00000000}, - {0x10, 0x0008000f}, {0x11, 0x0003f100}, - {0x10, 0x0009000f}, {0x11, 0x00023100}, - {0x12, 0x00032000}, {0x12, 0x00071000}, - {0x12, 0x000b0000}, {0x12, 0x000fc000}, - {0x13, 0x000287b3}, {0x13, 0x000244b7}, - {0x13, 0x000204ab}, {0x13, 0x0001c49f}, - {0x13, 0x00018493}, {0x13, 0x0001429b}, - {0x13, 0x00010299}, {0x13, 0x0000c29c}, - {0x13, 0x000081a0}, {0x13, 0x000040ac}, - {0x13, 0x00000020}, {0x14, 0x0001944c}, - {0x14, 0x00059444}, {0x14, 0x0009944c}, - {0x14, 0x000d9444}, {0x15, 0x0000f474}, - {0x15, 0x0004f477}, {0x15, 0x0008f455}, - {0x15, 0x000cf455}, {0x16, 0x00000339}, - {0x16, 0x00040339}, {0x16, 0x00080339}, - {0x16, 0x000c0366}, {0x00, 0x00010159}, - {0x18, 0x0000f401}, {0xfe, 0x00000000}, - {0xfe, 0x00000000}, {0x1f, 0x00000003}, - {0xfe, 0x00000000}, {0xfe, 0x00000000}, - {0x1e, 0x00000247}, {0x1f, 0x00000000}, - {0x00, 0x00030159}, - {0xff, 0xffffffff} -}; - -static int rtl8723au_identify_chip(struct rtl8xxxu_priv *priv) -{ - struct device *dev = &priv->udev->dev; - u32 val32, sys_cfg, vendor; - int ret = 0; - - sys_cfg = rtl8xxxu_read32(priv, REG_SYS_CFG); - priv->chip_cut = u32_get_bits(sys_cfg, SYS_CFG_CHIP_VERSION_MASK); - if (sys_cfg & SYS_CFG_TRP_VAUX_EN) { - dev_info(dev, "Unsupported test chip\n"); - ret = -ENOTSUPP; - goto out; - } - - strscpy(priv->chip_name, "8723AU", sizeof(priv->chip_name)); - priv->usb_interrupts = 1; - priv->rtl_chip = RTL8723A; - - priv->rf_paths = 1; - priv->rx_paths = 1; - priv->tx_paths = 1; - - val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL); - if (val32 & MULTI_WIFI_FUNC_EN) - priv->has_wifi = 1; - if (val32 & MULTI_BT_FUNC_EN) - priv->has_bluetooth = 1; - if (val32 & MULTI_GPS_FUNC_EN) - priv->has_gps = 1; - priv->is_multi_func = 1; - - vendor = sys_cfg & SYS_CFG_VENDOR_ID; - rtl8xxxu_identify_vendor_1bit(priv, vendor); - - val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS); - priv->rom_rev = u32_get_bits(val32, GPIO_RF_RL_ID); - - rtl8xxxu_config_endpoints_sie(priv); - - /* - * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX - */ - if (!priv->ep_tx_count) - ret = rtl8xxxu_config_endpoints_no_sie(priv); - -out: - return ret; -} - -static int rtl8723au_parse_efuse(struct rtl8xxxu_priv *priv) -{ - struct rtl8723au_efuse *efuse = &priv->efuse_wifi.efuse8723; - - if (efuse->rtl_id != cpu_to_le16(0x8129)) - return -EINVAL; - - ether_addr_copy(priv->mac_addr, efuse->mac_addr); - - memcpy(priv->cck_tx_power_index_A, - efuse->cck_tx_power_index_A, - sizeof(efuse->cck_tx_power_index_A)); - memcpy(priv->cck_tx_power_index_B, - efuse->cck_tx_power_index_B, - sizeof(efuse->cck_tx_power_index_B)); - - memcpy(priv->ht40_1s_tx_power_index_A, - efuse->ht40_1s_tx_power_index_A, - sizeof(efuse->ht40_1s_tx_power_index_A)); - memcpy(priv->ht40_1s_tx_power_index_B, - efuse->ht40_1s_tx_power_index_B, - sizeof(efuse->ht40_1s_tx_power_index_B)); - - memcpy(priv->ht20_tx_power_index_diff, - efuse->ht20_tx_power_index_diff, - sizeof(efuse->ht20_tx_power_index_diff)); - memcpy(priv->ofdm_tx_power_index_diff, - efuse->ofdm_tx_power_index_diff, - sizeof(efuse->ofdm_tx_power_index_diff)); - - memcpy(priv->ht40_max_power_offset, - efuse->ht40_max_power_offset, - sizeof(efuse->ht40_max_power_offset)); - memcpy(priv->ht20_max_power_offset, - efuse->ht20_max_power_offset, - sizeof(efuse->ht20_max_power_offset)); - - if (priv->efuse_wifi.efuse8723.version >= 0x01) - priv->default_crystal_cap = priv->efuse_wifi.efuse8723.xtal_k & 0x3f; - else - priv->fops->set_crystal_cap = NULL; - - priv->power_base = &rtl8723a_power_base; - - return 0; -} - -static int rtl8723au_load_firmware(struct rtl8xxxu_priv *priv) -{ - const char *fw_name; - int ret; - - switch (priv->chip_cut) { - case 0: - fw_name = "rtlwifi/rtl8723aufw_A.bin"; - break; - case 1: - if (priv->enable_bluetooth) - fw_name = "rtlwifi/rtl8723aufw_B.bin"; - else - fw_name = "rtlwifi/rtl8723aufw_B_NoBT.bin"; - - break; - default: - return -EINVAL; - } - - ret = rtl8xxxu_load_firmware(priv, fw_name); - return ret; -} - -static int rtl8723au_init_phy_rf(struct rtl8xxxu_priv *priv) -{ - int ret; - - ret = rtl8xxxu_init_phy_rf(priv, rtl8723au_radioa_1t_init_table, RF_A); - - /* Reduce 80M spur */ - rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x0381808d); - rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83); - rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff82); - rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83); - - return ret; -} - -static int rtl8723a_emu_to_active(struct rtl8xxxu_priv *priv) -{ - u8 val8; - u32 val32; - int count, ret = 0; - - /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface*/ - val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL); - val8 |= LDOA15_ENABLE; - rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8); - - /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/ - val8 = rtl8xxxu_read8(priv, 0x0067); - val8 &= ~BIT(4); - rtl8xxxu_write8(priv, 0x0067, val8); - - mdelay(1); - - /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */ - val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL); - val8 &= ~SYS_ISO_ANALOG_IPS; - rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8); - - /* disable SW LPS 0x04[10]= 0 */ - val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); - val8 &= ~BIT(2); - rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); - - /* wait till 0x04[17] = 1 power ready*/ - for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { - val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); - if (val32 & BIT(17)) - break; - - udelay(10); - } - - if (!count) { - ret = -EBUSY; - goto exit; - } - - /* We should be able to optimize the following three entries into one */ - - /* release WLON reset 0x04[16]= 1*/ - val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2); - val8 |= BIT(0); - rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8); - - /* disable HWPDN 0x04[15]= 0*/ - val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); - val8 &= ~BIT(7); - rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); - - /* disable WL suspend*/ - val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); - val8 &= ~(BIT(3) | BIT(4)); - rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); - - /* set, then poll until 0 */ - val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); - val32 |= APS_FSMCO_MAC_ENABLE; - rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); - - for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { - val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); - if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) { - ret = 0; - break; - } - udelay(10); - } - - if (!count) { - ret = -EBUSY; - goto exit; - } - - /* 0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */ - /* - * Note: Vendor driver actually clears this bit, despite the - * documentation claims it's being set! - */ - val8 = rtl8xxxu_read8(priv, REG_LEDCFG2); - val8 |= LEDCFG2_DPDT_SELECT; - val8 &= ~LEDCFG2_DPDT_SELECT; - rtl8xxxu_write8(priv, REG_LEDCFG2, val8); - -exit: - return ret; -} - -static int rtl8723au_power_on(struct rtl8xxxu_priv *priv) -{ - u8 val8; - u16 val16; - u32 val32; - int ret; - - /* - * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register - */ - rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0); - - rtl8xxxu_disabled_to_emu(priv); - - ret = rtl8723a_emu_to_active(priv); - if (ret) - goto exit; - - /* - * 0x0004[19] = 1, reset 8051 - */ - val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2); - val8 |= BIT(3); - rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8); - - /* - * Enable MAC DMA/WMAC/SCHEDULE/SEC block - * Set CR bit10 to enable 32k calibration. - */ - val16 = rtl8xxxu_read16(priv, REG_CR); - val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE | - CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | - CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE | - CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE | - CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE); - rtl8xxxu_write16(priv, REG_CR, val16); - - /* For EFuse PG */ - val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL); - val32 &= ~(BIT(28) | BIT(29) | BIT(30)); - val32 |= (0x06 << 28); - rtl8xxxu_write32(priv, REG_EFUSE_CTRL, val32); -exit: - return ret; -} - -#define XTAL1 GENMASK(23, 18) -#define XTAL0 GENMASK(17, 12) - -void rtl8723a_set_crystal_cap(struct rtl8xxxu_priv *priv, u8 crystal_cap) -{ - struct rtl8xxxu_cfo_tracking *cfo = &priv->cfo_tracking; - u32 val32; - - if (crystal_cap == cfo->crystal_cap) - return; - - val32 = rtl8xxxu_read32(priv, REG_MAC_PHY_CTRL); - - dev_dbg(&priv->udev->dev, - "%s: Adjusting crystal cap from 0x%x (actually 0x%lx 0x%lx) to 0x%x\n", - __func__, - cfo->crystal_cap, - FIELD_GET(XTAL1, val32), - FIELD_GET(XTAL0, val32), - crystal_cap); - - val32 &= ~(XTAL1 | XTAL0); - val32 |= FIELD_PREP(XTAL1, crystal_cap) | - FIELD_PREP(XTAL0, crystal_cap); - rtl8xxxu_write32(priv, REG_MAC_PHY_CTRL, val32); - - cfo->crystal_cap = crystal_cap; -} - -s8 rtl8723a_cck_rssi(struct rtl8xxxu_priv *priv, struct rtl8723au_phy_stats *phy_stats) -{ - u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a; - s8 rx_pwr_all = 0x00; - - switch (cck_agc_rpt & 0xc0) { - case 0xc0: - rx_pwr_all = -46 - (cck_agc_rpt & 0x3e); - break; - case 0x80: - rx_pwr_all = -26 - (cck_agc_rpt & 0x3e); - break; - case 0x40: - rx_pwr_all = -12 - (cck_agc_rpt & 0x3e); - break; - case 0x00: - rx_pwr_all = 16 - (cck_agc_rpt & 0x3e); - break; - } - - return rx_pwr_all; -} - -static int rtl8723au_led_brightness_set(struct led_classdev *led_cdev, - enum led_brightness brightness) -{ - struct rtl8xxxu_priv *priv = container_of(led_cdev, - struct rtl8xxxu_priv, - led_cdev); - u8 ledcfg = rtl8xxxu_read8(priv, REG_LEDCFG2); - - if (brightness == LED_OFF) { - ledcfg &= ~LEDCFG2_HW_LED_CONTROL; - ledcfg |= LEDCFG2_SW_LED_CONTROL | LEDCFG2_SW_LED_DISABLE; - } else if (brightness == LED_ON) { - ledcfg &= ~(LEDCFG2_HW_LED_CONTROL | LEDCFG2_SW_LED_DISABLE); - ledcfg |= LEDCFG2_SW_LED_CONTROL; - } else if (brightness == RTL8XXXU_HW_LED_CONTROL) { - ledcfg &= ~LEDCFG2_SW_LED_DISABLE; - ledcfg |= LEDCFG2_HW_LED_CONTROL | LEDCFG2_HW_LED_ENABLE; - } - - rtl8xxxu_write8(priv, REG_LEDCFG2, ledcfg); - - return 0; -} - -struct rtl8xxxu_fileops rtl8723au_fops = { - .identify_chip = rtl8723au_identify_chip, - .parse_efuse = rtl8723au_parse_efuse, - .load_firmware = rtl8723au_load_firmware, - .power_on = rtl8723au_power_on, - .power_off = rtl8xxxu_power_off, - .read_efuse = rtl8xxxu_read_efuse, - .reset_8051 = rtl8xxxu_reset_8051, - .llt_init = rtl8xxxu_init_llt_table, - .init_phy_bb = rtl8xxxu_gen1_init_phy_bb, - .init_phy_rf = rtl8723au_init_phy_rf, - .phy_lc_calibrate = rtl8723a_phy_lc_calibrate, - .phy_iq_calibrate = rtl8xxxu_gen1_phy_iq_calibrate, - .config_channel = rtl8xxxu_gen1_config_channel, - .parse_rx_desc = rtl8xxxu_parse_rxdesc16, - .parse_phystats = rtl8723au_rx_parse_phystats, - .init_aggregation = rtl8xxxu_gen1_init_aggregation, - .enable_rf = rtl8xxxu_gen1_enable_rf, - .disable_rf = rtl8xxxu_gen1_disable_rf, - .usb_quirks = rtl8xxxu_gen1_usb_quirks, - .set_tx_power = rtl8xxxu_gen1_set_tx_power, - .update_rate_mask = rtl8xxxu_update_rate_mask, - .report_connect = rtl8xxxu_gen1_report_connect, - .report_rssi = rtl8xxxu_gen1_report_rssi, - .fill_txdesc = rtl8xxxu_fill_txdesc_v1, - .set_crystal_cap = rtl8723a_set_crystal_cap, - .cck_rssi = rtl8723a_cck_rssi, - .led_classdev_brightness_set = rtl8723au_led_brightness_set, - .writeN_block_size = 1024, - .rx_agg_buf_size = 16000, - .tx_desc_size = sizeof(struct rtl8xxxu_txdesc32), - .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc16), - .max_sec_cam_num = 32, - .adda_1t_init = 0x0b1b25a0, - .adda_1t_path_on = 0x0bdb25a0, - .adda_2t_path_on_a = 0x04db25a4, - .adda_2t_path_on_b = 0x0b1b25a4, - .trxff_boundary = 0x27ff, - .pbp_rx = PBP_PAGE_SIZE_128, - .pbp_tx = PBP_PAGE_SIZE_128, - .mactable = rtl8723au_mac_init_table, - .total_page_num = TX_TOTAL_PAGE_NUM, - .page_num_hi = TX_PAGE_NUM_HI_PQ, - .page_num_lo = TX_PAGE_NUM_LO_PQ, - .page_num_norm = TX_PAGE_NUM_NORM_PQ, -}; diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c deleted file mode 100644 index 3355d8e97870..000000000000 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c +++ /dev/null @@ -1,1779 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * RTL8XXXU mac80211 USB driver - 8723b specific subdriver - * - * Copyright (c) 2014 - 2017 Jes Sorensen - * - * Portions, notably calibration code: - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This driver was written as a replacement for the vendor provided - * rtl8723au driver. As the Realtek 8xxx chips are very similar in - * their programming interface, I have started adding support for - * additional 8xxx chips like the 8192cu, 8188cus, etc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "rtl8xxxu.h" -#include "rtl8xxxu_regs.h" - -static const struct rtl8xxxu_reg8val rtl8723b_mac_init_table[] = { - {0x02f, 0x30}, {0x035, 0x00}, {0x039, 0x08}, {0x04e, 0xe0}, - {0x064, 0x00}, {0x067, 0x20}, {0x428, 0x0a}, {0x429, 0x10}, - {0x430, 0x00}, {0x431, 0x00}, - {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05}, - {0x436, 0x07}, {0x437, 0x08}, {0x43c, 0x04}, {0x43d, 0x05}, - {0x43e, 0x07}, {0x43f, 0x08}, {0x440, 0x5d}, {0x441, 0x01}, - {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, {0x446, 0x00}, - {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xf0}, {0x44a, 0x0f}, - {0x44b, 0x3e}, {0x44c, 0x10}, {0x44d, 0x00}, {0x44e, 0x00}, - {0x44f, 0x00}, {0x450, 0x00}, {0x451, 0xf0}, {0x452, 0x0f}, - {0x453, 0x00}, {0x456, 0x5e}, {0x460, 0x66}, {0x461, 0x66}, - {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff}, - {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2}, - {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3}, - {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4}, - {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4}, - {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a}, - {0x516, 0x0a}, {0x525, 0x4f}, - {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55c, 0x50}, - {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a}, - {0x620, 0xff}, {0x621, 0xff}, {0x622, 0xff}, {0x623, 0xff}, - {0x624, 0xff}, {0x625, 0xff}, {0x626, 0xff}, {0x627, 0xff}, - {0x638, 0x50}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e}, - {0x63f, 0x0e}, {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00}, - {0x652, 0xc8}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43}, - {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43}, - {0x70a, 0x65}, {0x70b, 0x87}, {0x765, 0x18}, {0x76e, 0x04}, - {0xffff, 0xff}, -}; - -static const struct rtl8xxxu_reg32val rtl8723b_phy_1t_init_table[] = { - {0x800, 0x80040000}, {0x804, 0x00000003}, - {0x808, 0x0000fc00}, {0x80c, 0x0000000a}, - {0x810, 0x10001331}, {0x814, 0x020c3d10}, - {0x818, 0x02200385}, {0x81c, 0x00000000}, - {0x820, 0x01000100}, {0x824, 0x00190204}, - {0x828, 0x00000000}, {0x82c, 0x00000000}, - {0x830, 0x00000000}, {0x834, 0x00000000}, - {0x838, 0x00000000}, {0x83c, 0x00000000}, - {0x840, 0x00010000}, {0x844, 0x00000000}, - {0x848, 0x00000000}, {0x84c, 0x00000000}, - {0x850, 0x00000000}, {0x854, 0x00000000}, - {0x858, 0x569a11a9}, {0x85c, 0x01000014}, - {0x860, 0x66f60110}, {0x864, 0x061f0649}, - {0x868, 0x00000000}, {0x86c, 0x27272700}, - {0x870, 0x07000760}, {0x874, 0x25004000}, - {0x878, 0x00000808}, {0x87c, 0x00000000}, - {0x880, 0xb0000c1c}, {0x884, 0x00000001}, - {0x888, 0x00000000}, {0x88c, 0xccc000c0}, - {0x890, 0x00000800}, {0x894, 0xfffffffe}, - {0x898, 0x40302010}, {0x89c, 0x00706050}, - {0x900, 0x00000000}, {0x904, 0x00000023}, - {0x908, 0x00000000}, {0x90c, 0x81121111}, - {0x910, 0x00000002}, {0x914, 0x00000201}, - {0xa00, 0x00d047c8}, {0xa04, 0x80ff800c}, - {0xa08, 0x8c838300}, {0xa0c, 0x2e7f120f}, - {0xa10, 0x9500bb78}, {0xa14, 0x1114d028}, - {0xa18, 0x00881117}, {0xa1c, 0x89140f00}, - {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317}, - {0xa28, 0x00000204}, {0xa2c, 0x00d30000}, - {0xa70, 0x101fbf00}, {0xa74, 0x00000007}, - {0xa78, 0x00000900}, {0xa7c, 0x225b0606}, - {0xa80, 0x21806490}, {0xb2c, 0x00000000}, - {0xc00, 0x48071d40}, {0xc04, 0x03a05611}, - {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c}, - {0xc10, 0x08800000}, {0xc14, 0x40000100}, - {0xc18, 0x08800000}, {0xc1c, 0x40000100}, - {0xc20, 0x00000000}, {0xc24, 0x00000000}, - {0xc28, 0x00000000}, {0xc2c, 0x00000000}, - {0xc30, 0x69e9ac44}, {0xc34, 0x469652af}, - {0xc38, 0x49795994}, {0xc3c, 0x0a97971c}, - {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7}, - {0xc48, 0xec020107}, {0xc4c, 0x007f037f}, - {0xc50, 0x69553420}, {0xc54, 0x43bc0094}, - {0xc58, 0x00013149}, {0xc5c, 0x00250492}, - {0xc60, 0x00000000}, {0xc64, 0x7112848b}, - {0xc68, 0x47c00bff}, {0xc6c, 0x00000036}, - {0xc70, 0x2c7f000d}, {0xc74, 0x020610db}, - {0xc78, 0x0000001f}, {0xc7c, 0x00b91612}, - {0xc80, 0x390000e4}, {0xc84, 0x20f60000}, - {0xc88, 0x40000100}, {0xc8c, 0x20200000}, - {0xc90, 0x00020e1a}, {0xc94, 0x00000000}, - {0xc98, 0x00020e1a}, {0xc9c, 0x00007f7f}, - {0xca0, 0x00000000}, {0xca4, 0x000300a0}, - {0xca8, 0x00000000}, {0xcac, 0x00000000}, - {0xcb0, 0x00000000}, {0xcb4, 0x00000000}, - {0xcb8, 0x00000000}, {0xcbc, 0x28000000}, - {0xcc0, 0x00000000}, {0xcc4, 0x00000000}, - {0xcc8, 0x00000000}, {0xccc, 0x00000000}, - {0xcd0, 0x00000000}, {0xcd4, 0x00000000}, - {0xcd8, 0x64b22427}, {0xcdc, 0x00766932}, - {0xce0, 0x00222222}, {0xce4, 0x00000000}, - {0xce8, 0x37644302}, {0xcec, 0x2f97d40c}, - {0xd00, 0x00000740}, {0xd04, 0x40020401}, - {0xd08, 0x0000907f}, {0xd0c, 0x20010201}, - {0xd10, 0xa0633333}, {0xd14, 0x3333bc53}, - {0xd18, 0x7a8f5b6f}, {0xd2c, 0xcc979975}, - {0xd30, 0x00000000}, {0xd34, 0x80608000}, - {0xd38, 0x00000000}, {0xd3c, 0x00127353}, - {0xd40, 0x00000000}, {0xd44, 0x00000000}, - {0xd48, 0x00000000}, {0xd4c, 0x00000000}, - {0xd50, 0x6437140a}, {0xd54, 0x00000000}, - {0xd58, 0x00000282}, {0xd5c, 0x30032064}, - {0xd60, 0x4653de68}, {0xd64, 0x04518a3c}, - {0xd68, 0x00002101}, {0xd6c, 0x2a201c16}, - {0xd70, 0x1812362e}, {0xd74, 0x322c2220}, - {0xd78, 0x000e3c24}, {0xe00, 0x2d2d2d2d}, - {0xe04, 0x2d2d2d2d}, {0xe08, 0x0390272d}, - {0xe10, 0x2d2d2d2d}, {0xe14, 0x2d2d2d2d}, - {0xe18, 0x2d2d2d2d}, {0xe1c, 0x2d2d2d2d}, - {0xe28, 0x00000000}, {0xe30, 0x1000dc1f}, - {0xe34, 0x10008c1f}, {0xe38, 0x02140102}, - {0xe3c, 0x681604c2}, {0xe40, 0x01007c00}, - {0xe44, 0x01004800}, {0xe48, 0xfb000000}, - {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f}, - {0xe54, 0x10008c1f}, {0xe58, 0x02140102}, - {0xe5c, 0x28160d05}, {0xe60, 0x00000008}, - {0xe68, 0x001b2556}, {0xe6c, 0x00c00096}, - {0xe70, 0x00c00096}, {0xe74, 0x01000056}, - {0xe78, 0x01000014}, {0xe7c, 0x01000056}, - {0xe80, 0x01000014}, {0xe84, 0x00c00096}, - {0xe88, 0x01000056}, {0xe8c, 0x00c00096}, - {0xed0, 0x00c00096}, {0xed4, 0x00c00096}, - {0xed8, 0x00c00096}, {0xedc, 0x000000d6}, - {0xee0, 0x000000d6}, {0xeec, 0x01c00016}, - {0xf14, 0x00000003}, {0xf4c, 0x00000000}, - {0xf00, 0x00000300}, - {0x820, 0x01000100}, {0x800, 0x83040000}, - {0xffff, 0xffffffff}, -}; - -static const struct rtl8xxxu_reg32val rtl8xxx_agc_8723bu_table[] = { - {0xc78, 0xfd000001}, {0xc78, 0xfc010001}, - {0xc78, 0xfb020001}, {0xc78, 0xfa030001}, - {0xc78, 0xf9040001}, {0xc78, 0xf8050001}, - {0xc78, 0xf7060001}, {0xc78, 0xf6070001}, - {0xc78, 0xf5080001}, {0xc78, 0xf4090001}, - {0xc78, 0xf30a0001}, {0xc78, 0xf20b0001}, - {0xc78, 0xf10c0001}, {0xc78, 0xf00d0001}, - {0xc78, 0xef0e0001}, {0xc78, 0xee0f0001}, - {0xc78, 0xed100001}, {0xc78, 0xec110001}, - {0xc78, 0xeb120001}, {0xc78, 0xea130001}, - {0xc78, 0xe9140001}, {0xc78, 0xe8150001}, - {0xc78, 0xe7160001}, {0xc78, 0xe6170001}, - {0xc78, 0xe5180001}, {0xc78, 0xe4190001}, - {0xc78, 0xe31a0001}, {0xc78, 0xa51b0001}, - {0xc78, 0xa41c0001}, {0xc78, 0xa31d0001}, - {0xc78, 0x671e0001}, {0xc78, 0x661f0001}, - {0xc78, 0x65200001}, {0xc78, 0x64210001}, - {0xc78, 0x63220001}, {0xc78, 0x4a230001}, - {0xc78, 0x49240001}, {0xc78, 0x48250001}, - {0xc78, 0x47260001}, {0xc78, 0x46270001}, - {0xc78, 0x45280001}, {0xc78, 0x44290001}, - {0xc78, 0x432a0001}, {0xc78, 0x422b0001}, - {0xc78, 0x292c0001}, {0xc78, 0x282d0001}, - {0xc78, 0x272e0001}, {0xc78, 0x262f0001}, - {0xc78, 0x0a300001}, {0xc78, 0x09310001}, - {0xc78, 0x08320001}, {0xc78, 0x07330001}, - {0xc78, 0x06340001}, {0xc78, 0x05350001}, - {0xc78, 0x04360001}, {0xc78, 0x03370001}, - {0xc78, 0x02380001}, {0xc78, 0x01390001}, - {0xc78, 0x013a0001}, {0xc78, 0x013b0001}, - {0xc78, 0x013c0001}, {0xc78, 0x013d0001}, - {0xc78, 0x013e0001}, {0xc78, 0x013f0001}, - {0xc78, 0xfc400001}, {0xc78, 0xfb410001}, - {0xc78, 0xfa420001}, {0xc78, 0xf9430001}, - {0xc78, 0xf8440001}, {0xc78, 0xf7450001}, - {0xc78, 0xf6460001}, {0xc78, 0xf5470001}, - {0xc78, 0xf4480001}, {0xc78, 0xf3490001}, - {0xc78, 0xf24a0001}, {0xc78, 0xf14b0001}, - {0xc78, 0xf04c0001}, {0xc78, 0xef4d0001}, - {0xc78, 0xee4e0001}, {0xc78, 0xed4f0001}, - {0xc78, 0xec500001}, {0xc78, 0xeb510001}, - {0xc78, 0xea520001}, {0xc78, 0xe9530001}, - {0xc78, 0xe8540001}, {0xc78, 0xe7550001}, - {0xc78, 0xe6560001}, {0xc78, 0xe5570001}, - {0xc78, 0xe4580001}, {0xc78, 0xe3590001}, - {0xc78, 0xa65a0001}, {0xc78, 0xa55b0001}, - {0xc78, 0xa45c0001}, {0xc78, 0xa35d0001}, - {0xc78, 0x675e0001}, {0xc78, 0x665f0001}, - {0xc78, 0x65600001}, {0xc78, 0x64610001}, - {0xc78, 0x63620001}, {0xc78, 0x62630001}, - {0xc78, 0x61640001}, {0xc78, 0x48650001}, - {0xc78, 0x47660001}, {0xc78, 0x46670001}, - {0xc78, 0x45680001}, {0xc78, 0x44690001}, - {0xc78, 0x436a0001}, {0xc78, 0x426b0001}, - {0xc78, 0x286c0001}, {0xc78, 0x276d0001}, - {0xc78, 0x266e0001}, {0xc78, 0x256f0001}, - {0xc78, 0x24700001}, {0xc78, 0x09710001}, - {0xc78, 0x08720001}, {0xc78, 0x07730001}, - {0xc78, 0x06740001}, {0xc78, 0x05750001}, - {0xc78, 0x04760001}, {0xc78, 0x03770001}, - {0xc78, 0x02780001}, {0xc78, 0x01790001}, - {0xc78, 0x017a0001}, {0xc78, 0x017b0001}, - {0xc78, 0x017c0001}, {0xc78, 0x017d0001}, - {0xc78, 0x017e0001}, {0xc78, 0x017f0001}, - {0xc50, 0x69553422}, - {0xc50, 0x69553420}, - {0x824, 0x00390204}, - {0xffff, 0xffffffff} -}; - -static const struct rtl8xxxu_rfregval rtl8723bu_radioa_1t_init_table[] = { - {0x00, 0x00010000}, {0xb0, 0x000dffe0}, - {0xfe, 0x00000000}, {0xfe, 0x00000000}, - {0xfe, 0x00000000}, {0xb1, 0x00000018}, - {0xfe, 0x00000000}, {0xfe, 0x00000000}, - {0xfe, 0x00000000}, {0xb2, 0x00084c00}, - {0xb5, 0x0000d2cc}, {0xb6, 0x000925aa}, - {0xb7, 0x00000010}, {0xb8, 0x0000907f}, - {0x5c, 0x00000002}, {0x7c, 0x00000002}, - {0x7e, 0x00000005}, {0x8b, 0x0006fc00}, - {0xb0, 0x000ff9f0}, {0x1c, 0x000739d2}, - {0x1e, 0x00000000}, {0xdf, 0x00000780}, - {0x50, 0x00067435}, - /* - * The 8723bu vendor driver indicates that bit 8 should be set in - * 0x51 for package types TFBGA90, TFBGA80, and TFBGA79. However - * they never actually check the package type - and just default - * to not setting it. - */ - {0x51, 0x0006b04e}, - {0x52, 0x000007d2}, {0x53, 0x00000000}, - {0x54, 0x00050400}, {0x55, 0x0004026e}, - {0xdd, 0x0000004c}, {0x70, 0x00067435}, - /* - * 0x71 has same package type condition as for register 0x51 - */ - {0x71, 0x0006b04e}, - {0x72, 0x000007d2}, {0x73, 0x00000000}, - {0x74, 0x00050400}, {0x75, 0x0004026e}, - {0xef, 0x00000100}, {0x34, 0x0000add7}, - {0x35, 0x00005c00}, {0x34, 0x00009dd4}, - {0x35, 0x00005000}, {0x34, 0x00008dd1}, - {0x35, 0x00004400}, {0x34, 0x00007dce}, - {0x35, 0x00003800}, {0x34, 0x00006cd1}, - {0x35, 0x00004400}, {0x34, 0x00005cce}, - {0x35, 0x00003800}, {0x34, 0x000048ce}, - {0x35, 0x00004400}, {0x34, 0x000034ce}, - {0x35, 0x00003800}, {0x34, 0x00002451}, - {0x35, 0x00004400}, {0x34, 0x0000144e}, - {0x35, 0x00003800}, {0x34, 0x00000051}, - {0x35, 0x00004400}, {0xef, 0x00000000}, - {0xef, 0x00000100}, {0xed, 0x00000010}, - {0x44, 0x0000add7}, {0x44, 0x00009dd4}, - {0x44, 0x00008dd1}, {0x44, 0x00007dce}, - {0x44, 0x00006cc1}, {0x44, 0x00005cce}, - {0x44, 0x000044d1}, {0x44, 0x000034ce}, - {0x44, 0x00002451}, {0x44, 0x0000144e}, - {0x44, 0x00000051}, {0xef, 0x00000000}, - {0xed, 0x00000000}, {0x7f, 0x00020080}, - {0xef, 0x00002000}, {0x3b, 0x000380ef}, - {0x3b, 0x000302fe}, {0x3b, 0x00028ce6}, - {0x3b, 0x000200bc}, {0x3b, 0x000188a5}, - {0x3b, 0x00010fbc}, {0x3b, 0x00008f71}, - {0x3b, 0x00000900}, {0xef, 0x00000000}, - {0xed, 0x00000001}, {0x40, 0x000380ef}, - {0x40, 0x000302fe}, {0x40, 0x00028ce6}, - {0x40, 0x000200bc}, {0x40, 0x000188a5}, - {0x40, 0x00010fbc}, {0x40, 0x00008f71}, - {0x40, 0x00000900}, {0xed, 0x00000000}, - {0x82, 0x00080000}, {0x83, 0x00008000}, - {0x84, 0x00048d80}, {0x85, 0x00068000}, - {0xa2, 0x00080000}, {0xa3, 0x00008000}, - {0xa4, 0x00048d80}, {0xa5, 0x00068000}, - {0xed, 0x00000002}, {0xef, 0x00000002}, - {0x56, 0x00000032}, {0x76, 0x00000032}, - {0x01, 0x00000780}, - {0xff, 0xffffffff} -}; - -static int rtl8723bu_identify_chip(struct rtl8xxxu_priv *priv) -{ - struct device *dev = &priv->udev->dev; - u32 val32, sys_cfg, vendor; - int ret = 0; - - sys_cfg = rtl8xxxu_read32(priv, REG_SYS_CFG); - priv->chip_cut = u32_get_bits(sys_cfg, SYS_CFG_CHIP_VERSION_MASK); - if (sys_cfg & SYS_CFG_TRP_VAUX_EN) { - dev_info(dev, "Unsupported test chip\n"); - ret = -ENOTSUPP; - goto out; - } - - strscpy(priv->chip_name, "8723BU", sizeof(priv->chip_name)); - priv->rtl_chip = RTL8723B; - priv->rf_paths = 1; - priv->rx_paths = 1; - priv->tx_paths = 1; - - val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL); - if (val32 & MULTI_WIFI_FUNC_EN) - priv->has_wifi = 1; - if (val32 & MULTI_BT_FUNC_EN) - priv->has_bluetooth = 1; - if (val32 & MULTI_GPS_FUNC_EN) - priv->has_gps = 1; - priv->is_multi_func = 1; - - vendor = sys_cfg & SYS_CFG_VENDOR_EXT_MASK; - rtl8xxxu_identify_vendor_2bits(priv, vendor); - - val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS); - priv->rom_rev = u32_get_bits(val32, GPIO_RF_RL_ID); - - rtl8xxxu_config_endpoints_sie(priv); - - /* - * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX - */ - if (!priv->ep_tx_count) - ret = rtl8xxxu_config_endpoints_no_sie(priv); - -out: - return ret; -} - -static void rtl8723bu_write_btreg(struct rtl8xxxu_priv *priv, u8 reg, u8 data) -{ - struct h2c_cmd h2c; - int reqnum = 0; - - memset(&h2c, 0, sizeof(struct h2c_cmd)); - h2c.bt_mp_oper.cmd = H2C_8723B_BT_MP_OPER; - h2c.bt_mp_oper.operreq = 0 | (reqnum << 4); - h2c.bt_mp_oper.opcode = BT_MP_OP_WRITE_REG_VALUE; - h2c.bt_mp_oper.data = data; - rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper)); - - reqnum++; - memset(&h2c, 0, sizeof(struct h2c_cmd)); - h2c.bt_mp_oper.cmd = H2C_8723B_BT_MP_OPER; - h2c.bt_mp_oper.operreq = 0 | (reqnum << 4); - h2c.bt_mp_oper.opcode = BT_MP_OP_WRITE_REG_VALUE; - h2c.bt_mp_oper.addr = reg; - rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper)); -} - -static void rtl8723bu_reset_8051(struct rtl8xxxu_priv *priv) -{ - u8 val8; - u16 sys_func; - - val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL); - val8 &= ~BIT(1); - rtl8xxxu_write8(priv, REG_RSV_CTRL, val8); - - val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); - val8 &= ~BIT(0); - rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); - - sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC); - sys_func &= ~SYS_FUNC_CPU_ENABLE; - rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func); - - val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL); - val8 &= ~BIT(1); - rtl8xxxu_write8(priv, REG_RSV_CTRL, val8); - - val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); - val8 |= BIT(0); - rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); - - sys_func |= SYS_FUNC_CPU_ENABLE; - rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func); -} - -static void -rtl8723b_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40) -{ - u32 val32, ofdm, mcs; - u8 cck, ofdmbase, mcsbase; - int group, tx_idx; - - tx_idx = 0; - group = rtl8xxxu_gen2_channel_to_group(channel); - - cck = priv->cck_tx_power_index_B[group]; - val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32); - val32 &= 0xffff00ff; - val32 |= (cck << 8); - rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); - - val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); - val32 &= 0xff; - val32 |= ((cck << 8) | (cck << 16) | (cck << 24)); - rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); - - ofdmbase = priv->ht40_1s_tx_power_index_B[group]; - ofdmbase += priv->ofdm_tx_power_diff[tx_idx].b; - ofdm = ofdmbase | ofdmbase << 8 | ofdmbase << 16 | ofdmbase << 24; - - rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm); - rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm); - - mcsbase = priv->ht40_1s_tx_power_index_B[group]; - if (ht40) - mcsbase += priv->ht40_tx_power_diff[tx_idx++].b; - else - mcsbase += priv->ht20_tx_power_diff[tx_idx++].b; - mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24; - - rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs); - rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs); -} - -static int rtl8723bu_parse_efuse(struct rtl8xxxu_priv *priv) -{ - struct rtl8723bu_efuse *efuse = &priv->efuse_wifi.efuse8723bu; - int i; - - if (efuse->rtl_id != cpu_to_le16(0x8129)) - return -EINVAL; - - ether_addr_copy(priv->mac_addr, efuse->mac_addr); - - memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base, - sizeof(efuse->tx_power_index_A.cck_base)); - memcpy(priv->cck_tx_power_index_B, efuse->tx_power_index_B.cck_base, - sizeof(efuse->tx_power_index_B.cck_base)); - - memcpy(priv->ht40_1s_tx_power_index_A, - efuse->tx_power_index_A.ht40_base, - sizeof(efuse->tx_power_index_A.ht40_base)); - memcpy(priv->ht40_1s_tx_power_index_B, - efuse->tx_power_index_B.ht40_base, - sizeof(efuse->tx_power_index_B.ht40_base)); - - priv->ofdm_tx_power_diff[0].a = - efuse->tx_power_index_A.ht20_ofdm_1s_diff.a; - priv->ofdm_tx_power_diff[0].b = - efuse->tx_power_index_B.ht20_ofdm_1s_diff.a; - - priv->ht20_tx_power_diff[0].a = - efuse->tx_power_index_A.ht20_ofdm_1s_diff.b; - priv->ht20_tx_power_diff[0].b = - efuse->tx_power_index_B.ht20_ofdm_1s_diff.b; - - priv->ht40_tx_power_diff[0].a = 0; - priv->ht40_tx_power_diff[0].b = 0; - - for (i = 1; i < RTL8723B_TX_COUNT; i++) { - priv->ofdm_tx_power_diff[i].a = - efuse->tx_power_index_A.pwr_diff[i - 1].ofdm; - priv->ofdm_tx_power_diff[i].b = - efuse->tx_power_index_B.pwr_diff[i - 1].ofdm; - - priv->ht20_tx_power_diff[i].a = - efuse->tx_power_index_A.pwr_diff[i - 1].ht20; - priv->ht20_tx_power_diff[i].b = - efuse->tx_power_index_B.pwr_diff[i - 1].ht20; - - priv->ht40_tx_power_diff[i].a = - efuse->tx_power_index_A.pwr_diff[i - 1].ht40; - priv->ht40_tx_power_diff[i].b = - efuse->tx_power_index_B.pwr_diff[i - 1].ht40; - } - - priv->default_crystal_cap = priv->efuse_wifi.efuse8723bu.xtal_k & 0x3f; - - return 0; -} - -static int rtl8723bu_load_firmware(struct rtl8xxxu_priv *priv) -{ - const char *fw_name; - int ret; - - if (priv->enable_bluetooth) - fw_name = "rtlwifi/rtl8723bu_bt.bin"; - else - fw_name = "rtlwifi/rtl8723bu_nic.bin"; - - ret = rtl8xxxu_load_firmware(priv, fw_name); - return ret; -} - -static void rtl8723bu_init_phy_bb(struct rtl8xxxu_priv *priv) -{ - u8 val8; - u16 val16; - - val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); - val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB | SYS_FUNC_DIO_RF; - rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); - - rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00); - - /* 6. 0x1f[7:0] = 0x07 */ - val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB; - rtl8xxxu_write8(priv, REG_RF_CTRL, val8); - - /* Why? */ - rtl8xxxu_write8(priv, REG_SYS_FUNC, 0xe3); - rtl8xxxu_write8(priv, REG_AFE_XTAL_CTRL + 1, 0x80); - rtl8xxxu_init_phy_regs(priv, rtl8723b_phy_1t_init_table); - - rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8723bu_table); -} - -static int rtl8723bu_init_phy_rf(struct rtl8xxxu_priv *priv) -{ - int ret; - - ret = rtl8xxxu_init_phy_rf(priv, rtl8723bu_radioa_1t_init_table, RF_A); - /* - * PHY LCK - */ - rtl8xxxu_write_rfreg(priv, RF_A, 0xb0, 0xdfbe0); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, 0x8c01); - msleep(200); - rtl8xxxu_write_rfreg(priv, RF_A, 0xb0, 0xdffe0); - - return ret; -} - -void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv *priv) -{ - u32 val32; - - val32 = rtl8xxxu_read32(priv, REG_PAD_CTRL1); - val32 &= ~(BIT(20) | BIT(24)); - rtl8xxxu_write32(priv, REG_PAD_CTRL1, val32); - - val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG); - val32 &= ~BIT(4); - rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32); - - val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG); - val32 |= BIT(3); - rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32); - - val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); - val32 |= BIT(24); - rtl8xxxu_write32(priv, REG_LEDCFG0, val32); - - val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); - val32 &= ~BIT(23); - rtl8xxxu_write32(priv, REG_LEDCFG0, val32); - - val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER); - val32 |= (BIT(0) | BIT(1)); - rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32); - - val32 = rtl8xxxu_read32(priv, REG_RFE_CTRL_ANTA_SRC); - val32 &= 0xffffff00; - val32 |= 0x77; - rtl8xxxu_write32(priv, REG_RFE_CTRL_ANTA_SRC, val32); - - val32 = rtl8xxxu_read32(priv, REG_PWR_DATA); - val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN; - rtl8xxxu_write32(priv, REG_PWR_DATA, val32); -} - -static int rtl8723bu_iqk_path_a(struct rtl8xxxu_priv *priv) -{ - u32 reg_eac, reg_e94, reg_e9c, path_sel, val32; - int result = 0; - - path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); - - /* - * Leave IQK mode - */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); - val32 &= 0x000000ff; - rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); - - /* - * Enable path A PA in TX IQK mode - */ - val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); - val32 |= 0x80000; - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x20000); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0003f); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xc7f87); - - /* - * Tx IQK setting - */ - rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); - rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); - - /* path-A IQK setting */ - rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); - rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); - rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); - rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); - - rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821403ea); - rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000); - rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000); - rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000); - - /* LO calibration setting */ - rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911); - - /* - * Enter IQK mode - */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); - val32 &= 0x000000ff; - val32 |= 0x80800000; - rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); - - /* - * The vendor driver indicates the USB module is always using - * S0S1 path 1 for the 8723bu. This may be different for 8192eu - */ - if (priv->rf_paths > 1) - rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000); - else - rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280); - - /* - * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu. - * No trace of this in the 8192eu or 8188eu vendor drivers. - */ - rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800); - - /* One shot, path A LOK & IQK */ - rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); - rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); - - mdelay(1); - - /* Restore Ant Path */ - rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel); -#ifdef RTL8723BU_BT - /* GNT_BT = 1 */ - rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800); -#endif - - /* - * Leave IQK mode - */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); - val32 &= 0x000000ff; - rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); - - /* Check failed */ - reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); - reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); - reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); - - val32 = (reg_e9c >> 16) & 0x3ff; - if (val32 & 0x200) - val32 = 0x400 - val32; - - if (!(reg_eac & BIT(28)) && - ((reg_e94 & 0x03ff0000) != 0x01420000) && - ((reg_e9c & 0x03ff0000) != 0x00420000) && - ((reg_e94 & 0x03ff0000) < 0x01100000) && - ((reg_e94 & 0x03ff0000) > 0x00f00000) && - val32 < 0xf) - result |= 0x01; - else /* If TX not OK, ignore RX */ - goto out; - -out: - return result; -} - -static int rtl8723bu_rx_iqk_path_a(struct rtl8xxxu_priv *priv) -{ - u32 reg_ea4, reg_eac, reg_e94, reg_e9c, path_sel, val32; - int result = 0; - - path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); - - /* - * Leave IQK mode - */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); - val32 &= 0x000000ff; - rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); - - /* - * Enable path A PA in TX IQK mode - */ - val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); - val32 |= 0x80000; - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7); - - /* - * Tx IQK setting - */ - rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); - rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); - - /* path-A IQK setting */ - rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); - rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); - rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); - rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); - - rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160ff0); - rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000); - rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000); - rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000); - - /* LO calibration setting */ - rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911); - - /* - * Enter IQK mode - */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); - val32 &= 0x000000ff; - val32 |= 0x80800000; - rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); - - /* - * The vendor driver indicates the USB module is always using - * S0S1 path 1 for the 8723bu. This may be different for 8192eu - */ - if (priv->rf_paths > 1) - rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000); - else - rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280); - - /* - * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu. - * No trace of this in the 8192eu or 8188eu vendor drivers. - */ - rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800); - - /* One shot, path A LOK & IQK */ - rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); - rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); - - mdelay(1); - - /* Restore Ant Path */ - rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel); -#ifdef RTL8723BU_BT - /* GNT_BT = 1 */ - rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800); -#endif - - /* - * Leave IQK mode - */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); - val32 &= 0x000000ff; - rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); - - /* Check failed */ - reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); - reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); - reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); - - val32 = (reg_e9c >> 16) & 0x3ff; - if (val32 & 0x200) - val32 = 0x400 - val32; - - if (!(reg_eac & BIT(28)) && - ((reg_e94 & 0x03ff0000) != 0x01420000) && - ((reg_e9c & 0x03ff0000) != 0x00420000) && - ((reg_e94 & 0x03ff0000) < 0x01100000) && - ((reg_e94 & 0x03ff0000) > 0x00f00000) && - val32 < 0xf) - result |= 0x01; - else /* If TX not OK, ignore RX */ - goto out; - - val32 = 0x80007c00 | (reg_e94 &0x3ff0000) | - ((reg_e9c & 0x3ff0000) >> 16); - rtl8xxxu_write32(priv, REG_TX_IQK, val32); - - /* - * Modify RX IQK mode - */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); - val32 &= 0x000000ff; - rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); - val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); - val32 |= 0x80000; - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7d77); - - /* - * PA, PAD setting - */ - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0xf80); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_55, 0x4021f); - - /* - * RX IQK setting - */ - rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); - - /* path-A IQK setting */ - rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); - rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c); - rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); - rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); - - rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82110000); - rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x2816001f); - rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000); - rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000); - - /* LO calibration setting */ - rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a8d1); - - /* - * Enter IQK mode - */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); - val32 &= 0x000000ff; - val32 |= 0x80800000; - rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); - - if (priv->rf_paths > 1) - rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000); - else - rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280); - - /* - * Disable BT - */ - rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800); - - /* One shot, path A LOK & IQK */ - rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); - rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); - - mdelay(1); - - /* Restore Ant Path */ - rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel); -#ifdef RTL8723BU_BT - /* GNT_BT = 1 */ - rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800); -#endif - - /* - * Leave IQK mode - */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); - val32 &= 0x000000ff; - rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); - - /* Check failed */ - reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); - reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); - - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x780); - - val32 = (reg_eac >> 16) & 0x3ff; - if (val32 & 0x200) - val32 = 0x400 - val32; - - if (!(reg_eac & BIT(27)) && - ((reg_ea4 & 0x03ff0000) != 0x01320000) && - ((reg_eac & 0x03ff0000) != 0x00360000) && - ((reg_ea4 & 0x03ff0000) < 0x01100000) && - ((reg_ea4 & 0x03ff0000) > 0x00f00000) && - val32 < 0xf) - result |= 0x02; - else /* If TX not OK, ignore RX */ - goto out; -out: - return result; -} - -static void rtl8723bu_phy_iqcalibrate(struct rtl8xxxu_priv *priv, - int result[][8], int t) -{ - struct device *dev = &priv->udev->dev; - u32 i, val32; - int path_a_ok /*, path_b_ok */; - int retry = 2; - static const u32 adda_regs[RTL8XXXU_ADDA_REGS] = { - REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH, - REG_RX_WAIT_CCA, REG_TX_CCK_RFON, - REG_TX_CCK_BBON, REG_TX_OFDM_RFON, - REG_TX_OFDM_BBON, REG_TX_TO_RX, - REG_TX_TO_TX, REG_RX_CCK, - REG_RX_OFDM, REG_RX_WAIT_RIFS, - REG_RX_TO_RX, REG_STANDBY, - REG_SLEEP, REG_PMPD_ANAEN - }; - static const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = { - REG_TXPAUSE, REG_BEACON_CTRL, - REG_BEACON_CTRL_1, REG_GPIO_MUXCFG - }; - static const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = { - REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR, - REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, - REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE, - REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE - }; - u8 xa_agc = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1) & 0xff; - u8 xb_agc = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1) & 0xff; - - /* - * Note: IQ calibration must be performed after loading - * PHY_REG.txt , and radio_a, radio_b.txt - */ - - if (t == 0) { - /* Save ADDA parameters, turn Path A ADDA on */ - rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup, - RTL8XXXU_ADDA_REGS); - rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup); - rtl8xxxu_save_regs(priv, iqk_bb_regs, - priv->bb_backup, RTL8XXXU_BB_REGS); - } - - rtl8xxxu_path_adda_on(priv, adda_regs, true); - - /* MAC settings */ - rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup); - - val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING); - val32 |= 0x0f000000; - rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32); - - rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600); - rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4); - rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000); - - /* - * RX IQ calibration setting for 8723B D cut large current issue - * when leaving IPS - */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); - val32 &= 0x000000ff; - rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); - - val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); - val32 |= 0x80000; - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); - - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7); - - val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED); - val32 |= 0x20; - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32); - - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_43, 0x60fbd); - - for (i = 0; i < retry; i++) { - path_a_ok = rtl8723bu_iqk_path_a(priv); - if (path_a_ok == 0x01) { - val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); - val32 &= 0x000000ff; - rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); - - val32 = rtl8xxxu_read32(priv, - REG_TX_POWER_BEFORE_IQK_A); - result[t][0] = (val32 >> 16) & 0x3ff; - val32 = rtl8xxxu_read32(priv, - REG_TX_POWER_AFTER_IQK_A); - result[t][1] = (val32 >> 16) & 0x3ff; - - break; - } - } - - if (!path_a_ok) - dev_dbg(dev, "%s: Path A TX IQK failed!\n", __func__); - - for (i = 0; i < retry; i++) { - path_a_ok = rtl8723bu_rx_iqk_path_a(priv); - if (path_a_ok == 0x03) { - val32 = rtl8xxxu_read32(priv, - REG_RX_POWER_BEFORE_IQK_A_2); - result[t][2] = (val32 >> 16) & 0x3ff; - val32 = rtl8xxxu_read32(priv, - REG_RX_POWER_AFTER_IQK_A_2); - result[t][3] = (val32 >> 16) & 0x3ff; - - break; - } - } - - if (!path_a_ok) - dev_dbg(dev, "%s: Path A RX IQK failed!\n", __func__); - - if (priv->tx_paths > 1) { -#if 1 - dev_warn(dev, "%s: Path B not supported\n", __func__); -#else - - /* - * Path A into standby - */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); - val32 &= 0x000000ff; - rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x10000); - - val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); - val32 &= 0x000000ff; - val32 |= 0x80800000; - rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); - - /* Turn Path B ADDA on */ - rtl8xxxu_path_adda_on(priv, adda_regs, false); - - for (i = 0; i < retry; i++) { - path_b_ok = rtl8xxxu_iqk_path_b(priv); - if (path_b_ok == 0x03) { - val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); - result[t][4] = (val32 >> 16) & 0x3ff; - val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); - result[t][5] = (val32 >> 16) & 0x3ff; - break; - } - } - - if (!path_b_ok) - dev_dbg(dev, "%s: Path B IQK failed!\n", __func__); - - for (i = 0; i < retry; i++) { - path_b_ok = rtl8723bu_rx_iqk_path_b(priv); - if (path_a_ok == 0x03) { - val32 = rtl8xxxu_read32(priv, - REG_RX_POWER_BEFORE_IQK_B_2); - result[t][6] = (val32 >> 16) & 0x3ff; - val32 = rtl8xxxu_read32(priv, - REG_RX_POWER_AFTER_IQK_B_2); - result[t][7] = (val32 >> 16) & 0x3ff; - break; - } - } - - if (!path_b_ok) - dev_dbg(dev, "%s: Path B RX IQK failed!\n", __func__); -#endif - } - - /* Back to BB mode, load original value */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); - val32 &= 0x000000ff; - rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); - - if (t) { - /* Reload ADDA power saving parameters */ - rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup, - RTL8XXXU_ADDA_REGS); - - /* Reload MAC parameters */ - rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup); - - /* Reload BB parameters */ - rtl8xxxu_restore_regs(priv, iqk_bb_regs, - priv->bb_backup, RTL8XXXU_BB_REGS); - - /* Restore RX initial gain */ - val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); - val32 &= 0xffffff00; - rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | 0x50); - rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | xa_agc); - - if (priv->tx_paths > 1) { - val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1); - val32 &= 0xffffff00; - rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1, - val32 | 0x50); - rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1, - val32 | xb_agc); - } - - /* Load 0xe30 IQC default value */ - rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00); - rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00); - } -} - -static void rtl8723bu_phy_iq_calibrate(struct rtl8xxxu_priv *priv) -{ - struct device *dev = &priv->udev->dev; - int result[4][8]; /* last is final result */ - int i, candidate; - bool path_a_ok, path_b_ok; - u32 reg_e94, reg_e9c, reg_ea4, reg_eac; - u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc; - u32 val32, bt_control; - s32 reg_tmp = 0; - bool simu; - - rtl8xxxu_gen2_prepare_calibrate(priv, 1); - - memset(result, 0, sizeof(result)); - candidate = -1; - - path_a_ok = false; - path_b_ok = false; - - bt_control = rtl8xxxu_read32(priv, REG_BT_CONTROL_8723BU); - - for (i = 0; i < 3; i++) { - rtl8723bu_phy_iqcalibrate(priv, result, i); - - if (i == 1) { - simu = rtl8xxxu_gen2_simularity_compare(priv, - result, 0, 1); - if (simu) { - candidate = 0; - break; - } - } - - if (i == 2) { - simu = rtl8xxxu_gen2_simularity_compare(priv, - result, 0, 2); - if (simu) { - candidate = 0; - break; - } - - simu = rtl8xxxu_gen2_simularity_compare(priv, - result, 1, 2); - if (simu) { - candidate = 1; - } else { - for (i = 0; i < 8; i++) - reg_tmp += result[3][i]; - - if (reg_tmp) - candidate = 3; - else - candidate = -1; - } - } - } - - for (i = 0; i < 4; i++) { - reg_e94 = result[i][0]; - reg_e9c = result[i][1]; - reg_ea4 = result[i][2]; - reg_eac = result[i][3]; - reg_eb4 = result[i][4]; - reg_ebc = result[i][5]; - reg_ec4 = result[i][6]; - reg_ecc = result[i][7]; - } - - if (candidate >= 0) { - reg_e94 = result[candidate][0]; - priv->rege94 = reg_e94; - reg_e9c = result[candidate][1]; - priv->rege9c = reg_e9c; - reg_ea4 = result[candidate][2]; - reg_eac = result[candidate][3]; - reg_eb4 = result[candidate][4]; - priv->regeb4 = reg_eb4; - reg_ebc = result[candidate][5]; - priv->regebc = reg_ebc; - reg_ec4 = result[candidate][6]; - reg_ecc = result[candidate][7]; - dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate); - dev_dbg(dev, - "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x ecc=%x\n", - __func__, reg_e94, reg_e9c, - reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc); - path_a_ok = true; - path_b_ok = true; - } else { - reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100; - reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0; - } - - if (reg_e94 && candidate >= 0) - rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result, - candidate, (reg_ea4 == 0)); - - if (priv->tx_paths > 1 && reg_eb4) - rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result, - candidate, (reg_ec4 == 0)); - - rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg, - priv->bb_recovery_backup, RTL8XXXU_BB_REGS); - - rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, bt_control); - - val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); - val32 |= 0x80000; - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x18000); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xe6177); - val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED); - val32 |= 0x20; - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32); - rtl8xxxu_write_rfreg(priv, RF_A, 0x43, 0x300bd); - - if (priv->rf_paths > 1) - dev_dbg(dev, "%s: 8723BU 2T not supported\n", __func__); - - rtl8xxxu_gen2_prepare_calibrate(priv, 0); -} - -static int rtl8723bu_active_to_emu(struct rtl8xxxu_priv *priv) -{ - u8 val8; - u16 val16; - u32 val32; - int count, ret = 0; - - /* Turn off RF */ - rtl8xxxu_write8(priv, REG_RF_CTRL, 0); - - /* Enable rising edge triggering interrupt */ - val16 = rtl8xxxu_read16(priv, REG_GPIO_INTM); - val16 &= ~GPIO_INTM_EDGE_TRIG_IRQ; - rtl8xxxu_write16(priv, REG_GPIO_INTM, val16); - - /* Release WLON reset 0x04[16]= 1*/ - val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); - val32 |= APS_FSMCO_WLON_RESET; - rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); - - /* 0x0005[1] = 1 turn off MAC by HW state machine*/ - val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); - val8 |= BIT(1); - rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); - - for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { - val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); - if ((val8 & BIT(1)) == 0) - break; - udelay(10); - } - - if (!count) { - dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n", - __func__); - ret = -EBUSY; - goto exit; - } - - /* Enable BT control XTAL setting */ - val8 = rtl8xxxu_read8(priv, REG_AFE_MISC); - val8 &= ~AFE_MISC_WL_XTAL_CTRL; - rtl8xxxu_write8(priv, REG_AFE_MISC, val8); - - /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */ - val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL); - val8 |= SYS_ISO_ANALOG_IPS; - rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8); - - /* 0x0020[0] = 0 disable LDOA12 MACRO block*/ - val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL); - val8 &= ~LDOA15_ENABLE; - rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8); - -exit: - return ret; -} - -static int rtl8723b_emu_to_active(struct rtl8xxxu_priv *priv) -{ - u8 val8; - u32 val32; - int count, ret = 0; - - /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface */ - val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL); - val8 |= LDOA15_ENABLE; - rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8); - - /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/ - val8 = rtl8xxxu_read8(priv, 0x0067); - val8 &= ~BIT(4); - rtl8xxxu_write8(priv, 0x0067, val8); - - mdelay(1); - - /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */ - val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL); - val8 &= ~SYS_ISO_ANALOG_IPS; - rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8); - - /* Disable SW LPS 0x04[10]= 0 */ - val32 = rtl8xxxu_read8(priv, REG_APS_FSMCO); - val32 &= ~APS_FSMCO_SW_LPS; - rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); - - /* Wait until 0x04[17] = 1 power ready */ - for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { - val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); - if (val32 & BIT(17)) - break; - - udelay(10); - } - - if (!count) { - ret = -EBUSY; - goto exit; - } - - /* We should be able to optimize the following three entries into one */ - - /* Release WLON reset 0x04[16]= 1*/ - val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); - val32 |= APS_FSMCO_WLON_RESET; - rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); - - /* Disable HWPDN 0x04[15]= 0*/ - val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); - val32 &= ~APS_FSMCO_HW_POWERDOWN; - rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); - - /* Disable WL suspend*/ - val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); - val32 &= ~(APS_FSMCO_HW_SUSPEND | APS_FSMCO_PCIE); - rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); - - /* Set, then poll until 0 */ - val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); - val32 |= APS_FSMCO_MAC_ENABLE; - rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); - - for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { - val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); - if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) { - ret = 0; - break; - } - udelay(10); - } - - if (!count) { - ret = -EBUSY; - goto exit; - } - - /* Enable WL control XTAL setting */ - val8 = rtl8xxxu_read8(priv, REG_AFE_MISC); - val8 |= AFE_MISC_WL_XTAL_CTRL; - rtl8xxxu_write8(priv, REG_AFE_MISC, val8); - - /* Enable falling edge triggering interrupt */ - val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 1); - val8 |= BIT(1); - rtl8xxxu_write8(priv, REG_GPIO_INTM + 1, val8); - - /* Enable GPIO9 interrupt mode */ - val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2 + 1); - val8 |= BIT(1); - rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2 + 1, val8); - - /* Enable GPIO9 input mode */ - val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2); - val8 &= ~BIT(1); - rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2, val8); - - /* Enable HSISR GPIO[C:0] interrupt */ - val8 = rtl8xxxu_read8(priv, REG_HSIMR); - val8 |= BIT(0); - rtl8xxxu_write8(priv, REG_HSIMR, val8); - - /* Enable HSISR GPIO9 interrupt */ - val8 = rtl8xxxu_read8(priv, REG_HSIMR + 2); - val8 |= BIT(1); - rtl8xxxu_write8(priv, REG_HSIMR + 2, val8); - - val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL); - val8 |= MULTI_WIFI_HW_ROF_EN; - rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL, val8); - - /* For GPIO9 internal pull high setting BIT(14) */ - val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL + 1); - val8 |= BIT(6); - rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL + 1, val8); - -exit: - return ret; -} - -static int rtl8723bu_power_on(struct rtl8xxxu_priv *priv) -{ - u8 val8; - u16 val16; - u32 val32; - int ret; - - rtl8xxxu_disabled_to_emu(priv); - - ret = rtl8723b_emu_to_active(priv); - if (ret) - goto exit; - - /* - * Enable MAC DMA/WMAC/SCHEDULE/SEC block - * Set CR bit10 to enable 32k calibration. - */ - val16 = rtl8xxxu_read16(priv, REG_CR); - val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE | - CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | - CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE | - CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE | - CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE); - rtl8xxxu_write16(priv, REG_CR, val16); - - /* - * BT coexist power on settings. This is identical for 1 and 2 - * antenna parts. - */ - rtl8xxxu_write8(priv, REG_PAD_CTRL1 + 3, 0x20); - - val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); - val16 |= SYS_FUNC_BBRSTB | SYS_FUNC_BB_GLB_RSTN; - rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); - - rtl8xxxu_write8(priv, REG_BT_CONTROL_8723BU + 1, 0x18); - rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04); - rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00); - /* Antenna inverse */ - rtl8xxxu_write8(priv, 0xfe08, 0x01); - - val16 = rtl8xxxu_read16(priv, REG_PWR_DATA); - val16 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN; - rtl8xxxu_write16(priv, REG_PWR_DATA, val16); - - val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); - val32 |= LEDCFG0_DPDT_SELECT; - rtl8xxxu_write32(priv, REG_LEDCFG0, val32); - - val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1); - val8 &= ~PAD_CTRL1_SW_DPDT_SEL_DATA; - rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8); -exit: - return ret; -} - -static void rtl8723bu_power_off(struct rtl8xxxu_priv *priv) -{ - u8 val8; - u16 val16; - - rtl8xxxu_flush_fifo(priv); - - /* - * Disable TX report timer - */ - val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL); - val8 &= ~TX_REPORT_CTRL_TIMER_ENABLE; - rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8); - - rtl8xxxu_write8(priv, REG_CR, 0x0000); - - rtl8xxxu_active_to_lps(priv); - - /* Reset Firmware if running in RAM */ - if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL) - rtl8xxxu_firmware_self_reset(priv); - - /* Reset MCU */ - val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); - val16 &= ~SYS_FUNC_CPU_ENABLE; - rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); - - /* Reset MCU ready status */ - rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00); - - rtl8723bu_active_to_emu(priv); - - val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); - val8 |= BIT(3); /* APS_FSMCO_HW_SUSPEND */ - rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); - - /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */ - val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2); - val8 |= BIT(0); - rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8); -} - -static void rtl8723b_enable_rf(struct rtl8xxxu_priv *priv) -{ - struct h2c_cmd h2c; - u32 val32; - u8 val8; - - val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA); - val32 |= (BIT(22) | BIT(23)); - rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32); - - /* - * No indication anywhere as to what 0x0790 does. The 2 antenna - * vendor code preserves bits 6-7 here. - */ - rtl8xxxu_write8(priv, 0x0790, 0x05); - /* - * 0x0778 seems to be related to enabling the number of antennas - * In the vendor driver halbtc8723b2ant_InitHwConfig() sets it - * to 0x03, while halbtc8723b1ant_InitHwConfig() sets it to 0x01 - */ - rtl8xxxu_write8(priv, 0x0778, 0x01); - - val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG); - val8 |= BIT(5); - rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8); - - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_IQADJ_G1, 0x780); - - rtl8723bu_write_btreg(priv, 0x3c, 0x15); /* BT TRx Mask on */ - - /* - * Set BT grant to low - */ - memset(&h2c, 0, sizeof(struct h2c_cmd)); - h2c.bt_grant.cmd = H2C_8723B_BT_GRANT; - h2c.bt_grant.data = 0; - rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_grant)); - - /* - * WLAN action by PTA - */ - rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x0c); - - /* - * BT select S0/S1 controlled by WiFi - */ - val8 = rtl8xxxu_read8(priv, 0x0067); - val8 |= BIT(5); - rtl8xxxu_write8(priv, 0x0067, val8); - - val32 = rtl8xxxu_read32(priv, REG_PWR_DATA); - val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN; - rtl8xxxu_write32(priv, REG_PWR_DATA, val32); - - /* - * Bits 6/7 are marked in/out ... but for what? - */ - rtl8xxxu_write8(priv, 0x0974, 0xff); - - val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER); - val32 |= (BIT(0) | BIT(1)); - rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32); - - rtl8xxxu_write8(priv, REG_RFE_CTRL_ANTA_SRC, 0x77); - - val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); - val32 &= ~BIT(24); - val32 |= BIT(23); - rtl8xxxu_write32(priv, REG_LEDCFG0, val32); - - /* - * Fix external switch Main->S1, Aux->S0 - */ - val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1); - val8 &= ~BIT(0); - rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8); - - memset(&h2c, 0, sizeof(struct h2c_cmd)); - h2c.ant_sel_rsv.cmd = H2C_8723B_ANT_SEL_RSV; - h2c.ant_sel_rsv.ant_inverse = 1; - h2c.ant_sel_rsv.int_switch_type = 0; - rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.ant_sel_rsv)); - - /* - * Different settings per different antenna position. - * Antenna Position: | Normal Inverse - * -------------------------------------------------- - * Antenna switch to BT: | 0x280, 0x00 - * Antenna switch to WiFi: | 0x0, 0x280 - * Antenna switch to PTA: | 0x200, 0x80 - */ - rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x80); - - /* - * Software control, antenna at WiFi side - */ - rtl8723bu_set_ps_tdma(priv, 0x08, 0x00, 0x00, 0x00, 0x00); - - rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555); - rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x55555555); - rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); - rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); - - memset(&h2c, 0, sizeof(struct h2c_cmd)); - h2c.bt_info.cmd = H2C_8723B_BT_INFO; - h2c.bt_info.data = BIT(0); - rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_info)); - - memset(&h2c, 0, sizeof(struct h2c_cmd)); - h2c.ignore_wlan.cmd = H2C_8723B_BT_IGNORE_WLANACT; - h2c.ignore_wlan.data = 0; - rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.ignore_wlan)); -} - -static void rtl8723bu_init_aggregation(struct rtl8xxxu_priv *priv) -{ - u32 agg_rx; - u8 agg_ctrl; - - /* - * For now simply disable RX aggregation - */ - agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL); - agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN; - - agg_rx = rtl8xxxu_read32(priv, REG_RXDMA_AGG_PG_TH); - agg_rx &= ~RXDMA_USB_AGG_ENABLE; - agg_rx &= ~0xff0f; - - rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl); - rtl8xxxu_write32(priv, REG_RXDMA_AGG_PG_TH, agg_rx); -} - -static void rtl8723bu_init_statistics(struct rtl8xxxu_priv *priv) -{ - u32 val32; - - /* Time duration for NHM unit: 4us, 0x2710=40ms */ - rtl8xxxu_write16(priv, REG_NHM_TIMER_8723B + 2, 0x2710); - rtl8xxxu_write16(priv, REG_NHM_TH9_TH10_8723B + 2, 0xffff); - rtl8xxxu_write32(priv, REG_NHM_TH3_TO_TH0_8723B, 0xffffff52); - rtl8xxxu_write32(priv, REG_NHM_TH7_TO_TH4_8723B, 0xffffffff); - /* TH8 */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); - val32 |= 0xff; - rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); - /* Enable CCK */ - val32 = rtl8xxxu_read32(priv, REG_NHM_TH9_TH10_8723B); - val32 |= BIT(8) | BIT(9) | BIT(10); - rtl8xxxu_write32(priv, REG_NHM_TH9_TH10_8723B, val32); - /* Max power amongst all RX antennas */ - val32 = rtl8xxxu_read32(priv, REG_OFDM0_FA_RSTC); - val32 |= BIT(7); - rtl8xxxu_write32(priv, REG_OFDM0_FA_RSTC, val32); -} - -static s8 rtl8723b_cck_rssi(struct rtl8xxxu_priv *priv, struct rtl8723au_phy_stats *phy_stats) -{ - u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a; - s8 rx_pwr_all = 0x00; - u8 vga_idx, lna_idx; - - lna_idx = u8_get_bits(cck_agc_rpt, CCK_AGC_RPT_LNA_IDX_MASK); - vga_idx = u8_get_bits(cck_agc_rpt, CCK_AGC_RPT_VGA_IDX_MASK); - - switch (lna_idx) { - case 6: - rx_pwr_all = -34 - (2 * vga_idx); - break; - case 4: - rx_pwr_all = -14 - (2 * vga_idx); - break; - case 1: - rx_pwr_all = 6 - (2 * vga_idx); - break; - case 0: - rx_pwr_all = 16 - (2 * vga_idx); - break; - default: - break; - } - - return rx_pwr_all; -} - -static int rtl8723bu_led_brightness_set(struct led_classdev *led_cdev, - enum led_brightness brightness) -{ - struct rtl8xxxu_priv *priv = container_of(led_cdev, - struct rtl8xxxu_priv, - led_cdev); - u8 ledcfg = rtl8xxxu_read8(priv, REG_LEDCFG2); - - ledcfg &= LEDCFG2_DPDT_SELECT; - - if (brightness == LED_OFF) - ledcfg |= LEDCFG2_SW_LED_CONTROL | LEDCFG2_SW_LED_DISABLE; - else if (brightness == LED_ON) - ledcfg |= LEDCFG2_SW_LED_CONTROL; - else if (brightness == RTL8XXXU_HW_LED_CONTROL) - ledcfg |= LEDCFG2_HW_LED_CONTROL | LEDCFG2_HW_LED_ENABLE; - - rtl8xxxu_write8(priv, REG_LEDCFG2, ledcfg); - - return 0; -} - -struct rtl8xxxu_fileops rtl8723bu_fops = { - .identify_chip = rtl8723bu_identify_chip, - .parse_efuse = rtl8723bu_parse_efuse, - .load_firmware = rtl8723bu_load_firmware, - .power_on = rtl8723bu_power_on, - .power_off = rtl8723bu_power_off, - .read_efuse = rtl8xxxu_read_efuse, - .reset_8051 = rtl8723bu_reset_8051, - .llt_init = rtl8xxxu_auto_llt_table, - .init_phy_bb = rtl8723bu_init_phy_bb, - .init_phy_rf = rtl8723bu_init_phy_rf, - .phy_init_antenna_selection = rtl8723bu_phy_init_antenna_selection, - .phy_lc_calibrate = rtl8723a_phy_lc_calibrate, - .phy_iq_calibrate = rtl8723bu_phy_iq_calibrate, - .config_channel = rtl8xxxu_gen2_config_channel, - .parse_rx_desc = rtl8xxxu_parse_rxdesc24, - .parse_phystats = rtl8723au_rx_parse_phystats, - .init_aggregation = rtl8723bu_init_aggregation, - .init_statistics = rtl8723bu_init_statistics, - .init_burst = rtl8xxxu_init_burst, - .enable_rf = rtl8723b_enable_rf, - .disable_rf = rtl8xxxu_gen2_disable_rf, - .usb_quirks = rtl8xxxu_gen2_usb_quirks, - .set_tx_power = rtl8723b_set_tx_power, - .update_rate_mask = rtl8xxxu_gen2_update_rate_mask, - .report_connect = rtl8xxxu_gen2_report_connect, - .report_rssi = rtl8xxxu_gen2_report_rssi, - .fill_txdesc = rtl8xxxu_fill_txdesc_v2, - .set_crystal_cap = rtl8723a_set_crystal_cap, - .cck_rssi = rtl8723b_cck_rssi, - .led_classdev_brightness_set = rtl8723bu_led_brightness_set, - .writeN_block_size = 1024, - .tx_desc_size = sizeof(struct rtl8xxxu_txdesc40), - .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc24), - .has_s0s1 = 1, - .has_tx_report = 1, - .gen2_thermal_meter = 1, - .needs_full_init = 1, - .init_reg_hmtfr = 1, - .ampdu_max_time = 0x5e, - .ustime_tsf_edca = 0x50, - .max_aggr_num = 0x0c14, - .supports_ap = 1, - .max_macid_num = 128, - .max_sec_cam_num = 64, - .adda_1t_init = 0x01c00014, - .adda_1t_path_on = 0x01c00014, - .adda_2t_path_on_a = 0x01c00014, - .adda_2t_path_on_b = 0x01c00014, - .trxff_boundary = 0x3f7f, - .pbp_rx = PBP_PAGE_SIZE_256, - .pbp_tx = PBP_PAGE_SIZE_256, - .mactable = rtl8723b_mac_init_table, - .total_page_num = TX_TOTAL_PAGE_NUM_8723B, - .page_num_hi = TX_PAGE_NUM_HI_PQ_8723B, - .page_num_lo = TX_PAGE_NUM_LO_PQ_8723B, - .page_num_norm = TX_PAGE_NUM_NORM_PQ_8723B, -}; diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c deleted file mode 100644 index 54f955b01475..000000000000 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c +++ /dev/null @@ -1,8302 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * RTL8XXXU mac80211 USB driver - * - * Copyright (c) 2014 - 2017 Jes Sorensen - * - * Portions, notably calibration code: - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This driver was written as a replacement for the vendor provided - * rtl8723au driver. As the Realtek 8xxx chips are very similar in - * their programming interface, I have started adding support for - * additional 8xxx chips like the 8192cu, 8188cus, etc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "rtl8xxxu.h" -#include "rtl8xxxu_regs.h" - -#define DRIVER_NAME "rtl8xxxu" - -int rtl8xxxu_debug; -static bool rtl8xxxu_ht40_2g; -static bool rtl8xxxu_dma_aggregation; -static int rtl8xxxu_dma_agg_timeout = -1; -static int rtl8xxxu_dma_agg_pages = -1; - -MODULE_AUTHOR("Jes Sorensen "); -MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver"); -MODULE_LICENSE("GPL"); -MODULE_FIRMWARE("rtlwifi/rtl8723aufw_A.bin"); -MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B.bin"); -MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B_NoBT.bin"); -MODULE_FIRMWARE("rtlwifi/rtl8188eufw.bin"); -MODULE_FIRMWARE("rtlwifi/rtl8192cufw_A.bin"); -MODULE_FIRMWARE("rtlwifi/rtl8192cufw_B.bin"); -MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin"); -MODULE_FIRMWARE("rtlwifi/rtl8192eu_nic.bin"); -MODULE_FIRMWARE("rtlwifi/rtl8723bu_nic.bin"); -MODULE_FIRMWARE("rtlwifi/rtl8723bu_bt.bin"); -MODULE_FIRMWARE("rtlwifi/rtl8188fufw.bin"); -MODULE_FIRMWARE("rtlwifi/rtl8710bufw_SMIC.bin"); -MODULE_FIRMWARE("rtlwifi/rtl8710bufw_UMC.bin"); -MODULE_FIRMWARE("rtlwifi/rtl8192fufw.bin"); - -module_param_named(debug, rtl8xxxu_debug, int, 0600); -MODULE_PARM_DESC(debug, "Set debug mask"); -module_param_named(ht40_2g, rtl8xxxu_ht40_2g, bool, 0600); -MODULE_PARM_DESC(ht40_2g, "Enable HT40 support on the 2.4GHz band"); -module_param_named(dma_aggregation, rtl8xxxu_dma_aggregation, bool, 0600); -MODULE_PARM_DESC(dma_aggregation, "Enable DMA packet aggregation"); -module_param_named(dma_agg_timeout, rtl8xxxu_dma_agg_timeout, int, 0600); -MODULE_PARM_DESC(dma_agg_timeout, "Set DMA aggregation timeout (range 1-127)"); -module_param_named(dma_agg_pages, rtl8xxxu_dma_agg_pages, int, 0600); -MODULE_PARM_DESC(dma_agg_pages, "Set DMA aggregation pages (range 1-127, 0 to disable)"); - -#define USB_VENDOR_ID_REALTEK 0x0bda -#define RTL8XXXU_RX_URBS 32 -#define RTL8XXXU_RX_URB_PENDING_WATER 8 -#define RTL8XXXU_TX_URBS 64 -#define RTL8XXXU_TX_URB_LOW_WATER 25 -#define RTL8XXXU_TX_URB_HIGH_WATER 32 - -static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv, - struct rtl8xxxu_rx_urb *rx_urb); - -static struct ieee80211_rate rtl8xxxu_rates[] = { - { .bitrate = 10, .hw_value = DESC_RATE_1M, .flags = 0 }, - { .bitrate = 20, .hw_value = DESC_RATE_2M, .flags = 0 }, - { .bitrate = 55, .hw_value = DESC_RATE_5_5M, .flags = 0 }, - { .bitrate = 110, .hw_value = DESC_RATE_11M, .flags = 0 }, - { .bitrate = 60, .hw_value = DESC_RATE_6M, .flags = 0 }, - { .bitrate = 90, .hw_value = DESC_RATE_9M, .flags = 0 }, - { .bitrate = 120, .hw_value = DESC_RATE_12M, .flags = 0 }, - { .bitrate = 180, .hw_value = DESC_RATE_18M, .flags = 0 }, - { .bitrate = 240, .hw_value = DESC_RATE_24M, .flags = 0 }, - { .bitrate = 360, .hw_value = DESC_RATE_36M, .flags = 0 }, - { .bitrate = 480, .hw_value = DESC_RATE_48M, .flags = 0 }, - { .bitrate = 540, .hw_value = DESC_RATE_54M, .flags = 0 }, -}; - -static struct ieee80211_channel rtl8xxxu_channels_2g[] = { - { .band = NL80211_BAND_2GHZ, .center_freq = 2412, - .hw_value = 1, .max_power = 30 }, - { .band = NL80211_BAND_2GHZ, .center_freq = 2417, - .hw_value = 2, .max_power = 30 }, - { .band = NL80211_BAND_2GHZ, .center_freq = 2422, - .hw_value = 3, .max_power = 30 }, - { .band = NL80211_BAND_2GHZ, .center_freq = 2427, - .hw_value = 4, .max_power = 30 }, - { .band = NL80211_BAND_2GHZ, .center_freq = 2432, - .hw_value = 5, .max_power = 30 }, - { .band = NL80211_BAND_2GHZ, .center_freq = 2437, - .hw_value = 6, .max_power = 30 }, - { .band = NL80211_BAND_2GHZ, .center_freq = 2442, - .hw_value = 7, .max_power = 30 }, - { .band = NL80211_BAND_2GHZ, .center_freq = 2447, - .hw_value = 8, .max_power = 30 }, - { .band = NL80211_BAND_2GHZ, .center_freq = 2452, - .hw_value = 9, .max_power = 30 }, - { .band = NL80211_BAND_2GHZ, .center_freq = 2457, - .hw_value = 10, .max_power = 30 }, - { .band = NL80211_BAND_2GHZ, .center_freq = 2462, - .hw_value = 11, .max_power = 30 }, - { .band = NL80211_BAND_2GHZ, .center_freq = 2467, - .hw_value = 12, .max_power = 30 }, - { .band = NL80211_BAND_2GHZ, .center_freq = 2472, - .hw_value = 13, .max_power = 30 }, - { .band = NL80211_BAND_2GHZ, .center_freq = 2484, - .hw_value = 14, .max_power = 30 } -}; - -static struct ieee80211_supported_band rtl8xxxu_supported_band = { - .channels = rtl8xxxu_channels_2g, - .n_channels = ARRAY_SIZE(rtl8xxxu_channels_2g), - .bitrates = rtl8xxxu_rates, - .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates), -}; - -static const struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = { - {0x800, 0x80040000}, {0x804, 0x00000003}, - {0x808, 0x0000fc00}, {0x80c, 0x0000000a}, - {0x810, 0x10001331}, {0x814, 0x020c3d10}, - {0x818, 0x02200385}, {0x81c, 0x00000000}, - {0x820, 0x01000100}, {0x824, 0x00390004}, - {0x828, 0x00000000}, {0x82c, 0x00000000}, - {0x830, 0x00000000}, {0x834, 0x00000000}, - {0x838, 0x00000000}, {0x83c, 0x00000000}, - {0x840, 0x00010000}, {0x844, 0x00000000}, - {0x848, 0x00000000}, {0x84c, 0x00000000}, - {0x850, 0x00000000}, {0x854, 0x00000000}, - {0x858, 0x569a569a}, {0x85c, 0x001b25a4}, - {0x860, 0x66f60110}, {0x864, 0x061f0130}, - {0x868, 0x00000000}, {0x86c, 0x32323200}, - {0x870, 0x07000760}, {0x874, 0x22004000}, - {0x878, 0x00000808}, {0x87c, 0x00000000}, - {0x880, 0xc0083070}, {0x884, 0x000004d5}, - {0x888, 0x00000000}, {0x88c, 0xccc000c0}, - {0x890, 0x00000800}, {0x894, 0xfffffffe}, - {0x898, 0x40302010}, {0x89c, 0x00706050}, - {0x900, 0x00000000}, {0x904, 0x00000023}, - {0x908, 0x00000000}, {0x90c, 0x81121111}, - {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c}, - {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f}, - {0xa10, 0x9500bb78}, {0xa14, 0x11144028}, - {0xa18, 0x00881117}, {0xa1c, 0x89140f00}, - {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317}, - {0xa28, 0x00000204}, {0xa2c, 0x00d30000}, - {0xa70, 0x101fbf00}, {0xa74, 0x00000007}, - {0xa78, 0x00000900}, - {0xc00, 0x48071d40}, {0xc04, 0x03a05611}, - {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c}, - {0xc10, 0x08800000}, {0xc14, 0x40000100}, - {0xc18, 0x08800000}, {0xc1c, 0x40000100}, - {0xc20, 0x00000000}, {0xc24, 0x00000000}, - {0xc28, 0x00000000}, {0xc2c, 0x00000000}, - {0xc30, 0x69e9ac44}, {0xc34, 0x469652af}, - {0xc38, 0x49795994}, {0xc3c, 0x0a97971c}, - {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7}, - {0xc48, 0xec020107}, {0xc4c, 0x007f037f}, - {0xc50, 0x69543420}, {0xc54, 0x43bc0094}, - {0xc58, 0x69543420}, {0xc5c, 0x433c0094}, - {0xc60, 0x00000000}, {0xc64, 0x7112848b}, - {0xc68, 0x47c00bff}, {0xc6c, 0x00000036}, - {0xc70, 0x2c7f000d}, {0xc74, 0x018610db}, - {0xc78, 0x0000001f}, {0xc7c, 0x00b91612}, - {0xc80, 0x40000100}, {0xc84, 0x20f60000}, - {0xc88, 0x40000100}, {0xc8c, 0x20200000}, - {0xc90, 0x00121820}, {0xc94, 0x00000000}, - {0xc98, 0x00121820}, {0xc9c, 0x00007f7f}, - {0xca0, 0x00000000}, {0xca4, 0x00000080}, - {0xca8, 0x00000000}, {0xcac, 0x00000000}, - {0xcb0, 0x00000000}, {0xcb4, 0x00000000}, - {0xcb8, 0x00000000}, {0xcbc, 0x28000000}, - {0xcc0, 0x00000000}, {0xcc4, 0x00000000}, - {0xcc8, 0x00000000}, {0xccc, 0x00000000}, - {0xcd0, 0x00000000}, {0xcd4, 0x00000000}, - {0xcd8, 0x64b22427}, {0xcdc, 0x00766932}, - {0xce0, 0x00222222}, {0xce4, 0x00000000}, - {0xce8, 0x37644302}, {0xcec, 0x2f97d40c}, - {0xd00, 0x00080740}, {0xd04, 0x00020401}, - {0xd08, 0x0000907f}, {0xd0c, 0x20010201}, - {0xd10, 0xa0633333}, {0xd14, 0x3333bc43}, - {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975}, - {0xd30, 0x00000000}, {0xd34, 0x80608000}, - {0xd38, 0x00000000}, {0xd3c, 0x00027293}, - {0xd40, 0x00000000}, {0xd44, 0x00000000}, - {0xd48, 0x00000000}, {0xd4c, 0x00000000}, - {0xd50, 0x6437140a}, {0xd54, 0x00000000}, - {0xd58, 0x00000000}, {0xd5c, 0x30032064}, - {0xd60, 0x4653de68}, {0xd64, 0x04518a3c}, - {0xd68, 0x00002101}, {0xd6c, 0x2a201c16}, - {0xd70, 0x1812362e}, {0xd74, 0x322c2220}, - {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a}, - {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a}, - {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a}, - {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a}, - {0xe28, 0x00000000}, {0xe30, 0x1000dc1f}, - {0xe34, 0x10008c1f}, {0xe38, 0x02140102}, - {0xe3c, 0x681604c2}, {0xe40, 0x01007c00}, - {0xe44, 0x01004800}, {0xe48, 0xfb000000}, - {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f}, - {0xe54, 0x10008c1f}, {0xe58, 0x02140102}, - {0xe5c, 0x28160d05}, {0xe60, 0x00000008}, - {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0}, - {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0}, - {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0}, - {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0}, - {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0}, - {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0}, - {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0}, - {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0}, - {0xf14, 0x00000003}, {0xf4c, 0x00000000}, - {0xf00, 0x00000300}, - {0xffff, 0xffffffff}, -}; - -static const struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = { - {0x024, 0x0011800f}, {0x028, 0x00ffdb83}, - {0x800, 0x80040002}, {0x804, 0x00000003}, - {0x808, 0x0000fc00}, {0x80c, 0x0000000a}, - {0x810, 0x10000330}, {0x814, 0x020c3d10}, - {0x818, 0x02200385}, {0x81c, 0x00000000}, - {0x820, 0x01000100}, {0x824, 0x00390004}, - {0x828, 0x01000100}, {0x82c, 0x00390004}, - {0x830, 0x27272727}, {0x834, 0x27272727}, - {0x838, 0x27272727}, {0x83c, 0x27272727}, - {0x840, 0x00010000}, {0x844, 0x00010000}, - {0x848, 0x27272727}, {0x84c, 0x27272727}, - {0x850, 0x00000000}, {0x854, 0x00000000}, - {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4}, - {0x860, 0x66e60230}, {0x864, 0x061f0130}, - {0x868, 0x27272727}, {0x86c, 0x2b2b2b27}, - {0x870, 0x07000700}, {0x874, 0x22184000}, - {0x878, 0x08080808}, {0x87c, 0x00000000}, - {0x880, 0xc0083070}, {0x884, 0x000004d5}, - {0x888, 0x00000000}, {0x88c, 0xcc0000c0}, - {0x890, 0x00000800}, {0x894, 0xfffffffe}, - {0x898, 0x40302010}, {0x89c, 0x00706050}, - {0x900, 0x00000000}, {0x904, 0x00000023}, - {0x908, 0x00000000}, {0x90c, 0x81121313}, - {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c}, - {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f}, - {0xa10, 0x9500bb78}, {0xa14, 0x11144028}, - {0xa18, 0x00881117}, {0xa1c, 0x89140f00}, - {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317}, - {0xa28, 0x00000204}, {0xa2c, 0x00d30000}, - {0xa70, 0x101fbf00}, {0xa74, 0x00000007}, - {0xc00, 0x48071d40}, {0xc04, 0x03a05633}, - {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c}, - {0xc10, 0x08800000}, {0xc14, 0x40000100}, - {0xc18, 0x08800000}, {0xc1c, 0x40000100}, - {0xc20, 0x00000000}, {0xc24, 0x00000000}, - {0xc28, 0x00000000}, {0xc2c, 0x00000000}, - {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf}, - {0xc38, 0x49795994}, {0xc3c, 0x0a97971c}, - {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7}, - {0xc48, 0xec020107}, {0xc4c, 0x007f037f}, - {0xc50, 0x69543420}, {0xc54, 0x43bc0094}, - {0xc58, 0x69543420}, {0xc5c, 0x433c0094}, - {0xc60, 0x00000000}, {0xc64, 0x5116848b}, - {0xc68, 0x47c00bff}, {0xc6c, 0x00000036}, - {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b}, - {0xc78, 0x0000001f}, {0xc7c, 0x00b99612}, - {0xc80, 0x40000100}, {0xc84, 0x20f60000}, - {0xc88, 0x40000100}, {0xc8c, 0xa0e40000}, - {0xc90, 0x00121820}, {0xc94, 0x00000000}, - {0xc98, 0x00121820}, {0xc9c, 0x00007f7f}, - {0xca0, 0x00000000}, {0xca4, 0x00000080}, - {0xca8, 0x00000000}, {0xcac, 0x00000000}, - {0xcb0, 0x00000000}, {0xcb4, 0x00000000}, - {0xcb8, 0x00000000}, {0xcbc, 0x28000000}, - {0xcc0, 0x00000000}, {0xcc4, 0x00000000}, - {0xcc8, 0x00000000}, {0xccc, 0x00000000}, - {0xcd0, 0x00000000}, {0xcd4, 0x00000000}, - {0xcd8, 0x64b22427}, {0xcdc, 0x00766932}, - {0xce0, 0x00222222}, {0xce4, 0x00000000}, - {0xce8, 0x37644302}, {0xcec, 0x2f97d40c}, - {0xd00, 0x00080740}, {0xd04, 0x00020403}, - {0xd08, 0x0000907f}, {0xd0c, 0x20010201}, - {0xd10, 0xa0633333}, {0xd14, 0x3333bc43}, - {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975}, - {0xd30, 0x00000000}, {0xd34, 0x80608000}, - {0xd38, 0x00000000}, {0xd3c, 0x00027293}, - {0xd40, 0x00000000}, {0xd44, 0x00000000}, - {0xd48, 0x00000000}, {0xd4c, 0x00000000}, - {0xd50, 0x6437140a}, {0xd54, 0x00000000}, - {0xd58, 0x00000000}, {0xd5c, 0x30032064}, - {0xd60, 0x4653de68}, {0xd64, 0x04518a3c}, - {0xd68, 0x00002101}, {0xd6c, 0x2a201c16}, - {0xd70, 0x1812362e}, {0xd74, 0x322c2220}, - {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a}, - {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a}, - {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a}, - {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a}, - {0xe28, 0x00000000}, {0xe30, 0x1000dc1f}, - {0xe34, 0x10008c1f}, {0xe38, 0x02140102}, - {0xe3c, 0x681604c2}, {0xe40, 0x01007c00}, - {0xe44, 0x01004800}, {0xe48, 0xfb000000}, - {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f}, - {0xe54, 0x10008c1f}, {0xe58, 0x02140102}, - {0xe5c, 0x28160d05}, {0xe60, 0x00000010}, - {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4}, - {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4}, - {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4}, - {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4}, - {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4}, - {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4}, - {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4}, - {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4}, - {0xf14, 0x00000003}, {0xf4c, 0x00000000}, - {0xf00, 0x00000300}, - {0xffff, 0xffffffff}, -}; - -static const struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = { - {0x024, 0x0011800f}, {0x028, 0x00ffdb83}, - {0x040, 0x000c0004}, {0x800, 0x80040000}, - {0x804, 0x00000001}, {0x808, 0x0000fc00}, - {0x80c, 0x0000000a}, {0x810, 0x10005388}, - {0x814, 0x020c3d10}, {0x818, 0x02200385}, - {0x81c, 0x00000000}, {0x820, 0x01000100}, - {0x824, 0x00390204}, {0x828, 0x00000000}, - {0x82c, 0x00000000}, {0x830, 0x00000000}, - {0x834, 0x00000000}, {0x838, 0x00000000}, - {0x83c, 0x00000000}, {0x840, 0x00010000}, - {0x844, 0x00000000}, {0x848, 0x00000000}, - {0x84c, 0x00000000}, {0x850, 0x00000000}, - {0x854, 0x00000000}, {0x858, 0x569a569a}, - {0x85c, 0x001b25a4}, {0x860, 0x66e60230}, - {0x864, 0x061f0130}, {0x868, 0x00000000}, - {0x86c, 0x20202000}, {0x870, 0x03000300}, - {0x874, 0x22004000}, {0x878, 0x00000808}, - {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070}, - {0x884, 0x000004d5}, {0x888, 0x00000000}, - {0x88c, 0xccc000c0}, {0x890, 0x00000800}, - {0x894, 0xfffffffe}, {0x898, 0x40302010}, - {0x89c, 0x00706050}, {0x900, 0x00000000}, - {0x904, 0x00000023}, {0x908, 0x00000000}, - {0x90c, 0x81121111}, {0xa00, 0x00d047c8}, - {0xa04, 0x80ff000c}, {0xa08, 0x8c838300}, - {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78}, - {0xa14, 0x11144028}, {0xa18, 0x00881117}, - {0xa1c, 0x89140f00}, {0xa20, 0x15160000}, - {0xa24, 0x070b0f12}, {0xa28, 0x00000104}, - {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00}, - {0xa74, 0x00000007}, {0xc00, 0x48071d40}, - {0xc04, 0x03a05611}, {0xc08, 0x000000e4}, - {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000}, - {0xc14, 0x40000100}, {0xc18, 0x08800000}, - {0xc1c, 0x40000100}, {0xc20, 0x00000000}, - {0xc24, 0x00000000}, {0xc28, 0x00000000}, - {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44}, - {0xc34, 0x469652cf}, {0xc38, 0x49795994}, - {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f}, - {0xc44, 0x000100b7}, {0xc48, 0xec020107}, - {0xc4c, 0x007f037f}, {0xc50, 0x6954342e}, - {0xc54, 0x43bc0094}, {0xc58, 0x6954342f}, - {0xc5c, 0x433c0094}, {0xc60, 0x00000000}, - {0xc64, 0x5116848b}, {0xc68, 0x47c00bff}, - {0xc6c, 0x00000036}, {0xc70, 0x2c46000d}, - {0xc74, 0x018610db}, {0xc78, 0x0000001f}, - {0xc7c, 0x00b91612}, {0xc80, 0x24000090}, - {0xc84, 0x20f60000}, {0xc88, 0x24000090}, - {0xc8c, 0x20200000}, {0xc90, 0x00121820}, - {0xc94, 0x00000000}, {0xc98, 0x00121820}, - {0xc9c, 0x00007f7f}, {0xca0, 0x00000000}, - {0xca4, 0x00000080}, {0xca8, 0x00000000}, - {0xcac, 0x00000000}, {0xcb0, 0x00000000}, - {0xcb4, 0x00000000}, {0xcb8, 0x00000000}, - {0xcbc, 0x28000000}, {0xcc0, 0x00000000}, - {0xcc4, 0x00000000}, {0xcc8, 0x00000000}, - {0xccc, 0x00000000}, {0xcd0, 0x00000000}, - {0xcd4, 0x00000000}, {0xcd8, 0x64b22427}, - {0xcdc, 0x00766932}, {0xce0, 0x00222222}, - {0xce4, 0x00000000}, {0xce8, 0x37644302}, - {0xcec, 0x2f97d40c}, {0xd00, 0x00080740}, - {0xd04, 0x00020401}, {0xd08, 0x0000907f}, - {0xd0c, 0x20010201}, {0xd10, 0xa0633333}, - {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b}, - {0xd2c, 0xcc979975}, {0xd30, 0x00000000}, - {0xd34, 0x80608000}, {0xd38, 0x00000000}, - {0xd3c, 0x00027293}, {0xd40, 0x00000000}, - {0xd44, 0x00000000}, {0xd48, 0x00000000}, - {0xd4c, 0x00000000}, {0xd50, 0x6437140a}, - {0xd54, 0x00000000}, {0xd58, 0x00000000}, - {0xd5c, 0x30032064}, {0xd60, 0x4653de68}, - {0xd64, 0x04518a3c}, {0xd68, 0x00002101}, - {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e}, - {0xd74, 0x322c2220}, {0xd78, 0x000e3c24}, - {0xe00, 0x24242424}, {0xe04, 0x24242424}, - {0xe08, 0x03902024}, {0xe10, 0x24242424}, - {0xe14, 0x24242424}, {0xe18, 0x24242424}, - {0xe1c, 0x24242424}, {0xe28, 0x00000000}, - {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f}, - {0xe38, 0x02140102}, {0xe3c, 0x681604c2}, - {0xe40, 0x01007c00}, {0xe44, 0x01004800}, - {0xe48, 0xfb000000}, {0xe4c, 0x000028d1}, - {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f}, - {0xe58, 0x02140102}, {0xe5c, 0x28160d05}, - {0xe60, 0x00000008}, {0xe68, 0x001b25a4}, - {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0}, - {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0}, - {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0}, - {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0}, - {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0}, - {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0}, - {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0}, - {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448}, - {0xf14, 0x00000003}, {0xf4c, 0x00000000}, - {0xf00, 0x00000300}, - {0xffff, 0xffffffff}, -}; - -static const struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = { - {0xc78, 0x7b000001}, {0xc78, 0x7b010001}, - {0xc78, 0x7b020001}, {0xc78, 0x7b030001}, - {0xc78, 0x7b040001}, {0xc78, 0x7b050001}, - {0xc78, 0x7a060001}, {0xc78, 0x79070001}, - {0xc78, 0x78080001}, {0xc78, 0x77090001}, - {0xc78, 0x760a0001}, {0xc78, 0x750b0001}, - {0xc78, 0x740c0001}, {0xc78, 0x730d0001}, - {0xc78, 0x720e0001}, {0xc78, 0x710f0001}, - {0xc78, 0x70100001}, {0xc78, 0x6f110001}, - {0xc78, 0x6e120001}, {0xc78, 0x6d130001}, - {0xc78, 0x6c140001}, {0xc78, 0x6b150001}, - {0xc78, 0x6a160001}, {0xc78, 0x69170001}, - {0xc78, 0x68180001}, {0xc78, 0x67190001}, - {0xc78, 0x661a0001}, {0xc78, 0x651b0001}, - {0xc78, 0x641c0001}, {0xc78, 0x631d0001}, - {0xc78, 0x621e0001}, {0xc78, 0x611f0001}, - {0xc78, 0x60200001}, {0xc78, 0x49210001}, - {0xc78, 0x48220001}, {0xc78, 0x47230001}, - {0xc78, 0x46240001}, {0xc78, 0x45250001}, - {0xc78, 0x44260001}, {0xc78, 0x43270001}, - {0xc78, 0x42280001}, {0xc78, 0x41290001}, - {0xc78, 0x402a0001}, {0xc78, 0x262b0001}, - {0xc78, 0x252c0001}, {0xc78, 0x242d0001}, - {0xc78, 0x232e0001}, {0xc78, 0x222f0001}, - {0xc78, 0x21300001}, {0xc78, 0x20310001}, - {0xc78, 0x06320001}, {0xc78, 0x05330001}, - {0xc78, 0x04340001}, {0xc78, 0x03350001}, - {0xc78, 0x02360001}, {0xc78, 0x01370001}, - {0xc78, 0x00380001}, {0xc78, 0x00390001}, - {0xc78, 0x003a0001}, {0xc78, 0x003b0001}, - {0xc78, 0x003c0001}, {0xc78, 0x003d0001}, - {0xc78, 0x003e0001}, {0xc78, 0x003f0001}, - {0xc78, 0x7b400001}, {0xc78, 0x7b410001}, - {0xc78, 0x7b420001}, {0xc78, 0x7b430001}, - {0xc78, 0x7b440001}, {0xc78, 0x7b450001}, - {0xc78, 0x7a460001}, {0xc78, 0x79470001}, - {0xc78, 0x78480001}, {0xc78, 0x77490001}, - {0xc78, 0x764a0001}, {0xc78, 0x754b0001}, - {0xc78, 0x744c0001}, {0xc78, 0x734d0001}, - {0xc78, 0x724e0001}, {0xc78, 0x714f0001}, - {0xc78, 0x70500001}, {0xc78, 0x6f510001}, - {0xc78, 0x6e520001}, {0xc78, 0x6d530001}, - {0xc78, 0x6c540001}, {0xc78, 0x6b550001}, - {0xc78, 0x6a560001}, {0xc78, 0x69570001}, - {0xc78, 0x68580001}, {0xc78, 0x67590001}, - {0xc78, 0x665a0001}, {0xc78, 0x655b0001}, - {0xc78, 0x645c0001}, {0xc78, 0x635d0001}, - {0xc78, 0x625e0001}, {0xc78, 0x615f0001}, - {0xc78, 0x60600001}, {0xc78, 0x49610001}, - {0xc78, 0x48620001}, {0xc78, 0x47630001}, - {0xc78, 0x46640001}, {0xc78, 0x45650001}, - {0xc78, 0x44660001}, {0xc78, 0x43670001}, - {0xc78, 0x42680001}, {0xc78, 0x41690001}, - {0xc78, 0x406a0001}, {0xc78, 0x266b0001}, - {0xc78, 0x256c0001}, {0xc78, 0x246d0001}, - {0xc78, 0x236e0001}, {0xc78, 0x226f0001}, - {0xc78, 0x21700001}, {0xc78, 0x20710001}, - {0xc78, 0x06720001}, {0xc78, 0x05730001}, - {0xc78, 0x04740001}, {0xc78, 0x03750001}, - {0xc78, 0x02760001}, {0xc78, 0x01770001}, - {0xc78, 0x00780001}, {0xc78, 0x00790001}, - {0xc78, 0x007a0001}, {0xc78, 0x007b0001}, - {0xc78, 0x007c0001}, {0xc78, 0x007d0001}, - {0xc78, 0x007e0001}, {0xc78, 0x007f0001}, - {0xc78, 0x3800001e}, {0xc78, 0x3801001e}, - {0xc78, 0x3802001e}, {0xc78, 0x3803001e}, - {0xc78, 0x3804001e}, {0xc78, 0x3805001e}, - {0xc78, 0x3806001e}, {0xc78, 0x3807001e}, - {0xc78, 0x3808001e}, {0xc78, 0x3c09001e}, - {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e}, - {0xc78, 0x440c001e}, {0xc78, 0x480d001e}, - {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e}, - {0xc78, 0x5210001e}, {0xc78, 0x5611001e}, - {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e}, - {0xc78, 0x6014001e}, {0xc78, 0x6015001e}, - {0xc78, 0x6016001e}, {0xc78, 0x6217001e}, - {0xc78, 0x6218001e}, {0xc78, 0x6219001e}, - {0xc78, 0x621a001e}, {0xc78, 0x621b001e}, - {0xc78, 0x621c001e}, {0xc78, 0x621d001e}, - {0xc78, 0x621e001e}, {0xc78, 0x621f001e}, - {0xffff, 0xffffffff} -}; - -static const struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = { - {0xc78, 0x7b000001}, {0xc78, 0x7b010001}, - {0xc78, 0x7b020001}, {0xc78, 0x7b030001}, - {0xc78, 0x7b040001}, {0xc78, 0x7b050001}, - {0xc78, 0x7b060001}, {0xc78, 0x7b070001}, - {0xc78, 0x7b080001}, {0xc78, 0x7a090001}, - {0xc78, 0x790a0001}, {0xc78, 0x780b0001}, - {0xc78, 0x770c0001}, {0xc78, 0x760d0001}, - {0xc78, 0x750e0001}, {0xc78, 0x740f0001}, - {0xc78, 0x73100001}, {0xc78, 0x72110001}, - {0xc78, 0x71120001}, {0xc78, 0x70130001}, - {0xc78, 0x6f140001}, {0xc78, 0x6e150001}, - {0xc78, 0x6d160001}, {0xc78, 0x6c170001}, - {0xc78, 0x6b180001}, {0xc78, 0x6a190001}, - {0xc78, 0x691a0001}, {0xc78, 0x681b0001}, - {0xc78, 0x671c0001}, {0xc78, 0x661d0001}, - {0xc78, 0x651e0001}, {0xc78, 0x641f0001}, - {0xc78, 0x63200001}, {0xc78, 0x62210001}, - {0xc78, 0x61220001}, {0xc78, 0x60230001}, - {0xc78, 0x46240001}, {0xc78, 0x45250001}, - {0xc78, 0x44260001}, {0xc78, 0x43270001}, - {0xc78, 0x42280001}, {0xc78, 0x41290001}, - {0xc78, 0x402a0001}, {0xc78, 0x262b0001}, - {0xc78, 0x252c0001}, {0xc78, 0x242d0001}, - {0xc78, 0x232e0001}, {0xc78, 0x222f0001}, - {0xc78, 0x21300001}, {0xc78, 0x20310001}, - {0xc78, 0x06320001}, {0xc78, 0x05330001}, - {0xc78, 0x04340001}, {0xc78, 0x03350001}, - {0xc78, 0x02360001}, {0xc78, 0x01370001}, - {0xc78, 0x00380001}, {0xc78, 0x00390001}, - {0xc78, 0x003a0001}, {0xc78, 0x003b0001}, - {0xc78, 0x003c0001}, {0xc78, 0x003d0001}, - {0xc78, 0x003e0001}, {0xc78, 0x003f0001}, - {0xc78, 0x7b400001}, {0xc78, 0x7b410001}, - {0xc78, 0x7b420001}, {0xc78, 0x7b430001}, - {0xc78, 0x7b440001}, {0xc78, 0x7b450001}, - {0xc78, 0x7b460001}, {0xc78, 0x7b470001}, - {0xc78, 0x7b480001}, {0xc78, 0x7a490001}, - {0xc78, 0x794a0001}, {0xc78, 0x784b0001}, - {0xc78, 0x774c0001}, {0xc78, 0x764d0001}, - {0xc78, 0x754e0001}, {0xc78, 0x744f0001}, - {0xc78, 0x73500001}, {0xc78, 0x72510001}, - {0xc78, 0x71520001}, {0xc78, 0x70530001}, - {0xc78, 0x6f540001}, {0xc78, 0x6e550001}, - {0xc78, 0x6d560001}, {0xc78, 0x6c570001}, - {0xc78, 0x6b580001}, {0xc78, 0x6a590001}, - {0xc78, 0x695a0001}, {0xc78, 0x685b0001}, - {0xc78, 0x675c0001}, {0xc78, 0x665d0001}, - {0xc78, 0x655e0001}, {0xc78, 0x645f0001}, - {0xc78, 0x63600001}, {0xc78, 0x62610001}, - {0xc78, 0x61620001}, {0xc78, 0x60630001}, - {0xc78, 0x46640001}, {0xc78, 0x45650001}, - {0xc78, 0x44660001}, {0xc78, 0x43670001}, - {0xc78, 0x42680001}, {0xc78, 0x41690001}, - {0xc78, 0x406a0001}, {0xc78, 0x266b0001}, - {0xc78, 0x256c0001}, {0xc78, 0x246d0001}, - {0xc78, 0x236e0001}, {0xc78, 0x226f0001}, - {0xc78, 0x21700001}, {0xc78, 0x20710001}, - {0xc78, 0x06720001}, {0xc78, 0x05730001}, - {0xc78, 0x04740001}, {0xc78, 0x03750001}, - {0xc78, 0x02760001}, {0xc78, 0x01770001}, - {0xc78, 0x00780001}, {0xc78, 0x00790001}, - {0xc78, 0x007a0001}, {0xc78, 0x007b0001}, - {0xc78, 0x007c0001}, {0xc78, 0x007d0001}, - {0xc78, 0x007e0001}, {0xc78, 0x007f0001}, - {0xc78, 0x3800001e}, {0xc78, 0x3801001e}, - {0xc78, 0x3802001e}, {0xc78, 0x3803001e}, - {0xc78, 0x3804001e}, {0xc78, 0x3805001e}, - {0xc78, 0x3806001e}, {0xc78, 0x3807001e}, - {0xc78, 0x3808001e}, {0xc78, 0x3c09001e}, - {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e}, - {0xc78, 0x440c001e}, {0xc78, 0x480d001e}, - {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e}, - {0xc78, 0x5210001e}, {0xc78, 0x5611001e}, - {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e}, - {0xc78, 0x6014001e}, {0xc78, 0x6015001e}, - {0xc78, 0x6016001e}, {0xc78, 0x6217001e}, - {0xc78, 0x6218001e}, {0xc78, 0x6219001e}, - {0xc78, 0x621a001e}, {0xc78, 0x621b001e}, - {0xc78, 0x621c001e}, {0xc78, 0x621d001e}, - {0xc78, 0x621e001e}, {0xc78, 0x621f001e}, - {0xffff, 0xffffffff} -}; - -static const struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = { - { /* RF_A */ - .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1, - .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2, - .lssiparm = REG_FPGA0_XA_LSSI_PARM, - .hspiread = REG_HSPI_XA_READBACK, - .lssiread = REG_FPGA0_XA_LSSI_READBACK, - .rf_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL, - }, - { /* RF_B */ - .hssiparm1 = REG_FPGA0_XB_HSSI_PARM1, - .hssiparm2 = REG_FPGA0_XB_HSSI_PARM2, - .lssiparm = REG_FPGA0_XB_LSSI_PARM, - .hspiread = REG_HSPI_XB_READBACK, - .lssiread = REG_FPGA0_XB_LSSI_READBACK, - .rf_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL, - }, -}; - -const u32 rtl8xxxu_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = { - REG_OFDM0_XA_RX_IQ_IMBALANCE, - REG_OFDM0_XB_RX_IQ_IMBALANCE, - REG_OFDM0_ENERGY_CCA_THRES, - REG_OFDM0_AGC_RSSI_TABLE, - REG_OFDM0_XA_TX_IQ_IMBALANCE, - REG_OFDM0_XB_TX_IQ_IMBALANCE, - REG_OFDM0_XC_TX_AFE, - REG_OFDM0_XD_TX_AFE, - REG_OFDM0_RX_IQ_EXT_ANTA -}; - -u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr) -{ - struct usb_device *udev = priv->udev; - int len; - u8 data; - - if (priv->rtl_chip == RTL8710B && addr <= 0xff) - addr |= 0x8000; - - mutex_lock(&priv->usb_buf_mutex); - len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), - REALTEK_USB_CMD_REQ, REALTEK_USB_READ, - addr, 0, &priv->usb_buf.val8, sizeof(u8), - RTW_USB_CONTROL_MSG_TIMEOUT); - data = priv->usb_buf.val8; - mutex_unlock(&priv->usb_buf_mutex); - - if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ) - dev_info(&udev->dev, "%s(%04x) = 0x%02x, len %i\n", - __func__, addr, data, len); - return data; -} - -u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr) -{ - struct usb_device *udev = priv->udev; - int len; - u16 data; - - if (priv->rtl_chip == RTL8710B && addr <= 0xff) - addr |= 0x8000; - - mutex_lock(&priv->usb_buf_mutex); - len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), - REALTEK_USB_CMD_REQ, REALTEK_USB_READ, - addr, 0, &priv->usb_buf.val16, sizeof(u16), - RTW_USB_CONTROL_MSG_TIMEOUT); - data = le16_to_cpu(priv->usb_buf.val16); - mutex_unlock(&priv->usb_buf_mutex); - - if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ) - dev_info(&udev->dev, "%s(%04x) = 0x%04x, len %i\n", - __func__, addr, data, len); - return data; -} - -u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr) -{ - struct usb_device *udev = priv->udev; - int len; - u32 data; - - if (priv->rtl_chip == RTL8710B && addr <= 0xff) - addr |= 0x8000; - - mutex_lock(&priv->usb_buf_mutex); - len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), - REALTEK_USB_CMD_REQ, REALTEK_USB_READ, - addr, 0, &priv->usb_buf.val32, sizeof(u32), - RTW_USB_CONTROL_MSG_TIMEOUT); - data = le32_to_cpu(priv->usb_buf.val32); - mutex_unlock(&priv->usb_buf_mutex); - - if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ) - dev_info(&udev->dev, "%s(%04x) = 0x%08x, len %i\n", - __func__, addr, data, len); - return data; -} - -int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val) -{ - struct usb_device *udev = priv->udev; - int ret; - - if (priv->rtl_chip == RTL8710B && addr <= 0xff) - addr |= 0x8000; - - mutex_lock(&priv->usb_buf_mutex); - priv->usb_buf.val8 = val; - ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), - REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, - addr, 0, &priv->usb_buf.val8, sizeof(u8), - RTW_USB_CONTROL_MSG_TIMEOUT); - - mutex_unlock(&priv->usb_buf_mutex); - - if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE) - dev_info(&udev->dev, "%s(%04x) = 0x%02x\n", - __func__, addr, val); - return ret; -} - -int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val) -{ - struct usb_device *udev = priv->udev; - int ret; - - if (priv->rtl_chip == RTL8710B && addr <= 0xff) - addr |= 0x8000; - - mutex_lock(&priv->usb_buf_mutex); - priv->usb_buf.val16 = cpu_to_le16(val); - ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), - REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, - addr, 0, &priv->usb_buf.val16, sizeof(u16), - RTW_USB_CONTROL_MSG_TIMEOUT); - mutex_unlock(&priv->usb_buf_mutex); - - if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE) - dev_info(&udev->dev, "%s(%04x) = 0x%04x\n", - __func__, addr, val); - return ret; -} - -int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val) -{ - struct usb_device *udev = priv->udev; - int ret; - - if (priv->rtl_chip == RTL8710B && addr <= 0xff) - addr |= 0x8000; - - mutex_lock(&priv->usb_buf_mutex); - priv->usb_buf.val32 = cpu_to_le32(val); - ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), - REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, - addr, 0, &priv->usb_buf.val32, sizeof(u32), - RTW_USB_CONTROL_MSG_TIMEOUT); - mutex_unlock(&priv->usb_buf_mutex); - - if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE) - dev_info(&udev->dev, "%s(%04x) = 0x%08x\n", - __func__, addr, val); - return ret; -} - -int rtl8xxxu_write8_set(struct rtl8xxxu_priv *priv, u16 addr, u8 bits) -{ - u8 val8; - - val8 = rtl8xxxu_read8(priv, addr); - val8 |= bits; - return rtl8xxxu_write8(priv, addr, val8); -} - -int rtl8xxxu_write8_clear(struct rtl8xxxu_priv *priv, u16 addr, u8 bits) -{ - u8 val8; - - val8 = rtl8xxxu_read8(priv, addr); - val8 &= ~bits; - return rtl8xxxu_write8(priv, addr, val8); -} - -int rtl8xxxu_write16_set(struct rtl8xxxu_priv *priv, u16 addr, u16 bits) -{ - u16 val16; - - val16 = rtl8xxxu_read16(priv, addr); - val16 |= bits; - return rtl8xxxu_write16(priv, addr, val16); -} - -int rtl8xxxu_write16_clear(struct rtl8xxxu_priv *priv, u16 addr, u16 bits) -{ - u16 val16; - - val16 = rtl8xxxu_read16(priv, addr); - val16 &= ~bits; - return rtl8xxxu_write16(priv, addr, val16); -} - -int rtl8xxxu_write32_set(struct rtl8xxxu_priv *priv, u16 addr, u32 bits) -{ - u32 val32; - - val32 = rtl8xxxu_read32(priv, addr); - val32 |= bits; - return rtl8xxxu_write32(priv, addr, val32); -} - -int rtl8xxxu_write32_clear(struct rtl8xxxu_priv *priv, u16 addr, u32 bits) -{ - u32 val32; - - val32 = rtl8xxxu_read32(priv, addr); - val32 &= ~bits; - return rtl8xxxu_write32(priv, addr, val32); -} - -int rtl8xxxu_write32_mask(struct rtl8xxxu_priv *priv, u16 addr, - u32 mask, u32 val) -{ - u32 orig, new, shift; - - shift = __ffs(mask); - - orig = rtl8xxxu_read32(priv, addr); - new = (orig & ~mask) | ((val << shift) & mask); - return rtl8xxxu_write32(priv, addr, new); -} - -int rtl8xxxu_write_rfreg_mask(struct rtl8xxxu_priv *priv, - enum rtl8xxxu_rfpath path, u8 reg, - u32 mask, u32 val) -{ - u32 orig, new, shift; - - shift = __ffs(mask); - - orig = rtl8xxxu_read_rfreg(priv, path, reg); - new = (orig & ~mask) | ((val << shift) & mask); - return rtl8xxxu_write_rfreg(priv, path, reg, new); -} - -static int -rtl8xxxu_writeN(struct rtl8xxxu_priv *priv, u16 addr, u8 *buf, u16 len) -{ - struct usb_device *udev = priv->udev; - int blocksize = priv->fops->writeN_block_size; - int ret, i, count, remainder; - - count = len / blocksize; - remainder = len % blocksize; - - for (i = 0; i < count; i++) { - ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), - REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, - addr, 0, buf, blocksize, - RTW_USB_CONTROL_MSG_TIMEOUT); - if (ret != blocksize) - goto write_error; - - addr += blocksize; - buf += blocksize; - } - - if (remainder) { - ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), - REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, - addr, 0, buf, remainder, - RTW_USB_CONTROL_MSG_TIMEOUT); - if (ret != remainder) - goto write_error; - } - - return len; - -write_error: - dev_info(&udev->dev, - "%s: Failed to write block at addr: %04x size: %04x\n", - __func__, addr, blocksize); - return -EAGAIN; -} - -u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv, - enum rtl8xxxu_rfpath path, u8 reg) -{ - u32 hssia, val32, retval; - - hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2); - if (path != RF_A) - val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2); - else - val32 = hssia; - - val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK; - val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT); - val32 |= FPGA0_HSSI_PARM2_EDGE_READ; - hssia &= ~FPGA0_HSSI_PARM2_EDGE_READ; - rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia); - - udelay(10); - - rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32); - udelay(100); - - hssia |= FPGA0_HSSI_PARM2_EDGE_READ; - rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia); - udelay(10); - - val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1); - if (val32 & FPGA0_HSSI_PARM1_PI) - retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread); - else - retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread); - - retval &= 0xfffff; - - if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_READ) - dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n", - __func__, reg, retval); - return retval; -} - -/* - * The RTL8723BU driver indicates that registers 0xb2 and 0xb6 can - * have write issues in high temperature conditions. We may have to - * retry writing them. - */ -int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv, - enum rtl8xxxu_rfpath path, u8 reg, u32 data) -{ - int ret, retval; - u32 dataaddr, val32; - - if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE) - dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n", - __func__, reg, data); - - data &= FPGA0_LSSI_PARM_DATA_MASK; - dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data; - - if (priv->rtl_chip == RTL8192E) { - val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); - val32 &= ~0x20000; - rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); - } - - /* Use XB for path B */ - ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr); - if (ret != sizeof(dataaddr)) - retval = -EIO; - else - retval = 0; - - udelay(1); - - if (priv->rtl_chip == RTL8192E) { - val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); - val32 |= 0x20000; - rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); - } - - return retval; -} - -static int -rtl8xxxu_gen1_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c, int len) -{ - struct device *dev = &priv->udev->dev; - int mbox_nr, retry, retval = 0; - int mbox_reg, mbox_ext_reg; - u8 val8; - - mutex_lock(&priv->h2c_mutex); - - mbox_nr = priv->next_mbox; - mbox_reg = REG_HMBOX_0 + (mbox_nr * 4); - mbox_ext_reg = REG_HMBOX_EXT_0 + (mbox_nr * 2); - - /* - * MBOX ready? - */ - retry = 100; - do { - val8 = rtl8xxxu_read8(priv, REG_HMTFR); - if (!(val8 & BIT(mbox_nr))) - break; - } while (retry--); - - if (!retry) { - dev_info(dev, "%s: Mailbox busy\n", __func__); - retval = -EBUSY; - goto error; - } - - /* - * Need to swap as it's being swapped again by rtl8xxxu_write16/32() - */ - if (len > sizeof(u32)) { - rtl8xxxu_write16(priv, mbox_ext_reg, le16_to_cpu(h2c->raw.ext)); - if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C) - dev_info(dev, "H2C_EXT %04x\n", - le16_to_cpu(h2c->raw.ext)); - } - rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data)); - if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C) - dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data)); - - priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX; - -error: - mutex_unlock(&priv->h2c_mutex); - return retval; -} - -int -rtl8xxxu_gen2_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c, int len) -{ - struct device *dev = &priv->udev->dev; - int mbox_nr, retry, retval = 0; - int mbox_reg, mbox_ext_reg; - u8 val8; - - mutex_lock(&priv->h2c_mutex); - - mbox_nr = priv->next_mbox; - mbox_reg = REG_HMBOX_0 + (mbox_nr * 4); - mbox_ext_reg = REG_HMBOX_EXT0_8723B + (mbox_nr * 4); - - /* - * MBOX ready? - */ - retry = 100; - do { - val8 = rtl8xxxu_read8(priv, REG_HMTFR); - if (!(val8 & BIT(mbox_nr))) - break; - } while (retry--); - - if (!retry) { - dev_info(dev, "%s: Mailbox busy\n", __func__); - retval = -EBUSY; - goto error; - } - - /* - * Need to swap as it's being swapped again by rtl8xxxu_write16/32() - */ - if (len > sizeof(u32)) { - rtl8xxxu_write32(priv, mbox_ext_reg, - le32_to_cpu(h2c->raw_wide.ext)); - if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C) - dev_info(dev, "H2C_EXT %08x\n", - le32_to_cpu(h2c->raw_wide.ext)); - } - rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data)); - if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C) - dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data)); - - priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX; - -error: - mutex_unlock(&priv->h2c_mutex); - return retval; -} - -void rtl8xxxu_gen1_enable_rf(struct rtl8xxxu_priv *priv) -{ - u8 val8; - u32 val32; - - val8 = rtl8xxxu_read8(priv, REG_SPS0_CTRL); - val8 |= BIT(0) | BIT(3); - rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8); - - val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM); - val32 &= ~(BIT(4) | BIT(5)); - val32 |= BIT(3); - if (priv->rf_paths == 2) { - val32 &= ~(BIT(20) | BIT(21)); - val32 |= BIT(19); - } - rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32); - - val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); - val32 &= ~OFDM_RF_PATH_TX_MASK; - if (priv->tx_paths == 2) - val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B; - else if (priv->rtl_chip == RTL8192C || priv->rtl_chip == RTL8191C) - val32 |= OFDM_RF_PATH_TX_B; - else - val32 |= OFDM_RF_PATH_TX_A; - rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); - - val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); - val32 &= ~FPGA_RF_MODE_JAPAN; - rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); - - if (priv->rf_paths == 2) - rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0); - else - rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0); - - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x32d95); - if (priv->rf_paths == 2) - rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x32d95); - - rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); -} - -void rtl8xxxu_gen1_disable_rf(struct rtl8xxxu_priv *priv) -{ - u8 sps0; - u32 val32; - - sps0 = rtl8xxxu_read8(priv, REG_SPS0_CTRL); - - /* RF RX code for preamble power saving */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM); - val32 &= ~(BIT(3) | BIT(4) | BIT(5)); - if (priv->rf_paths == 2) - val32 &= ~(BIT(19) | BIT(20) | BIT(21)); - rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32); - - /* Disable TX for four paths */ - val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); - val32 &= ~OFDM_RF_PATH_TX_MASK; - rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); - - /* Enable power saving */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); - val32 |= FPGA_RF_MODE_JAPAN; - rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); - - /* AFE control register to power down bits [30:22] */ - if (priv->rf_paths == 2) - rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0); - else - rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0); - - /* Power down RF module */ - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0); - if (priv->rf_paths == 2) - rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0); - - sps0 &= ~(BIT(0) | BIT(3)); - rtl8xxxu_write8(priv, REG_SPS0_CTRL, sps0); -} - -static void rtl8xxxu_stop_tx_beacon(struct rtl8xxxu_priv *priv) -{ - u8 val8; - - val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2); - val8 &= ~BIT(6); - rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8); - - rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x64); - val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2); - val8 &= ~BIT(0); - rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8); -} - -static void rtl8xxxu_start_tx_beacon(struct rtl8xxxu_priv *priv) -{ - u8 val8; - - val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2); - val8 |= EN_BCNQ_DL >> 16; - rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8); - - rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x80); - val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2); - val8 &= 0xF0; - rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8); -} - - -/* - * The rtl8723a has 3 channel groups for it's efuse settings. It only - * supports the 2.4GHz band, so channels 1 - 14: - * group 0: channels 1 - 3 - * group 1: channels 4 - 9 - * group 2: channels 10 - 14 - * - * Note: We index from 0 in the code - */ -static int rtl8xxxu_gen1_channel_to_group(int channel) -{ - int group; - - if (channel < 4) - group = 0; - else if (channel < 10) - group = 1; - else - group = 2; - - return group; -} - -/* - * Valid for rtl8723bu and rtl8192eu - */ -int rtl8xxxu_gen2_channel_to_group(int channel) -{ - int group; - - if (channel < 3) - group = 0; - else if (channel < 6) - group = 1; - else if (channel < 9) - group = 2; - else if (channel < 12) - group = 3; - else - group = 4; - - return group; -} - -void rtl8xxxu_gen1_config_channel(struct ieee80211_hw *hw) -{ - struct rtl8xxxu_priv *priv = hw->priv; - u32 val32, rsr; - u8 val8, opmode; - bool ht = true; - int sec_ch_above, channel; - int i; - - opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE); - rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); - channel = hw->conf.chandef.chan->hw_value; - - switch (hw->conf.chandef.width) { - case NL80211_CHAN_WIDTH_20_NOHT: - ht = false; - fallthrough; - case NL80211_CHAN_WIDTH_20: - opmode |= BW_OPMODE_20MHZ; - rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode); - - val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); - val32 &= ~FPGA_RF_MODE; - rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); - - val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); - val32 &= ~FPGA_RF_MODE; - rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); - - val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2); - val32 |= FPGA0_ANALOG2_20MHZ; - rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32); - break; - case NL80211_CHAN_WIDTH_40: - if (hw->conf.chandef.center_freq1 > - hw->conf.chandef.chan->center_freq) { - sec_ch_above = 1; - channel += 2; - } else { - sec_ch_above = 0; - channel -= 2; - } - - opmode &= ~BW_OPMODE_20MHZ; - rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode); - rsr &= ~RSR_RSC_BANDWIDTH_40M; - if (sec_ch_above) - rsr |= RSR_RSC_UPPER_SUB_CHANNEL; - else - rsr |= RSR_RSC_LOWER_SUB_CHANNEL; - rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr); - - val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); - val32 |= FPGA_RF_MODE; - rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); - - val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); - val32 |= FPGA_RF_MODE; - rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); - - /* - * Set Control channel to upper or lower. These settings - * are required only for 40MHz - */ - val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM); - val32 &= ~CCK0_SIDEBAND; - if (!sec_ch_above) - val32 |= CCK0_SIDEBAND; - rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32); - - val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF); - val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */ - if (sec_ch_above) - val32 |= OFDM_LSTF_PRIME_CH_LOW; - else - val32 |= OFDM_LSTF_PRIME_CH_HIGH; - rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); - - val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2); - val32 &= ~FPGA0_ANALOG2_20MHZ; - rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32); - - val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); - val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL); - if (sec_ch_above) - val32 |= FPGA0_PS_UPPER_CHANNEL; - else - val32 |= FPGA0_PS_LOWER_CHANNEL; - rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); - break; - - default: - break; - } - - for (i = RF_A; i < priv->rf_paths; i++) { - val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); - val32 &= ~MODE_AG_CHANNEL_MASK; - val32 |= channel; - rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); - } - - if (ht) - val8 = 0x0e; - else - val8 = 0x0a; - - rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8); - rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8); - - rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808); - rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a); - - for (i = RF_A; i < priv->rf_paths; i++) { - val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); - if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) - val32 &= ~MODE_AG_CHANNEL_20MHZ; - else - val32 |= MODE_AG_CHANNEL_20MHZ; - rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); - } -} - -void rtl8xxxu_gen2_config_channel(struct ieee80211_hw *hw) -{ - struct rtl8xxxu_priv *priv = hw->priv; - u32 val32; - u8 val8, subchannel; - u16 rf_mode_bw; - bool ht = true; - int sec_ch_above, channel; - int i; - - rf_mode_bw = rtl8xxxu_read16(priv, REG_WMAC_TRXPTCL_CTL); - rf_mode_bw &= ~WMAC_TRXPTCL_CTL_BW_MASK; - channel = hw->conf.chandef.chan->hw_value; - -/* Hack */ - subchannel = 0; - - switch (hw->conf.chandef.width) { - case NL80211_CHAN_WIDTH_20_NOHT: - ht = false; - fallthrough; - case NL80211_CHAN_WIDTH_20: - rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_20; - subchannel = 0; - - val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); - val32 &= ~FPGA_RF_MODE; - rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); - - val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); - val32 &= ~FPGA_RF_MODE; - rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); - - val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT); - val32 &= ~(BIT(30) | BIT(31)); - rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32); - - break; - case NL80211_CHAN_WIDTH_40: - rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_40; - - if (hw->conf.chandef.center_freq1 > - hw->conf.chandef.chan->center_freq) { - sec_ch_above = 1; - channel += 2; - } else { - sec_ch_above = 0; - channel -= 2; - } - - val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); - val32 |= FPGA_RF_MODE; - rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); - - val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); - val32 |= FPGA_RF_MODE; - rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); - - /* - * Set Control channel to upper or lower. These settings - * are required only for 40MHz - */ - val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM); - val32 &= ~CCK0_SIDEBAND; - if (!sec_ch_above) - val32 |= CCK0_SIDEBAND; - rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32); - - val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF); - val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */ - if (sec_ch_above) - val32 |= OFDM_LSTF_PRIME_CH_LOW; - else - val32 |= OFDM_LSTF_PRIME_CH_HIGH; - rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); - - val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); - val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL); - if (sec_ch_above) - val32 |= FPGA0_PS_UPPER_CHANNEL; - else - val32 |= FPGA0_PS_LOWER_CHANNEL; - rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); - break; - case NL80211_CHAN_WIDTH_80: - rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_80; - break; - default: - break; - } - - for (i = RF_A; i < priv->rf_paths; i++) { - val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); - val32 &= ~MODE_AG_CHANNEL_MASK; - val32 |= channel; - rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); - } - - rtl8xxxu_write16(priv, REG_WMAC_TRXPTCL_CTL, rf_mode_bw); - rtl8xxxu_write8(priv, REG_DATA_SUBCHANNEL, subchannel); - - if (ht) - val8 = 0x0e; - else - val8 = 0x0a; - - rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8); - rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8); - - rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808); - rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a); - - for (i = RF_A; i < priv->rf_paths; i++) { - val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); - val32 &= ~MODE_AG_BW_MASK; - switch(hw->conf.chandef.width) { - case NL80211_CHAN_WIDTH_80: - val32 |= MODE_AG_BW_80MHZ_8723B; - break; - case NL80211_CHAN_WIDTH_40: - val32 |= MODE_AG_BW_40MHZ_8723B; - break; - default: - val32 |= MODE_AG_BW_20MHZ_8723B; - break; - } - rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); - } -} - -void -rtl8xxxu_gen1_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40) -{ - struct rtl8xxxu_power_base *power_base = priv->power_base; - u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS]; - u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS]; - u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b; - u8 val8, base; - int group, i; - - group = rtl8xxxu_gen1_channel_to_group(channel); - - cck[0] = priv->cck_tx_power_index_A[group]; - cck[1] = priv->cck_tx_power_index_B[group]; - - if (priv->hi_pa) { - if (cck[0] > 0x20) - cck[0] = 0x20; - if (cck[1] > 0x20) - cck[1] = 0x20; - } - - ofdm[0] = priv->ht40_1s_tx_power_index_A[group]; - ofdm[1] = priv->ht40_1s_tx_power_index_B[group]; - - ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a; - ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b; - - mcsbase[0] = ofdm[0]; - mcsbase[1] = ofdm[1]; - if (!ht40) { - mcsbase[0] += priv->ht20_tx_power_index_diff[group].a; - mcsbase[1] += priv->ht20_tx_power_index_diff[group].b; - } - - if (priv->tx_paths > 1) { - if (ofdm[0] > priv->ht40_2s_tx_power_index_diff[group].a) - ofdm[0] -= priv->ht40_2s_tx_power_index_diff[group].a; - if (ofdm[1] > priv->ht40_2s_tx_power_index_diff[group].b) - ofdm[1] -= priv->ht40_2s_tx_power_index_diff[group].b; - } - - if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL) - dev_info(&priv->udev->dev, - "%s: Setting TX power CCK A: %02x, " - "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n", - __func__, cck[0], cck[1], ofdm[0], ofdm[1]); - - for (i = 0; i < RTL8723A_MAX_RF_PATHS; i++) { - if (cck[i] > RF6052_MAX_TX_PWR) - cck[i] = RF6052_MAX_TX_PWR; - if (ofdm[i] > RF6052_MAX_TX_PWR) - ofdm[i] = RF6052_MAX_TX_PWR; - } - - val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32); - val32 &= 0xffff00ff; - val32 |= (cck[0] << 8); - rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); - - val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); - val32 &= 0xff; - val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24)); - rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); - - val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); - val32 &= 0xffffff00; - val32 |= cck[1]; - rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); - - val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32); - val32 &= 0xff; - val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24)); - rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32); - - ofdm_a = ofdmbase[0] | ofdmbase[0] << 8 | - ofdmbase[0] << 16 | ofdmbase[0] << 24; - ofdm_b = ofdmbase[1] | ofdmbase[1] << 8 | - ofdmbase[1] << 16 | ofdmbase[1] << 24; - - rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, - ofdm_a + power_base->reg_0e00); - rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, - ofdm_b + power_base->reg_0830); - - rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, - ofdm_a + power_base->reg_0e04); - rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, - ofdm_b + power_base->reg_0834); - - mcs_a = mcsbase[0] | mcsbase[0] << 8 | - mcsbase[0] << 16 | mcsbase[0] << 24; - mcs_b = mcsbase[1] | mcsbase[1] << 8 | - mcsbase[1] << 16 | mcsbase[1] << 24; - - rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, - mcs_a + power_base->reg_0e10); - rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, - mcs_b + power_base->reg_083c); - - rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, - mcs_a + power_base->reg_0e14); - rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, - mcs_b + power_base->reg_0848); - - rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, - mcs_a + power_base->reg_0e18); - rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, - mcs_b + power_base->reg_084c); - - rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, - mcs_a + power_base->reg_0e1c); - val8 = u32_get_bits(mcs_a + power_base->reg_0e1c, 0xff000000); - for (i = 0; i < 3; i++) { - base = i != 2 ? 8 : 6; - val8 = max_t(int, val8 - base, 0); - rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8); - } - - rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, - mcs_b + power_base->reg_0868); - val8 = u32_get_bits(mcs_b + power_base->reg_0868, 0xff000000); - for (i = 0; i < 3; i++) { - base = i != 2 ? 8 : 6; - val8 = max_t(int, val8 - base, 0); - rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8); - } -} - -static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv *priv, - enum nl80211_iftype linktype, int port_num) -{ - u8 val8, type; - - switch (linktype) { - case NL80211_IFTYPE_UNSPECIFIED: - type = MSR_LINKTYPE_NONE; - break; - case NL80211_IFTYPE_ADHOC: - type = MSR_LINKTYPE_ADHOC; - break; - case NL80211_IFTYPE_STATION: - type = MSR_LINKTYPE_STATION; - break; - case NL80211_IFTYPE_AP: - type = MSR_LINKTYPE_AP; - break; - default: - return; - } - - switch (port_num) { - case 0: - val8 = rtl8xxxu_read8(priv, REG_MSR) & 0x0c; - val8 |= type; - break; - case 1: - val8 = rtl8xxxu_read8(priv, REG_MSR) & 0x03; - val8 |= type << 2; - break; - default: - return; - } - - rtl8xxxu_write8(priv, REG_MSR, val8); -} - -static void -rtl8xxxu_set_retry(struct rtl8xxxu_priv *priv, u16 short_retry, u16 long_retry) -{ - u16 val16; - - val16 = ((short_retry << RETRY_LIMIT_SHORT_SHIFT) & - RETRY_LIMIT_SHORT_MASK) | - ((long_retry << RETRY_LIMIT_LONG_SHIFT) & - RETRY_LIMIT_LONG_MASK); - - rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16); -} - -static void -rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv *priv, u16 cck, u16 ofdm) -{ - u16 val16; - - val16 = ((cck << SPEC_SIFS_CCK_SHIFT) & SPEC_SIFS_CCK_MASK) | - ((ofdm << SPEC_SIFS_OFDM_SHIFT) & SPEC_SIFS_OFDM_MASK); - - rtl8xxxu_write16(priv, REG_SPEC_SIFS, val16); -} - -static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv) -{ - struct device *dev = &priv->udev->dev; - char cut = 'A' + priv->chip_cut; - - dev_info(dev, - "RTL%s rev %c (%s) romver %d, %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n", - priv->chip_name, cut, priv->chip_vendor, priv->rom_rev, - priv->tx_paths, priv->rx_paths, priv->ep_tx_count, - priv->has_wifi, priv->has_bluetooth, priv->has_gps, - priv->hi_pa); - - dev_info(dev, "RTL%s MAC: %pM\n", priv->chip_name, priv->mac_addr); -} - -void rtl8xxxu_identify_vendor_1bit(struct rtl8xxxu_priv *priv, u32 vendor) -{ - if (vendor) { - strscpy(priv->chip_vendor, "UMC", sizeof(priv->chip_vendor)); - priv->vendor_umc = 1; - } else { - strscpy(priv->chip_vendor, "TSMC", sizeof(priv->chip_vendor)); - } -} - -void rtl8xxxu_identify_vendor_2bits(struct rtl8xxxu_priv *priv, u32 vendor) -{ - switch (vendor) { - case SYS_CFG_VENDOR_ID_TSMC: - strscpy(priv->chip_vendor, "TSMC", sizeof(priv->chip_vendor)); - break; - case SYS_CFG_VENDOR_ID_SMIC: - strscpy(priv->chip_vendor, "SMIC", sizeof(priv->chip_vendor)); - priv->vendor_smic = 1; - break; - case SYS_CFG_VENDOR_ID_UMC: - strscpy(priv->chip_vendor, "UMC", sizeof(priv->chip_vendor)); - priv->vendor_umc = 1; - break; - default: - strscpy(priv->chip_vendor, "unknown", sizeof(priv->chip_vendor)); - } -} - -void rtl8xxxu_config_endpoints_sie(struct rtl8xxxu_priv *priv) -{ - u16 val16; - - val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX); - - if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) { - priv->ep_tx_high_queue = 1; - priv->ep_tx_count++; - } - - if (val16 & NORMAL_SIE_EP_TX_NORMAL_MASK) { - priv->ep_tx_normal_queue = 1; - priv->ep_tx_count++; - } - - if (val16 & NORMAL_SIE_EP_TX_LOW_MASK) { - priv->ep_tx_low_queue = 1; - priv->ep_tx_count++; - } -} - -int rtl8xxxu_config_endpoints_no_sie(struct rtl8xxxu_priv *priv) -{ - struct device *dev = &priv->udev->dev; - - switch (priv->nr_out_eps) { - case 6: - case 5: - case 4: - case 3: - priv->ep_tx_low_queue = 1; - priv->ep_tx_count++; - fallthrough; - case 2: - priv->ep_tx_normal_queue = 1; - priv->ep_tx_count++; - fallthrough; - case 1: - priv->ep_tx_high_queue = 1; - priv->ep_tx_count++; - break; - default: - dev_info(dev, "Unsupported USB TX end-points\n"); - return -ENOTSUPP; - } - - return 0; -} - -int -rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data) -{ - int i; - u8 val8; - u32 val32; - - /* Write Address */ - rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 1, offset & 0xff); - val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 2); - val8 &= 0xfc; - val8 |= (offset >> 8) & 0x03; - rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 2, val8); - - val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 3); - rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 3, val8 & 0x7f); - - /* Poll for data read */ - val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL); - for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) { - val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL); - if (val32 & BIT(31)) - break; - } - - if (i == RTL8XXXU_MAX_REG_POLL) - return -EIO; - - udelay(50); - val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL); - - *data = val32 & 0xff; - return 0; -} - -int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv) -{ - struct device *dev = &priv->udev->dev; - int i, ret = 0; - u8 val8, word_mask, header, extheader; - u16 val16, efuse_addr, offset; - u32 val32; - - val16 = rtl8xxxu_read16(priv, REG_9346CR); - if (val16 & EEPROM_ENABLE) - priv->has_eeprom = 1; - if (val16 & EEPROM_BOOT) - priv->boot_eeprom = 1; - - if (priv->is_multi_func) { - val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST); - val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT; - rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32); - } - - dev_dbg(dev, "Booting from %s\n", - priv->boot_eeprom ? "EEPROM" : "EFUSE"); - - rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_ENABLE); - - /* 1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */ - val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL); - if (!(val16 & SYS_ISO_PWC_EV12V)) { - val16 |= SYS_ISO_PWC_EV12V; - rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16); - } - /* Reset: 0x0000[28], default valid */ - val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); - if (!(val16 & SYS_FUNC_ELDR)) { - val16 |= SYS_FUNC_ELDR; - rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); - } - - /* - * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid - */ - val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR); - if (!(val16 & SYS_CLK_LOADER_ENABLE) || !(val16 & SYS_CLK_ANA8M)) { - val16 |= (SYS_CLK_LOADER_ENABLE | SYS_CLK_ANA8M); - rtl8xxxu_write16(priv, REG_SYS_CLKR, val16); - } - - /* Default value is 0xff */ - memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN); - - efuse_addr = 0; - while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) { - u16 map_addr; - - ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &header); - if (ret || header == 0xff) - goto exit; - - if ((header & 0x1f) == 0x0f) { /* extended header */ - offset = (header & 0xe0) >> 5; - - ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, - &extheader); - if (ret) - goto exit; - /* All words disabled */ - if ((extheader & 0x0f) == 0x0f) - continue; - - offset |= ((extheader & 0xf0) >> 1); - word_mask = extheader & 0x0f; - } else { - offset = (header >> 4) & 0x0f; - word_mask = header & 0x0f; - } - - /* Get word enable value from PG header */ - - /* We have 8 bits to indicate validity */ - map_addr = offset * 8; - for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) { - /* Check word enable condition in the section */ - if (word_mask & BIT(i)) { - map_addr += 2; - continue; - } - - ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8); - if (ret) - goto exit; - if (map_addr >= EFUSE_MAP_LEN - 1) { - dev_warn(dev, "%s: Illegal map_addr (%04x), " - "efuse corrupt!\n", - __func__, map_addr); - ret = -EINVAL; - goto exit; - } - priv->efuse_wifi.raw[map_addr++] = val8; - - ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8); - if (ret) - goto exit; - priv->efuse_wifi.raw[map_addr++] = val8; - } - } - -exit: - rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_DISABLE); - - return ret; -} - -static void rtl8xxxu_dump_efuse(struct rtl8xxxu_priv *priv) -{ - dev_info(&priv->udev->dev, - "Dumping efuse for RTL%s (0x%02x bytes):\n", - priv->chip_name, EFUSE_MAP_LEN); - - print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1, - priv->efuse_wifi.raw, EFUSE_MAP_LEN, true); -} - -void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv) -{ - u8 val8; - u16 sys_func; - - val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); - val8 &= ~BIT(0); - rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); - - sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC); - sys_func &= ~SYS_FUNC_CPU_ENABLE; - rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func); - - val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); - val8 |= BIT(0); - rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); - - sys_func |= SYS_FUNC_CPU_ENABLE; - rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func); -} - -static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv) -{ - struct device *dev = &priv->udev->dev; - u16 reg_mcu_fw_dl; - int ret = 0, i; - u32 val32; - - if (priv->rtl_chip == RTL8710B) - reg_mcu_fw_dl = REG_8051FW_CTRL_V1_8710B; - else - reg_mcu_fw_dl = REG_MCU_FW_DL; - - /* Poll checksum report */ - for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) { - val32 = rtl8xxxu_read32(priv, reg_mcu_fw_dl); - if (val32 & MCU_FW_DL_CSUM_REPORT) - break; - } - - if (i == RTL8XXXU_FIRMWARE_POLL_MAX) { - dev_warn(dev, "Firmware checksum poll timed out\n"); - ret = -EAGAIN; - goto exit; - } - - val32 = rtl8xxxu_read32(priv, reg_mcu_fw_dl); - val32 |= MCU_FW_DL_READY; - val32 &= ~MCU_WINT_INIT_READY; - rtl8xxxu_write32(priv, reg_mcu_fw_dl, val32); - - /* - * Reset the 8051 in order for the firmware to start running, - * otherwise it won't come up on the 8192eu - */ - priv->fops->reset_8051(priv); - - /* Wait for firmware to become ready */ - for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) { - val32 = rtl8xxxu_read32(priv, reg_mcu_fw_dl); - if (val32 & MCU_WINT_INIT_READY) - break; - - udelay(100); - } - - if (i == RTL8XXXU_FIRMWARE_POLL_MAX) { - dev_warn(dev, "Firmware failed to start\n"); - ret = -EAGAIN; - goto exit; - } - - /* - * Init H2C command - */ - if (priv->fops->init_reg_hmtfr) - rtl8xxxu_write8(priv, REG_HMTFR, 0x0f); -exit: - return ret; -} - -static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv) -{ - int pages, remainder, i, ret; - u16 reg_fw_start_address; - u16 reg_mcu_fw_dl; - u8 val8; - u16 val16; - u32 val32; - u8 *fwptr; - - if (priv->rtl_chip == RTL8192F) - reg_fw_start_address = REG_FW_START_ADDRESS_8192F; - else - reg_fw_start_address = REG_FW_START_ADDRESS; - - if (priv->rtl_chip == RTL8710B) { - reg_mcu_fw_dl = REG_8051FW_CTRL_V1_8710B; - } else { - reg_mcu_fw_dl = REG_MCU_FW_DL; - - val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC + 1); - val8 |= 4; - rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8); - - /* 8051 enable */ - val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); - val16 |= SYS_FUNC_CPU_ENABLE; - rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); - } - - val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl); - if (val8 & MCU_FW_RAM_SEL) { - dev_info(&priv->udev->dev, - "Firmware is already running, resetting the MCU.\n"); - rtl8xxxu_write8(priv, reg_mcu_fw_dl, 0x00); - priv->fops->reset_8051(priv); - } - - /* MCU firmware download enable */ - val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl); - val8 |= MCU_FW_DL_ENABLE; - rtl8xxxu_write8(priv, reg_mcu_fw_dl, val8); - - /* 8051 reset */ - val32 = rtl8xxxu_read32(priv, reg_mcu_fw_dl); - val32 &= ~BIT(19); - rtl8xxxu_write32(priv, reg_mcu_fw_dl, val32); - - if (priv->rtl_chip == RTL8710B) { - /* We must set 0x8090[8]=1 before download FW. */ - val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl + 1); - val8 |= BIT(0); - rtl8xxxu_write8(priv, reg_mcu_fw_dl + 1, val8); - } - - /* Reset firmware download checksum */ - val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl); - val8 |= MCU_FW_DL_CSUM_REPORT; - rtl8xxxu_write8(priv, reg_mcu_fw_dl, val8); - - pages = priv->fw_size / RTL_FW_PAGE_SIZE; - remainder = priv->fw_size % RTL_FW_PAGE_SIZE; - - fwptr = priv->fw_data->data; - - for (i = 0; i < pages; i++) { - val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl + 2) & 0xF8; - val8 |= i; - rtl8xxxu_write8(priv, reg_mcu_fw_dl + 2, val8); - - ret = rtl8xxxu_writeN(priv, reg_fw_start_address, - fwptr, RTL_FW_PAGE_SIZE); - if (ret != RTL_FW_PAGE_SIZE) { - ret = -EAGAIN; - goto fw_abort; - } - - fwptr += RTL_FW_PAGE_SIZE; - } - - if (remainder) { - val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl + 2) & 0xF8; - val8 |= i; - rtl8xxxu_write8(priv, reg_mcu_fw_dl + 2, val8); - ret = rtl8xxxu_writeN(priv, reg_fw_start_address, - fwptr, remainder); - if (ret != remainder) { - ret = -EAGAIN; - goto fw_abort; - } - } - - ret = 0; -fw_abort: - /* MCU firmware download disable */ - val16 = rtl8xxxu_read16(priv, reg_mcu_fw_dl); - val16 &= ~MCU_FW_DL_ENABLE; - rtl8xxxu_write16(priv, reg_mcu_fw_dl, val16); - - return ret; -} - -int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, const char *fw_name) -{ - struct device *dev = &priv->udev->dev; - const struct firmware *fw; - int ret = 0; - u16 signature; - - dev_info(dev, "%s: Loading firmware %s\n", DRIVER_NAME, fw_name); - if (request_firmware(&fw, fw_name, &priv->udev->dev)) { - dev_warn(dev, "request_firmware(%s) failed\n", fw_name); - ret = -EAGAIN; - goto exit; - } - if (!fw) { - dev_warn(dev, "Firmware data not available\n"); - ret = -EINVAL; - goto exit; - } - - priv->fw_data = kmemdup(fw->data, fw->size, GFP_KERNEL); - if (!priv->fw_data) { - ret = -ENOMEM; - goto exit; - } - priv->fw_size = fw->size - sizeof(struct rtl8xxxu_firmware_header); - - signature = le16_to_cpu(priv->fw_data->signature); - switch (signature & 0xfff0) { - case 0x92e0: - case 0x92c0: - case 0x88e0: - case 0x88c0: - case 0x5300: - case 0x2300: - case 0x88f0: - case 0x10b0: - case 0x92f0: - break; - default: - ret = -EINVAL; - dev_warn(dev, "%s: Invalid firmware signature: 0x%04x\n", - __func__, signature); - } - - dev_info(dev, "Firmware revision %i.%i (signature 0x%04x)\n", - le16_to_cpu(priv->fw_data->major_version), - priv->fw_data->minor_version, signature); - -exit: - release_firmware(fw); - return ret; -} - -void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv) -{ - u16 val16; - int i = 100; - - /* Inform 8051 to perform reset */ - rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20); - - for (i = 100; i > 0; i--) { - val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); - - if (!(val16 & SYS_FUNC_CPU_ENABLE)) { - dev_dbg(&priv->udev->dev, - "%s: Firmware self reset success!\n", __func__); - break; - } - udelay(50); - } - - if (!i) { - /* Force firmware reset */ - val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); - val16 &= ~SYS_FUNC_CPU_ENABLE; - rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); - } -} - -static int -rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv) -{ - const struct rtl8xxxu_reg8val *array = priv->fops->mactable; - int i, ret; - u16 reg; - u8 val; - - for (i = 0; ; i++) { - reg = array[i].reg; - val = array[i].val; - - if (reg == 0xffff && val == 0xff) - break; - - ret = rtl8xxxu_write8(priv, reg, val); - if (ret != 1) { - dev_warn(&priv->udev->dev, - "Failed to initialize MAC " - "(reg: %04x, val %02x)\n", reg, val); - return -EAGAIN; - } - } - - switch (priv->rtl_chip) { - case RTL8188C: - case RTL8188R: - case RTL8191C: - case RTL8192C: - case RTL8723A: - rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a); - break; - case RTL8188E: - rtl8xxxu_write16(priv, REG_MAX_AGGR_NUM, 0x0707); - break; - default: - break; - } - - return 0; -} - -int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv, - const struct rtl8xxxu_reg32val *array) -{ - int i, ret; - u16 reg; - u32 val; - - for (i = 0; ; i++) { - reg = array[i].reg; - val = array[i].val; - - if (reg == 0xffff && val == 0xffffffff) - break; - - ret = rtl8xxxu_write32(priv, reg, val); - if (ret != sizeof(val)) { - dev_warn(&priv->udev->dev, - "Failed to initialize PHY\n"); - return -EAGAIN; - } - udelay(1); - } - - return 0; -} - -void rtl8xxxu_gen1_init_phy_bb(struct rtl8xxxu_priv *priv) -{ - u8 val8, ldoa15, ldov12d, lpldo, ldohci12; - u16 val16; - u32 val32; - - val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL); - udelay(2); - val8 |= AFE_PLL_320_ENABLE; - rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8); - udelay(2); - - rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL + 1, 0xff); - udelay(2); - - val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); - val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB; - rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); - - val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL); - val32 &= ~AFE_XTAL_RF_GATE; - if (priv->has_bluetooth) - val32 &= ~AFE_XTAL_BT_GATE; - rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32); - - /* 6. 0x1f[7:0] = 0x07 */ - val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB; - rtl8xxxu_write8(priv, REG_RF_CTRL, val8); - - if (priv->hi_pa) - rtl8xxxu_init_phy_regs(priv, rtl8188ru_phy_1t_highpa_table); - else if (priv->tx_paths == 2) - rtl8xxxu_init_phy_regs(priv, rtl8192cu_phy_2t_init_table); - else - rtl8xxxu_init_phy_regs(priv, rtl8723a_phy_1t_init_table); - - if (priv->rtl_chip == RTL8188R && priv->hi_pa && - priv->vendor_umc && priv->chip_cut == 1) - rtl8xxxu_write8(priv, REG_OFDM0_AGC_PARM1 + 2, 0x50); - - if (priv->hi_pa) - rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_highpa_table); - else - rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_standard_table); - - ldoa15 = LDOA15_ENABLE | LDOA15_OBUF; - ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT); - ldohci12 = 0x57; - lpldo = 1; - val32 = (lpldo << 24) | (ldohci12 << 16) | (ldov12d << 8) | ldoa15; - rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32); -} - -/* - * Most of this is black magic retrieved from the old rtl8723au driver - */ -static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv) -{ - u32 val32; - - priv->fops->init_phy_bb(priv); - - if (priv->tx_paths == 1 && priv->rx_paths == 2) { - /* - * For 1T2R boards, patch the registers. - * - * It looks like 8191/2 1T2R boards use path B for TX - */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO); - val32 &= ~(BIT(0) | BIT(1)); - val32 |= BIT(1); - rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32); - - val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO); - val32 &= ~0x300033; - val32 |= 0x200022; - rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32); - - val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING); - val32 &= ~CCK0_AFE_RX_MASK; - val32 &= 0x00ffffff; - val32 |= 0x40000000; - val32 |= CCK0_AFE_RX_ANT_B; - rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32); - - val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); - val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK); - val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B | - OFDM_RF_PATH_TX_B); - rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); - - val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1); - val32 &= ~(BIT(4) | BIT(5)); - val32 |= BIT(4); - rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32); - - val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON); - val32 &= ~(BIT(27) | BIT(26)); - val32 |= BIT(27); - rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32); - - val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON); - val32 &= ~(BIT(27) | BIT(26)); - val32 |= BIT(27); - rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32); - - val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON); - val32 &= ~(BIT(27) | BIT(26)); - val32 |= BIT(27); - rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32); - - val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON); - val32 &= ~(BIT(27) | BIT(26)); - val32 |= BIT(27); - rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32); - - val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX); - val32 &= ~(BIT(27) | BIT(26)); - val32 |= BIT(27); - rtl8xxxu_write32(priv, REG_TX_TO_TX, val32); - } - - if (priv->fops->set_crystal_cap) - priv->fops->set_crystal_cap(priv, priv->default_crystal_cap); - - if (priv->rtl_chip == RTL8192E) - rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x000f81fb); - - return 0; -} - -static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv, - const struct rtl8xxxu_rfregval *array, - enum rtl8xxxu_rfpath path) -{ - int i, ret; - u8 reg; - u32 val; - - for (i = 0; ; i++) { - reg = array[i].reg; - val = array[i].val; - - if (reg == 0xff && val == 0xffffffff) - break; - - switch (reg) { - case 0xfe: - msleep(50); - continue; - case 0xfd: - mdelay(5); - continue; - case 0xfc: - mdelay(1); - continue; - case 0xfb: - udelay(50); - continue; - case 0xfa: - udelay(5); - continue; - case 0xf9: - udelay(1); - continue; - } - - ret = rtl8xxxu_write_rfreg(priv, path, reg, val); - if (ret) { - dev_warn(&priv->udev->dev, - "Failed to initialize RF\n"); - return -EAGAIN; - } - udelay(1); - } - - return 0; -} - -int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv, - const struct rtl8xxxu_rfregval *table, - enum rtl8xxxu_rfpath path) -{ - u32 val32; - u16 val16, rfsi_rfenv; - u16 reg_sw_ctrl, reg_int_oe, reg_hssi_parm2; - - switch (path) { - case RF_A: - reg_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL; - reg_int_oe = REG_FPGA0_XA_RF_INT_OE; - reg_hssi_parm2 = REG_FPGA0_XA_HSSI_PARM2; - break; - case RF_B: - reg_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL; - reg_int_oe = REG_FPGA0_XB_RF_INT_OE; - reg_hssi_parm2 = REG_FPGA0_XB_HSSI_PARM2; - break; - default: - dev_err(&priv->udev->dev, "%s:Unsupported RF path %c\n", - __func__, path + 'A'); - return -EINVAL; - } - /* For path B, use XB */ - rfsi_rfenv = rtl8xxxu_read16(priv, reg_sw_ctrl); - rfsi_rfenv &= FPGA0_RF_RFENV; - - /* - * These two we might be able to optimize into one - */ - val32 = rtl8xxxu_read32(priv, reg_int_oe); - val32 |= BIT(20); /* 0x10 << 16 */ - rtl8xxxu_write32(priv, reg_int_oe, val32); - udelay(1); - - val32 = rtl8xxxu_read32(priv, reg_int_oe); - val32 |= BIT(4); - rtl8xxxu_write32(priv, reg_int_oe, val32); - udelay(1); - - /* - * These two we might be able to optimize into one - */ - val32 = rtl8xxxu_read32(priv, reg_hssi_parm2); - val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN; - rtl8xxxu_write32(priv, reg_hssi_parm2, val32); - udelay(1); - - val32 = rtl8xxxu_read32(priv, reg_hssi_parm2); - val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN; - rtl8xxxu_write32(priv, reg_hssi_parm2, val32); - udelay(1); - - rtl8xxxu_init_rf_regs(priv, table, path); - - /* For path B, use XB */ - val16 = rtl8xxxu_read16(priv, reg_sw_ctrl); - val16 &= ~FPGA0_RF_RFENV; - val16 |= rfsi_rfenv; - rtl8xxxu_write16(priv, reg_sw_ctrl, val16); - - return 0; -} - -static int rtl8xxxu_llt_write(struct rtl8xxxu_priv *priv, u8 address, u8 data) -{ - int ret = -EBUSY; - int count = 0; - u32 value; - - value = LLT_OP_WRITE | address << 8 | data; - - rtl8xxxu_write32(priv, REG_LLT_INIT, value); - - do { - value = rtl8xxxu_read32(priv, REG_LLT_INIT); - if ((value & LLT_OP_MASK) == LLT_OP_INACTIVE) { - ret = 0; - break; - } - } while (count++ < 20); - - return ret; -} - -int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv) -{ - int ret; - int i, last_entry; - u8 last_tx_page; - - last_tx_page = priv->fops->total_page_num; - - if (priv->fops->last_llt_entry) - last_entry = priv->fops->last_llt_entry; - else - last_entry = 255; - - for (i = 0; i < last_tx_page; i++) { - ret = rtl8xxxu_llt_write(priv, i, i + 1); - if (ret) - goto exit; - } - - ret = rtl8xxxu_llt_write(priv, last_tx_page, 0xff); - if (ret) - goto exit; - - /* Mark remaining pages as a ring buffer */ - for (i = last_tx_page + 1; i < last_entry; i++) { - ret = rtl8xxxu_llt_write(priv, i, (i + 1)); - if (ret) - goto exit; - } - - /* Let last entry point to the start entry of ring buffer */ - ret = rtl8xxxu_llt_write(priv, last_entry, last_tx_page + 1); - if (ret) - goto exit; - -exit: - return ret; -} - -int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv) -{ - u32 val32; - int ret = 0; - int i; - - val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT); - val32 |= AUTO_LLT_INIT_LLT; - rtl8xxxu_write32(priv, REG_AUTO_LLT, val32); - - for (i = 500; i; i--) { - val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT); - if (!(val32 & AUTO_LLT_INIT_LLT)) - break; - usleep_range(2, 4); - } - - if (!i) { - ret = -EBUSY; - dev_warn(&priv->udev->dev, "LLT table init failed\n"); - } - - return ret; -} - -static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv) -{ - u16 val16, hi, lo; - u16 hiq, mgq, bkq, beq, viq, voq; - int hip, mgp, bkp, bep, vip, vop; - int ret = 0; - u32 val32; - - switch (priv->ep_tx_count) { - case 1: - if (priv->ep_tx_high_queue) { - hi = TRXDMA_QUEUE_HIGH; - } else if (priv->ep_tx_low_queue) { - hi = TRXDMA_QUEUE_LOW; - } else if (priv->ep_tx_normal_queue) { - hi = TRXDMA_QUEUE_NORMAL; - } else { - hi = 0; - ret = -EINVAL; - } - - hiq = hi; - mgq = hi; - bkq = hi; - beq = hi; - viq = hi; - voq = hi; - - hip = 0; - mgp = 0; - bkp = 0; - bep = 0; - vip = 0; - vop = 0; - break; - case 2: - if (priv->ep_tx_high_queue && priv->ep_tx_low_queue) { - hi = TRXDMA_QUEUE_HIGH; - lo = TRXDMA_QUEUE_LOW; - } else if (priv->ep_tx_normal_queue && priv->ep_tx_low_queue) { - hi = TRXDMA_QUEUE_NORMAL; - lo = TRXDMA_QUEUE_LOW; - } else if (priv->ep_tx_high_queue && priv->ep_tx_normal_queue) { - hi = TRXDMA_QUEUE_HIGH; - lo = TRXDMA_QUEUE_NORMAL; - } else { - ret = -EINVAL; - hi = 0; - lo = 0; - } - - hiq = hi; - mgq = hi; - bkq = lo; - beq = lo; - viq = hi; - voq = hi; - - hip = 0; - mgp = 0; - bkp = 1; - bep = 1; - vip = 0; - vop = 0; - break; - case 3: - beq = TRXDMA_QUEUE_LOW; - bkq = TRXDMA_QUEUE_LOW; - viq = TRXDMA_QUEUE_NORMAL; - voq = TRXDMA_QUEUE_HIGH; - mgq = TRXDMA_QUEUE_HIGH; - hiq = TRXDMA_QUEUE_HIGH; - - hip = hiq ^ 3; - mgp = mgq ^ 3; - bkp = bkq ^ 3; - bep = beq ^ 3; - vip = viq ^ 3; - vop = viq ^ 3; - break; - default: - ret = -EINVAL; - } - - /* - * None of the vendor drivers are configuring the beacon - * queue here .... why? - */ - if (!ret) { - /* Only RTL8192F seems to do it like this. */ - if (priv->rtl_chip == RTL8192F) { - val32 = rtl8xxxu_read32(priv, REG_TRXDMA_CTRL); - val32 &= 0x7; - val32 |= (voq << TRXDMA_CTRL_VOQ_SHIFT_8192F) | - (viq << TRXDMA_CTRL_VIQ_SHIFT_8192F) | - (beq << TRXDMA_CTRL_BEQ_SHIFT_8192F) | - (bkq << TRXDMA_CTRL_BKQ_SHIFT_8192F) | - (mgq << TRXDMA_CTRL_MGQ_SHIFT_8192F) | - (hiq << TRXDMA_CTRL_HIQ_SHIFT_8192F); - rtl8xxxu_write32(priv, REG_TRXDMA_CTRL, val32); - } else { - val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL); - val16 &= 0x7; - val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) | - (viq << TRXDMA_CTRL_VIQ_SHIFT) | - (beq << TRXDMA_CTRL_BEQ_SHIFT) | - (bkq << TRXDMA_CTRL_BKQ_SHIFT) | - (mgq << TRXDMA_CTRL_MGQ_SHIFT) | - (hiq << TRXDMA_CTRL_HIQ_SHIFT); - rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16); - } - - priv->pipe_out[TXDESC_QUEUE_VO] = - usb_sndbulkpipe(priv->udev, priv->out_ep[vop]); - priv->pipe_out[TXDESC_QUEUE_VI] = - usb_sndbulkpipe(priv->udev, priv->out_ep[vip]); - priv->pipe_out[TXDESC_QUEUE_BE] = - usb_sndbulkpipe(priv->udev, priv->out_ep[bep]); - priv->pipe_out[TXDESC_QUEUE_BK] = - usb_sndbulkpipe(priv->udev, priv->out_ep[bkp]); - priv->pipe_out[TXDESC_QUEUE_BEACON] = - usb_sndbulkpipe(priv->udev, priv->out_ep[0]); - priv->pipe_out[TXDESC_QUEUE_MGNT] = - usb_sndbulkpipe(priv->udev, priv->out_ep[mgp]); - priv->pipe_out[TXDESC_QUEUE_HIGH] = - usb_sndbulkpipe(priv->udev, priv->out_ep[hip]); - priv->pipe_out[TXDESC_QUEUE_CMD] = - usb_sndbulkpipe(priv->udev, priv->out_ep[0]); - } - - return ret; -} - -void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv, bool iqk_ok, - int result[][8], int candidate, bool tx_only) -{ - u32 oldval, x, tx0_a, reg; - int y, tx0_c; - u32 val32; - - if (!iqk_ok) - return; - - val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE); - oldval = val32 >> 22; - - x = result[candidate][0]; - if ((x & 0x00000200) != 0) - x = x | 0xfffffc00; - tx0_a = (x * oldval) >> 8; - - val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE); - val32 &= ~0x3ff; - val32 |= tx0_a; - rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32); - - val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); - val32 &= ~BIT(31); - if ((x * oldval >> 7) & 0x1) - val32 |= BIT(31); - rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); - - y = result[candidate][1]; - if ((y & 0x00000200) != 0) - y = y | 0xfffffc00; - tx0_c = (y * oldval) >> 8; - - val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE); - val32 &= ~0xf0000000; - val32 |= (((tx0_c & 0x3c0) >> 6) << 28); - rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32); - - val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE); - val32 &= ~0x003f0000; - val32 |= ((tx0_c & 0x3f) << 16); - rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32); - - val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); - val32 &= ~BIT(29); - if ((y * oldval >> 7) & 0x1) - val32 |= BIT(29); - rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); - - if (tx_only) { - dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__); - return; - } - - reg = result[candidate][2]; - - val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE); - val32 &= ~0x3ff; - val32 |= (reg & 0x3ff); - rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32); - - reg = result[candidate][3] & 0x3F; - - val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE); - val32 &= ~0xfc00; - val32 |= ((reg << 10) & 0xfc00); - rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32); - - reg = (result[candidate][3] >> 6) & 0xF; - - val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA); - val32 &= ~0xf0000000; - val32 |= (reg << 28); - rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32); -} - -void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv, bool iqk_ok, - int result[][8], int candidate, bool tx_only) -{ - u32 oldval, x, tx1_a, reg; - int y, tx1_c; - u32 val32; - - if (!iqk_ok) - return; - - val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE); - oldval = val32 >> 22; - - x = result[candidate][4]; - if ((x & 0x00000200) != 0) - x = x | 0xfffffc00; - tx1_a = (x * oldval) >> 8; - - val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE); - val32 &= ~0x3ff; - val32 |= tx1_a; - rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32); - - val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); - val32 &= ~BIT(27); - if ((x * oldval >> 7) & 0x1) - val32 |= BIT(27); - rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); - - y = result[candidate][5]; - if ((y & 0x00000200) != 0) - y = y | 0xfffffc00; - tx1_c = (y * oldval) >> 8; - - val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE); - val32 &= ~0xf0000000; - val32 |= (((tx1_c & 0x3c0) >> 6) << 28); - rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32); - - val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE); - val32 &= ~0x003f0000; - val32 |= ((tx1_c & 0x3f) << 16); - rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32); - - val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); - val32 &= ~BIT(25); - if ((y * oldval >> 7) & 0x1) - val32 |= BIT(25); - rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); - - if (tx_only) { - dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__); - return; - } - - reg = result[candidate][6]; - - val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE); - val32 &= ~0x3ff; - val32 |= (reg & 0x3ff); - rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32); - - reg = result[candidate][7] & 0x3f; - - val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE); - val32 &= ~0xfc00; - val32 |= ((reg << 10) & 0xfc00); - rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32); - - reg = (result[candidate][7] >> 6) & 0xf; - - if (priv->rtl_chip == RTL8192F) { - rtl8xxxu_write32_mask(priv, REG_RXIQB_EXT, 0x000000f0, reg); - } else { - val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_RSSI_TABLE); - val32 &= ~0x0000f000; - val32 |= (reg << 12); - rtl8xxxu_write32(priv, REG_OFDM0_AGC_RSSI_TABLE, val32); - } -} - -#define MAX_TOLERANCE 5 - -bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv, - int result[][8], int c1, int c2) -{ - u32 i, j, diff, simubitmap, bound = 0; - int candidate[2] = {-1, -1}; /* for path A and path B */ - bool retval = true; - - if (priv->tx_paths > 1) - bound = 8; - else - bound = 4; - - simubitmap = 0; - - for (i = 0; i < bound; i++) { - diff = (result[c1][i] > result[c2][i]) ? - (result[c1][i] - result[c2][i]) : - (result[c2][i] - result[c1][i]); - if (diff > MAX_TOLERANCE) { - if ((i == 2 || i == 6) && !simubitmap) { - if (result[c1][i] + result[c1][i + 1] == 0) - candidate[(i / 4)] = c2; - else if (result[c2][i] + result[c2][i + 1] == 0) - candidate[(i / 4)] = c1; - else - simubitmap = simubitmap | (1 << i); - } else { - simubitmap = simubitmap | (1 << i); - } - } - } - - if (simubitmap == 0) { - for (i = 0; i < (bound / 4); i++) { - if (candidate[i] >= 0) { - for (j = i * 4; j < (i + 1) * 4 - 2; j++) - result[3][j] = result[candidate[i]][j]; - retval = false; - } - } - return retval; - } else if (!(simubitmap & 0x0f)) { - /* path A OK */ - for (i = 0; i < 4; i++) - result[3][i] = result[c1][i]; - } else if (!(simubitmap & 0xf0) && priv->tx_paths > 1) { - /* path B OK */ - for (i = 4; i < 8; i++) - result[3][i] = result[c1][i]; - } - - return false; -} - -bool rtl8xxxu_gen2_simularity_compare(struct rtl8xxxu_priv *priv, - int result[][8], int c1, int c2) -{ - u32 i, j, diff, simubitmap, bound = 0; - int candidate[2] = {-1, -1}; /* for path A and path B */ - int tmp1, tmp2; - bool retval = true; - - if (priv->tx_paths > 1) - bound = 8; - else - bound = 4; - - simubitmap = 0; - - for (i = 0; i < bound; i++) { - if (i & 1) { - if ((result[c1][i] & 0x00000200)) - tmp1 = result[c1][i] | 0xfffffc00; - else - tmp1 = result[c1][i]; - - if ((result[c2][i]& 0x00000200)) - tmp2 = result[c2][i] | 0xfffffc00; - else - tmp2 = result[c2][i]; - } else { - tmp1 = result[c1][i]; - tmp2 = result[c2][i]; - } - - diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1); - - if (diff > MAX_TOLERANCE) { - if ((i == 2 || i == 6) && !simubitmap) { - if (result[c1][i] + result[c1][i + 1] == 0) - candidate[(i / 4)] = c2; - else if (result[c2][i] + result[c2][i + 1] == 0) - candidate[(i / 4)] = c1; - else - simubitmap = simubitmap | (1 << i); - } else { - simubitmap = simubitmap | (1 << i); - } - } - } - - if (simubitmap == 0) { - for (i = 0; i < (bound / 4); i++) { - if (candidate[i] >= 0) { - for (j = i * 4; j < (i + 1) * 4 - 2; j++) - result[3][j] = result[candidate[i]][j]; - retval = false; - } - } - return retval; - } else { - if (!(simubitmap & 0x03)) { - /* path A TX OK */ - for (i = 0; i < 2; i++) - result[3][i] = result[c1][i]; - } - - if (!(simubitmap & 0x0c)) { - /* path A RX OK */ - for (i = 2; i < 4; i++) - result[3][i] = result[c1][i]; - } - - if (!(simubitmap & 0x30) && priv->tx_paths > 1) { - /* path B TX OK */ - for (i = 4; i < 6; i++) - result[3][i] = result[c1][i]; - } - - if (!(simubitmap & 0xc0) && priv->tx_paths > 1) { - /* path B RX OK */ - for (i = 6; i < 8; i++) - result[3][i] = result[c1][i]; - } - } - - return false; -} - -void -rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup) -{ - int i; - - for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++) - backup[i] = rtl8xxxu_read8(priv, reg[i]); - - backup[i] = rtl8xxxu_read32(priv, reg[i]); -} - -void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv, - const u32 *reg, u32 *backup) -{ - int i; - - for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++) - rtl8xxxu_write8(priv, reg[i], backup[i]); - - rtl8xxxu_write32(priv, reg[i], backup[i]); -} - -void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs, - u32 *backup, int count) -{ - int i; - - for (i = 0; i < count; i++) - backup[i] = rtl8xxxu_read32(priv, regs[i]); -} - -void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs, - u32 *backup, int count) -{ - int i; - - for (i = 0; i < count; i++) - rtl8xxxu_write32(priv, regs[i], backup[i]); -} - - -void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs, - bool path_a_on) -{ - u32 path_on; - int i; - - if (priv->tx_paths == 1) { - path_on = priv->fops->adda_1t_path_on; - rtl8xxxu_write32(priv, regs[0], priv->fops->adda_1t_init); - } else { - path_on = path_a_on ? priv->fops->adda_2t_path_on_a : - priv->fops->adda_2t_path_on_b; - - rtl8xxxu_write32(priv, regs[0], path_on); - } - - for (i = 1 ; i < RTL8XXXU_ADDA_REGS ; i++) - rtl8xxxu_write32(priv, regs[i], path_on); -} - -void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv, - const u32 *regs, u32 *backup) -{ - int i = 0; - - rtl8xxxu_write8(priv, regs[i], 0x3f); - - for (i = 1 ; i < (RTL8XXXU_MAC_REGS - 1); i++) - rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3))); - - rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5))); -} - -static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv *priv) -{ - u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32; - int result = 0; - - /* path-A IQK setting */ - rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f); - rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f); - rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102); - - val32 = (priv->rf_paths > 1) ? 0x28160202 : - /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */ - 0x28160502; - rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32); - - /* path-B IQK setting */ - if (priv->rf_paths > 1) { - rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22); - rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22); - rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102); - rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202); - } - - /* LO calibration setting */ - rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1); - - /* One shot, path A LOK & IQK */ - rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); - rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); - - mdelay(1); - - /* Check failed */ - reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); - reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); - reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); - reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); - - if (!(reg_eac & BIT(28)) && - ((reg_e94 & 0x03ff0000) != 0x01420000) && - ((reg_e9c & 0x03ff0000) != 0x00420000)) - result |= 0x01; - else /* If TX not OK, ignore RX */ - goto out; - - /* If TX is OK, check whether RX is OK */ - if (!(reg_eac & BIT(27)) && - ((reg_ea4 & 0x03ff0000) != 0x01320000) && - ((reg_eac & 0x03ff0000) != 0x00360000)) - result |= 0x02; - else - dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n", - __func__); -out: - return result; -} - -static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv *priv) -{ - u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc; - int result = 0; - - /* One shot, path B LOK & IQK */ - rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002); - rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000); - - mdelay(1); - - /* Check failed */ - reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); - reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); - reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); - reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2); - reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2); - - if (!(reg_eac & BIT(31)) && - ((reg_eb4 & 0x03ff0000) != 0x01420000) && - ((reg_ebc & 0x03ff0000) != 0x00420000)) - result |= 0x01; - else - goto out; - - if (!(reg_eac & BIT(30)) && - (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) && - (((reg_ecc & 0x03ff0000) >> 16) != 0x36)) - result |= 0x02; - else - dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n", - __func__); -out: - return result; -} - -static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv, - int result[][8], int t) -{ - struct device *dev = &priv->udev->dev; - u32 i, val32; - int path_a_ok, path_b_ok; - int retry = 2; - static const u32 adda_regs[RTL8XXXU_ADDA_REGS] = { - REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH, - REG_RX_WAIT_CCA, REG_TX_CCK_RFON, - REG_TX_CCK_BBON, REG_TX_OFDM_RFON, - REG_TX_OFDM_BBON, REG_TX_TO_RX, - REG_TX_TO_TX, REG_RX_CCK, - REG_RX_OFDM, REG_RX_WAIT_RIFS, - REG_RX_TO_RX, REG_STANDBY, - REG_SLEEP, REG_PMPD_ANAEN - }; - static const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = { - REG_TXPAUSE, REG_BEACON_CTRL, - REG_BEACON_CTRL_1, REG_GPIO_MUXCFG - }; - static const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = { - REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR, - REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, - REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE, - REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE - }; - - /* - * Note: IQ calibration must be performed after loading - * PHY_REG.txt , and radio_a, radio_b.txt - */ - - if (t == 0) { - /* Save ADDA parameters, turn Path A ADDA on */ - rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup, - RTL8XXXU_ADDA_REGS); - rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup); - rtl8xxxu_save_regs(priv, iqk_bb_regs, - priv->bb_backup, RTL8XXXU_BB_REGS); - } - - rtl8xxxu_path_adda_on(priv, adda_regs, true); - - if (t == 0) { - val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1); - if (val32 & FPGA0_HSSI_PARM1_PI) - priv->pi_enabled = 1; - } - - if (!priv->pi_enabled) { - /* Switch BB to PI mode to do IQ Calibration. */ - rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100); - rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100); - } - - val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); - val32 &= ~FPGA_RF_MODE_CCK; - rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); - - rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600); - rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4); - rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000); - - if (!priv->no_pape) { - val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL); - val32 |= (FPGA0_RF_PAPE | - (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT)); - rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32); - } - - val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE); - val32 &= ~BIT(10); - rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32); - val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE); - val32 &= ~BIT(10); - rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32); - - if (priv->tx_paths > 1) { - rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000); - rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000); - } - - /* MAC settings */ - rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup); - - /* Page B init */ - rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000); - - if (priv->tx_paths > 1) - rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000); - - /* IQ calibration setting */ - rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); - rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); - rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); - - for (i = 0; i < retry; i++) { - path_a_ok = rtl8xxxu_iqk_path_a(priv); - if (path_a_ok == 0x03) { - val32 = rtl8xxxu_read32(priv, - REG_TX_POWER_BEFORE_IQK_A); - result[t][0] = (val32 >> 16) & 0x3ff; - val32 = rtl8xxxu_read32(priv, - REG_TX_POWER_AFTER_IQK_A); - result[t][1] = (val32 >> 16) & 0x3ff; - val32 = rtl8xxxu_read32(priv, - REG_RX_POWER_BEFORE_IQK_A_2); - result[t][2] = (val32 >> 16) & 0x3ff; - val32 = rtl8xxxu_read32(priv, - REG_RX_POWER_AFTER_IQK_A_2); - result[t][3] = (val32 >> 16) & 0x3ff; - break; - } else if (i == (retry - 1) && path_a_ok == 0x01) { - /* TX IQK OK */ - dev_dbg(dev, "%s: Path A IQK Only Tx Success!!\n", - __func__); - - val32 = rtl8xxxu_read32(priv, - REG_TX_POWER_BEFORE_IQK_A); - result[t][0] = (val32 >> 16) & 0x3ff; - val32 = rtl8xxxu_read32(priv, - REG_TX_POWER_AFTER_IQK_A); - result[t][1] = (val32 >> 16) & 0x3ff; - } - } - - if (!path_a_ok) - dev_dbg(dev, "%s: Path A IQK failed!\n", __func__); - - if (priv->tx_paths > 1) { - /* - * Path A into standby - */ - rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0); - rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000); - rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); - - /* Turn Path B ADDA on */ - rtl8xxxu_path_adda_on(priv, adda_regs, false); - - for (i = 0; i < retry; i++) { - path_b_ok = rtl8xxxu_iqk_path_b(priv); - if (path_b_ok == 0x03) { - val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); - result[t][4] = (val32 >> 16) & 0x3ff; - val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); - result[t][5] = (val32 >> 16) & 0x3ff; - val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2); - result[t][6] = (val32 >> 16) & 0x3ff; - val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2); - result[t][7] = (val32 >> 16) & 0x3ff; - break; - } else if (i == (retry - 1) && path_b_ok == 0x01) { - /* TX IQK OK */ - val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); - result[t][4] = (val32 >> 16) & 0x3ff; - val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); - result[t][5] = (val32 >> 16) & 0x3ff; - } - } - - if (!path_b_ok) - dev_dbg(dev, "%s: Path B IQK failed!\n", __func__); - } - - /* Back to BB mode, load original value */ - rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0); - - if (t) { - if (!priv->pi_enabled) { - /* - * Switch back BB to SI mode after finishing - * IQ Calibration - */ - val32 = 0x01000000; - rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32); - rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32); - } - - /* Reload ADDA power saving parameters */ - rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup, - RTL8XXXU_ADDA_REGS); - - /* Reload MAC parameters */ - rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup); - - /* Reload BB parameters */ - rtl8xxxu_restore_regs(priv, iqk_bb_regs, - priv->bb_backup, RTL8XXXU_BB_REGS); - - /* Restore RX initial gain */ - rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3); - - if (priv->tx_paths > 1) { - rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, - 0x00032ed3); - } - - /* Load 0xe30 IQC default value */ - rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00); - rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00); - } -} - -void rtl8xxxu_gen2_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start) -{ - struct h2c_cmd h2c; - - memset(&h2c, 0, sizeof(struct h2c_cmd)); - h2c.bt_wlan_calibration.cmd = H2C_8723B_BT_WLAN_CALIBRATION; - h2c.bt_wlan_calibration.data = start; - - rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_wlan_calibration)); -} - -void rtl8xxxu_gen1_phy_iq_calibrate(struct rtl8xxxu_priv *priv) -{ - struct device *dev = &priv->udev->dev; - int result[4][8]; /* last is final result */ - int i, candidate; - bool path_a_ok, path_b_ok; - u32 reg_e94, reg_e9c, reg_ea4, reg_eac; - u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc; - s32 reg_tmp = 0; - bool simu; - - memset(result, 0, sizeof(result)); - candidate = -1; - - path_a_ok = false; - path_b_ok = false; - - rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); - - for (i = 0; i < 3; i++) { - rtl8xxxu_phy_iqcalibrate(priv, result, i); - - if (i == 1) { - simu = rtl8xxxu_simularity_compare(priv, result, 0, 1); - if (simu) { - candidate = 0; - break; - } - } - - if (i == 2) { - simu = rtl8xxxu_simularity_compare(priv, result, 0, 2); - if (simu) { - candidate = 0; - break; - } - - simu = rtl8xxxu_simularity_compare(priv, result, 1, 2); - if (simu) { - candidate = 1; - } else { - for (i = 0; i < 8; i++) - reg_tmp += result[3][i]; - - if (reg_tmp) - candidate = 3; - else - candidate = -1; - } - } - } - - for (i = 0; i < 4; i++) { - reg_e94 = result[i][0]; - reg_e9c = result[i][1]; - reg_ea4 = result[i][2]; - reg_eac = result[i][3]; - reg_eb4 = result[i][4]; - reg_ebc = result[i][5]; - reg_ec4 = result[i][6]; - reg_ecc = result[i][7]; - } - - if (candidate >= 0) { - reg_e94 = result[candidate][0]; - priv->rege94 = reg_e94; - reg_e9c = result[candidate][1]; - priv->rege9c = reg_e9c; - reg_ea4 = result[candidate][2]; - reg_eac = result[candidate][3]; - reg_eb4 = result[candidate][4]; - priv->regeb4 = reg_eb4; - reg_ebc = result[candidate][5]; - priv->regebc = reg_ebc; - reg_ec4 = result[candidate][6]; - reg_ecc = result[candidate][7]; - dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate); - dev_dbg(dev, - "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x ecc=%x\n", - __func__, reg_e94, reg_e9c, - reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc); - path_a_ok = true; - path_b_ok = true; - } else { - reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100; - reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0; - } - - if (reg_e94 && candidate >= 0) - rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result, - candidate, (reg_ea4 == 0)); - - if (priv->tx_paths > 1 && reg_eb4) - rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result, - candidate, (reg_ec4 == 0)); - - rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg, - priv->bb_recovery_backup, RTL8XXXU_BB_REGS); -} - -void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv) -{ - u32 val32; - u32 rf_amode, rf_bmode = 0, lstf; - - /* Check continuous TX and Packet TX */ - lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF); - - if (lstf & OFDM_LSTF_MASK) { - /* Disable all continuous TX */ - val32 = lstf & ~OFDM_LSTF_MASK; - rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); - - /* Read original RF mode Path A */ - rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_AC); - - /* Set RF mode to standby Path A */ - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, - (rf_amode & 0x8ffff) | 0x10000); - - /* Path-B */ - if (priv->tx_paths > 1) { - rf_bmode = rtl8xxxu_read_rfreg(priv, RF_B, - RF6052_REG_AC); - - rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, - (rf_bmode & 0x8ffff) | 0x10000); - } - } else { - /* Deal with Packet TX case */ - /* block all queues */ - rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); - } - - /* Start LC calibration */ - if (priv->fops->has_s0s1) - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdfbe0); - val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG); - val32 |= 0x08000; - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32); - - msleep(100); - - if (priv->fops->has_s0s1) - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdffe0); - - /* Restore original parameters */ - if (lstf & OFDM_LSTF_MASK) { - /* Path-A */ - rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf); - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, rf_amode); - - /* Path-B */ - if (priv->tx_paths > 1) - rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, - rf_bmode); - } else /* Deal with Packet TX case */ - rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); -} - -static int rtl8xxxu_set_mac(struct rtl8xxxu_priv *priv, int port_num) -{ - int i; - u16 reg; - - switch (port_num) { - case 0: - reg = REG_MACID; - break; - case 1: - reg = REG_MACID1; - break; - default: - WARN_ONCE(1, "%s: invalid port_num\n", __func__); - return -EINVAL; - } - - for (i = 0; i < ETH_ALEN; i++) - rtl8xxxu_write8(priv, reg + i, priv->vifs[port_num]->addr[i]); - - return 0; -} - -static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv *priv, const u8 *bssid, int port_num) -{ - int i; - u16 reg; - - dev_dbg(&priv->udev->dev, "%s: (%pM)\n", __func__, bssid); - - switch (port_num) { - case 0: - reg = REG_BSSID; - break; - case 1: - reg = REG_BSSID1; - break; - default: - WARN_ONCE(1, "%s: invalid port_num\n", __func__); - return -EINVAL; - } - - for (i = 0; i < ETH_ALEN; i++) - rtl8xxxu_write8(priv, reg + i, bssid[i]); - - return 0; -} - -static void -rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv *priv, u8 ampdu_factor) -{ - u8 vals[4] = { 0x41, 0xa8, 0x72, 0xb9 }; - u8 max_agg = 0xf; - int i; - - ampdu_factor = 1 << (ampdu_factor + 2); - if (ampdu_factor > max_agg) - ampdu_factor = max_agg; - - for (i = 0; i < 4; i++) { - if ((vals[i] & 0xf0) > (ampdu_factor << 4)) - vals[i] = (vals[i] & 0x0f) | (ampdu_factor << 4); - - if ((vals[i] & 0x0f) > ampdu_factor) - vals[i] = (vals[i] & 0xf0) | ampdu_factor; - - rtl8xxxu_write8(priv, REG_AGGLEN_LMT + i, vals[i]); - } -} - -static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv *priv, u8 density) -{ - u8 val8; - - val8 = rtl8xxxu_read8(priv, REG_AMPDU_MIN_SPACE); - val8 &= 0xf8; - val8 |= density; - rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8); -} - -static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv *priv) -{ - u8 val8; - int count, ret = 0; - - /* Start of rtl8723AU_card_enable_flow */ - /* Act to Cardemu sequence*/ - /* Turn off RF */ - rtl8xxxu_write8(priv, REG_RF_CTRL, 0); - - /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */ - val8 = rtl8xxxu_read8(priv, REG_LEDCFG2); - val8 &= ~LEDCFG2_DPDT_SELECT; - rtl8xxxu_write8(priv, REG_LEDCFG2, val8); - - /* 0x0005[1] = 1 turn off MAC by HW state machine*/ - val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); - val8 |= BIT(1); - rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); - - for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { - val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); - if ((val8 & BIT(1)) == 0) - break; - udelay(10); - } - - if (!count) { - dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n", - __func__); - ret = -EBUSY; - goto exit; - } - - /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */ - val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL); - val8 |= SYS_ISO_ANALOG_IPS; - rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8); - - /* 0x0020[0] = 0 disable LDOA12 MACRO block*/ - val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL); - val8 &= ~LDOA15_ENABLE; - rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8); - -exit: - return ret; -} - -int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv) -{ - u8 val8; - u8 val32; - int count, ret = 0; - - rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); - - /* - * Poll - wait for RX packet to complete - */ - for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { - val32 = rtl8xxxu_read32(priv, 0x5f8); - if (!val32) - break; - udelay(10); - } - - if (!count) { - dev_warn(&priv->udev->dev, - "%s: RX poll timed out (0x05f8)\n", __func__); - ret = -EBUSY; - goto exit; - } - - /* Disable CCK and OFDM, clock gated */ - val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); - val8 &= ~SYS_FUNC_BBRSTB; - rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); - - udelay(2); - - /* Reset baseband */ - val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); - val8 &= ~SYS_FUNC_BB_GLB_RSTN; - rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); - - /* Reset MAC TRX */ - val8 = rtl8xxxu_read8(priv, REG_CR); - val8 = CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE; - rtl8xxxu_write8(priv, REG_CR, val8); - - /* Reset MAC TRX */ - val8 = rtl8xxxu_read8(priv, REG_CR + 1); - val8 &= ~BIT(1); /* CR_SECURITY_ENABLE */ - rtl8xxxu_write8(priv, REG_CR + 1, val8); - - /* Respond TX OK to scheduler */ - val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST); - val8 |= DUAL_TSF_TX_OK; - rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8); - -exit: - return ret; -} - -void rtl8xxxu_disabled_to_emu(struct rtl8xxxu_priv *priv) -{ - u8 val8; - - /* Clear suspend enable and power down enable*/ - val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); - val8 &= ~(BIT(3) | BIT(7)); - rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); - - /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ - val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2); - val8 &= ~BIT(0); - rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8); - - /* 0x04[12:11] = 11 enable WL suspend*/ - val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); - val8 &= ~(BIT(3) | BIT(4)); - rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); -} - -static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv *priv) -{ - u8 val8; - - /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */ - rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20); - - /* 0x04[12:11] = 01 enable WL suspend */ - val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); - val8 &= ~BIT(4); - val8 |= BIT(3); - rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); - - val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); - val8 |= BIT(7); - rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); - - /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */ - val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2); - val8 |= BIT(0); - rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8); - - return 0; -} - -int rtl8xxxu_flush_fifo(struct rtl8xxxu_priv *priv) -{ - struct device *dev = &priv->udev->dev; - u32 val32; - int retry, retval; - - rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); - - val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM); - val32 |= RXPKT_NUM_RW_RELEASE_EN; - rtl8xxxu_write32(priv, REG_RXPKT_NUM, val32); - - retry = 100; - retval = -EBUSY; - - do { - val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM); - if (val32 & RXPKT_NUM_RXDMA_IDLE) { - retval = 0; - break; - } - } while (retry--); - - rtl8xxxu_write16(priv, REG_RQPN_NPQ, 0); - rtl8xxxu_write32(priv, REG_RQPN, 0x80000000); - mdelay(2); - - if (!retry) - dev_warn(dev, "Failed to flush FIFO\n"); - - return retval; -} - -void rtl8xxxu_gen1_usb_quirks(struct rtl8xxxu_priv *priv) -{ - /* Fix USB interface interference issue */ - rtl8xxxu_write8(priv, 0xfe40, 0xe0); - rtl8xxxu_write8(priv, 0xfe41, 0x8d); - rtl8xxxu_write8(priv, 0xfe42, 0x80); - /* - * This sets TXDMA_OFFSET_DROP_DATA_EN (bit 9) as well as bits - * 8 and 5, for which I have found no documentation. - */ - rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320); - - /* - * Solve too many protocol error on USB bus. - * Can't do this for 8188/8192 UMC A cut parts - */ - if (!(!priv->chip_cut && priv->vendor_umc)) { - rtl8xxxu_write8(priv, 0xfe40, 0xe6); - rtl8xxxu_write8(priv, 0xfe41, 0x94); - rtl8xxxu_write8(priv, 0xfe42, 0x80); - - rtl8xxxu_write8(priv, 0xfe40, 0xe0); - rtl8xxxu_write8(priv, 0xfe41, 0x19); - rtl8xxxu_write8(priv, 0xfe42, 0x80); - - rtl8xxxu_write8(priv, 0xfe40, 0xe5); - rtl8xxxu_write8(priv, 0xfe41, 0x91); - rtl8xxxu_write8(priv, 0xfe42, 0x80); - - rtl8xxxu_write8(priv, 0xfe40, 0xe2); - rtl8xxxu_write8(priv, 0xfe41, 0x81); - rtl8xxxu_write8(priv, 0xfe42, 0x80); - } -} - -void rtl8xxxu_gen2_usb_quirks(struct rtl8xxxu_priv *priv) -{ - u32 val32; - - val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK); - val32 |= TXDMA_OFFSET_DROP_DATA_EN; - rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32); -} - -void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv) -{ - u8 val8; - u16 val16; - u32 val32; - - /* - * Workaround for 8188RU LNA power leakage problem. - */ - if (priv->rtl_chip == RTL8188R) { - val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM); - val32 |= BIT(1); - rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32); - } - - rtl8xxxu_flush_fifo(priv); - - rtl8xxxu_active_to_lps(priv); - - /* Turn off RF */ - rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00); - - /* Reset Firmware if running in RAM */ - if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL) - rtl8xxxu_firmware_self_reset(priv); - - /* Reset MCU */ - val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); - val16 &= ~SYS_FUNC_CPU_ENABLE; - rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); - - /* Reset MCU ready status */ - rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00); - - rtl8xxxu_active_to_emu(priv); - rtl8xxxu_emu_to_disabled(priv); - - /* Reset MCU IO Wrapper */ - val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); - val8 &= ~BIT(0); - rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); - - val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); - val8 |= BIT(0); - rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); - - /* RSV_CTRL 0x1C[7:0] = 0x0e lock ISO/CLK/Power control register */ - rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e); -} - -void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv, - u8 arg1, u8 arg2, u8 arg3, u8 arg4, u8 arg5) -{ - struct h2c_cmd h2c; - - memset(&h2c, 0, sizeof(struct h2c_cmd)); - h2c.b_type_dma.cmd = H2C_8723B_B_TYPE_TDMA; - h2c.b_type_dma.data1 = arg1; - h2c.b_type_dma.data2 = arg2; - h2c.b_type_dma.data3 = arg3; - h2c.b_type_dma.data4 = arg4; - h2c.b_type_dma.data5 = arg5; - rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.b_type_dma)); -} - -void rtl8xxxu_gen2_disable_rf(struct rtl8xxxu_priv *priv) -{ - u32 val32; - - val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA); - val32 &= ~(BIT(22) | BIT(23)); - rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32); -} - -static void rtl8xxxu_init_queue_reserved_page(struct rtl8xxxu_priv *priv) -{ - struct rtl8xxxu_fileops *fops = priv->fops; - u32 hq, lq, nq, eq, pubq; - u32 val32; - - hq = 0; - lq = 0; - nq = 0; - eq = 0; - pubq = 0; - - if (priv->ep_tx_high_queue) - hq = fops->page_num_hi; - if (priv->ep_tx_low_queue) - lq = fops->page_num_lo; - if (priv->ep_tx_normal_queue) - nq = fops->page_num_norm; - - val32 = (nq << RQPN_NPQ_SHIFT) | (eq << RQPN_EPQ_SHIFT); - rtl8xxxu_write32(priv, REG_RQPN_NPQ, val32); - - pubq = fops->total_page_num - hq - lq - nq - 1; - - val32 = RQPN_LOAD; - val32 |= (hq << RQPN_HI_PQ_SHIFT); - val32 |= (lq << RQPN_LO_PQ_SHIFT); - val32 |= (pubq << RQPN_PUB_PQ_SHIFT); - - rtl8xxxu_write32(priv, REG_RQPN, val32); -} - -void rtl8xxxu_init_burst(struct rtl8xxxu_priv *priv) -{ - u8 val8; - - /* - * For USB high speed set 512B packets - */ - val8 = rtl8xxxu_read8(priv, REG_RXDMA_PRO_8723B); - u8p_replace_bits(&val8, 1, RXDMA_PRO_DMA_BURST_SIZE); - u8p_replace_bits(&val8, 3, RXDMA_PRO_DMA_BURST_CNT); - val8 |= RXDMA_PRO_DMA_MODE; - rtl8xxxu_write8(priv, REG_RXDMA_PRO_8723B, val8); - - /* - * Enable single packet AMPDU - */ - val8 = rtl8xxxu_read8(priv, REG_HT_SINGLE_AMPDU_8723B); - val8 |= HT_SINGLE_AMPDU_ENABLE; - rtl8xxxu_write8(priv, REG_HT_SINGLE_AMPDU_8723B, val8); - - rtl8xxxu_write16(priv, REG_MAX_AGGR_NUM, priv->fops->max_aggr_num); - rtl8xxxu_write8(priv, REG_AMPDU_MAX_TIME_8723B, - priv->fops->ampdu_max_time); - rtl8xxxu_write32(priv, REG_AGGLEN_LMT, 0xffffffff); - rtl8xxxu_write8(priv, REG_RX_PKT_LIMIT, 0x18); - rtl8xxxu_write8(priv, REG_PIFS, 0x00); - if (priv->rtl_chip == RTL8188F || priv->rtl_chip == RTL8710B || - priv->rtl_chip == RTL8192F) { - rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, FWHW_TXQ_CTRL_AMPDU_RETRY); - rtl8xxxu_write32(priv, REG_FAST_EDCA_CTRL, 0x03086666); - } - rtl8xxxu_write8(priv, REG_USTIME_TSF_8723B, priv->fops->ustime_tsf_edca); - rtl8xxxu_write8(priv, REG_USTIME_EDCA, priv->fops->ustime_tsf_edca); - - /* to prevent mac is reseted by bus. */ - val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL); - val8 |= RSV_CTRL_WLOCK_1C | RSV_CTRL_DIS_PRST; - rtl8xxxu_write8(priv, REG_RSV_CTRL, val8); -} - -static u8 rtl8xxxu_acquire_macid(struct rtl8xxxu_priv *priv) -{ - u8 macid; - - macid = find_first_zero_bit(priv->mac_id_map, RTL8XXXU_MAX_MAC_ID_NUM); - if (macid < RTL8XXXU_MAX_MAC_ID_NUM) - set_bit(macid, priv->mac_id_map); - - return macid; -} - -static void rtl8xxxu_release_macid(struct rtl8xxxu_priv *priv, u8 macid) -{ - clear_bit(macid, priv->mac_id_map); -} - -static inline u8 rtl8xxxu_get_macid(struct rtl8xxxu_priv *priv, - struct ieee80211_sta *sta) -{ - struct rtl8xxxu_sta_info *sta_info; - - if (!sta) - return 0; - - sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv; - if (!sta_info) - return 0; - - return sta_info->macid; -} - -static int rtl8xxxu_init_device(struct ieee80211_hw *hw) -{ - struct rtl8xxxu_priv *priv = hw->priv; - struct device *dev = &priv->udev->dev; - struct rtl8xxxu_fileops *fops = priv->fops; - bool macpower; - int ret; - u8 val8; - u16 val16; - u32 val32; - - /* Check if MAC is already powered on */ - val8 = rtl8xxxu_read8(priv, REG_CR); - val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR); - - /* - * Fix 92DU-VC S3 hang with the reason is that secondary mac is not - * initialized. First MAC returns 0xea, second MAC returns 0x00 - */ - if (val8 == 0xea || !(val16 & SYS_CLK_MAC_CLK_ENABLE)) - macpower = false; - else - macpower = true; - - if (fops->needs_full_init) - macpower = false; - - ret = fops->power_on(priv); - if (ret < 0) { - dev_warn(dev, "%s: Failed power on\n", __func__); - goto exit; - } - - if (!macpower) - rtl8xxxu_init_queue_reserved_page(priv); - - ret = rtl8xxxu_init_queue_priority(priv); - dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret); - if (ret) - goto exit; - - /* - * Set RX page boundary - */ - rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, fops->trxff_boundary); - - ret = rtl8xxxu_download_firmware(priv); - dev_dbg(dev, "%s: download_firmware %i\n", __func__, ret); - if (ret) - goto exit; - ret = rtl8xxxu_start_firmware(priv); - dev_dbg(dev, "%s: start_firmware %i\n", __func__, ret); - if (ret) - goto exit; - - if (fops->phy_init_antenna_selection) - fops->phy_init_antenna_selection(priv); - - ret = rtl8xxxu_init_mac(priv); - - dev_dbg(dev, "%s: init_mac %i\n", __func__, ret); - if (ret) - goto exit; - - ret = rtl8xxxu_init_phy_bb(priv); - dev_dbg(dev, "%s: init_phy_bb %i\n", __func__, ret); - if (ret) - goto exit; - - ret = fops->init_phy_rf(priv); - if (ret) - goto exit; - - /* Mac APLL Setting */ - if (priv->rtl_chip == RTL8192F) - rtl8xxxu_write16_set(priv, REG_AFE_CTRL4, BIT(4) | BIT(15)); - - /* RFSW Control - clear bit 14 ?? */ - if (priv->rtl_chip != RTL8723B && priv->rtl_chip != RTL8192E && - priv->rtl_chip != RTL8188E && priv->rtl_chip != RTL8710B && - priv->rtl_chip != RTL8192F) - rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003); - - val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW | - FPGA0_RF_ANTSWB | - ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB) << FPGA0_RF_BD_CTRL_SHIFT); - if (!priv->no_pape) { - val32 |= (FPGA0_RF_PAPE | - (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT)); - } - rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32); - - /* 0x860[6:5]= 00 - why? - this sets antenna B */ - if (priv->rtl_chip != RTL8192E && priv->rtl_chip != RTL8188E && - priv->rtl_chip != RTL8710B && priv->rtl_chip != RTL8192F) - rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66f60210); - - if (!macpower) { - /* - * Set TX buffer boundary - */ - val8 = fops->total_page_num + 1; - - rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8); - rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8); - rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8); - rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8); - rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8); - } - - /* - * The vendor drivers set PBP for all devices, except 8192e. - * There is no explanation for this in any of the sources. - */ - val8 = (fops->pbp_rx << PBP_PAGE_SIZE_RX_SHIFT) | - (fops->pbp_tx << PBP_PAGE_SIZE_TX_SHIFT); - if (priv->rtl_chip != RTL8192E) - rtl8xxxu_write8(priv, REG_PBP, val8); - - dev_dbg(dev, "%s: macpower %i\n", __func__, macpower); - if (!macpower) { - ret = fops->llt_init(priv); - if (ret) { - dev_warn(dev, "%s: LLT table init failed\n", __func__); - goto exit; - } - - /* - * Chip specific quirks - */ - fops->usb_quirks(priv); - - /* - * Enable TX report and TX report timer for 8723bu/8188eu/... - */ - if (fops->has_tx_report) { - /* - * The RTL8188EU has two types of TX reports: - * rpt_sel=1: - * One report for one frame. We can use this for frames - * with IEEE80211_TX_CTL_REQ_TX_STATUS. - * rpt_sel=2: - * One report for many frames transmitted over a period - * of time. (This is what REG_TX_REPORT_TIME is for.) The - * report includes the number of frames transmitted - * successfully, and the number of unsuccessful - * transmissions. We use this for software rate control. - * - * Bit 0 of REG_TX_REPORT_CTRL is required for both types. - * Bit 1 (TX_REPORT_CTRL_TIMER_ENABLE) is required for - * type 2. - */ - val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL); - if (priv->rtl_chip == RTL8188E) - val8 |= BIT(0); - val8 |= TX_REPORT_CTRL_TIMER_ENABLE; - rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8); - /* Set MAX RPT MACID */ - rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL + 1, 0x02); - /* TX report Timer. Unit: 32us */ - rtl8xxxu_write16(priv, REG_TX_REPORT_TIME, 0xcdf0); - - /* tmp ps ? */ - val8 = rtl8xxxu_read8(priv, 0xa3); - val8 &= 0xf8; - rtl8xxxu_write8(priv, 0xa3, val8); - } - - if (priv->rtl_chip == RTL8710B || priv->rtl_chip == RTL8192F) - rtl8xxxu_write8(priv, REG_EARLY_MODE_CONTROL_8710B, 0); - } - - /* - * Unit in 8 bytes. - * Get Rx PHY status in order to report RSSI and others. - */ - rtl8xxxu_write8(priv, REG_RX_DRVINFO_SZ, 4); - - if (priv->rtl_chip == RTL8192E) { - rtl8xxxu_write32(priv, REG_HIMR0, 0x00); - rtl8xxxu_write32(priv, REG_HIMR1, 0x00); - } else if (priv->rtl_chip == RTL8188F) { - rtl8xxxu_write32(priv, REG_HISR0, 0xffffffff); - rtl8xxxu_write32(priv, REG_HISR1, 0xffffffff); - } else if (priv->rtl_chip == RTL8188E) { - rtl8xxxu_write32(priv, REG_HISR0, 0xffffffff); - val32 = IMR0_PSTIMEOUT | IMR0_TBDER | IMR0_CPWM | IMR0_CPWM2; - rtl8xxxu_write32(priv, REG_HIMR0, val32); - val32 = IMR1_TXERR | IMR1_RXERR | IMR1_TXFOVW | IMR1_RXFOVW; - rtl8xxxu_write32(priv, REG_HIMR1, val32); - val8 = rtl8xxxu_read8(priv, REG_USB_SPECIAL_OPTION); - val8 |= USB_SPEC_INT_BULK_SELECT; - rtl8xxxu_write8(priv, REG_USB_SPECIAL_OPTION, val8); - } else if (priv->rtl_chip == RTL8710B) { - rtl8xxxu_write32(priv, REG_HIMR0_8710B, 0); - } else if (priv->rtl_chip != RTL8192F) { - /* - * Enable all interrupts - not obvious USB needs to do this - */ - rtl8xxxu_write32(priv, REG_HISR, 0xffffffff); - rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff); - } - - /* - * Configure initial WMAC settings - */ - val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST | - RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL | - RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC; - rtl8xxxu_write32(priv, REG_RCR, val32); - priv->regrcr = val32; - - if (fops->init_reg_rxfltmap) { - /* Accept all data frames */ - rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff); - - /* - * Since ADF is removed from RCR, ps-poll will not be indicate to driver, - * RxFilterMap should mask ps-poll to gurantee AP mode can rx ps-poll. - */ - rtl8xxxu_write16(priv, REG_RXFLTMAP1, 0x400); - - /* Accept all management frames */ - rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff); - } else { - /* - * Accept all multicast - */ - rtl8xxxu_write32(priv, REG_MAR, 0xffffffff); - rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff); - } - - /* - * Init adaptive controls - */ - val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); - val32 &= ~RESPONSE_RATE_BITMAP_ALL; - val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M; - rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); - - /* CCK = 0x0a, OFDM = 0x10 */ - rtl8xxxu_set_spec_sifs(priv, 0x10, 0x10); - rtl8xxxu_set_retry(priv, 0x30, 0x30); - rtl8xxxu_set_spec_sifs(priv, 0x0a, 0x10); - - /* - * Init EDCA - */ - rtl8xxxu_write16(priv, REG_MAC_SPEC_SIFS, 0x100a); - - /* Set CCK SIFS */ - rtl8xxxu_write16(priv, REG_SIFS_CCK, 0x100a); - - /* Set OFDM SIFS */ - rtl8xxxu_write16(priv, REG_SIFS_OFDM, 0x100a); - - /* TXOP */ - rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b); - rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f); - rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324); - rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226); - - /* Set data auto rate fallback retry count */ - rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000); - rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404); - rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201); - rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605); - - val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL); - val8 |= FWHW_TXQ_CTRL_AMPDU_RETRY; - rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, val8); - - /* Set ACK timeout */ - rtl8xxxu_write8(priv, REG_ACKTO, 0x40); - - /* - * Initialize beacon parameters - */ - val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8); - rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16); - rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404); - if (priv->rtl_chip != RTL8188F && priv->rtl_chip != RTL8710B && - priv->rtl_chip != RTL8192F) - /* Firmware will control REG_DRVERLYINT when power saving is enable, */ - /* so don't set this register on STA mode. */ - rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME); - rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME); - rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F); - - /* - * Initialize burst parameters - */ - if (priv->fops->init_burst) - priv->fops->init_burst(priv); - - if (fops->init_aggregation) - fops->init_aggregation(priv); - - if (fops->init_reg_pkt_life_time) { - rtl8xxxu_write16(priv, REG_PKT_VO_VI_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */ - rtl8xxxu_write16(priv, REG_PKT_BE_BK_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */ - } - - /* - * Enable CCK and OFDM block - */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); - val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM); - rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); - - /* - * Invalidate all CAM entries - bit 30 is undocumented - */ - rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30)); - - /* - * Start out with default power levels for channel 6, 20MHz - */ - fops->set_tx_power(priv, 1, false); - - /* Let the 8051 take control of antenna setting */ - if (priv->rtl_chip != RTL8192E && priv->rtl_chip != RTL8188F && - priv->rtl_chip != RTL8710B && priv->rtl_chip != RTL8192C) { - val8 = rtl8xxxu_read8(priv, REG_LEDCFG2); - val8 |= LEDCFG2_DPDT_SELECT; - rtl8xxxu_write8(priv, REG_LEDCFG2, val8); - } - - rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, 0xff); - - /* Disable BAR - not sure if this has any effect on USB */ - rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff); - - if (priv->rtl_chip != RTL8188F && priv->rtl_chip != RTL8188E && - priv->rtl_chip != RTL8710B && priv->rtl_chip != RTL8192F) - rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0); - - if (fops->init_statistics) - fops->init_statistics(priv); - - if (priv->rtl_chip == RTL8192E) { - /* - * 0x4c6[3] 1: RTS BW = Data BW - * 0: RTS BW depends on CCA / secondary CCA result. - */ - val8 = rtl8xxxu_read8(priv, REG_QUEUE_CTRL); - val8 &= ~BIT(3); - rtl8xxxu_write8(priv, REG_QUEUE_CTRL, val8); - /* - * Reset USB mode switch setting - */ - rtl8xxxu_write8(priv, REG_ACLK_MON, 0x00); - } else if (priv->rtl_chip == RTL8188F || priv->rtl_chip == RTL8188E || - priv->rtl_chip == RTL8192F) { - /* - * Init GPIO settings for 8188f, 8188e, 8192f - */ - val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG); - val8 &= ~GPIO_MUXCFG_IO_SEL_ENBT; - rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8); - } - - if (priv->rtl_chip == RTL8188F) - /* CCK PD */ - rtl8xxxu_write8(priv, REG_CCK_PD_THRESH, CCK_PD_TYPE1_LV1_TH); - - fops->phy_lc_calibrate(priv); - - fops->phy_iq_calibrate(priv); - - /* - * This should enable thermal meter - */ - if (fops->gen2_thermal_meter) { - if (priv->rtl_chip == RTL8188F || priv->rtl_chip == RTL8710B) { - val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_T_METER_8723B); - val32 |= 0x30000; - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER_8723B, val32); - } else { - rtl8xxxu_write_rfreg(priv, - RF_A, RF6052_REG_T_METER_8723B, 0x37cf8); - } - } else { - rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60); - } - - /* Set NAV_UPPER to 30000us */ - val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT); - rtl8xxxu_write8(priv, REG_NAV_UPPER, val8); - - if (priv->rtl_chip == RTL8723A) { - /* - * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test, - * but we need to find root cause. - * This is 8723au only. - */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); - if ((val32 & 0xff000000) != 0x83000000) { - val32 |= FPGA_RF_MODE_CCK; - rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); - } - } else if (priv->rtl_chip == RTL8192E || priv->rtl_chip == RTL8188E) { - rtl8xxxu_write8(priv, REG_USB_HRPWM, 0x00); - } - - val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL); - val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK; - /* ack for xmit mgmt frames. */ - rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32); - - if (priv->rtl_chip == RTL8192E) { - /* - * Fix LDPC rx hang issue. - */ - val32 = rtl8xxxu_read32(priv, REG_AFE_MISC); - rtl8xxxu_write8(priv, REG_8192E_LDOV12_CTRL, 0x75); - val32 &= 0xfff00fff; - val32 |= 0x0007e000; - rtl8xxxu_write32(priv, REG_AFE_MISC, val32); - - /* - * 0x824[9] = 0x82C[9] = 0xA80[7] those registers setting - * should be equal or CCK RSSI report may be incorrect - */ - val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2); - priv->cck_agc_report_type = - u32_get_bits(val32, FPGA0_HSSI_PARM2_CCK_HIGH_PWR); - - val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_HSSI_PARM2); - if (priv->cck_agc_report_type != - u32_get_bits(val32, FPGA0_HSSI_PARM2_CCK_HIGH_PWR)) { - if (priv->cck_agc_report_type) - val32 |= FPGA0_HSSI_PARM2_CCK_HIGH_PWR; - else - val32 &= ~FPGA0_HSSI_PARM2_CCK_HIGH_PWR; - rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM2, val32); - } - - val32 = rtl8xxxu_read32(priv, REG_AGC_RPT); - if (priv->cck_agc_report_type) - val32 |= AGC_RPT_CCK; - else - val32 &= ~AGC_RPT_CCK; - rtl8xxxu_write32(priv, REG_AGC_RPT, val32); - } - - if (priv->rtl_chip == RTL8710B) { - /* - * 0x76D[5:4] is Port0,Port1 Enable Bit. - * This is only for 8710B, 2b'00 for MP and 2b'11 for Normal Driver - */ - val8 = rtl8xxxu_read8(priv, REG_PORT_CONTROL_8710B); - val8 |= BIT(5) | BIT(4); - rtl8xxxu_write8(priv, REG_PORT_CONTROL_8710B, val8); - - /* Set 0x5c[8] and [2:0] = 1, LDO mode */ - val32 = rtl8xxxu_read32(priv, REG_WL_RF_PSS_8710B); - val32 |= 0x107; - rtl8xxxu_write32(priv, REG_WL_RF_PSS_8710B, val32); - } - - val32 = rtl8xxxu_read32(priv, 0xa9c); - priv->cck_new_agc = u32_get_bits(val32, BIT(17)); - - /* Initialise the center frequency offset tracking */ - if (priv->fops->set_crystal_cap) { - val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING); - priv->cfo_tracking.atc_status = val32 & CFO_TRACKING_ATC_STATUS; - priv->cfo_tracking.adjust = true; - priv->cfo_tracking.crystal_cap = priv->default_crystal_cap; - } - - if (priv->rtl_chip == RTL8188E) - rtl8188e_ra_info_init_all(&priv->ra_info); - - set_bit(RTL8XXXU_BC_MC_MACID, priv->mac_id_map); - set_bit(RTL8XXXU_BC_MC_MACID1, priv->mac_id_map); - -exit: - return ret; -} - -static void rtl8xxxu_cam_write(struct rtl8xxxu_priv *priv, - struct ieee80211_key_conf *key, const u8 *mac) -{ - u32 cmd, val32, addr, ctrl; - int j, i, tmp_debug; - - tmp_debug = rtl8xxxu_debug; - if (rtl8xxxu_debug & RTL8XXXU_DEBUG_KEY) - rtl8xxxu_debug |= RTL8XXXU_DEBUG_REG_WRITE; - - /* - * This is a bit of a hack - the lower bits of the cipher - * suite selector happens to match the cipher index in the CAM - */ - addr = key->hw_key_idx << CAM_CMD_KEY_SHIFT; - ctrl = (key->cipher & 0x0f) << 2 | key->keyidx | CAM_WRITE_VALID; - if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) - ctrl |= BIT(6); - - for (j = 5; j >= 0; j--) { - switch (j) { - case 0: - val32 = ctrl | (mac[0] << 16) | (mac[1] << 24); - break; - case 1: - val32 = mac[2] | (mac[3] << 8) | - (mac[4] << 16) | (mac[5] << 24); - break; - default: - i = (j - 2) << 2; - val32 = key->key[i] | (key->key[i + 1] << 8) | - key->key[i + 2] << 16 | key->key[i + 3] << 24; - break; - } - - rtl8xxxu_write32(priv, REG_CAM_WRITE, val32); - cmd = CAM_CMD_POLLING | CAM_CMD_WRITE | (addr + j); - rtl8xxxu_write32(priv, REG_CAM_CMD, cmd); - udelay(100); - } - - rtl8xxxu_debug = tmp_debug; -} - -static -int rtl8xxxu_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant) -{ - struct rtl8xxxu_priv *priv = hw->priv; - - *tx_ant = BIT(priv->tx_paths) - 1; - *rx_ant = BIT(priv->rx_paths) - 1; - - return 0; -} - -static int rtl8xxxu_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta, - bool set) -{ - struct rtl8xxxu_priv *priv = hw->priv; - - schedule_delayed_work(&priv->update_beacon_work, 0); - - return 0; -} - -static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw, - struct ieee80211_vif *vif, const u8 *mac) -{ - struct rtl8xxxu_priv *priv = hw->priv; - u8 val8; - - val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL); - val8 |= BEACON_DISABLE_TSF_UPDATE; - rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8); -} - -static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw, - struct ieee80211_vif *vif) -{ - struct rtl8xxxu_priv *priv = hw->priv; - u8 val8; - - val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL); - val8 &= ~BEACON_DISABLE_TSF_UPDATE; - rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8); -} - -void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv, - u32 ramask, u8 rateid, int sgi, int txbw_40mhz, - u8 macid) -{ - struct h2c_cmd h2c; - - memset(&h2c, 0, sizeof(struct h2c_cmd)); - - h2c.ramask.cmd = H2C_SET_RATE_MASK; - h2c.ramask.mask_lo = cpu_to_le16(ramask & 0xffff); - h2c.ramask.mask_hi = cpu_to_le16(ramask >> 16); - - h2c.ramask.arg = 0x80; - if (sgi) - h2c.ramask.arg |= 0x20; - - dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n", - __func__, ramask, h2c.ramask.arg, sizeof(h2c.ramask)); - rtl8xxxu_gen1_h2c_cmd(priv, &h2c, sizeof(h2c.ramask)); -} - -void rtl8xxxu_gen2_update_rate_mask(struct rtl8xxxu_priv *priv, - u32 ramask, u8 rateid, int sgi, int txbw_40mhz, - u8 macid) -{ - struct h2c_cmd h2c; - u8 bw; - - if (txbw_40mhz) - bw = RTL8XXXU_CHANNEL_WIDTH_40; - else - bw = RTL8XXXU_CHANNEL_WIDTH_20; - - memset(&h2c, 0, sizeof(struct h2c_cmd)); - - h2c.b_macid_cfg.cmd = H2C_8723B_MACID_CFG_RAID; - h2c.b_macid_cfg.ramask0 = ramask & 0xff; - h2c.b_macid_cfg.ramask1 = (ramask >> 8) & 0xff; - h2c.b_macid_cfg.ramask2 = (ramask >> 16) & 0xff; - h2c.b_macid_cfg.ramask3 = (ramask >> 24) & 0xff; - h2c.b_macid_cfg.macid = macid; - - h2c.b_macid_cfg.data1 = rateid; - if (sgi) - h2c.b_macid_cfg.data1 |= BIT(7); - - h2c.b_macid_cfg.data2 = bw; - - dev_dbg(&priv->udev->dev, "%s: rate mask %08x, rateid %02x, sgi %d, size %zi\n", - __func__, ramask, rateid, sgi, sizeof(h2c.b_macid_cfg)); - rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.b_macid_cfg)); -} - -void rtl8xxxu_gen1_report_connect(struct rtl8xxxu_priv *priv, - u8 macid, u8 role, bool connect) -{ - struct h2c_cmd h2c; - - memset(&h2c, 0, sizeof(struct h2c_cmd)); - - h2c.joinbss.cmd = H2C_JOIN_BSS_REPORT; - - if (connect) - h2c.joinbss.data = H2C_JOIN_BSS_CONNECT; - else - h2c.joinbss.data = H2C_JOIN_BSS_DISCONNECT; - - rtl8xxxu_gen1_h2c_cmd(priv, &h2c, sizeof(h2c.joinbss)); -} - -void rtl8xxxu_gen2_report_connect(struct rtl8xxxu_priv *priv, - u8 macid, u8 role, bool connect) -{ - /* - * The firmware turns on the rate control when it knows it's - * connected to a network. - */ - struct h2c_cmd h2c; - - memset(&h2c, 0, sizeof(struct h2c_cmd)); - - h2c.media_status_rpt.cmd = H2C_8723B_MEDIA_STATUS_RPT; - if (connect) - h2c.media_status_rpt.parm |= BIT(0); - else - h2c.media_status_rpt.parm &= ~BIT(0); - - h2c.media_status_rpt.parm |= ((role << 4) & 0xf0); - h2c.media_status_rpt.macid = macid; - - rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.media_status_rpt)); -} - -void rtl8xxxu_gen1_report_rssi(struct rtl8xxxu_priv *priv, u8 macid, u8 rssi) -{ - struct h2c_cmd h2c; - const int h2c_size = 4; - - memset(&h2c, 0, sizeof(struct h2c_cmd)); - - h2c.rssi_report.cmd = H2C_SET_RSSI; - h2c.rssi_report.macid = macid; - h2c.rssi_report.rssi = rssi; - - rtl8xxxu_gen1_h2c_cmd(priv, &h2c, h2c_size); -} - -void rtl8xxxu_gen2_report_rssi(struct rtl8xxxu_priv *priv, u8 macid, u8 rssi) -{ - struct h2c_cmd h2c; - int h2c_size = sizeof(h2c.rssi_report); - - if (priv->rtl_chip == RTL8723B) - h2c_size = 4; - - memset(&h2c, 0, sizeof(struct h2c_cmd)); - - h2c.rssi_report.cmd = H2C_8723B_RSSI_SETTING; - h2c.rssi_report.macid = macid; - h2c.rssi_report.rssi = rssi; - - rtl8xxxu_gen2_h2c_cmd(priv, &h2c, h2c_size); -} - -void rtl8xxxu_gen1_init_aggregation(struct rtl8xxxu_priv *priv) -{ - u8 agg_ctrl, usb_spec, page_thresh, timeout; - - usb_spec = rtl8xxxu_read8(priv, REG_USB_SPECIAL_OPTION); - usb_spec &= ~USB_SPEC_USB_AGG_ENABLE; - rtl8xxxu_write8(priv, REG_USB_SPECIAL_OPTION, usb_spec); - - agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL); - agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN; - - if (!rtl8xxxu_dma_aggregation) { - rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl); - return; - } - - agg_ctrl |= TRXDMA_CTRL_RXDMA_AGG_EN; - rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl); - - /* - * The number of packets we can take looks to be buffer size / 512 - * which matches the 512 byte rounding we have to do when de-muxing - * the packets. - * - * Sample numbers from the vendor driver: - * USB High-Speed mode values: - * RxAggBlockCount = 8 : 512 byte unit - * RxAggBlockTimeout = 6 - * RxAggPageCount = 48 : 128 byte unit - * RxAggPageTimeout = 4 or 6 (absolute time 34ms/(2^6)) - */ - - page_thresh = (priv->fops->rx_agg_buf_size / 512); - if (rtl8xxxu_dma_agg_pages >= 0) { - if (rtl8xxxu_dma_agg_pages <= page_thresh) - timeout = page_thresh; - else if (rtl8xxxu_dma_agg_pages <= 6) - dev_err(&priv->udev->dev, - "%s: dma_agg_pages=%i too small, minimum is 6\n", - __func__, rtl8xxxu_dma_agg_pages); - else - dev_err(&priv->udev->dev, - "%s: dma_agg_pages=%i larger than limit %i\n", - __func__, rtl8xxxu_dma_agg_pages, page_thresh); - } - rtl8xxxu_write8(priv, REG_RXDMA_AGG_PG_TH, page_thresh); - /* - * REG_RXDMA_AGG_PG_TH + 1 seems to be the timeout register on - * gen2 chips and rtl8188eu. The rtl8723au seems unhappy if we - * don't set it, so better set both. - */ - timeout = 4; - - if (rtl8xxxu_dma_agg_timeout >= 0) { - if (rtl8xxxu_dma_agg_timeout <= 127) - timeout = rtl8xxxu_dma_agg_timeout; - else - dev_err(&priv->udev->dev, - "%s: Invalid dma_agg_timeout: %i\n", - __func__, rtl8xxxu_dma_agg_timeout); - } - - rtl8xxxu_write8(priv, REG_RXDMA_AGG_PG_TH + 1, timeout); - rtl8xxxu_write8(priv, REG_USB_DMA_AGG_TO, timeout); - priv->rx_buf_aggregation = 1; -} - -static const struct ieee80211_rate rtl8xxxu_legacy_ratetable[] = { - {.bitrate = 10, .hw_value = 0x00,}, - {.bitrate = 20, .hw_value = 0x01,}, - {.bitrate = 55, .hw_value = 0x02,}, - {.bitrate = 110, .hw_value = 0x03,}, - {.bitrate = 60, .hw_value = 0x04,}, - {.bitrate = 90, .hw_value = 0x05,}, - {.bitrate = 120, .hw_value = 0x06,}, - {.bitrate = 180, .hw_value = 0x07,}, - {.bitrate = 240, .hw_value = 0x08,}, - {.bitrate = 360, .hw_value = 0x09,}, - {.bitrate = 480, .hw_value = 0x0a,}, - {.bitrate = 540, .hw_value = 0x0b,}, -}; - -static void rtl8xxxu_desc_to_mcsrate(u16 rate, u8 *mcs, u8 *nss) -{ - if (rate <= DESC_RATE_54M) - return; - - if (rate >= DESC_RATE_MCS0 && rate <= DESC_RATE_MCS15) { - if (rate < DESC_RATE_MCS8) - *nss = 1; - else - *nss = 2; - *mcs = rate - DESC_RATE_MCS0; - } -} - -static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg) -{ - struct ieee80211_hw *hw = priv->hw; - u32 val32; - u8 rate_idx = 0; - - rate_cfg &= RESPONSE_RATE_BITMAP_ALL; - - val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); - if (hw->conf.chandef.chan->band == NL80211_BAND_5GHZ) - val32 &= RESPONSE_RATE_RRSR_INIT_5G; - else - val32 &= RESPONSE_RATE_RRSR_INIT_2G; - val32 |= rate_cfg; - rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); - - dev_dbg(&priv->udev->dev, "%s: rates %08x\n", __func__, rate_cfg); - - if (rate_cfg) - rate_idx = __fls(rate_cfg); - - rtl8xxxu_write8(priv, REG_INIRTS_RATE_SEL, rate_idx); -} - -static u16 -rtl8xxxu_wireless_mode(struct ieee80211_hw *hw, struct ieee80211_sta *sta) -{ - u16 network_type = WIRELESS_MODE_UNKNOWN; - - if (hw->conf.chandef.chan->band == NL80211_BAND_5GHZ) { - if (sta->deflink.vht_cap.vht_supported) - network_type = WIRELESS_MODE_AC; - else if (sta->deflink.ht_cap.ht_supported) - network_type = WIRELESS_MODE_N_5G; - - network_type |= WIRELESS_MODE_A; - } else { - if (sta->deflink.vht_cap.vht_supported) - network_type = WIRELESS_MODE_AC; - else if (sta->deflink.ht_cap.ht_supported) - network_type = WIRELESS_MODE_N_24G; - - if (sta->deflink.supp_rates[0] <= 0xf) - network_type |= WIRELESS_MODE_B; - else if (sta->deflink.supp_rates[0] & 0xf) - network_type |= (WIRELESS_MODE_B | WIRELESS_MODE_G); - else - network_type |= WIRELESS_MODE_G; - } - - return network_type; -} - -static void rtl8xxxu_set_aifs(struct rtl8xxxu_priv *priv, u8 slot_time) -{ - u32 reg_edca_param[IEEE80211_NUM_ACS] = { - [IEEE80211_AC_VO] = REG_EDCA_VO_PARAM, - [IEEE80211_AC_VI] = REG_EDCA_VI_PARAM, - [IEEE80211_AC_BE] = REG_EDCA_BE_PARAM, - [IEEE80211_AC_BK] = REG_EDCA_BK_PARAM, - }; - u32 val32; - u16 wireless_mode = 0; - u8 aifs, aifsn, sifs; - int i; - - for (i = 0; i < ARRAY_SIZE(priv->vifs); i++) { - struct ieee80211_sta *sta; - - if (!priv->vifs[i]) - continue; - - rcu_read_lock(); - sta = ieee80211_find_sta(priv->vifs[i], priv->vifs[i]->bss_conf.bssid); - if (sta) - wireless_mode = rtl8xxxu_wireless_mode(priv->hw, sta); - rcu_read_unlock(); - - if (wireless_mode) - break; - } - - if (priv->hw->conf.chandef.chan->band == NL80211_BAND_5GHZ || - (wireless_mode & WIRELESS_MODE_N_24G)) - sifs = 16; - else - sifs = 10; - - for (i = 0; i < IEEE80211_NUM_ACS; i++) { - val32 = rtl8xxxu_read32(priv, reg_edca_param[i]); - - /* It was set in conf_tx. */ - aifsn = val32 & 0xff; - - /* aifsn not set yet or already fixed */ - if (aifsn < 2 || aifsn > 15) - continue; - - aifs = aifsn * slot_time + sifs; - - val32 &= ~0xff; - val32 |= aifs; - rtl8xxxu_write32(priv, reg_edca_param[i], val32); - } -} - -void rtl8xxxu_update_ra_report(struct rtl8xxxu_ra_report *rarpt, - u8 rate, u8 sgi, u8 bw) -{ - u8 mcs, nss; - - rarpt->txrate.flags = 0; - - if (rate <= DESC_RATE_54M) { - rarpt->txrate.legacy = rtl8xxxu_legacy_ratetable[rate].bitrate; - } else { - rtl8xxxu_desc_to_mcsrate(rate, &mcs, &nss); - rarpt->txrate.flags |= RATE_INFO_FLAGS_MCS; - - rarpt->txrate.mcs = mcs; - rarpt->txrate.nss = nss; - - if (sgi) - rarpt->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; - - rarpt->txrate.bw = bw; - } - - rarpt->bit_rate = cfg80211_calculate_bitrate(&rarpt->txrate); - rarpt->desc_rate = rate; -} - -static void -rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif, - struct ieee80211_bss_conf *bss_conf, u64 changed) -{ - struct rtl8xxxu_vif *rtlvif = (struct rtl8xxxu_vif *)vif->drv_priv; - struct rtl8xxxu_priv *priv = hw->priv; - struct device *dev = &priv->udev->dev; - struct rtl8xxxu_sta_info *sta_info; - struct ieee80211_sta *sta; - struct rtl8xxxu_ra_report *rarpt; - u8 val8, macid; - u32 val32; - - rarpt = &priv->ra_report; - - if (changed & BSS_CHANGED_ASSOC) { - dev_dbg(dev, "Changed ASSOC: %i!\n", vif->cfg.assoc); - - rtl8xxxu_set_linktype(priv, vif->type, rtlvif->port_num); - - if (vif->cfg.assoc) { - u32 ramask; - int sgi = 0; - u8 highest_rate; - u8 bw; - - rcu_read_lock(); - sta = ieee80211_find_sta(vif, bss_conf->bssid); - if (!sta) { - dev_info(dev, "%s: ASSOC no sta found\n", - __func__); - rcu_read_unlock(); - goto error; - } - macid = rtl8xxxu_get_macid(priv, sta); - - if (sta->deflink.ht_cap.ht_supported) - dev_info(dev, "%s: HT supported\n", __func__); - if (sta->deflink.vht_cap.vht_supported) - dev_info(dev, "%s: VHT supported\n", __func__); - - /* TODO: Set bits 28-31 for rate adaptive id */ - ramask = (sta->deflink.supp_rates[0] & 0xfff) | - sta->deflink.ht_cap.mcs.rx_mask[0] << 12 | - sta->deflink.ht_cap.mcs.rx_mask[1] << 20; - if (sta->deflink.ht_cap.cap & - (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20)) - sgi = 1; - - highest_rate = fls(ramask) - 1; - if (rtl8xxxu_ht40_2g && - (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)) - bw = RATE_INFO_BW_40; - else - bw = RATE_INFO_BW_20; - - sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv; - sta_info->rssi_level = RTL8XXXU_RATR_STA_INIT; - rcu_read_unlock(); - - rtl8xxxu_update_ra_report(rarpt, highest_rate, sgi, bw); - - priv->fops->update_rate_mask(priv, ramask, 0, sgi, - bw == RATE_INFO_BW_40, macid); - - rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff); - - if (rtlvif->port_num == 0) - rtl8xxxu_stop_tx_beacon(priv); - - /* joinbss sequence */ - rtl8xxxu_write16(priv, REG_BCN_PSR_RPT, - 0xc000 | vif->cfg.aid); - - priv->fops->report_connect(priv, 0, H2C_MACID_ROLE_AP, true); - } else { - val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL); - val8 |= BEACON_DISABLE_TSF_UPDATE; - rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8); - - priv->fops->report_connect(priv, 0, H2C_MACID_ROLE_AP, false); - } - } - - if (changed & BSS_CHANGED_ERP_PREAMBLE) { - dev_dbg(dev, "Changed ERP_PREAMBLE: Use short preamble %i\n", - bss_conf->use_short_preamble); - val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); - if (bss_conf->use_short_preamble) - val32 |= RSR_ACK_SHORT_PREAMBLE; - else - val32 &= ~RSR_ACK_SHORT_PREAMBLE; - rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); - } - - if (changed & BSS_CHANGED_ERP_SLOT) { - dev_dbg(dev, "Changed ERP_SLOT: short_slot_time %i\n", - bss_conf->use_short_slot); - - if (bss_conf->use_short_slot) - val8 = 9; - else - val8 = 20; - rtl8xxxu_write8(priv, REG_SLOT, val8); - - rtl8xxxu_set_aifs(priv, val8); - } - - if (changed & BSS_CHANGED_BSSID) { - dev_dbg(dev, "Changed BSSID!\n"); - rtl8xxxu_set_bssid(priv, bss_conf->bssid, rtlvif->port_num); - } - - if (changed & BSS_CHANGED_BASIC_RATES) { - dev_dbg(dev, "Changed BASIC_RATES!\n"); - rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates); - } - - if (changed & BSS_CHANGED_BEACON_ENABLED) { - if (bss_conf->enable_beacon) - rtl8xxxu_start_tx_beacon(priv); - else - rtl8xxxu_stop_tx_beacon(priv); - } - - if (changed & BSS_CHANGED_BEACON) - schedule_delayed_work(&priv->update_beacon_work, 0); - -error: - return; -} - -static int rtl8xxxu_start_ap(struct ieee80211_hw *hw, struct ieee80211_vif *vif, - struct ieee80211_bss_conf *link_conf) -{ - struct rtl8xxxu_vif *rtlvif = (struct rtl8xxxu_vif *)vif->drv_priv; - struct rtl8xxxu_priv *priv = hw->priv; - struct device *dev = &priv->udev->dev; - - dev_dbg(dev, "Start AP mode\n"); - rtl8xxxu_set_bssid(priv, vif->bss_conf.bssid, rtlvif->port_num); - rtl8xxxu_write16(priv, REG_BCN_INTERVAL, vif->bss_conf.beacon_int); - priv->fops->report_connect(priv, RTL8XXXU_BC_MC_MACID, 0, true); - - return 0; -} - -static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue) -{ - u32 rtlqueue; - - switch (queue) { - case IEEE80211_AC_VO: - rtlqueue = TXDESC_QUEUE_VO; - break; - case IEEE80211_AC_VI: - rtlqueue = TXDESC_QUEUE_VI; - break; - case IEEE80211_AC_BE: - rtlqueue = TXDESC_QUEUE_BE; - break; - case IEEE80211_AC_BK: - rtlqueue = TXDESC_QUEUE_BK; - break; - default: - rtlqueue = TXDESC_QUEUE_BE; - } - - return rtlqueue; -} - -static u32 rtl8xxxu_queue_select(struct ieee80211_hdr *hdr, struct sk_buff *skb) -{ - u32 queue; - - if (unlikely(ieee80211_is_beacon(hdr->frame_control))) - queue = TXDESC_QUEUE_BEACON; - else if (ieee80211_is_mgmt(hdr->frame_control)) - queue = TXDESC_QUEUE_MGNT; - else - queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb)); - - return queue; -} - -/* - * Despite newer chips 8723b/8812/8821 having a larger TX descriptor - * format. The descriptor checksum is still only calculated over the - * initial 32 bytes of the descriptor! - */ -static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_txdesc32 *tx_desc) -{ - __le16 *ptr = (__le16 *)tx_desc; - u16 csum = 0; - int i; - - /* - * Clear csum field before calculation, as the csum field is - * in the middle of the struct. - */ - tx_desc->csum = cpu_to_le16(0); - - for (i = 0; i < (sizeof(struct rtl8xxxu_txdesc32) / sizeof(u16)); i++) - csum = csum ^ le16_to_cpu(ptr[i]); - - tx_desc->csum |= cpu_to_le16(csum); -} - -static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv *priv) -{ - struct rtl8xxxu_tx_urb *tx_urb, *tmp; - unsigned long flags; - - spin_lock_irqsave(&priv->tx_urb_lock, flags); - list_for_each_entry_safe(tx_urb, tmp, &priv->tx_urb_free_list, list) { - list_del(&tx_urb->list); - priv->tx_urb_free_count--; - usb_free_urb(&tx_urb->urb); - } - spin_unlock_irqrestore(&priv->tx_urb_lock, flags); -} - -static struct rtl8xxxu_tx_urb * -rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv *priv) -{ - struct rtl8xxxu_tx_urb *tx_urb; - unsigned long flags; - - spin_lock_irqsave(&priv->tx_urb_lock, flags); - tx_urb = list_first_entry_or_null(&priv->tx_urb_free_list, - struct rtl8xxxu_tx_urb, list); - if (tx_urb) { - list_del(&tx_urb->list); - priv->tx_urb_free_count--; - if (priv->tx_urb_free_count < RTL8XXXU_TX_URB_LOW_WATER && - !priv->tx_stopped) { - priv->tx_stopped = true; - ieee80211_stop_queues(priv->hw); - } - } - - spin_unlock_irqrestore(&priv->tx_urb_lock, flags); - - return tx_urb; -} - -static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv *priv, - struct rtl8xxxu_tx_urb *tx_urb) -{ - unsigned long flags; - - INIT_LIST_HEAD(&tx_urb->list); - - spin_lock_irqsave(&priv->tx_urb_lock, flags); - - list_add(&tx_urb->list, &priv->tx_urb_free_list); - priv->tx_urb_free_count++; - if (priv->tx_urb_free_count > RTL8XXXU_TX_URB_HIGH_WATER && - priv->tx_stopped) { - priv->tx_stopped = false; - ieee80211_wake_queues(priv->hw); - } - - spin_unlock_irqrestore(&priv->tx_urb_lock, flags); -} - -static void rtl8xxxu_tx_complete(struct urb *urb) -{ - struct sk_buff *skb = (struct sk_buff *)urb->context; - struct ieee80211_tx_info *tx_info; - struct ieee80211_hw *hw; - struct rtl8xxxu_priv *priv; - struct rtl8xxxu_tx_urb *tx_urb = - container_of(urb, struct rtl8xxxu_tx_urb, urb); - - tx_info = IEEE80211_SKB_CB(skb); - hw = tx_info->rate_driver_data[0]; - priv = hw->priv; - - skb_pull(skb, priv->fops->tx_desc_size); - - ieee80211_tx_info_clear_status(tx_info); - tx_info->status.rates[0].idx = -1; - tx_info->status.rates[0].count = 0; - - if (!urb->status) - tx_info->flags |= IEEE80211_TX_STAT_ACK; - - ieee80211_tx_status_irqsafe(hw, skb); - - rtl8xxxu_free_tx_urb(priv, tx_urb); -} - -static void rtl8xxxu_dump_action(struct device *dev, - struct ieee80211_hdr *hdr) -{ - struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr; - u16 cap, timeout; - - if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION)) - return; - - switch (mgmt->u.action.u.addba_resp.action_code) { - case WLAN_ACTION_ADDBA_RESP: - cap = le16_to_cpu(mgmt->u.action.u.addba_resp.capab); - timeout = le16_to_cpu(mgmt->u.action.u.addba_resp.timeout); - dev_info(dev, "WLAN_ACTION_ADDBA_RESP: " - "timeout %i, tid %02x, buf_size %02x, policy %02x, " - "status %02x\n", - timeout, - (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2, - (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6, - (cap >> 1) & 0x1, - le16_to_cpu(mgmt->u.action.u.addba_resp.status)); - break; - case WLAN_ACTION_ADDBA_REQ: - cap = le16_to_cpu(mgmt->u.action.u.addba_req.capab); - timeout = le16_to_cpu(mgmt->u.action.u.addba_req.timeout); - dev_info(dev, "WLAN_ACTION_ADDBA_REQ: " - "timeout %i, tid %02x, buf_size %02x, policy %02x\n", - timeout, - (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2, - (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6, - (cap >> 1) & 0x1); - break; - default: - dev_info(dev, "action frame %02x\n", - mgmt->u.action.u.addba_resp.action_code); - break; - } -} - -/* - * Fill in v1 (gen1) specific TX descriptor bits. - * This format is used on 8188cu/8192cu/8723au - */ -void -rtl8xxxu_fill_txdesc_v1(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, - struct ieee80211_tx_info *tx_info, - struct rtl8xxxu_txdesc32 *tx_desc, bool sgi, - bool short_preamble, bool ampdu_enable, u32 rts_rate, - u8 macid) -{ - struct rtl8xxxu_priv *priv = hw->priv; - struct device *dev = &priv->udev->dev; - u8 *qc = ieee80211_get_qos_ctl(hdr); - u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK; - u32 rate = 0; - u16 seq_number; - - if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX) - dev_info(dev, "%s: TX rate: %d, pkt size %u\n", - __func__, rate, le16_to_cpu(tx_desc->pkt_size)); - - seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); - - tx_desc->txdw5 = cpu_to_le32(rate); - - if (ieee80211_is_data(hdr->frame_control)) - tx_desc->txdw5 |= cpu_to_le32(0x0001ff00); - - tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC32_SEQ_SHIFT); - - if (ampdu_enable && test_bit(tid, priv->tid_tx_operational)) - tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_ENABLE); - else - tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_BREAK); - - if (ieee80211_is_mgmt(hdr->frame_control)) { - tx_desc->txdw5 = cpu_to_le32(rate); - tx_desc->txdw4 |= cpu_to_le32(TXDESC32_USE_DRIVER_RATE); - tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC32_RETRY_LIMIT_SHIFT); - tx_desc->txdw5 |= cpu_to_le32(TXDESC32_RETRY_LIMIT_ENABLE); - } - - if (ieee80211_is_data_qos(hdr->frame_control)) - tx_desc->txdw4 |= cpu_to_le32(TXDESC32_QOS); - - if (short_preamble) - tx_desc->txdw4 |= cpu_to_le32(TXDESC32_SHORT_PREAMBLE); - - if (sgi) - tx_desc->txdw5 |= cpu_to_le32(TXDESC32_SHORT_GI); - - /* - * rts_rate is zero if RTS/CTS or CTS to SELF are not enabled - */ - tx_desc->txdw4 |= cpu_to_le32(rts_rate << TXDESC32_RTS_RATE_SHIFT); - if (ampdu_enable || tx_info->control.use_rts) { - tx_desc->txdw4 |= cpu_to_le32(TXDESC32_RTS_CTS_ENABLE); - tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE); - } else if (tx_info->control.use_cts_prot) { - tx_desc->txdw4 |= cpu_to_le32(TXDESC32_CTS_SELF_ENABLE); - tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE); - } -} - -/* - * Fill in v2 (gen2) specific TX descriptor bits. - * This format is used on 8192eu/8723bu - */ -void -rtl8xxxu_fill_txdesc_v2(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, - struct ieee80211_tx_info *tx_info, - struct rtl8xxxu_txdesc32 *tx_desc32, bool sgi, - bool short_preamble, bool ampdu_enable, u32 rts_rate, - u8 macid) -{ - struct rtl8xxxu_priv *priv = hw->priv; - struct device *dev = &priv->udev->dev; - struct rtl8xxxu_txdesc40 *tx_desc40; - u8 *qc = ieee80211_get_qos_ctl(hdr); - u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK; - u32 rate = 0; - u16 seq_number; - - tx_desc40 = (struct rtl8xxxu_txdesc40 *)tx_desc32; - - if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX) - dev_info(dev, "%s: TX rate: %d, pkt size %u\n", - __func__, rate, le16_to_cpu(tx_desc40->pkt_size)); - - tx_desc40->txdw1 |= cpu_to_le32(macid << TXDESC40_MACID_SHIFT); - - seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); - - tx_desc40->txdw4 = cpu_to_le32(rate); - if (ieee80211_is_data(hdr->frame_control)) { - tx_desc40->txdw4 |= cpu_to_le32(0x1f << - TXDESC40_DATA_RATE_FB_SHIFT); - } - - tx_desc40->txdw9 = cpu_to_le32((u32)seq_number << TXDESC40_SEQ_SHIFT); - - if (ampdu_enable && test_bit(tid, priv->tid_tx_operational)) - tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_ENABLE); - else - tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_BREAK); - - if (ieee80211_is_mgmt(hdr->frame_control)) { - tx_desc40->txdw4 = cpu_to_le32(rate); - tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_USE_DRIVER_RATE); - tx_desc40->txdw4 |= - cpu_to_le32(6 << TXDESC40_RETRY_LIMIT_SHIFT); - tx_desc40->txdw4 |= cpu_to_le32(TXDESC40_RETRY_LIMIT_ENABLE); - } - - if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) - tx_desc40->txdw8 |= cpu_to_le32(TXDESC40_HW_SEQ_ENABLE); - - if (short_preamble) - tx_desc40->txdw5 |= cpu_to_le32(TXDESC40_SHORT_PREAMBLE); - - tx_desc40->txdw4 |= cpu_to_le32(rts_rate << TXDESC40_RTS_RATE_SHIFT); - - /* - * rts_rate is zero if RTS/CTS or CTS to SELF are not enabled - */ - if (ampdu_enable || tx_info->control.use_rts) { - tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_RTS_CTS_ENABLE); - tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_HW_RTS_ENABLE); - } else if (tx_info->control.use_cts_prot) { - /* - * For some reason the vendor driver doesn't set - * TXDESC40_HW_RTS_ENABLE for CTS to SELF - */ - tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_CTS_SELF_ENABLE); - } -} - -/* - * Fill in v3 (gen1) specific TX descriptor bits. - * This format is a hybrid between the v1 and v2 formats, only seen - * on 8188eu devices so far. - */ -void -rtl8xxxu_fill_txdesc_v3(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, - struct ieee80211_tx_info *tx_info, - struct rtl8xxxu_txdesc32 *tx_desc, bool sgi, - bool short_preamble, bool ampdu_enable, u32 rts_rate, - u8 macid) -{ - struct rtl8xxxu_priv *priv = hw->priv; - struct device *dev = &priv->udev->dev; - struct rtl8xxxu_ra_info *ra = &priv->ra_info; - u8 *qc = ieee80211_get_qos_ctl(hdr); - u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK; - u32 rate = 0; - u16 seq_number; - - seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); - - if (ieee80211_is_data(hdr->frame_control)) { - rate = ra->decision_rate; - tx_desc->txdw5 = cpu_to_le32(rate); - tx_desc->txdw4 |= cpu_to_le32(TXDESC32_USE_DRIVER_RATE); - tx_desc->txdw4 |= le32_encode_bits(ra->pt_stage, TXDESC32_PT_STAGE_MASK); - /* Data/RTS rate FB limit */ - tx_desc->txdw5 |= cpu_to_le32(0x0001ff00); - } - - if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX) - dev_info(dev, "%s: TX rate: %d, pkt size %d\n", - __func__, rate, le16_to_cpu(tx_desc->pkt_size)); - - tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC32_SEQ_SHIFT); - - if (ampdu_enable && test_bit(tid, priv->tid_tx_operational)) - tx_desc->txdw2 |= cpu_to_le32(TXDESC40_AGG_ENABLE); - else - tx_desc->txdw2 |= cpu_to_le32(TXDESC40_AGG_BREAK); - - if (ieee80211_is_mgmt(hdr->frame_control)) { - tx_desc->txdw5 = cpu_to_le32(rate); - tx_desc->txdw4 |= cpu_to_le32(TXDESC32_USE_DRIVER_RATE); - tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC32_RETRY_LIMIT_SHIFT); - tx_desc->txdw5 |= cpu_to_le32(TXDESC32_RETRY_LIMIT_ENABLE); - } - - if (ieee80211_is_data_qos(hdr->frame_control)) { - tx_desc->txdw4 |= cpu_to_le32(TXDESC32_QOS); - - if (conf_is_ht40(&hw->conf)) { - tx_desc->txdw4 |= cpu_to_le32(TXDESC_DATA_BW); - - if (conf_is_ht40_minus(&hw->conf)) - tx_desc->txdw4 |= cpu_to_le32(TXDESC_PRIME_CH_OFF_UPPER); - else - tx_desc->txdw4 |= cpu_to_le32(TXDESC_PRIME_CH_OFF_LOWER); - } - } - - if (short_preamble) - tx_desc->txdw4 |= cpu_to_le32(TXDESC32_SHORT_PREAMBLE); - - if (sgi && ra->rate_sgi) - tx_desc->txdw5 |= cpu_to_le32(TXDESC32_SHORT_GI); - - /* - * rts_rate is zero if RTS/CTS or CTS to SELF are not enabled - */ - tx_desc->txdw4 |= cpu_to_le32(rts_rate << TXDESC32_RTS_RATE_SHIFT); - if (ampdu_enable || tx_info->control.use_rts) { - tx_desc->txdw4 |= cpu_to_le32(TXDESC32_RTS_CTS_ENABLE); - tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE); - } else if (tx_info->control.use_cts_prot) { - tx_desc->txdw4 |= cpu_to_le32(TXDESC32_CTS_SELF_ENABLE); - tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE); - } - - tx_desc->txdw2 |= cpu_to_le32(TXDESC_ANTENNA_SELECT_A | - TXDESC_ANTENNA_SELECT_B); - tx_desc->txdw7 |= cpu_to_le16(TXDESC_ANTENNA_SELECT_C >> 16); -} - -static void rtl8xxxu_tx(struct ieee80211_hw *hw, - struct ieee80211_tx_control *control, - struct sk_buff *skb) -{ - struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; - struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); - struct rtl8xxxu_priv *priv = hw->priv; - struct rtl8xxxu_txdesc32 *tx_desc; - struct rtl8xxxu_tx_urb *tx_urb; - struct ieee80211_sta *sta = NULL; - struct ieee80211_vif *vif = tx_info->control.vif; - struct rtl8xxxu_vif *rtlvif = vif ? (struct rtl8xxxu_vif *)vif->drv_priv : NULL; - struct device *dev = &priv->udev->dev; - u32 queue, rts_rate; - u16 pktlen = skb->len; - int tx_desc_size = priv->fops->tx_desc_size; - u8 macid; - int ret; - bool ampdu_enable, sgi = false, short_preamble = false, bmc = false; - - if (skb_headroom(skb) < tx_desc_size) { - dev_warn(dev, - "%s: Not enough headroom (%i) for tx descriptor\n", - __func__, skb_headroom(skb)); - goto error; - } - - if (unlikely(skb->len > (65535 - tx_desc_size))) { - dev_warn(dev, "%s: Trying to send over-sized skb (%i)\n", - __func__, skb->len); - goto error; - } - - tx_urb = rtl8xxxu_alloc_tx_urb(priv); - if (!tx_urb) { - dev_warn(dev, "%s: Unable to allocate tx urb\n", __func__); - goto error; - } - - if (ieee80211_is_action(hdr->frame_control)) - rtl8xxxu_dump_action(dev, hdr); - - tx_info->rate_driver_data[0] = hw; - - if (control && control->sta) - sta = control->sta; - - queue = rtl8xxxu_queue_select(hdr, skb); - - tx_desc = skb_push(skb, tx_desc_size); - - memset(tx_desc, 0, tx_desc_size); - tx_desc->pkt_size = cpu_to_le16(pktlen); - tx_desc->pkt_offset = tx_desc_size; - - /* These bits mean different things to the RTL8192F. */ - if (priv->rtl_chip != RTL8192F) - tx_desc->txdw0 = - TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT; - if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) || - is_broadcast_ether_addr(ieee80211_get_DA(hdr))) { - tx_desc->txdw0 |= TXDESC_BROADMULTICAST; - bmc = true; - } - - - tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT); - macid = rtl8xxxu_get_macid(priv, sta); - - if (tx_info->control.hw_key) { - switch (tx_info->control.hw_key->cipher) { - case WLAN_CIPHER_SUITE_WEP40: - case WLAN_CIPHER_SUITE_WEP104: - case WLAN_CIPHER_SUITE_TKIP: - tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4); - break; - case WLAN_CIPHER_SUITE_CCMP: - tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES); - break; - default: - break; - } - if (bmc && rtlvif && rtlvif->hw_key_idx != 0xff) { - tx_desc->txdw1 |= cpu_to_le32(TXDESC_EN_DESC_ID); - macid = rtlvif->hw_key_idx; - } - } - - /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */ - ampdu_enable = false; - if (ieee80211_is_data_qos(hdr->frame_control) && sta) { - if (sta->deflink.ht_cap.ht_supported) { - u32 ampdu, val32; - u8 *qc = ieee80211_get_qos_ctl(hdr); - u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK; - - ampdu = (u32)sta->deflink.ht_cap.ampdu_density; - val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT; - tx_desc->txdw2 |= cpu_to_le32(val32); - - ampdu_enable = true; - - if (!test_bit(tid, priv->tx_aggr_started) && - !(skb->protocol == cpu_to_be16(ETH_P_PAE))) - if (!ieee80211_start_tx_ba_session(sta, tid, 0)) - set_bit(tid, priv->tx_aggr_started); - } - } - - if (ieee80211_is_data_qos(hdr->frame_control) && - sta && sta->deflink.ht_cap.cap & - (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20)) - sgi = true; - - if (sta && vif && vif->bss_conf.use_short_preamble) - short_preamble = true; - - if (skb->len > hw->wiphy->rts_threshold) - tx_info->control.use_rts = true; - - if (sta && vif && vif->bss_conf.use_cts_prot) - tx_info->control.use_cts_prot = true; - - if (ampdu_enable || tx_info->control.use_rts || - tx_info->control.use_cts_prot) - rts_rate = DESC_RATE_24M; - else - rts_rate = 0; - - priv->fops->fill_txdesc(hw, hdr, tx_info, tx_desc, sgi, short_preamble, - ampdu_enable, rts_rate, macid); - - rtl8xxxu_calc_tx_desc_csum(tx_desc); - - /* avoid zero checksum make tx hang */ - if (priv->rtl_chip == RTL8710B || priv->rtl_chip == RTL8192F) - tx_desc->csum = ~tx_desc->csum; - - usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue], - skb->data, skb->len, rtl8xxxu_tx_complete, skb); - - usb_anchor_urb(&tx_urb->urb, &priv->tx_anchor); - ret = usb_submit_urb(&tx_urb->urb, GFP_ATOMIC); - if (ret) { - usb_unanchor_urb(&tx_urb->urb); - rtl8xxxu_free_tx_urb(priv, tx_urb); - goto error; - } - return; -error: - dev_kfree_skb(skb); -} - -static void rtl8xxxu_send_beacon_frame(struct ieee80211_hw *hw, - struct ieee80211_vif *vif) -{ - struct rtl8xxxu_priv *priv = hw->priv; - struct sk_buff *skb = ieee80211_beacon_get(hw, vif, 0); - struct device *dev = &priv->udev->dev; - int retry; - u8 val8; - - /* BCN_VALID, write 1 to clear, cleared by SW */ - val8 = rtl8xxxu_read8(priv, REG_TDECTRL + 2); - val8 |= BIT_BCN_VALID >> 16; - rtl8xxxu_write8(priv, REG_TDECTRL + 2, val8); - - /* SW_BCN_SEL - Port0 */ - val8 = rtl8xxxu_read8(priv, REG_DWBCN1_CTRL_8723B + 2); - val8 &= ~(BIT_SW_BCN_SEL >> 16); - rtl8xxxu_write8(priv, REG_DWBCN1_CTRL_8723B + 2, val8); - - if (skb) - rtl8xxxu_tx(hw, NULL, skb); - - retry = 100; - do { - val8 = rtl8xxxu_read8(priv, REG_TDECTRL + 2); - if (val8 & (BIT_BCN_VALID >> 16)) - break; - usleep_range(10, 20); - } while (--retry); - - if (!retry) - dev_err(dev, "%s: Failed to read beacon valid bit\n", __func__); -} - -static void rtl8xxxu_update_beacon_work_callback(struct work_struct *work) -{ - struct rtl8xxxu_priv *priv = - container_of(work, struct rtl8xxxu_priv, update_beacon_work.work); - struct ieee80211_hw *hw = priv->hw; - struct ieee80211_vif *vif = priv->vifs[0]; - - if (!vif) { - WARN_ONCE(true, "no vif to update beacon\n"); - return; - } - - if (vif->bss_conf.csa_active) { - if (ieee80211_beacon_cntdwn_is_complete(vif, 0)) { - ieee80211_csa_finish(vif, 0); - return; - } - schedule_delayed_work(&priv->update_beacon_work, - msecs_to_jiffies(vif->bss_conf.beacon_int)); - } - rtl8xxxu_send_beacon_frame(hw, vif); -} - -static inline bool rtl8xxxu_is_packet_match_bssid(struct rtl8xxxu_priv *priv, - struct ieee80211_hdr *hdr, - int port_num) -{ - return priv->vifs[port_num] && - priv->vifs[port_num]->type == NL80211_IFTYPE_STATION && - priv->vifs[port_num]->cfg.assoc && - ether_addr_equal(priv->vifs[port_num]->bss_conf.bssid, hdr->addr2); -} - -static inline bool rtl8xxxu_is_sta_sta(struct rtl8xxxu_priv *priv) -{ - return (priv->vifs[0] && priv->vifs[0]->cfg.assoc && - priv->vifs[0]->type == NL80211_IFTYPE_STATION) && - (priv->vifs[1] && priv->vifs[1]->cfg.assoc && - priv->vifs[1]->type == NL80211_IFTYPE_STATION); -} - -void rtl8723au_rx_parse_phystats(struct rtl8xxxu_priv *priv, - struct ieee80211_rx_status *rx_status, - struct rtl8723au_phy_stats *phy_stats, - u32 rxmcs, struct ieee80211_hdr *hdr, - bool crc_icv_err) -{ - if (phy_stats->sgi_en) - rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; - - if (rxmcs < DESC_RATE_6M) { - /* - * Handle PHY stats for CCK rates - */ - rx_status->signal = priv->fops->cck_rssi(priv, phy_stats); - } else { - bool parse_cfo = priv->fops->set_crystal_cap && - !crc_icv_err && - !ieee80211_is_ctl(hdr->frame_control) && - !rtl8xxxu_is_sta_sta(priv) && - (rtl8xxxu_is_packet_match_bssid(priv, hdr, 0) || - rtl8xxxu_is_packet_match_bssid(priv, hdr, 1)); - - if (parse_cfo) { - priv->cfo_tracking.cfo_tail[0] = phy_stats->path_cfotail[0]; - priv->cfo_tracking.cfo_tail[1] = phy_stats->path_cfotail[1]; - - priv->cfo_tracking.packet_count++; - } - - rx_status->signal = - (phy_stats->cck_sig_qual_ofdm_pwdb_all >> 1) - 110; - } -} - -static void jaguar2_rx_parse_phystats_type0(struct rtl8xxxu_priv *priv, - struct ieee80211_rx_status *rx_status, - struct jaguar2_phy_stats_type0 *phy_stats0, - u32 rxmcs, struct ieee80211_hdr *hdr, - bool crc_icv_err) -{ - s8 rx_power = phy_stats0->pwdb - 110; - - if (!priv->cck_new_agc) - rx_power = priv->fops->cck_rssi(priv, (struct rtl8723au_phy_stats *)phy_stats0); - - rx_status->signal = rx_power; -} - -static void jaguar2_rx_parse_phystats_type1(struct rtl8xxxu_priv *priv, - struct ieee80211_rx_status *rx_status, - struct jaguar2_phy_stats_type1 *phy_stats1, - u32 rxmcs, struct ieee80211_hdr *hdr, - bool crc_icv_err) -{ - bool parse_cfo = priv->fops->set_crystal_cap && - !crc_icv_err && - !ieee80211_is_ctl(hdr->frame_control) && - !rtl8xxxu_is_sta_sta(priv) && - (rtl8xxxu_is_packet_match_bssid(priv, hdr, 0) || - rtl8xxxu_is_packet_match_bssid(priv, hdr, 1)); - u8 pwdb_max = 0; - int rx_path; - - if (parse_cfo) { - /* Only path-A and path-B have CFO tail and short CFO */ - priv->cfo_tracking.cfo_tail[RF_A] = phy_stats1->cfo_tail[RF_A]; - priv->cfo_tracking.cfo_tail[RF_B] = phy_stats1->cfo_tail[RF_B]; - - priv->cfo_tracking.packet_count++; - } - - for (rx_path = 0; rx_path < priv->rx_paths; rx_path++) - pwdb_max = max(pwdb_max, phy_stats1->pwdb[rx_path]); - - rx_status->signal = pwdb_max - 110; -} - -static void jaguar2_rx_parse_phystats_type2(struct rtl8xxxu_priv *priv, - struct ieee80211_rx_status *rx_status, - struct jaguar2_phy_stats_type2 *phy_stats2, - u32 rxmcs, struct ieee80211_hdr *hdr, - bool crc_icv_err) -{ - u8 pwdb_max = 0; - int rx_path; - - for (rx_path = 0; rx_path < priv->rx_paths; rx_path++) - pwdb_max = max(pwdb_max, phy_stats2->pwdb[rx_path]); - - rx_status->signal = pwdb_max - 110; -} - -void jaguar2_rx_parse_phystats(struct rtl8xxxu_priv *priv, - struct ieee80211_rx_status *rx_status, - struct rtl8723au_phy_stats *phy_stats, - u32 rxmcs, struct ieee80211_hdr *hdr, - bool crc_icv_err) -{ - struct jaguar2_phy_stats_type0 *phy_stats0 = (struct jaguar2_phy_stats_type0 *)phy_stats; - struct jaguar2_phy_stats_type1 *phy_stats1 = (struct jaguar2_phy_stats_type1 *)phy_stats; - struct jaguar2_phy_stats_type2 *phy_stats2 = (struct jaguar2_phy_stats_type2 *)phy_stats; - - switch (phy_stats0->page_num) { - case 0: - /* CCK */ - jaguar2_rx_parse_phystats_type0(priv, rx_status, phy_stats0, - rxmcs, hdr, crc_icv_err); - break; - case 1: - /* OFDM */ - jaguar2_rx_parse_phystats_type1(priv, rx_status, phy_stats1, - rxmcs, hdr, crc_icv_err); - break; - case 2: - /* Also OFDM but different (how?) */ - jaguar2_rx_parse_phystats_type2(priv, rx_status, phy_stats2, - rxmcs, hdr, crc_icv_err); - break; - default: - return; - } -} - -static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv *priv) -{ - struct rtl8xxxu_rx_urb *rx_urb, *tmp; - unsigned long flags; - - spin_lock_irqsave(&priv->rx_urb_lock, flags); - - list_for_each_entry_safe(rx_urb, tmp, - &priv->rx_urb_pending_list, list) { - list_del(&rx_urb->list); - priv->rx_urb_pending_count--; - usb_free_urb(&rx_urb->urb); - } - - spin_unlock_irqrestore(&priv->rx_urb_lock, flags); -} - -static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv, - struct rtl8xxxu_rx_urb *rx_urb) -{ - struct sk_buff *skb; - unsigned long flags; - int pending = 0; - - spin_lock_irqsave(&priv->rx_urb_lock, flags); - - if (!priv->shutdown) { - list_add_tail(&rx_urb->list, &priv->rx_urb_pending_list); - priv->rx_urb_pending_count++; - pending = priv->rx_urb_pending_count; - } else { - skb = (struct sk_buff *)rx_urb->urb.context; - dev_kfree_skb_irq(skb); - usb_free_urb(&rx_urb->urb); - } - - spin_unlock_irqrestore(&priv->rx_urb_lock, flags); - - if (pending > RTL8XXXU_RX_URB_PENDING_WATER) - schedule_work(&priv->rx_urb_wq); -} - -static void rtl8xxxu_rx_urb_work(struct work_struct *work) -{ - struct rtl8xxxu_priv *priv; - struct rtl8xxxu_rx_urb *rx_urb, *tmp; - struct list_head local; - struct sk_buff *skb; - unsigned long flags; - int ret; - - priv = container_of(work, struct rtl8xxxu_priv, rx_urb_wq); - INIT_LIST_HEAD(&local); - - spin_lock_irqsave(&priv->rx_urb_lock, flags); - - list_splice_init(&priv->rx_urb_pending_list, &local); - priv->rx_urb_pending_count = 0; - - spin_unlock_irqrestore(&priv->rx_urb_lock, flags); - - list_for_each_entry_safe(rx_urb, tmp, &local, list) { - list_del_init(&rx_urb->list); - ret = rtl8xxxu_submit_rx_urb(priv, rx_urb); - /* - * If out of memory or temporary error, put it back on the - * queue and try again. Otherwise the device is dead/gone - * and we should drop it. - */ - switch (ret) { - case 0: - break; - case -ENOMEM: - case -EAGAIN: - rtl8xxxu_queue_rx_urb(priv, rx_urb); - break; - default: - dev_warn(&priv->udev->dev, - "failed to requeue urb with error %i\n", ret); - skb = (struct sk_buff *)rx_urb->urb.context; - dev_kfree_skb(skb); - usb_free_urb(&rx_urb->urb); - } - } -} - -/* - * The RTL8723BU/RTL8192EU vendor driver use coexistence table type - * 0-7 to represent writing different combinations of register values - * to REG_BT_COEX_TABLEs. It's for different kinds of coexistence use - * cases which Realtek doesn't provide detail for these settings. Keep - * this aligned with vendor driver for easier maintenance. - */ -static -void rtl8723bu_set_coex_with_type(struct rtl8xxxu_priv *priv, u8 type) -{ - switch (type) { - case 0: - rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555); - rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x55555555); - rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); - rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); - break; - case 1: - case 3: - rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555); - rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x5a5a5a5a); - rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); - rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); - break; - case 2: - rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x5a5a5a5a); - rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x5a5a5a5a); - rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); - rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); - break; - case 4: - rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x5a5a5a5a); - rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaaaa5a5a); - rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); - rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); - break; - case 5: - rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x5a5a5a5a); - rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaa5a5a5a); - rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); - rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); - break; - case 6: - rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555); - rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaaaaaaaa); - rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); - rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); - break; - case 7: - rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0xaaaaaaaa); - rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaaaaaaaa); - rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); - rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); - break; - default: - break; - } -} - -static -void rtl8723bu_update_bt_link_info(struct rtl8xxxu_priv *priv, u8 bt_info) -{ - struct rtl8xxxu_btcoex *btcoex = &priv->bt_coex; - - if (bt_info & BT_INFO_8723B_1ANT_B_INQ_PAGE) - btcoex->c2h_bt_inquiry = true; - else - btcoex->c2h_bt_inquiry = false; - - if (!(bt_info & BT_INFO_8723B_1ANT_B_CONNECTION)) { - btcoex->bt_status = BT_8723B_1ANT_STATUS_NON_CONNECTED_IDLE; - btcoex->has_sco = false; - btcoex->has_hid = false; - btcoex->has_pan = false; - btcoex->has_a2dp = false; - } else { - if ((bt_info & 0x1f) == BT_INFO_8723B_1ANT_B_CONNECTION) - btcoex->bt_status = BT_8723B_1ANT_STATUS_CONNECTED_IDLE; - else if ((bt_info & BT_INFO_8723B_1ANT_B_SCO_ESCO) || - (bt_info & BT_INFO_8723B_1ANT_B_SCO_BUSY)) - btcoex->bt_status = BT_8723B_1ANT_STATUS_SCO_BUSY; - else if (bt_info & BT_INFO_8723B_1ANT_B_ACL_BUSY) - btcoex->bt_status = BT_8723B_1ANT_STATUS_ACL_BUSY; - else - btcoex->bt_status = BT_8723B_1ANT_STATUS_MAX; - - if (bt_info & BT_INFO_8723B_1ANT_B_FTP) - btcoex->has_pan = true; - else - btcoex->has_pan = false; - - if (bt_info & BT_INFO_8723B_1ANT_B_A2DP) - btcoex->has_a2dp = true; - else - btcoex->has_a2dp = false; - - if (bt_info & BT_INFO_8723B_1ANT_B_HID) - btcoex->has_hid = true; - else - btcoex->has_hid = false; - - if (bt_info & BT_INFO_8723B_1ANT_B_SCO_ESCO) - btcoex->has_sco = true; - else - btcoex->has_sco = false; - } - - if (!btcoex->has_a2dp && !btcoex->has_sco && - !btcoex->has_pan && btcoex->has_hid) - btcoex->hid_only = true; - else - btcoex->hid_only = false; - - if (!btcoex->has_sco && !btcoex->has_pan && - !btcoex->has_hid && btcoex->has_a2dp) - btcoex->has_a2dp = true; - else - btcoex->has_a2dp = false; - - if (btcoex->bt_status == BT_8723B_1ANT_STATUS_SCO_BUSY || - btcoex->bt_status == BT_8723B_1ANT_STATUS_ACL_BUSY) - btcoex->bt_busy = true; - else - btcoex->bt_busy = false; -} - -static inline bool rtl8xxxu_is_assoc(struct rtl8xxxu_priv *priv) -{ - return (priv->vifs[0] && priv->vifs[0]->cfg.assoc) || - (priv->vifs[1] && priv->vifs[1]->cfg.assoc); -} - -static -void rtl8723bu_handle_bt_inquiry(struct rtl8xxxu_priv *priv) -{ - struct rtl8xxxu_btcoex *btcoex; - - btcoex = &priv->bt_coex; - - if (!rtl8xxxu_is_assoc(priv)) { - rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0); - rtl8723bu_set_coex_with_type(priv, 0); - } else if (btcoex->has_sco || btcoex->has_hid || btcoex->has_a2dp) { - rtl8723bu_set_ps_tdma(priv, 0x61, 0x35, 0x3, 0x11, 0x11); - rtl8723bu_set_coex_with_type(priv, 4); - } else if (btcoex->has_pan) { - rtl8723bu_set_ps_tdma(priv, 0x61, 0x3f, 0x3, 0x11, 0x11); - rtl8723bu_set_coex_with_type(priv, 4); - } else { - rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0); - rtl8723bu_set_coex_with_type(priv, 7); - } -} - -static -void rtl8723bu_handle_bt_info(struct rtl8xxxu_priv *priv) -{ - struct rtl8xxxu_btcoex *btcoex; - - btcoex = &priv->bt_coex; - - if (rtl8xxxu_is_assoc(priv)) { - u32 val32 = 0; - u32 high_prio_tx = 0, high_prio_rx = 0; - - val32 = rtl8xxxu_read32(priv, 0x770); - high_prio_tx = val32 & 0x0000ffff; - high_prio_rx = (val32 & 0xffff0000) >> 16; - - if (btcoex->bt_busy) { - if (btcoex->hid_only) { - rtl8723bu_set_ps_tdma(priv, 0x61, 0x20, - 0x3, 0x11, 0x11); - rtl8723bu_set_coex_with_type(priv, 5); - } else if (btcoex->a2dp_only) { - rtl8723bu_set_ps_tdma(priv, 0x61, 0x35, - 0x3, 0x11, 0x11); - rtl8723bu_set_coex_with_type(priv, 4); - } else if ((btcoex->has_a2dp && btcoex->has_pan) || - (btcoex->has_hid && btcoex->has_a2dp && - btcoex->has_pan)) { - rtl8723bu_set_ps_tdma(priv, 0x51, 0x21, - 0x3, 0x10, 0x10); - rtl8723bu_set_coex_with_type(priv, 4); - } else if (btcoex->has_hid && btcoex->has_a2dp) { - rtl8723bu_set_ps_tdma(priv, 0x51, 0x21, - 0x3, 0x10, 0x10); - rtl8723bu_set_coex_with_type(priv, 3); - } else { - rtl8723bu_set_ps_tdma(priv, 0x61, 0x35, - 0x3, 0x11, 0x11); - rtl8723bu_set_coex_with_type(priv, 4); - } - } else { - rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0); - if (high_prio_tx + high_prio_rx <= 60) - rtl8723bu_set_coex_with_type(priv, 2); - else - rtl8723bu_set_coex_with_type(priv, 7); - } - } else { - rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0); - rtl8723bu_set_coex_with_type(priv, 0); - } -} - -static void rtl8xxxu_c2hcmd_callback(struct work_struct *work) -{ - struct rtl8xxxu_priv *priv; - struct rtl8723bu_c2h *c2h; - struct sk_buff *skb = NULL; - u8 bt_info = 0; - struct rtl8xxxu_btcoex *btcoex; - struct rtl8xxxu_ra_report *rarpt; - u8 bw; - - priv = container_of(work, struct rtl8xxxu_priv, c2hcmd_work); - btcoex = &priv->bt_coex; - rarpt = &priv->ra_report; - - while (!skb_queue_empty(&priv->c2hcmd_queue)) { - skb = skb_dequeue(&priv->c2hcmd_queue); - - c2h = (struct rtl8723bu_c2h *)skb->data; - - switch (c2h->id) { - case C2H_8723B_BT_INFO: - bt_info = c2h->bt_info.bt_info; - - rtl8723bu_update_bt_link_info(priv, bt_info); - if (btcoex->c2h_bt_inquiry) { - rtl8723bu_handle_bt_inquiry(priv); - break; - } - rtl8723bu_handle_bt_info(priv); - break; - case C2H_8723B_RA_REPORT: - bw = rarpt->txrate.bw; - - if (skb->len >= offsetofend(typeof(*c2h), ra_report.bw)) { - if (c2h->ra_report.bw == RTL8XXXU_CHANNEL_WIDTH_40) - bw = RATE_INFO_BW_40; - else - bw = RATE_INFO_BW_20; - } - - rtl8xxxu_update_ra_report(rarpt, c2h->ra_report.rate, - c2h->ra_report.sgi, bw); - break; - default: - break; - } - - dev_kfree_skb(skb); - } -} - -static void rtl8723bu_handle_c2h(struct rtl8xxxu_priv *priv, - struct sk_buff *skb) -{ - struct rtl8723bu_c2h *c2h = (struct rtl8723bu_c2h *)skb->data; - struct device *dev = &priv->udev->dev; - int len; - - len = skb->len - 2; - - dev_dbg(dev, "C2H ID %02x seq %02x, len %02x source %02x\n", - c2h->id, c2h->seq, len, c2h->bt_info.response_source); - - switch(c2h->id) { - case C2H_8723B_BT_INFO: - if (c2h->bt_info.response_source > - BT_INFO_SRC_8723B_BT_ACTIVE_SEND) - dev_dbg(dev, "C2H_BT_INFO WiFi only firmware\n"); - else - dev_dbg(dev, "C2H_BT_INFO BT/WiFi coexist firmware\n"); - - if (c2h->bt_info.bt_has_reset) - dev_dbg(dev, "BT has been reset\n"); - if (c2h->bt_info.tx_rx_mask) - dev_dbg(dev, "BT TRx mask\n"); - - break; - case C2H_8723B_BT_MP_INFO: - dev_dbg(dev, "C2H_MP_INFO ext ID %02x, status %02x\n", - c2h->bt_mp_info.ext_id, c2h->bt_mp_info.status); - break; - case C2H_8723B_RA_REPORT: - dev_dbg(dev, - "C2H RA RPT: rate %02x, unk %i, macid %02x, noise %i\n", - c2h->ra_report.rate, c2h->ra_report.sgi, - c2h->ra_report.macid, c2h->ra_report.noisy_state); - break; - default: - dev_info(dev, "Unhandled C2H event %02x seq %02x\n", - c2h->id, c2h->seq); - print_hex_dump(KERN_INFO, "C2H content: ", DUMP_PREFIX_NONE, - 16, 1, c2h->raw.payload, len, false); - break; - } - - skb_queue_tail(&priv->c2hcmd_queue, skb); - - schedule_work(&priv->c2hcmd_work); -} - -static void rtl8188e_c2hcmd_callback(struct work_struct *work) -{ - struct rtl8xxxu_priv *priv = container_of(work, struct rtl8xxxu_priv, c2hcmd_work); - struct device *dev = &priv->udev->dev; - struct sk_buff *skb = NULL; - struct rtl8xxxu_rxdesc16 *rx_desc; - - while (!skb_queue_empty(&priv->c2hcmd_queue)) { - skb = skb_dequeue(&priv->c2hcmd_queue); - - rx_desc = (struct rtl8xxxu_rxdesc16 *)(skb->data - sizeof(struct rtl8xxxu_rxdesc16)); - - switch (rx_desc->rpt_sel) { - case 1: - dev_dbg(dev, "C2H TX report type 1\n"); - - break; - case 2: - dev_dbg(dev, "C2H TX report type 2\n"); - - rtl8188e_handle_ra_tx_report2(priv, skb); - - break; - case 3: - dev_dbg(dev, "C2H USB interrupt report\n"); - - break; - default: - dev_warn(dev, "%s: rpt_sel should not be %d\n", - __func__, rx_desc->rpt_sel); - - break; - } - - dev_kfree_skb(skb); - } -} - -#define rtl8xxxu_iterate_vifs_atomic(priv, iterator, data) \ - ieee80211_iterate_active_interfaces_atomic((priv)->hw, \ - IEEE80211_IFACE_ITER_NORMAL, iterator, data) - -struct rtl8xxxu_rx_update_rssi_data { - struct rtl8xxxu_priv *priv; - struct ieee80211_hdr *hdr; - struct ieee80211_rx_status *rx_status; - u8 *bssid; -}; - -static void rtl8xxxu_rx_update_rssi_iter(void *data, u8 *mac, - struct ieee80211_vif *vif) -{ - struct rtl8xxxu_rx_update_rssi_data *iter_data = data; - struct ieee80211_sta *sta; - struct ieee80211_hdr *hdr = iter_data->hdr; - struct rtl8xxxu_priv *priv = iter_data->priv; - struct rtl8xxxu_sta_info *sta_info; - struct ieee80211_rx_status *rx_status = iter_data->rx_status; - u8 *bssid = iter_data->bssid; - - if (!ether_addr_equal(vif->bss_conf.bssid, bssid)) - return; - - if (!(ether_addr_equal(vif->addr, hdr->addr1) || - ieee80211_is_beacon(hdr->frame_control))) - return; - - sta = ieee80211_find_sta_by_ifaddr(priv->hw, hdr->addr2, - vif->addr); - if (!sta) - return; - - sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv; - ewma_rssi_add(&sta_info->avg_rssi, -rx_status->signal); -} - -static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr) -{ - __le16 fc = hdr->frame_control; - u8 *bssid; - - if (ieee80211_has_tods(fc)) - bssid = hdr->addr1; - else if (ieee80211_has_fromds(fc)) - bssid = hdr->addr2; - else - bssid = hdr->addr3; - - return bssid; -} - -static void rtl8xxxu_rx_update_rssi(struct rtl8xxxu_priv *priv, - struct ieee80211_rx_status *rx_status, - struct ieee80211_hdr *hdr) -{ - struct rtl8xxxu_rx_update_rssi_data data = {}; - - if (ieee80211_is_ctl(hdr->frame_control)) - return; - - data.priv = priv; - data.hdr = hdr; - data.rx_status = rx_status; - data.bssid = get_hdr_bssid(hdr); - - rtl8xxxu_iterate_vifs_atomic(priv, rtl8xxxu_rx_update_rssi_iter, &data); -} - -int rtl8xxxu_parse_rxdesc16(struct rtl8xxxu_priv *priv, struct sk_buff *skb) -{ - struct ieee80211_hw *hw = priv->hw; - struct ieee80211_rx_status *rx_status; - struct rtl8xxxu_rxdesc16 *rx_desc; - struct rtl8723au_phy_stats *phy_stats; - struct sk_buff *next_skb = NULL; - __le32 *_rx_desc_le; - u32 *_rx_desc; - int drvinfo_sz, desc_shift; - int i, pkt_cnt, pkt_len, urb_len, pkt_offset; - - urb_len = skb->len; - pkt_cnt = 0; - - if (urb_len < sizeof(struct rtl8xxxu_rxdesc16)) { - kfree_skb(skb); - return RX_TYPE_ERROR; - } - - do { - rx_desc = (struct rtl8xxxu_rxdesc16 *)skb->data; - _rx_desc_le = (__le32 *)skb->data; - _rx_desc = (u32 *)skb->data; - - for (i = 0; - i < (sizeof(struct rtl8xxxu_rxdesc16) / sizeof(u32)); i++) - _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]); - - /* - * Only read pkt_cnt from the header if we're parsing the - * first packet - */ - if (!pkt_cnt) - pkt_cnt = rx_desc->pkt_cnt; - pkt_len = rx_desc->pktlen; - - drvinfo_sz = rx_desc->drvinfo_sz * 8; - desc_shift = rx_desc->shift; - pkt_offset = roundup(pkt_len + drvinfo_sz + desc_shift + - sizeof(struct rtl8xxxu_rxdesc16), 128); - - /* - * Only clone the skb if there's enough data at the end to - * at least cover the rx descriptor - */ - if (pkt_cnt > 1 && - urb_len >= (pkt_offset + sizeof(struct rtl8xxxu_rxdesc16))) - next_skb = skb_clone(skb, GFP_ATOMIC); - - rx_status = IEEE80211_SKB_RXCB(skb); - memset(rx_status, 0, sizeof(struct ieee80211_rx_status)); - - skb_pull(skb, sizeof(struct rtl8xxxu_rxdesc16)); - - if (rx_desc->rpt_sel) { - skb_queue_tail(&priv->c2hcmd_queue, skb); - schedule_work(&priv->c2hcmd_work); - } else { - struct ieee80211_hdr *hdr; - - phy_stats = (struct rtl8723au_phy_stats *)skb->data; - - skb_pull(skb, drvinfo_sz + desc_shift); - - skb_trim(skb, pkt_len); - - hdr = (struct ieee80211_hdr *)skb->data; - if (rx_desc->phy_stats) { - priv->fops->parse_phystats( - priv, rx_status, phy_stats, - rx_desc->rxmcs, - hdr, - rx_desc->crc32 || rx_desc->icverr); - if (!rx_desc->crc32 && !rx_desc->icverr) - rtl8xxxu_rx_update_rssi(priv, - rx_status, - hdr); - } - - rx_status->mactime = rx_desc->tsfl; - rx_status->flag |= RX_FLAG_MACTIME_START; - - if (!rx_desc->swdec && - rx_desc->security != RX_DESC_ENC_NONE) - rx_status->flag |= RX_FLAG_DECRYPTED; - if (rx_desc->crc32) - rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; - if (rx_desc->bw) - rx_status->bw = RATE_INFO_BW_40; - - if (rx_desc->rxht) { - rx_status->encoding = RX_ENC_HT; - rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0; - } else { - rx_status->rate_idx = rx_desc->rxmcs; - } - - rx_status->freq = hw->conf.chandef.chan->center_freq; - rx_status->band = hw->conf.chandef.chan->band; - - ieee80211_rx_irqsafe(hw, skb); - } - - skb = next_skb; - if (skb) - skb_pull(next_skb, pkt_offset); - - pkt_cnt--; - urb_len -= pkt_offset; - next_skb = NULL; - } while (skb && pkt_cnt > 0 && - urb_len >= sizeof(struct rtl8xxxu_rxdesc16)); - - return RX_TYPE_DATA_PKT; -} - -int rtl8xxxu_parse_rxdesc24(struct rtl8xxxu_priv *priv, struct sk_buff *skb) -{ - struct ieee80211_hw *hw = priv->hw; - struct ieee80211_rx_status *rx_status; - struct rtl8xxxu_rxdesc24 *rx_desc; - struct rtl8723au_phy_stats *phy_stats; - struct sk_buff *next_skb = NULL; - __le32 *_rx_desc_le; - u32 *_rx_desc; - int drvinfo_sz, desc_shift; - int i, pkt_len, urb_len, pkt_offset; - - urb_len = skb->len; - - if (urb_len < sizeof(struct rtl8xxxu_rxdesc24)) { - kfree_skb(skb); - return RX_TYPE_ERROR; - } - - do { - rx_desc = (struct rtl8xxxu_rxdesc24 *)skb->data; - _rx_desc_le = (__le32 *)skb->data; - _rx_desc = (u32 *)skb->data; - - for (i = 0; i < (sizeof(struct rtl8xxxu_rxdesc24) / sizeof(u32)); i++) - _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]); - - pkt_len = rx_desc->pktlen; - - drvinfo_sz = rx_desc->drvinfo_sz * 8; - desc_shift = rx_desc->shift; - pkt_offset = roundup(pkt_len + drvinfo_sz + desc_shift + - sizeof(struct rtl8xxxu_rxdesc24), 8); - - /* - * Only clone the skb if there's enough data at the end to - * at least cover the rx descriptor - */ - if (urb_len >= (pkt_offset + sizeof(struct rtl8xxxu_rxdesc24))) - next_skb = skb_clone(skb, GFP_ATOMIC); - - rx_status = IEEE80211_SKB_RXCB(skb); - memset(rx_status, 0, sizeof(struct ieee80211_rx_status)); - - skb_pull(skb, sizeof(struct rtl8xxxu_rxdesc24)); - - phy_stats = (struct rtl8723au_phy_stats *)skb->data; - - skb_pull(skb, drvinfo_sz + desc_shift); - - skb_trim(skb, pkt_len); - - if (rx_desc->rpt_sel) { - struct device *dev = &priv->udev->dev; - dev_dbg(dev, "%s: C2H packet\n", __func__); - rtl8723bu_handle_c2h(priv, skb); - } else { - struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; - - if (rx_desc->phy_stats) { - priv->fops->parse_phystats(priv, rx_status, phy_stats, - rx_desc->rxmcs, hdr, - rx_desc->crc32 || rx_desc->icverr); - if (!rx_desc->crc32 && !rx_desc->icverr) - rtl8xxxu_rx_update_rssi(priv, - rx_status, - hdr); - } - - rx_status->mactime = rx_desc->tsfl; - rx_status->flag |= RX_FLAG_MACTIME_START; - - if (!rx_desc->swdec && - rx_desc->security != RX_DESC_ENC_NONE) - rx_status->flag |= RX_FLAG_DECRYPTED; - if (rx_desc->crc32) - rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; - if (rx_desc->bw) - rx_status->bw = RATE_INFO_BW_40; - - if (rx_desc->rxmcs >= DESC_RATE_MCS0) { - rx_status->encoding = RX_ENC_HT; - rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0; - } else { - rx_status->rate_idx = rx_desc->rxmcs; - } - - rx_status->freq = hw->conf.chandef.chan->center_freq; - rx_status->band = hw->conf.chandef.chan->band; - - ieee80211_rx_irqsafe(hw, skb); - } - - skb = next_skb; - if (skb) - skb_pull(next_skb, pkt_offset); - - urb_len -= pkt_offset; - next_skb = NULL; - } while (skb && urb_len >= sizeof(struct rtl8xxxu_rxdesc24)); - - return RX_TYPE_DATA_PKT; -} - -static void rtl8xxxu_rx_complete(struct urb *urb) -{ - struct rtl8xxxu_rx_urb *rx_urb = - container_of(urb, struct rtl8xxxu_rx_urb, urb); - struct ieee80211_hw *hw = rx_urb->hw; - struct rtl8xxxu_priv *priv = hw->priv; - struct sk_buff *skb = (struct sk_buff *)urb->context; - struct device *dev = &priv->udev->dev; - - skb_put(skb, urb->actual_length); - - if (urb->status == 0) { - priv->fops->parse_rx_desc(priv, skb); - - skb = NULL; - rx_urb->urb.context = NULL; - rtl8xxxu_queue_rx_urb(priv, rx_urb); - } else { - dev_dbg(dev, "%s: status %i\n", __func__, urb->status); - goto cleanup; - } - return; - -cleanup: - usb_free_urb(urb); - dev_kfree_skb(skb); -} - -static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv, - struct rtl8xxxu_rx_urb *rx_urb) -{ - struct rtl8xxxu_fileops *fops = priv->fops; - struct sk_buff *skb; - int skb_size; - int ret, rx_desc_sz; - - rx_desc_sz = fops->rx_desc_size; - - if (priv->rx_buf_aggregation && fops->rx_agg_buf_size) { - skb_size = fops->rx_agg_buf_size; - skb_size += (rx_desc_sz + sizeof(struct rtl8723au_phy_stats)); - } else { - skb_size = IEEE80211_MAX_FRAME_LEN; - } - - skb = __netdev_alloc_skb(NULL, skb_size, GFP_KERNEL); - if (!skb) - return -ENOMEM; - - memset(skb->data, 0, rx_desc_sz); - usb_fill_bulk_urb(&rx_urb->urb, priv->udev, priv->pipe_in, skb->data, - skb_size, rtl8xxxu_rx_complete, skb); - usb_anchor_urb(&rx_urb->urb, &priv->rx_anchor); - ret = usb_submit_urb(&rx_urb->urb, GFP_ATOMIC); - if (ret) - usb_unanchor_urb(&rx_urb->urb); - return ret; -} - -static void rtl8xxxu_int_complete(struct urb *urb) -{ - struct rtl8xxxu_priv *priv = (struct rtl8xxxu_priv *)urb->context; - struct device *dev = &priv->udev->dev; - int ret; - - if (rtl8xxxu_debug & RTL8XXXU_DEBUG_INTERRUPT) - dev_dbg(dev, "%s: status %i\n", __func__, urb->status); - if (urb->status == 0) { - usb_anchor_urb(urb, &priv->int_anchor); - ret = usb_submit_urb(urb, GFP_ATOMIC); - if (ret) - usb_unanchor_urb(urb); - } else { - dev_dbg(dev, "%s: Error %i\n", __func__, urb->status); - } -} - - -static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw) -{ - struct rtl8xxxu_priv *priv = hw->priv; - struct urb *urb; - u32 val32; - int ret; - - urb = usb_alloc_urb(0, GFP_KERNEL); - if (!urb) - return -ENOMEM; - - usb_fill_int_urb(urb, priv->udev, priv->pipe_interrupt, - priv->int_buf, USB_INTR_CONTENT_LENGTH, - rtl8xxxu_int_complete, priv, 1); - usb_anchor_urb(urb, &priv->int_anchor); - ret = usb_submit_urb(urb, GFP_KERNEL); - if (ret) { - usb_unanchor_urb(urb); - goto error; - } - - val32 = rtl8xxxu_read32(priv, REG_USB_HIMR); - val32 |= USB_HIMR_CPWM; - rtl8xxxu_write32(priv, REG_USB_HIMR, val32); - -error: - usb_free_urb(urb); - return ret; -} - -static void rtl8xxxu_switch_ports(struct rtl8xxxu_priv *priv) -{ - u8 macid[ETH_ALEN], bssid[ETH_ALEN], macid_1[ETH_ALEN], bssid_1[ETH_ALEN]; - u8 msr, bcn_ctrl, bcn_ctrl_1, atimwnd[2], atimwnd_1[2]; - struct rtl8xxxu_vif *rtlvif; - struct ieee80211_vif *vif; - u8 tsftr[8], tsftr_1[8]; - int i; - - msr = rtl8xxxu_read8(priv, REG_MSR); - bcn_ctrl = rtl8xxxu_read8(priv, REG_BEACON_CTRL); - bcn_ctrl_1 = rtl8xxxu_read8(priv, REG_BEACON_CTRL_1); - - for (i = 0; i < ARRAY_SIZE(atimwnd); i++) - atimwnd[i] = rtl8xxxu_read8(priv, REG_ATIMWND + i); - for (i = 0; i < ARRAY_SIZE(atimwnd_1); i++) - atimwnd_1[i] = rtl8xxxu_read8(priv, REG_ATIMWND_1 + i); - - for (i = 0; i < ARRAY_SIZE(tsftr); i++) - tsftr[i] = rtl8xxxu_read8(priv, REG_TSFTR + i); - for (i = 0; i < ARRAY_SIZE(tsftr); i++) - tsftr_1[i] = rtl8xxxu_read8(priv, REG_TSFTR1 + i); - - for (i = 0; i < ARRAY_SIZE(macid); i++) - macid[i] = rtl8xxxu_read8(priv, REG_MACID + i); - - for (i = 0; i < ARRAY_SIZE(bssid); i++) - bssid[i] = rtl8xxxu_read8(priv, REG_BSSID + i); - - for (i = 0; i < ARRAY_SIZE(macid_1); i++) - macid_1[i] = rtl8xxxu_read8(priv, REG_MACID1 + i); - - for (i = 0; i < ARRAY_SIZE(bssid_1); i++) - bssid_1[i] = rtl8xxxu_read8(priv, REG_BSSID1 + i); - - /* disable bcn function, disable update TSF */ - rtl8xxxu_write8(priv, REG_BEACON_CTRL, (bcn_ctrl & - (~BEACON_FUNCTION_ENABLE)) | BEACON_DISABLE_TSF_UPDATE); - rtl8xxxu_write8(priv, REG_BEACON_CTRL_1, (bcn_ctrl_1 & - (~BEACON_FUNCTION_ENABLE)) | BEACON_DISABLE_TSF_UPDATE); - - /* switch msr */ - msr = (msr & 0xf0) | ((msr & 0x03) << 2) | ((msr & 0x0c) >> 2); - rtl8xxxu_write8(priv, REG_MSR, msr); - - /* write port0 */ - rtl8xxxu_write8(priv, REG_BEACON_CTRL, bcn_ctrl_1 & ~BEACON_FUNCTION_ENABLE); - for (i = 0; i < ARRAY_SIZE(atimwnd_1); i++) - rtl8xxxu_write8(priv, REG_ATIMWND + i, atimwnd_1[i]); - for (i = 0; i < ARRAY_SIZE(tsftr_1); i++) - rtl8xxxu_write8(priv, REG_TSFTR + i, tsftr_1[i]); - for (i = 0; i < ARRAY_SIZE(macid_1); i++) - rtl8xxxu_write8(priv, REG_MACID + i, macid_1[i]); - for (i = 0; i < ARRAY_SIZE(bssid_1); i++) - rtl8xxxu_write8(priv, REG_BSSID + i, bssid_1[i]); - - /* write port1 */ - rtl8xxxu_write8(priv, REG_BEACON_CTRL_1, bcn_ctrl & ~BEACON_FUNCTION_ENABLE); - for (i = 0; i < ARRAY_SIZE(atimwnd); i++) - rtl8xxxu_write8(priv, REG_ATIMWND_1 + i, atimwnd[i]); - for (i = 0; i < ARRAY_SIZE(tsftr); i++) - rtl8xxxu_write8(priv, REG_TSFTR1 + i, tsftr[i]); - for (i = 0; i < ARRAY_SIZE(macid); i++) - rtl8xxxu_write8(priv, REG_MACID1 + i, macid[i]); - for (i = 0; i < ARRAY_SIZE(bssid); i++) - rtl8xxxu_write8(priv, REG_BSSID1 + i, bssid[i]); - - /* write bcn ctl */ - rtl8xxxu_write8(priv, REG_BEACON_CTRL, bcn_ctrl_1); - rtl8xxxu_write8(priv, REG_BEACON_CTRL_1, bcn_ctrl); - - vif = priv->vifs[0]; - priv->vifs[0] = priv->vifs[1]; - priv->vifs[1] = vif; - - /* priv->vifs[0] is NULL here, based on how this function is currently - * called from rtl8xxxu_add_interface(). - * When this function will be used in the future for a different - * scenario, please check whether vifs[0] or vifs[1] can be NULL and if - * necessary add code to set port_num = 1. - */ - rtlvif = (struct rtl8xxxu_vif *)priv->vifs[1]->drv_priv; - rtlvif->port_num = 1; -} - -static int rtl8xxxu_add_interface(struct ieee80211_hw *hw, - struct ieee80211_vif *vif) -{ - struct rtl8xxxu_vif *rtlvif = (struct rtl8xxxu_vif *)vif->drv_priv; - struct rtl8xxxu_priv *priv = hw->priv; - int port_num; - u8 val8; - - if (!priv->vifs[0]) - port_num = 0; - else if (!priv->vifs[1]) - port_num = 1; - else - return -EOPNOTSUPP; - - switch (vif->type) { - case NL80211_IFTYPE_STATION: - if (port_num == 0) { - rtl8xxxu_stop_tx_beacon(priv); - - val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL); - val8 |= BEACON_ATIM | BEACON_FUNCTION_ENABLE | - BEACON_DISABLE_TSF_UPDATE; - rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8); - } - break; - case NL80211_IFTYPE_AP: - if (port_num == 1) { - rtl8xxxu_switch_ports(priv); - port_num = 0; - } - - rtl8xxxu_write8(priv, REG_BEACON_CTRL, - BEACON_DISABLE_TSF_UPDATE | BEACON_CTRL_MBSSID); - rtl8xxxu_write8(priv, REG_ATIMWND, 0x0c); /* 12ms */ - rtl8xxxu_write16(priv, REG_TSFTR_SYN_OFFSET, 0x7fff); /* ~32ms */ - rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, DUAL_TSF_RESET_TSF0); - - /* enable BCN0 function */ - rtl8xxxu_write8(priv, REG_BEACON_CTRL, - BEACON_DISABLE_TSF_UPDATE | - BEACON_FUNCTION_ENABLE | BEACON_CTRL_MBSSID | - BEACON_CTRL_TX_BEACON_RPT); - - /* select BCN on port 0 */ - val8 = rtl8xxxu_read8(priv, REG_CCK_CHECK); - val8 &= ~BIT_BCN_PORT_SEL; - rtl8xxxu_write8(priv, REG_CCK_CHECK, val8); - break; - default: - return -EOPNOTSUPP; - } - - priv->vifs[port_num] = vif; - rtlvif->port_num = port_num; - rtlvif->hw_key_idx = 0xff; - - rtl8xxxu_set_linktype(priv, vif->type, port_num); - ether_addr_copy(priv->mac_addr, vif->addr); - rtl8xxxu_set_mac(priv, port_num); - - return 0; -} - -static void rtl8xxxu_remove_interface(struct ieee80211_hw *hw, - struct ieee80211_vif *vif) -{ - struct rtl8xxxu_vif *rtlvif = (struct rtl8xxxu_vif *)vif->drv_priv; - struct rtl8xxxu_priv *priv = hw->priv; - - dev_dbg(&priv->udev->dev, "%s\n", __func__); - - priv->vifs[rtlvif->port_num] = NULL; -} - -static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed) -{ - struct rtl8xxxu_priv *priv = hw->priv; - struct device *dev = &priv->udev->dev; - int ret = 0, channel; - bool ht40; - - if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL) - dev_info(dev, - "%s: channel: %i (changed %08x chandef.width %02x)\n", - __func__, hw->conf.chandef.chan->hw_value, - changed, hw->conf.chandef.width); - - if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { - switch (hw->conf.chandef.width) { - case NL80211_CHAN_WIDTH_20_NOHT: - case NL80211_CHAN_WIDTH_20: - ht40 = false; - break; - case NL80211_CHAN_WIDTH_40: - ht40 = true; - break; - default: - ret = -ENOTSUPP; - goto exit; - } - - channel = hw->conf.chandef.chan->hw_value; - - priv->fops->set_tx_power(priv, channel, ht40); - - priv->fops->config_channel(hw); - } - -exit: - return ret; -} - -static int rtl8xxxu_conf_tx(struct ieee80211_hw *hw, - struct ieee80211_vif *vif, - unsigned int link_id, u16 queue, - const struct ieee80211_tx_queue_params *param) -{ - struct rtl8xxxu_priv *priv = hw->priv; - struct device *dev = &priv->udev->dev; - u32 val32; - u8 aifs, acm_ctrl, acm_bit; - - aifs = param->aifs; - - val32 = aifs | - fls(param->cw_min) << EDCA_PARAM_ECW_MIN_SHIFT | - fls(param->cw_max) << EDCA_PARAM_ECW_MAX_SHIFT | - (u32)param->txop << EDCA_PARAM_TXOP_SHIFT; - - acm_ctrl = rtl8xxxu_read8(priv, REG_ACM_HW_CTRL); - dev_dbg(dev, - "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n", - __func__, queue, val32, param->acm, acm_ctrl); - - switch (queue) { - case IEEE80211_AC_VO: - acm_bit = ACM_HW_CTRL_VO; - rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32); - break; - case IEEE80211_AC_VI: - acm_bit = ACM_HW_CTRL_VI; - rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32); - break; - case IEEE80211_AC_BE: - acm_bit = ACM_HW_CTRL_BE; - rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32); - break; - case IEEE80211_AC_BK: - acm_bit = ACM_HW_CTRL_BK; - rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32); - break; - default: - acm_bit = 0; - break; - } - - if (param->acm) - acm_ctrl |= acm_bit; - else - acm_ctrl &= ~acm_bit; - rtl8xxxu_write8(priv, REG_ACM_HW_CTRL, acm_ctrl); - - return 0; -} - -static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw, - unsigned int changed_flags, - unsigned int *total_flags, u64 multicast) -{ - struct rtl8xxxu_priv *priv = hw->priv; - u32 rcr = priv->regrcr; - - dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n", - __func__, changed_flags, *total_flags); - - /* - * FIF_ALLMULTI ignored as all multicast frames are accepted (REG_MAR) - */ - - if (*total_flags & FIF_FCSFAIL) - rcr |= RCR_ACCEPT_CRC32; - else - rcr &= ~RCR_ACCEPT_CRC32; - - /* - * FIF_PLCPFAIL not supported? - */ - - if (*total_flags & FIF_BCN_PRBRESP_PROMISC) - rcr &= ~(RCR_CHECK_BSSID_BEACON | RCR_CHECK_BSSID_MATCH); - else - rcr |= RCR_CHECK_BSSID_BEACON | RCR_CHECK_BSSID_MATCH; - - if (priv->vifs[0] && priv->vifs[0]->type == NL80211_IFTYPE_AP) - rcr &= ~(RCR_CHECK_BSSID_MATCH | RCR_CHECK_BSSID_BEACON); - - if (*total_flags & FIF_CONTROL) - rcr |= RCR_ACCEPT_CTRL_FRAME; - else - rcr &= ~RCR_ACCEPT_CTRL_FRAME; - - if (*total_flags & FIF_OTHER_BSS) - rcr |= RCR_ACCEPT_AP; - else - rcr &= ~RCR_ACCEPT_AP; - - if (*total_flags & FIF_PSPOLL) - rcr |= RCR_ACCEPT_PM; - else - rcr &= ~RCR_ACCEPT_PM; - - /* - * FIF_PROBE_REQ ignored as probe requests always seem to be accepted - */ - - rtl8xxxu_write32(priv, REG_RCR, rcr); - priv->regrcr = rcr; - - *total_flags &= (FIF_ALLMULTI | FIF_FCSFAIL | FIF_BCN_PRBRESP_PROMISC | - FIF_CONTROL | FIF_OTHER_BSS | FIF_PSPOLL | - FIF_PROBE_REQ); -} - -static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, u32 rts) -{ - if (rts > 2347 && rts != (u32)-1) - return -EINVAL; - - return 0; -} - -static int rtl8xxxu_get_free_sec_cam(struct ieee80211_hw *hw) -{ - struct rtl8xxxu_priv *priv = hw->priv; - - return find_first_zero_bit(priv->cam_map, priv->fops->max_sec_cam_num); -} - -static int rtl8xxxu_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, - struct ieee80211_vif *vif, - struct ieee80211_sta *sta, - struct ieee80211_key_conf *key) -{ - struct rtl8xxxu_vif *rtlvif = (struct rtl8xxxu_vif *)vif->drv_priv; - struct rtl8xxxu_priv *priv = hw->priv; - struct device *dev = &priv->udev->dev; - u8 mac_addr[ETH_ALEN]; - u8 val8; - u16 val16; - u32 val32; - int retval = -EOPNOTSUPP; - - dev_dbg(dev, "%s: cmd %02x, cipher %08x, index %i\n", - __func__, cmd, key->cipher, key->keyidx); - - if (key->keyidx > 3) - return -EOPNOTSUPP; - - switch (key->cipher) { - case WLAN_CIPHER_SUITE_WEP40: - case WLAN_CIPHER_SUITE_WEP104: - - break; - case WLAN_CIPHER_SUITE_CCMP: - key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX; - break; - case WLAN_CIPHER_SUITE_TKIP: - key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; - break; - default: - return -EOPNOTSUPP; - } - - if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) { - dev_dbg(dev, "%s: pairwise key\n", __func__); - ether_addr_copy(mac_addr, sta->addr); - } else { - dev_dbg(dev, "%s: group key\n", __func__); - ether_addr_copy(mac_addr, vif->bss_conf.bssid); - } - - val16 = rtl8xxxu_read16(priv, REG_CR); - val16 |= CR_SECURITY_ENABLE; - rtl8xxxu_write16(priv, REG_CR, val16); - - val8 = SEC_CFG_TX_SEC_ENABLE | SEC_CFG_TXBC_USE_DEFKEY | - SEC_CFG_RX_SEC_ENABLE | SEC_CFG_RXBC_USE_DEFKEY; - val8 |= SEC_CFG_TX_USE_DEFKEY | SEC_CFG_RX_USE_DEFKEY; - rtl8xxxu_write8(priv, REG_SECURITY_CFG, val8); - - switch (cmd) { - case SET_KEY: - - retval = rtl8xxxu_get_free_sec_cam(hw); - if (retval < 0) - return -EOPNOTSUPP; - - key->hw_key_idx = retval; - - if (vif->type == NL80211_IFTYPE_AP && !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) - rtlvif->hw_key_idx = key->hw_key_idx; - - key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; - rtl8xxxu_cam_write(priv, key, mac_addr); - set_bit(key->hw_key_idx, priv->cam_map); - retval = 0; - break; - case DISABLE_KEY: - rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000); - val32 = CAM_CMD_POLLING | CAM_CMD_WRITE | - key->hw_key_idx << CAM_CMD_KEY_SHIFT; - rtl8xxxu_write32(priv, REG_CAM_CMD, val32); - rtlvif->hw_key_idx = 0xff; - clear_bit(key->hw_key_idx, priv->cam_map); - retval = 0; - break; - default: - dev_warn(dev, "%s: Unsupported command %02x\n", __func__, cmd); - } - - return retval; -} - -static int -rtl8xxxu_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, - struct ieee80211_ampdu_params *params) -{ - struct rtl8xxxu_priv *priv = hw->priv; - struct device *dev = &priv->udev->dev; - u8 ampdu_factor, ampdu_density; - struct ieee80211_sta *sta = params->sta; - u16 tid = params->tid; - enum ieee80211_ampdu_mlme_action action = params->action; - - switch (action) { - case IEEE80211_AMPDU_TX_START: - dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_START\n", __func__); - ampdu_factor = sta->deflink.ht_cap.ampdu_factor; - ampdu_density = sta->deflink.ht_cap.ampdu_density; - rtl8xxxu_set_ampdu_factor(priv, ampdu_factor); - rtl8xxxu_set_ampdu_min_space(priv, ampdu_density); - dev_dbg(dev, - "Changed HT: ampdu_factor %02x, ampdu_density %02x\n", - ampdu_factor, ampdu_density); - return IEEE80211_AMPDU_TX_START_IMMEDIATE; - case IEEE80211_AMPDU_TX_STOP_CONT: - case IEEE80211_AMPDU_TX_STOP_FLUSH: - case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: - dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_STOP\n", __func__); - rtl8xxxu_set_ampdu_factor(priv, 0); - rtl8xxxu_set_ampdu_min_space(priv, 0); - clear_bit(tid, priv->tx_aggr_started); - clear_bit(tid, priv->tid_tx_operational); - ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); - break; - case IEEE80211_AMPDU_TX_OPERATIONAL: - dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_OPERATIONAL\n", __func__); - set_bit(tid, priv->tid_tx_operational); - break; - case IEEE80211_AMPDU_RX_START: - dev_dbg(dev, "%s: IEEE80211_AMPDU_RX_START\n", __func__); - break; - case IEEE80211_AMPDU_RX_STOP: - dev_dbg(dev, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__); - break; - default: - break; - } - return 0; -} - -static void -rtl8xxxu_sta_statistics(struct ieee80211_hw *hw, struct ieee80211_vif *vif, - struct ieee80211_sta *sta, struct station_info *sinfo) -{ - struct rtl8xxxu_priv *priv = hw->priv; - - sinfo->txrate = priv->ra_report.txrate; - sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BITRATE); -} - -static u8 rtl8xxxu_signal_to_snr(int signal) -{ - if (signal < RTL8XXXU_NOISE_FLOOR_MIN) - signal = RTL8XXXU_NOISE_FLOOR_MIN; - else if (signal > 0) - signal = 0; - return (u8)(signal - RTL8XXXU_NOISE_FLOOR_MIN); -} - -static void rtl8xxxu_refresh_rate_mask(struct rtl8xxxu_priv *priv, - int signal, struct ieee80211_sta *sta, - bool force) -{ - struct rtl8xxxu_sta_info *sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv; - struct ieee80211_hw *hw = priv->hw; - u16 wireless_mode; - u8 rssi_level, ratr_idx; - u8 txbw_40mhz; - u8 snr, snr_thresh_high, snr_thresh_low; - u8 go_up_gap = 5; - u8 macid = rtl8xxxu_get_macid(priv, sta); - - rssi_level = sta_info->rssi_level; - snr = rtl8xxxu_signal_to_snr(signal); - snr_thresh_high = RTL8XXXU_SNR_THRESH_HIGH; - snr_thresh_low = RTL8XXXU_SNR_THRESH_LOW; - txbw_40mhz = (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) ? 1 : 0; - - switch (rssi_level) { - case RTL8XXXU_RATR_STA_MID: - snr_thresh_high += go_up_gap; - break; - case RTL8XXXU_RATR_STA_LOW: - snr_thresh_high += go_up_gap; - snr_thresh_low += go_up_gap; - break; - default: - break; - } - - if (snr > snr_thresh_high) - rssi_level = RTL8XXXU_RATR_STA_HIGH; - else if (snr > snr_thresh_low) - rssi_level = RTL8XXXU_RATR_STA_MID; - else - rssi_level = RTL8XXXU_RATR_STA_LOW; - - if (rssi_level != sta_info->rssi_level || force) { - int sgi = 0; - u32 rate_bitmap = 0; - - rate_bitmap = (sta->deflink.supp_rates[0] & 0xfff) | - (sta->deflink.ht_cap.mcs.rx_mask[0] << 12) | - (sta->deflink.ht_cap.mcs.rx_mask[1] << 20); - if (sta->deflink.ht_cap.cap & - (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20)) - sgi = 1; - - wireless_mode = rtl8xxxu_wireless_mode(hw, sta); - switch (wireless_mode) { - case WIRELESS_MODE_B: - ratr_idx = RATEID_IDX_B; - if (rate_bitmap & 0x0000000c) - rate_bitmap &= 0x0000000d; - else - rate_bitmap &= 0x0000000f; - break; - case WIRELESS_MODE_A: - case WIRELESS_MODE_G: - ratr_idx = RATEID_IDX_G; - if (rssi_level == RTL8XXXU_RATR_STA_HIGH) - rate_bitmap &= 0x00000f00; - else - rate_bitmap &= 0x00000ff0; - break; - case (WIRELESS_MODE_B | WIRELESS_MODE_G): - ratr_idx = RATEID_IDX_BG; - if (rssi_level == RTL8XXXU_RATR_STA_HIGH) - rate_bitmap &= 0x00000f00; - else if (rssi_level == RTL8XXXU_RATR_STA_MID) - rate_bitmap &= 0x00000ff0; - else - rate_bitmap &= 0x00000ff5; - break; - case WIRELESS_MODE_N_24G: - case WIRELESS_MODE_N_5G: - case (WIRELESS_MODE_G | WIRELESS_MODE_N_24G): - case (WIRELESS_MODE_A | WIRELESS_MODE_N_5G): - if (priv->tx_paths == 2 && priv->rx_paths == 2) - ratr_idx = RATEID_IDX_GN_N2SS; - else - ratr_idx = RATEID_IDX_GN_N1SS; - break; - case (WIRELESS_MODE_B | WIRELESS_MODE_G | WIRELESS_MODE_N_24G): - case (WIRELESS_MODE_B | WIRELESS_MODE_N_24G): - if (txbw_40mhz) { - if (priv->tx_paths == 2 && priv->rx_paths == 2) - ratr_idx = RATEID_IDX_BGN_40M_2SS; - else - ratr_idx = RATEID_IDX_BGN_40M_1SS; - } else { - if (priv->tx_paths == 2 && priv->rx_paths == 2) - ratr_idx = RATEID_IDX_BGN_20M_2SS_BN; - else - ratr_idx = RATEID_IDX_BGN_20M_1SS_BN; - } - - if (priv->tx_paths == 2 && priv->rx_paths == 2) { - if (rssi_level == RTL8XXXU_RATR_STA_HIGH) { - rate_bitmap &= 0x0f8f0000; - } else if (rssi_level == RTL8XXXU_RATR_STA_MID) { - rate_bitmap &= 0x0f8ff000; - } else { - if (txbw_40mhz) - rate_bitmap &= 0x0f8ff015; - else - rate_bitmap &= 0x0f8ff005; - } - } else { - if (rssi_level == RTL8XXXU_RATR_STA_HIGH) { - rate_bitmap &= 0x000f0000; - } else if (rssi_level == RTL8XXXU_RATR_STA_MID) { - rate_bitmap &= 0x000ff000; - } else { - if (txbw_40mhz) - rate_bitmap &= 0x000ff015; - else - rate_bitmap &= 0x000ff005; - } - } - break; - default: - ratr_idx = RATEID_IDX_BGN_40M_2SS; - rate_bitmap &= 0x0fffffff; - break; - } - - sta_info->rssi_level = rssi_level; - priv->fops->update_rate_mask(priv, rate_bitmap, ratr_idx, sgi, txbw_40mhz, macid); - } -} - -static void rtl8xxxu_set_atc_status(struct rtl8xxxu_priv *priv, bool atc_status) -{ - struct rtl8xxxu_cfo_tracking *cfo = &priv->cfo_tracking; - u32 val32; - - if (atc_status == cfo->atc_status) - return; - - cfo->atc_status = atc_status; - - val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING); - if (atc_status) - val32 |= CFO_TRACKING_ATC_STATUS; - else - val32 &= ~CFO_TRACKING_ATC_STATUS; - rtl8xxxu_write32(priv, REG_OFDM1_CFO_TRACKING, val32); -} - -/* Central frequency offset correction */ -static void rtl8xxxu_track_cfo(struct rtl8xxxu_priv *priv) -{ - struct rtl8xxxu_cfo_tracking *cfo = &priv->cfo_tracking; - int cfo_khz_a, cfo_khz_b, cfo_average; - int crystal_cap; - - if (!rtl8xxxu_is_assoc(priv)) { - /* Reset */ - cfo->adjust = true; - - if (cfo->crystal_cap > priv->default_crystal_cap) - priv->fops->set_crystal_cap(priv, cfo->crystal_cap - 1); - else if (cfo->crystal_cap < priv->default_crystal_cap) - priv->fops->set_crystal_cap(priv, cfo->crystal_cap + 1); - - rtl8xxxu_set_atc_status(priv, true); - - return; - } - - if (cfo->packet_count == cfo->packet_count_pre) - /* No new information. */ - return; - - cfo->packet_count_pre = cfo->packet_count; - - /* CFO_tail[1:0] is S(8,7), (num_subcarrier>>7) x 312.5K = CFO value(K Hz) */ - cfo_khz_a = (int)((cfo->cfo_tail[0] * 3125) / 10) >> 7; - cfo_khz_b = (int)((cfo->cfo_tail[1] * 3125) / 10) >> 7; - - if (priv->tx_paths == 1) - cfo_average = cfo_khz_a; - else - cfo_average = (cfo_khz_a + cfo_khz_b) / 2; - - dev_dbg(&priv->udev->dev, "cfo_average: %d\n", cfo_average); - - if (cfo->adjust) { - if (abs(cfo_average) < CFO_TH_XTAL_LOW) - cfo->adjust = false; - } else { - if (abs(cfo_average) > CFO_TH_XTAL_HIGH) - cfo->adjust = true; - } - - /* - * TODO: We should return here only if bluetooth is enabled. - * See the vendor drivers for how to determine that. - */ - if (priv->has_bluetooth) - return; - - if (!cfo->adjust) - return; - - crystal_cap = cfo->crystal_cap; - - if (cfo_average > CFO_TH_XTAL_LOW) - crystal_cap++; - else if (cfo_average < -CFO_TH_XTAL_LOW) - crystal_cap--; - - crystal_cap = clamp(crystal_cap, 0, 0x3f); - - priv->fops->set_crystal_cap(priv, crystal_cap); - - rtl8xxxu_set_atc_status(priv, abs(cfo_average) >= CFO_TH_ATC); -} - -static void rtl8xxxu_ra_iter(void *data, struct ieee80211_sta *sta) -{ - struct rtl8xxxu_sta_info *sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv; - struct rtl8xxxu_priv *priv = data; - int signal = -ewma_rssi_read(&sta_info->avg_rssi); - - priv->fops->report_rssi(priv, rtl8xxxu_get_macid(priv, sta), - rtl8xxxu_signal_to_snr(signal)); - rtl8xxxu_refresh_rate_mask(priv, signal, sta, false); -} - -struct rtl8xxxu_stas_entry { - struct list_head list; - struct ieee80211_sta *sta; -}; - -struct rtl8xxxu_iter_stas_data { - struct rtl8xxxu_priv *priv; - struct list_head list; -}; - -static void rtl8xxxu_collect_sta_iter(void *data, struct ieee80211_sta *sta) -{ - struct rtl8xxxu_iter_stas_data *iter_stas = data; - struct rtl8xxxu_stas_entry *stas_entry; - - stas_entry = kmalloc(sizeof(*stas_entry), GFP_ATOMIC); - if (!stas_entry) - return; - - stas_entry->sta = sta; - list_add_tail(&stas_entry->list, &iter_stas->list); -} - -static void rtl8xxxu_watchdog_callback(struct work_struct *work) -{ - - struct rtl8xxxu_iter_stas_data iter_data; - struct rtl8xxxu_stas_entry *sta_entry, *tmp; - struct rtl8xxxu_priv *priv; - - priv = container_of(work, struct rtl8xxxu_priv, ra_watchdog.work); - iter_data.priv = priv; - INIT_LIST_HEAD(&iter_data.list); - - mutex_lock(&priv->sta_mutex); - ieee80211_iterate_stations_atomic(priv->hw, rtl8xxxu_collect_sta_iter, - &iter_data); - list_for_each_entry_safe(sta_entry, tmp, &iter_data.list, list) { - list_del_init(&sta_entry->list); - rtl8xxxu_ra_iter(priv, sta_entry->sta); - kfree(sta_entry); - } - mutex_unlock(&priv->sta_mutex); - - if (priv->fops->set_crystal_cap) - rtl8xxxu_track_cfo(priv); - - schedule_delayed_work(&priv->ra_watchdog, 2 * HZ); -} - -static int rtl8xxxu_start(struct ieee80211_hw *hw) -{ - struct rtl8xxxu_priv *priv = hw->priv; - struct rtl8xxxu_rx_urb *rx_urb; - struct rtl8xxxu_tx_urb *tx_urb; - struct sk_buff *skb; - unsigned long flags; - int ret, i; - - ret = 0; - - init_usb_anchor(&priv->rx_anchor); - init_usb_anchor(&priv->tx_anchor); - init_usb_anchor(&priv->int_anchor); - - priv->fops->enable_rf(priv); - if (priv->usb_interrupts) { - ret = rtl8xxxu_submit_int_urb(hw); - if (ret) - goto exit; - } - - for (i = 0; i < RTL8XXXU_TX_URBS; i++) { - tx_urb = kmalloc(sizeof(struct rtl8xxxu_tx_urb), GFP_KERNEL); - if (!tx_urb) { - if (!i) - ret = -ENOMEM; - - goto error_out; - } - usb_init_urb(&tx_urb->urb); - INIT_LIST_HEAD(&tx_urb->list); - tx_urb->hw = hw; - list_add(&tx_urb->list, &priv->tx_urb_free_list); - priv->tx_urb_free_count++; - } - - priv->tx_stopped = false; - - spin_lock_irqsave(&priv->rx_urb_lock, flags); - priv->shutdown = false; - spin_unlock_irqrestore(&priv->rx_urb_lock, flags); - - for (i = 0; i < RTL8XXXU_RX_URBS; i++) { - rx_urb = kmalloc(sizeof(struct rtl8xxxu_rx_urb), GFP_KERNEL); - if (!rx_urb) { - if (!i) - ret = -ENOMEM; - - goto error_out; - } - usb_init_urb(&rx_urb->urb); - INIT_LIST_HEAD(&rx_urb->list); - rx_urb->hw = hw; - - ret = rtl8xxxu_submit_rx_urb(priv, rx_urb); - if (ret) { - if (ret != -ENOMEM) { - skb = (struct sk_buff *)rx_urb->urb.context; - dev_kfree_skb(skb); - } - rtl8xxxu_queue_rx_urb(priv, rx_urb); - } - } - - schedule_delayed_work(&priv->ra_watchdog, 2 * HZ); -exit: - /* - * Accept all data and mgmt frames - */ - rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff); - rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff); - - rtl8xxxu_write32_mask(priv, REG_OFDM0_XA_AGC_CORE1, - OFDM0_X_AGC_CORE1_IGI_MASK, 0x1e); - - return ret; - -error_out: - rtl8xxxu_free_tx_resources(priv); - /* - * Disable all data and mgmt frames - */ - rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000); - rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000); - - return ret; -} - -static void rtl8xxxu_stop(struct ieee80211_hw *hw) -{ - struct rtl8xxxu_priv *priv = hw->priv; - unsigned long flags; - - rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); - - rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000); - rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000); - - spin_lock_irqsave(&priv->rx_urb_lock, flags); - priv->shutdown = true; - spin_unlock_irqrestore(&priv->rx_urb_lock, flags); - - usb_kill_anchored_urbs(&priv->rx_anchor); - usb_kill_anchored_urbs(&priv->tx_anchor); - if (priv->usb_interrupts) - usb_kill_anchored_urbs(&priv->int_anchor); - - rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); - - priv->fops->disable_rf(priv); - - /* - * Disable interrupts - */ - if (priv->usb_interrupts) - rtl8xxxu_write32(priv, REG_USB_HIMR, 0); - - cancel_work_sync(&priv->c2hcmd_work); - cancel_delayed_work_sync(&priv->ra_watchdog); - cancel_delayed_work_sync(&priv->update_beacon_work); - - rtl8xxxu_free_rx_resources(priv); - rtl8xxxu_free_tx_resources(priv); -} - -static int rtl8xxxu_sta_add(struct ieee80211_hw *hw, - struct ieee80211_vif *vif, - struct ieee80211_sta *sta) -{ - struct rtl8xxxu_sta_info *sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv; - struct rtl8xxxu_vif *rtlvif = (struct rtl8xxxu_vif *)vif->drv_priv; - struct rtl8xxxu_priv *priv = hw->priv; - - mutex_lock(&priv->sta_mutex); - ewma_rssi_init(&sta_info->avg_rssi); - if (vif->type == NL80211_IFTYPE_AP) { - sta_info->rssi_level = RTL8XXXU_RATR_STA_INIT; - sta_info->macid = rtl8xxxu_acquire_macid(priv); - if (sta_info->macid >= RTL8XXXU_MAX_MAC_ID_NUM) { - mutex_unlock(&priv->sta_mutex); - return -ENOSPC; - } - - rtl8xxxu_refresh_rate_mask(priv, 0, sta, true); - priv->fops->report_connect(priv, sta_info->macid, H2C_MACID_ROLE_STA, true); - } else { - switch (rtlvif->port_num) { - case 0: - sta_info->macid = RTL8XXXU_BC_MC_MACID; - break; - case 1: - sta_info->macid = RTL8XXXU_BC_MC_MACID1; - break; - default: - break; - } - } - mutex_unlock(&priv->sta_mutex); - - return 0; -} - -static int rtl8xxxu_sta_remove(struct ieee80211_hw *hw, - struct ieee80211_vif *vif, - struct ieee80211_sta *sta) -{ - struct rtl8xxxu_sta_info *sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv; - struct rtl8xxxu_priv *priv = hw->priv; - - mutex_lock(&priv->sta_mutex); - if (vif->type == NL80211_IFTYPE_AP) - rtl8xxxu_release_macid(priv, sta_info->macid); - mutex_unlock(&priv->sta_mutex); - - return 0; -} - -static const struct ieee80211_ops rtl8xxxu_ops = { - .add_chanctx = ieee80211_emulate_add_chanctx, - .remove_chanctx = ieee80211_emulate_remove_chanctx, - .change_chanctx = ieee80211_emulate_change_chanctx, - .switch_vif_chanctx = ieee80211_emulate_switch_vif_chanctx, - .tx = rtl8xxxu_tx, - .wake_tx_queue = ieee80211_handle_wake_tx_queue, - .add_interface = rtl8xxxu_add_interface, - .remove_interface = rtl8xxxu_remove_interface, - .config = rtl8xxxu_config, - .conf_tx = rtl8xxxu_conf_tx, - .bss_info_changed = rtl8xxxu_bss_info_changed, - .start_ap = rtl8xxxu_start_ap, - .configure_filter = rtl8xxxu_configure_filter, - .set_rts_threshold = rtl8xxxu_set_rts_threshold, - .start = rtl8xxxu_start, - .stop = rtl8xxxu_stop, - .sw_scan_start = rtl8xxxu_sw_scan_start, - .sw_scan_complete = rtl8xxxu_sw_scan_complete, - .set_key = rtl8xxxu_set_key, - .ampdu_action = rtl8xxxu_ampdu_action, - .sta_statistics = rtl8xxxu_sta_statistics, - .get_antenna = rtl8xxxu_get_antenna, - .set_tim = rtl8xxxu_set_tim, - .sta_add = rtl8xxxu_sta_add, - .sta_remove = rtl8xxxu_sta_remove, -}; - -static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv, - struct usb_interface *interface) -{ - struct usb_interface_descriptor *interface_desc; - struct usb_host_interface *host_interface; - struct usb_endpoint_descriptor *endpoint; - struct device *dev = &priv->udev->dev; - int i, j = 0, endpoints; - u8 dir, xtype, num; - int ret = 0; - - host_interface = interface->cur_altsetting; - interface_desc = &host_interface->desc; - endpoints = interface_desc->bNumEndpoints; - - for (i = 0; i < endpoints; i++) { - endpoint = &host_interface->endpoint[i].desc; - - dir = endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK; - num = usb_endpoint_num(endpoint); - xtype = usb_endpoint_type(endpoint); - if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB) - dev_dbg(dev, - "%s: endpoint: dir %02x, # %02x, type %02x\n", - __func__, dir, num, xtype); - if (usb_endpoint_dir_in(endpoint) && - usb_endpoint_xfer_bulk(endpoint)) { - if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB) - dev_dbg(dev, "%s: in endpoint num %i\n", - __func__, num); - - if (priv->pipe_in) { - dev_warn(dev, - "%s: Too many IN pipes\n", __func__); - ret = -EINVAL; - goto exit; - } - - priv->pipe_in = usb_rcvbulkpipe(priv->udev, num); - } - - if (usb_endpoint_dir_in(endpoint) && - usb_endpoint_xfer_int(endpoint)) { - if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB) - dev_dbg(dev, "%s: interrupt endpoint num %i\n", - __func__, num); - - if (priv->pipe_interrupt) { - dev_warn(dev, "%s: Too many INTERRUPT pipes\n", - __func__); - ret = -EINVAL; - goto exit; - } - - priv->pipe_interrupt = usb_rcvintpipe(priv->udev, num); - } - - if (usb_endpoint_dir_out(endpoint) && - usb_endpoint_xfer_bulk(endpoint)) { - if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB) - dev_dbg(dev, "%s: out endpoint num %i\n", - __func__, num); - if (j >= RTL8XXXU_OUT_ENDPOINTS) { - dev_warn(dev, - "%s: Too many OUT pipes\n", __func__); - ret = -EINVAL; - goto exit; - } - priv->out_ep[j++] = num; - } - } -exit: - priv->nr_out_eps = j; - return ret; -} - -static void rtl8xxxu_init_led(struct rtl8xxxu_priv *priv) -{ - struct led_classdev *led = &priv->led_cdev; - - if (!priv->fops->led_classdev_brightness_set) - return; - - led->brightness_set_blocking = priv->fops->led_classdev_brightness_set; - - snprintf(priv->led_name, sizeof(priv->led_name), - "rtl8xxxu-usb%s", dev_name(&priv->udev->dev)); - led->name = priv->led_name; - led->max_brightness = RTL8XXXU_HW_LED_CONTROL; - - if (led_classdev_register(&priv->udev->dev, led)) - return; - - priv->led_registered = true; - - led->brightness = led->max_brightness; - priv->fops->led_classdev_brightness_set(led, led->brightness); -} - -static void rtl8xxxu_deinit_led(struct rtl8xxxu_priv *priv) -{ - struct led_classdev *led = &priv->led_cdev; - - if (!priv->led_registered) - return; - - priv->fops->led_classdev_brightness_set(led, LED_OFF); - led_classdev_unregister(led); -} - -static const struct ieee80211_iface_limit rtl8xxxu_limits[] = { - { .max = 2, .types = BIT(NL80211_IFTYPE_STATION), }, - { .max = 1, .types = BIT(NL80211_IFTYPE_AP), }, -}; - -static const struct ieee80211_iface_combination rtl8xxxu_combinations[] = { - { - .limits = rtl8xxxu_limits, - .n_limits = ARRAY_SIZE(rtl8xxxu_limits), - .max_interfaces = 2, - .num_different_channels = 1, - }, -}; - -static int rtl8xxxu_probe(struct usb_interface *interface, - const struct usb_device_id *id) -{ - struct rtl8xxxu_priv *priv; - struct ieee80211_hw *hw; - struct usb_device *udev; - struct ieee80211_supported_band *sband; - int ret; - int untested = 1; - - udev = usb_get_dev(interface_to_usbdev(interface)); - - switch (id->idVendor) { - case USB_VENDOR_ID_REALTEK: - switch(id->idProduct) { - case 0x1724: - case 0x8176: - case 0x8178: - case 0x817f: - case 0x818b: - case 0xf179: - case 0x8179: - case 0xb711: - case 0xf192: - case 0x2005: - untested = 0; - break; - } - break; - case 0x7392: - if (id->idProduct == 0x7811 || id->idProduct == 0xa611 || id->idProduct == 0xb811) - untested = 0; - break; - case 0x050d: - if (id->idProduct == 0x1004) - untested = 0; - break; - case 0x20f4: - if (id->idProduct == 0x648b) - untested = 0; - break; - case 0x2001: - if (id->idProduct == 0x3308) - untested = 0; - break; - case 0x2357: - if (id->idProduct == 0x0109 || id->idProduct == 0x0135) - untested = 0; - break; - case 0x0b05: - if (id->idProduct == 0x18f1) - untested = 0; - break; - default: - break; - } - - if (untested) { - rtl8xxxu_debug |= RTL8XXXU_DEBUG_EFUSE; - dev_info(&udev->dev, - "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n", - id->idVendor, id->idProduct); - dev_info(&udev->dev, - "Please report results to Jes.Sorensen@gmail.com\n"); - } - - hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops); - if (!hw) { - ret = -ENOMEM; - goto err_put_dev; - } - - priv = hw->priv; - priv->hw = hw; - priv->udev = udev; - priv->fops = (struct rtl8xxxu_fileops *)id->driver_info; - mutex_init(&priv->usb_buf_mutex); - mutex_init(&priv->syson_indirect_access_mutex); - mutex_init(&priv->h2c_mutex); - mutex_init(&priv->sta_mutex); - INIT_LIST_HEAD(&priv->tx_urb_free_list); - spin_lock_init(&priv->tx_urb_lock); - INIT_LIST_HEAD(&priv->rx_urb_pending_list); - spin_lock_init(&priv->rx_urb_lock); - INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work); - INIT_DELAYED_WORK(&priv->ra_watchdog, rtl8xxxu_watchdog_callback); - INIT_DELAYED_WORK(&priv->update_beacon_work, rtl8xxxu_update_beacon_work_callback); - skb_queue_head_init(&priv->c2hcmd_queue); - - usb_set_intfdata(interface, hw); - - ret = rtl8xxxu_parse_usb(priv, interface); - if (ret) - goto err_set_intfdata; - - ret = priv->fops->identify_chip(priv); - if (ret) { - dev_err(&udev->dev, "Fatal - failed to identify chip\n"); - goto err_set_intfdata; - } - - hw->wiphy->available_antennas_tx = BIT(priv->tx_paths) - 1; - hw->wiphy->available_antennas_rx = BIT(priv->rx_paths) - 1; - - if (priv->rtl_chip == RTL8188E) - INIT_WORK(&priv->c2hcmd_work, rtl8188e_c2hcmd_callback); - else - INIT_WORK(&priv->c2hcmd_work, rtl8xxxu_c2hcmd_callback); - - ret = priv->fops->read_efuse(priv); - if (ret) { - dev_err(&udev->dev, "Fatal - failed to read EFuse\n"); - goto err_set_intfdata; - } - - ret = priv->fops->parse_efuse(priv); - if (ret) { - dev_err(&udev->dev, "Fatal - failed to parse EFuse\n"); - goto err_set_intfdata; - } - - if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) - rtl8xxxu_dump_efuse(priv); - - rtl8xxxu_print_chipinfo(priv); - - ret = priv->fops->load_firmware(priv); - if (ret) { - dev_err(&udev->dev, "Fatal - failed to load firmware\n"); - goto err_set_intfdata; - } - - ret = rtl8xxxu_init_device(hw); - if (ret) - goto err_set_intfdata; - - hw->vif_data_size = sizeof(struct rtl8xxxu_vif); - - hw->wiphy->max_scan_ssids = 1; - hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN; - if (priv->fops->max_macid_num) - hw->wiphy->max_ap_assoc_sta = priv->fops->max_macid_num - 1; - hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION); - if (priv->fops->supports_ap) - hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_AP); - hw->queues = 4; - - hw->wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH; - - if (priv->fops->supports_concurrent) { - hw->wiphy->iface_combinations = rtl8xxxu_combinations; - hw->wiphy->n_iface_combinations = ARRAY_SIZE(rtl8xxxu_combinations); - } - - sband = &rtl8xxxu_supported_band; - sband->ht_cap.ht_supported = true; - sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; - sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16; - sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40; - memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs)); - sband->ht_cap.mcs.rx_mask[0] = 0xff; - sband->ht_cap.mcs.rx_mask[4] = 0x01; - if (priv->rf_paths > 1) { - sband->ht_cap.mcs.rx_mask[1] = 0xff; - sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40; - } - sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; - /* - * Some APs will negotiate HT20_40 in a noisy environment leading - * to miserable performance. Rather than defaulting to this, only - * enable it if explicitly requested at module load time. - */ - if (rtl8xxxu_ht40_2g) { - dev_info(&udev->dev, "Enabling HT_20_40 on the 2.4GHz band\n"); - sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40; - } - hw->wiphy->bands[NL80211_BAND_2GHZ] = sband; - - hw->wiphy->rts_threshold = 2347; - - SET_IEEE80211_DEV(priv->hw, &interface->dev); - SET_IEEE80211_PERM_ADDR(hw, priv->mac_addr); - - hw->extra_tx_headroom = priv->fops->tx_desc_size; - ieee80211_hw_set(hw, SIGNAL_DBM); - - /* - * The firmware handles rate control, except for RTL8188EU, - * where we handle the rate control in the driver. - */ - ieee80211_hw_set(hw, HAS_RATE_CONTROL); - ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); - ieee80211_hw_set(hw, AMPDU_AGGREGATION); - ieee80211_hw_set(hw, MFP_CAPABLE); - - wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST); - - ret = ieee80211_register_hw(priv->hw); - if (ret) { - dev_err(&udev->dev, "%s: Failed to register: %i\n", - __func__, ret); - goto err_set_intfdata; - } - - rtl8xxxu_init_led(priv); - - return 0; - -err_set_intfdata: - usb_set_intfdata(interface, NULL); - - kfree(priv->fw_data); - mutex_destroy(&priv->usb_buf_mutex); - mutex_destroy(&priv->syson_indirect_access_mutex); - mutex_destroy(&priv->h2c_mutex); - - ieee80211_free_hw(hw); -err_put_dev: - usb_put_dev(udev); - - return ret; -} - -static void rtl8xxxu_disconnect(struct usb_interface *interface) -{ - struct rtl8xxxu_priv *priv; - struct ieee80211_hw *hw; - - hw = usb_get_intfdata(interface); - priv = hw->priv; - - rtl8xxxu_deinit_led(priv); - - ieee80211_unregister_hw(hw); - - priv->fops->power_off(priv); - - usb_set_intfdata(interface, NULL); - - dev_info(&priv->udev->dev, "disconnecting\n"); - - kfree(priv->fw_data); - mutex_destroy(&priv->usb_buf_mutex); - mutex_destroy(&priv->syson_indirect_access_mutex); - mutex_destroy(&priv->h2c_mutex); - - if (priv->udev->state != USB_STATE_NOTATTACHED) { - dev_info(&priv->udev->dev, - "Device still attached, trying to reset\n"); - usb_reset_device(priv->udev); - } - usb_put_dev(priv->udev); - ieee80211_free_hw(hw); -} - -static const struct usb_device_id dev_table[] = { -{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8724, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8723au_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1724, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8723au_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0724, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8723au_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818b, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192eu_fops}, -/* TP-Link TL-WN822N v4 */ -{USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0108, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192eu_fops}, -/* D-Link DWA-131 rev E1, tested by David Patiño */ -{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3319, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192eu_fops}, -/* Tested by Myckel Habets */ -{USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0109, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192eu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb720, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8723bu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0xa611, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8723bu_fops}, -/* RTL8188FU */ -{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xf179, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8188fu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8179, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8188eu_fops}, -/* Tested by Hans de Goede - rtl8188etv */ -{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0179, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8188eu_fops}, -/* Sitecom rtl8188eus */ -{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0076, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8188eu_fops}, -/* D-Link USB-GO-N150 */ -{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3311, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8188eu_fops}, -/* D-Link DWA-125 REV D1 */ -{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330f, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8188eu_fops}, -/* D-Link DWA-123 REV D1 */ -{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3310, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8188eu_fops}, -/* D-Link DWA-121 rev B1 */ -{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x331b, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8188eu_fops}, -/* Abocom - Abocom */ -{USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8179, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8188eu_fops}, -/* Elecom WDC-150SU2M */ -{USB_DEVICE_AND_INTERFACE_INFO(0x056e, 0x4008, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8188eu_fops}, -/* TP-Link TL-WN722N v2 */ -{USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x010c, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8188eu_fops}, -/* TP-Link TL-WN727N v5.21 */ -{USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0111, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8188eu_fops}, -/* MERCUSYS MW150US v2 */ -{USB_DEVICE_AND_INTERFACE_INFO(0x2c4e, 0x0102, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8188eu_fops}, -/* ASUS USB-N10 Nano B1 */ -{USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x18f0, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8188eu_fops}, - /* Edimax EW-7811Un V2 */ -{USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0xb811, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8188eu_fops}, -/* Rosewill USB-N150 Nano */ -{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xffef, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8188eu_fops}, -/* RTL8710BU aka RTL8188GU (not to be confused with RTL8188GTVU) */ -{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb711, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8710bu_fops}, -/* TOTOLINK N150UA V5 / N150UA-B */ -{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2005, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8710bu_fops}, -/* Comfast CF-826F */ -{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xf192, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192fu_fops}, -/* Asus USB-N13 rev C1 */ -{USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x18f1, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192fu_fops}, -/* EDIMAX EW-7722UTn V3 */ -{USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0xb722, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192fu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x318b, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192fu_fops}, -/* TP-Link TL-WN823N V2 */ -{USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0135, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192fu_fops}, -#ifdef CONFIG_RTL8XXXU_UNTESTED -/* Still supported by rtlwifi */ -{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8178, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817f, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -/* Tested by Larry Finger */ -{USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -/* Tested by Andrea Merello */ -{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -/* Tested by Jocelyn Mayer */ -{USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -/* Tested by Stefano Bravi */ -{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -/* Currently untested 8188 series devices */ -{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x018a, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8191, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8170, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8177, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817a, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817b, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817d, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817e, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818a, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1e1e, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x5088, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -/* Currently untested 8192 series devices */ -{USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2e2e, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192cu_fops}, -/* found in rtl8192eu vendor driver */ -{USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0107, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192eu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab33, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192eu_fops}, -{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818c, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192eu_fops}, -/* D-Link DWA-131 rev C1 */ -{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3312, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192eu_fops}, -/* TP-Link TL-WN8200ND V2 */ -{USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0126, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192eu_fops}, -/* Mercusys MW300UM */ -{USB_DEVICE_AND_INTERFACE_INFO(0x2c4e, 0x0100, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192eu_fops}, -/* Mercusys MW300UH */ -{USB_DEVICE_AND_INTERFACE_INFO(0x2c4e, 0x0104, 0xff, 0xff, 0xff), - .driver_info = (unsigned long)&rtl8192eu_fops}, -#endif -{ } -}; - -static struct usb_driver rtl8xxxu_driver = { - .name = DRIVER_NAME, - .probe = rtl8xxxu_probe, - .disconnect = rtl8xxxu_disconnect, - .id_table = dev_table, - .no_dynamic_id = 1, - .disable_hub_initiated_lpm = 1, -}; - -MODULE_DEVICE_TABLE(usb, dev_table); - -module_usb_driver(rtl8xxxu_driver); diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h deleted file mode 100644 index 61c0c0ec07b3..000000000000 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h +++ /dev/null @@ -1,1381 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2014 - 2017 Jes Sorensen - * - * Register definitions taken from original Realtek rtl8723au driver - */ - -/* 0x0000 ~ 0x00FF System Configuration */ -#define REG_SYS_ISO_CTRL 0x0000 -#define SYS_ISO_MD2PP BIT(0) -#define SYS_ISO_ANALOG_IPS BIT(5) -#define SYS_ISO_DIOR BIT(9) -#define SYS_ISO_PWC_EV25V BIT(14) -#define SYS_ISO_PWC_EV12V BIT(15) - -#define REG_SYS_FUNC 0x0002 -#define SYS_FUNC_BBRSTB BIT(0) -#define SYS_FUNC_BB_GLB_RSTN BIT(1) -#define SYS_FUNC_USBA BIT(2) -#define SYS_FUNC_UPLL BIT(3) -#define SYS_FUNC_USBD BIT(4) -#define SYS_FUNC_DIO_PCIE BIT(5) -#define SYS_FUNC_PCIEA BIT(6) -#define SYS_FUNC_PPLL BIT(7) -#define SYS_FUNC_PCIED BIT(8) -#define SYS_FUNC_DIOE BIT(9) -#define SYS_FUNC_CPU_ENABLE BIT(10) -#define SYS_FUNC_DCORE BIT(11) -#define SYS_FUNC_ELDR BIT(12) -#define SYS_FUNC_DIO_RF BIT(13) -#define SYS_FUNC_HWPDN BIT(14) -#define SYS_FUNC_MREGEN BIT(15) - -#define REG_APS_FSMCO 0x0004 -#define APS_FSMCO_PFM_ALDN BIT(1) -#define APS_FSMCO_PFM_WOWL BIT(3) -#define APS_FSMCO_ENABLE_POWERDOWN BIT(4) -#define APS_FSMCO_MAC_ENABLE BIT(8) -#define APS_FSMCO_MAC_OFF BIT(9) -#define APS_FSMCO_SW_LPS BIT(10) -#define APS_FSMCO_HW_SUSPEND BIT(11) -#define APS_FSMCO_PCIE BIT(12) -#define APS_FSMCO_HW_POWERDOWN BIT(15) -#define APS_FSMCO_WLON_RESET BIT(16) - -#define REG_SYS_CLKR 0x0008 -#define SYS_CLK_ANAD16V_ENABLE BIT(0) -#define SYS_CLK_ANA8M BIT(1) -#define SYS_CLK_MACSLP BIT(4) -#define SYS_CLK_LOADER_ENABLE BIT(5) -#define SYS_CLK_80M_SSC_DISABLE BIT(7) -#define SYS_CLK_80M_SSC_ENABLE_HO BIT(8) -#define SYS_CLK_PHY_SSC_RSTB BIT(9) -#define SYS_CLK_SEC_CLK_ENABLE BIT(10) -#define SYS_CLK_MAC_CLK_ENABLE BIT(11) -#define SYS_CLK_ENABLE BIT(12) -#define SYS_CLK_RING_CLK_ENABLE BIT(13) - -#define REG_9346CR 0x000a -#define EEPROM_BOOT BIT(4) -#define EEPROM_ENABLE BIT(5) - -#define REG_EE_VPD 0x000c -#define REG_AFE_MISC 0x0010 -#define AFE_MISC_WL_XTAL_CTRL BIT(6) - -#define REG_SPS0_CTRL 0x0011 -#define REG_SPS_OCP_CFG 0x0018 -#define REG_8192E_LDOV12_CTRL 0x0014 -#define REG_SYS_SWR_CTRL2 0x0014 -#define REG_RSV_CTRL 0x001c -#define RSV_CTRL_WLOCK_1C BIT(5) -#define RSV_CTRL_DIS_PRST BIT(6) - -#define REG_RF_CTRL 0x001f -#define RF_ENABLE BIT(0) -#define RF_RSTB BIT(1) -#define RF_SDMRSTB BIT(2) - -#define REG_LDOA15_CTRL 0x0020 -#define LDOA15_ENABLE BIT(0) -#define LDOA15_STANDBY BIT(1) -#define LDOA15_OBUF BIT(2) -#define LDOA15_REG_VOS BIT(3) -#define LDOA15_VOADJ_SHIFT 4 - -#define REG_LDOV12D_CTRL 0x0021 -#define LDOV12D_ENABLE BIT(0) -#define LDOV12D_STANDBY BIT(1) -#define LDOV12D_VADJ_SHIFT 4 - -#define REG_LDOHCI12_CTRL 0x0022 - -#define REG_LPLDO_CTRL 0x0023 -#define LPLDO_HSM BIT(2) -#define LPLDO_LSM_DIS BIT(3) - -#define REG_AFE_XTAL_CTRL 0x0024 -#define AFE_XTAL_ENABLE BIT(0) -#define AFE_XTAL_B_SELECT BIT(1) -#define AFE_XTAL_GATE_USB BIT(8) -#define AFE_XTAL_GATE_AFE BIT(11) -#define AFE_XTAL_RF_GATE BIT(14) -#define AFE_XTAL_GATE_DIG BIT(17) -#define AFE_XTAL_BT_GATE BIT(20) - -/* - * 0x0028 is also known as REG_AFE_CTRL2 on 8723bu/8192eu - */ -#define REG_AFE_PLL_CTRL 0x0028 -#define AFE_PLL_ENABLE BIT(0) -#define AFE_PLL_320_ENABLE BIT(1) -#define APE_PLL_FREF_SELECT BIT(2) -#define AFE_PLL_EDGE_SELECT BIT(3) -#define AFE_PLL_WDOGB BIT(4) -#define AFE_PLL_LPF_ENABLE BIT(5) - -#define REG_MAC_PHY_CTRL 0x002c - -#define REG_EFUSE_CTRL 0x0030 -#define REG_EFUSE_TEST 0x0034 -#define EFUSE_TRPT BIT(7) - /* 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 */ -#define EFUSE_CELL_SEL (BIT(8) | BIT(9)) -#define EFUSE_LDOE25_ENABLE BIT(31) -#define EFUSE_SELECT_MASK 0x0300 -#define EFUSE_WIFI_SELECT 0x0000 -#define EFUSE_BT0_SELECT 0x0100 -#define EFUSE_BT1_SELECT 0x0200 -#define EFUSE_BT2_SELECT 0x0300 - -#define EFUSE_ACCESS_ENABLE 0x69 /* RTL8723 only */ -#define EFUSE_ACCESS_DISABLE 0x00 /* RTL8723 only */ - -#define REG_PWR_DATA 0x0038 -#define PWR_DATA_EEPRPAD_RFE_CTRL_EN BIT(11) - -#define REG_CAL_TIMER 0x003c -#define REG_ACLK_MON 0x003e -#define REG_GPIO_MUXCFG 0x0040 -#define GPIO_MUXCFG_IO_SEL_ENBT BIT(5) -#define REG_GPIO_IO_SEL 0x0042 -#define REG_MAC_PINMUX_CFG 0x0043 -#define REG_GPIO_PIN_CTRL 0x0044 -#define REG_GPIO_INTM 0x0048 -#define GPIO_INTM_EDGE_TRIG_IRQ BIT(9) - -#define REG_LEDCFG0 0x004c -#define LEDCFG0_LED0CM GENMASK(2, 0) -#define LEDCFG0_LED1CM GENMASK(10, 8) -#define LED_MODE_SW_CTRL 0x0 -#define LED_MODE_TX_OR_RX_EVENTS 0x3 -#define LEDCFG0_LED0SV BIT(3) -#define LEDCFG0_LED1SV BIT(11) -#define LED_SW_OFF 0x0 -#define LED_SW_ON 0x1 -#define LEDCFG0_LED0_IO_MODE BIT(7) -#define LEDCFG0_LED1_IO_MODE BIT(15) -#define LED_IO_MODE_OUTPUT 0x0 -#define LED_IO_MODE_INPUT 0x1 -#define LEDCFG0_LED2EN BIT(21) -#define LED_GPIO_DISABLE 0x0 -#define LED_GPIO_ENABLE 0x1 -#define LEDCFG0_DPDT_SELECT BIT(23) -#define REG_LEDCFG1 0x004d -#define LEDCFG1_HW_LED_CONTROL BIT(1) -#define LEDCFG1_LED_DISABLE BIT(7) -#define REG_LEDCFG2 0x004e -#define LEDCFG2_HW_LED_CONTROL BIT(1) -#define LEDCFG2_HW_LED_ENABLE BIT(5) -#define LEDCFG2_SW_LED_DISABLE BIT(3) -#define LEDCFG2_SW_LED_CONTROL BIT(5) -#define LEDCFG2_DPDT_SELECT BIT(7) -#define REG_LEDCFG3 0x004f -#define REG_LEDCFG REG_LEDCFG2 -#define REG_FSIMR 0x0050 -#define REG_FSISR 0x0054 -#define REG_HSIMR 0x0058 -#define REG_HSISR 0x005c -/* RTL8723 WIFI/BT/GPS Multi-Function GPIO Pin Control. */ -#define REG_GPIO_PIN_CTRL_2 0x0060 -/* RTL8723 WIFI/BT/GPS Multi-Function GPIO Select. */ -#define REG_GPIO_IO_SEL_2 0x0062 -#define GPIO_IO_SEL_2_GPIO09_INPUT BIT(1) -#define GPIO_IO_SEL_2_GPIO09_IRQ BIT(9) - -/* RTL8723B */ -#define REG_PAD_CTRL1 0x0064 -#define PAD_CTRL1_SW_DPDT_SEL_DATA BIT(0) - -/* RTL8723 only WIFI/BT/GPS Multi-Function control source. */ -#define REG_MULTI_FUNC_CTRL 0x0068 - -#define MULTI_FN_WIFI_HW_PWRDOWN_EN BIT(0) /* Enable GPIO[9] as WiFi HW - powerdown source */ -#define MULTI_FN_WIFI_HW_PWRDOWN_SL BIT(1) /* WiFi HW powerdown polarity - control */ -#define MULTI_WIFI_FUNC_EN BIT(2) /* WiFi function enable */ - -#define MULTI_WIFI_HW_ROF_EN BIT(3) /* Enable GPIO[9] as WiFi RF HW - powerdown source */ -#define MULTI_BT_HW_PWRDOWN_EN BIT(16) /* Enable GPIO[11] as BT HW - powerdown source */ -#define MULTI_BT_HW_PWRDOWN_SL BIT(17) /* BT HW powerdown polarity - control */ -#define MULTI_BT_FUNC_EN BIT(18) /* BT function enable */ -#define MULTI_BT_HW_ROF_EN BIT(19) /* Enable GPIO[11] as BT/GPS - RF HW powerdown source */ -#define MULTI_GPS_HW_PWRDOWN_EN BIT(20) /* Enable GPIO[10] as GPS HW - powerdown source */ -#define MULTI_GPS_HW_PWRDOWN_SL BIT(21) /* GPS HW powerdown polarity - control */ -#define MULTI_GPS_FUNC_EN BIT(22) /* GPS function enable */ - -#define REG_AFE_CTRL4 0x0078 /* 8192eu/8723bu */ -#define REG_LDO_SW_CTRL 0x007c /* 8192eu */ - -#define REG_MCU_FW_DL 0x0080 -#define MCU_FW_DL_ENABLE BIT(0) -#define MCU_FW_DL_READY BIT(1) -#define MCU_FW_DL_CSUM_REPORT BIT(2) -#define MCU_MAC_INIT_READY BIT(3) -#define MCU_BB_INIT_READY BIT(4) -#define MCU_RF_INIT_READY BIT(5) -#define MCU_WINT_INIT_READY BIT(6) -#define MCU_FW_RAM_SEL BIT(7) /* 1: RAM, 0:ROM */ -#define MCU_CP_RESET BIT(23) - -#define REG_HMBOX_EXT_0 0x0088 -#define REG_HMBOX_EXT_1 0x008a -#define REG_HMBOX_EXT_2 0x008c -#define REG_HMBOX_EXT_3 0x008e - -#define REG_RSVD_1 0x0097 - -/* Interrupt registers for 8192e/8723bu/8812 */ -#define REG_HIMR0 0x00b0 -#define IMR0_TXCCK BIT(30) /* TXRPT interrupt when CCX bit - of the packet is set */ -#define IMR0_PSTIMEOUT BIT(29) /* Power Save Time Out Int */ -#define IMR0_GTINT4 BIT(28) /* Set when GTIMER4 expires */ -#define IMR0_GTINT3 BIT(27) /* Set when GTIMER3 expires */ -#define IMR0_TBDER BIT(26) /* Transmit Beacon0 Error */ -#define IMR0_TBDOK BIT(25) /* Transmit Beacon0 OK */ -#define IMR0_TSF_BIT32_TOGGLE BIT(24) /* TSF Timer BIT32 toggle - indication interrupt */ -#define IMR0_BCNDMAINT0 BIT(20) /* Beacon DMA Interrupt 0 */ -#define IMR0_BCNDERR0 BIT(16) /* Beacon Queue DMA Error 0 */ -#define IMR0_HSISR_IND_ON_INT BIT(15) /* HSISR Indicator (HSIMR & - HSISR is true) */ -#define IMR0_BCNDMAINT_E BIT(14) /* Beacon DMA Interrupt - Extension for Win7 */ -#define IMR0_ATIMEND BIT(12) /* CTWidnow End or - ATIM Window End */ -#define IMR0_HISR1_IND_INT BIT(11) /* HISR1 Indicator - (HISR1 & HIMR1 is true) */ -#define IMR0_C2HCMD BIT(10) /* CPU to Host Command INT - Status, Write 1 to clear */ -#define IMR0_CPWM2 BIT(9) /* CPU power Mode exchange INT - Status, Write 1 to clear */ -#define IMR0_CPWM BIT(8) /* CPU power Mode exchange INT - Status, Write 1 to clear */ -#define IMR0_HIGHDOK BIT(7) /* High Queue DMA OK */ -#define IMR0_MGNTDOK BIT(6) /* Management Queue DMA OK */ -#define IMR0_BKDOK BIT(5) /* AC_BK DMA OK */ -#define IMR0_BEDOK BIT(4) /* AC_BE DMA OK */ -#define IMR0_VIDOK BIT(3) /* AC_VI DMA OK */ -#define IMR0_VODOK BIT(2) /* AC_VO DMA OK */ -#define IMR0_RDU BIT(1) /* Rx Descriptor Unavailable */ -#define IMR0_ROK BIT(0) /* Receive DMA OK */ -#define REG_HISR0 0x00b4 -#define REG_HIMR1 0x00b8 -#define IMR1_BCNDMAINT7 BIT(27) /* Beacon DMA Interrupt 7 */ -#define IMR1_BCNDMAINT6 BIT(26) /* Beacon DMA Interrupt 6 */ -#define IMR1_BCNDMAINT5 BIT(25) /* Beacon DMA Interrupt 5 */ -#define IMR1_BCNDMAINT4 BIT(24) /* Beacon DMA Interrupt 4 */ -#define IMR1_BCNDMAINT3 BIT(23) /* Beacon DMA Interrupt 3 */ -#define IMR1_BCNDMAINT2 BIT(22) /* Beacon DMA Interrupt 2 */ -#define IMR1_BCNDMAINT1 BIT(21) /* Beacon DMA Interrupt 1 */ -#define IMR1_BCNDERR7 BIT(20) /* Beacon Queue DMA Err Int 7 */ -#define IMR1_BCNDERR6 BIT(19) /* Beacon Queue DMA Err Int 6 */ -#define IMR1_BCNDERR5 BIT(18) /* Beacon Queue DMA Err Int 5 */ -#define IMR1_BCNDERR4 BIT(17) /* Beacon Queue DMA Err Int 4 */ -#define IMR1_BCNDERR3 BIT(16) /* Beacon Queue DMA Err Int 3 */ -#define IMR1_BCNDERR2 BIT(15) /* Beacon Queue DMA Err Int 2 */ -#define IMR1_BCNDERR1 BIT(14) /* Beacon Queue DMA Err Int 1 */ -#define IMR1_ATIMEND_E BIT(13) /* ATIM Window End Extension - for Win7 */ -#define IMR1_TXERR BIT(11) /* Tx Error Flag Int Status, - write 1 to clear */ -#define IMR1_RXERR BIT(10) /* Rx Error Flag Int Status, - write 1 to clear */ -#define IMR1_TXFOVW BIT(9) /* Transmit FIFO Overflow */ -#define IMR1_RXFOVW BIT(8) /* Receive FIFO Overflow */ -#define REG_HISR1 0x00bc - -/* Host suspend counter on FPGA platform */ -#define REG_HOST_SUSP_CNT 0x00bc -/* Efuse access protection for RTL8723 */ -#define REG_EFUSE_ACCESS 0x00cf -#define REG_BIST_SCAN 0x00d0 -#define REG_BIST_RPT 0x00d4 -#define REG_BIST_ROM_RPT 0x00d8 -#define REG_RSVD_4 0x00dc -#define REG_USB_SIE_INTF 0x00e0 -#define REG_PCIE_MIO_INTF 0x00e4 -#define REG_PCIE_MIO_INTD 0x00e8 -#define REG_HPON_FSM 0x00ec -#define HPON_FSM_BONDING_MASK (BIT(22) | BIT(23)) -#define HPON_FSM_BONDING_1T2R BIT(22) -#define REG_SYS_CFG 0x00f0 -#define SYS_CFG_XCLK_VLD BIT(0) -#define SYS_CFG_ACLK_VLD BIT(1) -#define SYS_CFG_UCLK_VLD BIT(2) -#define SYS_CFG_PCLK_VLD BIT(3) -#define SYS_CFG_PCIRSTB BIT(4) -#define SYS_CFG_V15_VLD BIT(5) -#define SYS_CFG_TRP_B15V_EN BIT(7) -#define SYS_CFG_SW_OFFLOAD_EN BIT(7) /* For chips with IOL support */ -#define SYS_CFG_SIC_IDLE BIT(8) -#define SYS_CFG_BD_MAC2 BIT(9) -#define SYS_CFG_BD_MAC1 BIT(10) -#define SYS_CFG_IC_MACPHY_MODE BIT(11) -#define SYS_CFG_CHIP_VER (BIT(12) | BIT(13) | BIT(14) | BIT(15)) -#define SYS_CFG_BT_FUNC BIT(16) -#define SYS_CFG_VENDOR_ID BIT(19) -#define SYS_CFG_VENDOR_EXT_MASK (BIT(18) | BIT(19)) -#define SYS_CFG_VENDOR_ID_TSMC 0 -#define SYS_CFG_VENDOR_ID_SMIC BIT(18) -#define SYS_CFG_VENDOR_ID_UMC BIT(19) -#define SYS_CFG_PAD_HWPD_IDN BIT(22) -#define SYS_CFG_TRP_VAUX_EN BIT(23) -#define SYS_CFG_TRP_BT_EN BIT(24) -#define SYS_CFG_SPS_LDO_SEL BIT(24) /* 8192eu */ -#define SYS_CFG_BD_PKG_SEL BIT(25) -#define SYS_CFG_BD_HCI_SEL BIT(26) -#define SYS_CFG_TYPE_ID BIT(27) -#define SYS_CFG_RTL_ID BIT(23) /* TestChip ID, - 1:Test(RLE); 0:MP(RL) */ -#define SYS_CFG_SPS_SEL BIT(24) /* 1:LDO regulator mode; - 0:Switching regulator mode*/ -#define SYS_CFG_CHIP_VERSION_MASK 0xf000 /* Bit 12 - 15 */ - -#define REG_GPIO_OUTSTS 0x00f4 /* For RTL8723 only. */ -#define GPIO_EFS_HCI_SEL (BIT(0) | BIT(1)) -#define GPIO_PAD_HCI_SEL (BIT(2) | BIT(3)) -#define GPIO_HCI_SEL (BIT(4) | BIT(5)) -#define GPIO_PKG_SEL_HCI BIT(6) -#define GPIO_FEN_GPS BIT(7) -#define GPIO_FEN_BT BIT(8) -#define GPIO_FEN_WL BIT(9) -#define GPIO_FEN_PCI BIT(10) -#define GPIO_FEN_USB BIT(11) -#define GPIO_BTRF_HWPDN_N BIT(12) -#define GPIO_WLRF_HWPDN_N BIT(13) -#define GPIO_PDN_BT_N BIT(14) -#define GPIO_PDN_GPS_N BIT(15) -#define GPIO_BT_CTL_HWPDN BIT(16) -#define GPIO_GPS_CTL_HWPDN BIT(17) -#define GPIO_PPHY_SUSB BIT(20) -#define GPIO_UPHY_SUSB BIT(21) -#define GPIO_PCI_SUSEN BIT(22) -#define GPIO_USB_SUSEN BIT(23) -#define GPIO_RF_RL_ID (BIT(31) | BIT(30) | BIT(29) | BIT(28)) - -#define REG_SYS_CFG2 0x00fc /* 8192eu */ - -/* 0x0100 ~ 0x01FF MACTOP General Configuration */ -#define REG_CR 0x0100 -#define CR_HCI_TXDMA_ENABLE BIT(0) -#define CR_HCI_RXDMA_ENABLE BIT(1) -#define CR_TXDMA_ENABLE BIT(2) -#define CR_RXDMA_ENABLE BIT(3) -#define CR_PROTOCOL_ENABLE BIT(4) -#define CR_SCHEDULE_ENABLE BIT(5) -#define CR_MAC_TX_ENABLE BIT(6) -#define CR_MAC_RX_ENABLE BIT(7) -#define CR_SW_BEACON_ENABLE BIT(8) -#define CR_SECURITY_ENABLE BIT(9) -#define CR_CALTIMER_ENABLE BIT(10) - -/* Media Status Register */ -#define REG_MSR 0x0102 -#define MSR_LINKTYPE_MASK 0x3 -#define MSR_LINKTYPE_NONE 0x0 -#define MSR_LINKTYPE_ADHOC 0x1 -#define MSR_LINKTYPE_STATION 0x2 -#define MSR_LINKTYPE_AP 0x3 - -#define REG_PBP 0x0104 -#define PBP_PAGE_SIZE_RX_SHIFT 0 -#define PBP_PAGE_SIZE_TX_SHIFT 4 -#define PBP_PAGE_SIZE_64 0x0 -#define PBP_PAGE_SIZE_128 0x1 -#define PBP_PAGE_SIZE_256 0x2 -#define PBP_PAGE_SIZE_512 0x3 -#define PBP_PAGE_SIZE_1024 0x4 - -/* 8188eu IOL magic */ -#define REG_PKT_BUF_ACCESS_CTRL 0x0106 -#define PKT_BUF_ACCESS_CTRL_TX 0x69 -#define PKT_BUF_ACCESS_CTRL_RX 0xa5 - -#define REG_TRXDMA_CTRL 0x010c -#define TRXDMA_CTRL_RXDMA_AGG_EN BIT(2) -#define TRXDMA_CTRL_VOQ_SHIFT 4 -#define TRXDMA_CTRL_VIQ_SHIFT 6 -#define TRXDMA_CTRL_BEQ_SHIFT 8 -#define TRXDMA_CTRL_BKQ_SHIFT 10 -#define TRXDMA_CTRL_MGQ_SHIFT 12 -#define TRXDMA_CTRL_HIQ_SHIFT 14 -#define TRXDMA_CTRL_VOQ_SHIFT_8192F 4 -#define TRXDMA_CTRL_VIQ_SHIFT_8192F 7 -#define TRXDMA_CTRL_BEQ_SHIFT_8192F 10 -#define TRXDMA_CTRL_BKQ_SHIFT_8192F 13 -#define TRXDMA_CTRL_MGQ_SHIFT_8192F 16 -#define TRXDMA_CTRL_HIQ_SHIFT_8192F 19 -#define TRXDMA_QUEUE_LOW 1 -#define TRXDMA_QUEUE_NORMAL 2 -#define TRXDMA_QUEUE_HIGH 3 - -#define REG_TRXFF_BNDY 0x0114 -#define REG_TRXFF_STATUS 0x0118 -#define REG_RXFF_PTR 0x011c -#define REG_HIMR 0x0120 -#define REG_HISR 0x0124 -#define REG_HIMRE 0x0128 -#define REG_HISRE 0x012c -#define REG_CPWM 0x012f -#define REG_FWIMR 0x0130 -#define REG_FWISR 0x0134 -#define REG_FTIMR 0x0138 -#define REG_PKTBUF_DBG_CTRL 0x0140 -#define REG_PKTBUF_DBG_DATA_L 0x0144 -#define REG_PKTBUF_DBG_DATA_H 0x0148 - -#define REG_TC0_CTRL 0x0150 -#define REG_TC1_CTRL 0x0154 -#define REG_TC2_CTRL 0x0158 -#define REG_TC3_CTRL 0x015c -#define REG_TC4_CTRL 0x0160 -#define REG_TCUNIT_BASE 0x0164 -#define REG_MBIST_START 0x0174 -#define REG_MBIST_DONE 0x0178 -#define REG_MBIST_FAIL 0x017c -/* 8188EU */ -#define REG_32K_CTRL 0x0194 -#define REG_C2HEVT_MSG_NORMAL 0x01a0 -/* 8192EU/8723BU/8812 */ -#define REG_C2HEVT_CMD_ID_8723B 0x01ae -#define REG_C2HEVT_CLEAR 0x01af -#define REG_C2HEVT_MSG_TEST 0x01b8 -#define REG_MCUTST_1 0x01c0 -#define REG_FMTHR 0x01c8 -#define REG_HMTFR 0x01cc -#define REG_HMBOX_0 0x01d0 -#define REG_HMBOX_1 0x01d4 -#define REG_HMBOX_2 0x01d8 -#define REG_HMBOX_3 0x01dc - -#define REG_LLT_INIT 0x01e0 -#define LLT_OP_INACTIVE 0x0 -#define LLT_OP_WRITE (0x1 << 30) -#define LLT_OP_READ (0x2 << 30) -#define LLT_OP_MASK (0x3 << 30) - -#define REG_BB_ACCESS_CTRL 0x01e8 -#define REG_BB_ACCESS_DATA 0x01ec - -#define REG_HMBOX_EXT0_8723B 0x01f0 -#define REG_HMBOX_EXT1_8723B 0x01f4 -#define REG_HMBOX_EXT2_8723B 0x01f8 -#define REG_HMBOX_EXT3_8723B 0x01fc - -/* 0x0200 ~ 0x027F TXDMA Configuration */ -#define REG_RQPN 0x0200 -#define RQPN_HI_PQ_SHIFT 0 -#define RQPN_LO_PQ_SHIFT 8 -#define RQPN_PUB_PQ_SHIFT 16 -#define RQPN_LOAD BIT(31) - -#define REG_FIFOPAGE 0x0204 -#define REG_TDECTRL 0x0208 -#define BIT_BCN_VALID BIT(16) - -#define REG_DWBCN0_CTRL_8188F REG_TDECTRL - -#define REG_TXDMA_OFFSET_CHK 0x020c -#define TXDMA_OFFSET_DROP_DATA_EN BIT(9) -#define REG_TXDMA_STATUS 0x0210 -#define REG_RQPN_NPQ 0x0214 -#define RQPN_NPQ_SHIFT 0 -#define RQPN_EPQ_SHIFT 16 - -#define REG_AUTO_LLT 0x0224 -#define AUTO_LLT_INIT_LLT BIT(16) - -#define REG_DWBCN1_CTRL_8723B 0x0228 -#define BIT_SW_BCN_SEL BIT(20) - -/* 0x0280 ~ 0x02FF RXDMA Configuration */ -#define REG_RXDMA_AGG_PG_TH 0x0280 /* 0-7 : USB DMA size bits - 8-14: USB DMA timeout - 15 : Aggregation enable - Only seems to be used - on 8723bu/8192eu */ -#define RXDMA_USB_AGG_ENABLE BIT(31) -#define REG_RXPKT_NUM 0x0284 -#define RXPKT_NUM_RXDMA_IDLE BIT(17) -#define RXPKT_NUM_RW_RELEASE_EN BIT(18) -#define REG_RXDMA_STATUS 0x0288 - -/* Presumably only found on newer chips such as 8723bu */ -#define REG_RX_DMA_CTRL_8723B 0x0286 -#define REG_RXDMA_PRO_8723B 0x0290 -#define RXDMA_PRO_DMA_MODE BIT(1) /* Set to 0x1. */ -#define RXDMA_PRO_DMA_BURST_CNT GENMASK(3, 2) /* Set to 0x3. */ -#define RXDMA_PRO_DMA_BURST_SIZE GENMASK(5, 4) /* Set to 0x1. */ - -#define REG_EARLY_MODE_CONTROL_8710B 0x02bc - -#define REG_RF_BB_CMD_ADDR 0x02c0 -#define REG_RF_BB_CMD_DATA 0x02c4 - -/* spec version 11 */ -/* 0x0400 ~ 0x047F Protocol Configuration */ -/* 8192c, 8192d */ -#define REG_VOQ_INFO 0x0400 -#define REG_VIQ_INFO 0x0404 -#define REG_BEQ_INFO 0x0408 -#define REG_BKQ_INFO 0x040c -/* 8188e, 8723a, 8812a, 8821a, 8192e, 8723b */ -#define REG_Q0_INFO 0x400 -#define REG_Q1_INFO 0x404 -#define REG_Q2_INFO 0x408 -#define REG_Q3_INFO 0x40c - -#define REG_MGQ_INFO 0x0410 -#define REG_HGQ_INFO 0x0414 -#define REG_BCNQ_INFO 0x0418 - -#define REG_CPU_MGQ_INFORMATION 0x041c -#define REG_FWHW_TXQ_CTRL 0x0420 -#define FWHW_TXQ_CTRL_AMPDU_RETRY BIT(7) -#define FWHW_TXQ_CTRL_XMIT_MGMT_ACK BIT(12) -#define EN_BCNQ_DL BIT(22) - -#define REG_HWSEQ_CTRL 0x0423 -#define REG_TXPKTBUF_BCNQ_BDNY 0x0424 -#define REG_TXPKTBUF_MGQ_BDNY 0x0425 -#define REG_LIFETIME_EN 0x0426 -#define REG_MULTI_BCNQ_OFFSET 0x0427 - -#define REG_SPEC_SIFS 0x0428 -#define SPEC_SIFS_CCK_MASK 0x00ff -#define SPEC_SIFS_CCK_SHIFT 0 -#define SPEC_SIFS_OFDM_MASK 0xff00 -#define SPEC_SIFS_OFDM_SHIFT 8 - -#define REG_RETRY_LIMIT 0x042a -#define RETRY_LIMIT_LONG_SHIFT 0 -#define RETRY_LIMIT_LONG_MASK 0x003f -#define RETRY_LIMIT_SHORT_SHIFT 8 -#define RETRY_LIMIT_SHORT_MASK 0x3f00 - -#define REG_DARFRC 0x0430 -#define REG_RARFRC 0x0438 -#define REG_RESPONSE_RATE_SET 0x0440 -#define RESPONSE_RATE_BITMAP_ALL 0xfffff -#define RESPONSE_RATE_RRSR_CCK_ONLY_1M 0xffff1 -#define RESPONSE_RATE_RRSR_INIT_2G 0x15f -#define RESPONSE_RATE_RRSR_INIT_5G 0x150 -#define RSR_1M BIT(0) -#define RSR_2M BIT(1) -#define RSR_5_5M BIT(2) -#define RSR_11M BIT(3) -#define RSR_6M BIT(4) -#define RSR_9M BIT(5) -#define RSR_12M BIT(6) -#define RSR_18M BIT(7) -#define RSR_24M BIT(8) -#define RSR_36M BIT(9) -#define RSR_48M BIT(10) -#define RSR_54M BIT(11) -#define RSR_MCS0 BIT(12) -#define RSR_MCS1 BIT(13) -#define RSR_MCS2 BIT(14) -#define RSR_MCS3 BIT(15) -#define RSR_MCS4 BIT(16) -#define RSR_MCS5 BIT(17) -#define RSR_MCS6 BIT(18) -#define RSR_MCS7 BIT(19) -#define RSR_RSC_LOWER_SUB_CHANNEL BIT(21) /* 0x200000 */ -#define RSR_RSC_UPPER_SUB_CHANNEL BIT(22) /* 0x400000 */ -#define RSR_RSC_BANDWIDTH_40M (RSR_RSC_UPPER_SUB_CHANNEL | \ - RSR_RSC_LOWER_SUB_CHANNEL) -#define RSR_ACK_SHORT_PREAMBLE BIT(23) - -#define REG_ARFR0 0x0444 -#define REG_ARFR1 0x0448 -#define REG_ARFR2 0x044c -#define REG_ARFR3 0x0450 -#define REG_CCK_CHECK 0x0454 -#define BIT_BCN_PORT_SEL BIT(5) -#define REG_AMPDU_MAX_TIME_8723B 0x0456 -#define REG_AGGLEN_LMT 0x0458 -#define REG_AMPDU_MIN_SPACE 0x045c -#define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045d -#define REG_FAST_EDCA_CTRL 0x0460 -#define REG_RD_RESP_PKT_TH 0x0463 -#define REG_INIRTS_RATE_SEL 0x0480 -/* 8723bu */ -#define REG_DATA_SUBCHANNEL 0x0483 -/* 8723au */ -#define REG_INIDATA_RATE_SEL 0x0484 -/* MACID_SLEEP_1/3 for 8723b, 8192e, 8812a, 8821a */ -#define REG_MACID_SLEEP_3_8732B 0x0484 -#define REG_MACID_SLEEP_1_8732B 0x0488 - -#define REG_POWER_STATUS 0x04a4 -#define REG_POWER_STAGE1 0x04b4 -#define REG_POWER_STAGE2 0x04b8 -#define REG_AMPDU_BURST_MODE_8723B 0x04bc -#define REG_PKT_VO_VI_LIFE_TIME 0x04c0 -#define REG_PKT_BE_BK_LIFE_TIME 0x04c2 -#define REG_STBC_SETTING 0x04c4 -#define REG_QUEUE_CTRL 0x04c6 -#define REG_HT_SINGLE_AMPDU_8723B 0x04c7 -#define HT_SINGLE_AMPDU_ENABLE BIT(7) -#define REG_PROT_MODE_CTRL 0x04c8 -#define REG_MAX_AGGR_NUM 0x04ca -#define REG_RTS_MAX_AGGR_NUM 0x04cb -#define REG_BAR_MODE_CTRL 0x04cc -#define REG_RA_TRY_RATE_AGG_LMT 0x04cf -/* MACID_DROP for 8723a */ -#define REG_MACID_DROP_8732A 0x04d0 -/* EARLY_MODE_CONTROL 8188e */ -#define REG_EARLY_MODE_CONTROL_8188E 0x04d0 -/* MACID_SLEEP_2 for 8723b, 8192e, 8812a, 8821a */ -#define REG_MACID_SLEEP_2_8732B 0x04d0 -#define REG_MACID_SLEEP 0x04d4 -#define REG_NQOS_SEQ 0x04dc -#define REG_QOS_SEQ 0x04de -#define REG_NEED_CPU_HANDLE 0x04e0 -#define REG_PKT_LOSE_RPT 0x04e1 -#define REG_PTCL_ERR_STATUS 0x04e2 -#define REG_TX_REPORT_CTRL 0x04ec -#define TX_REPORT_CTRL_TIMER_ENABLE BIT(1) - -#define REG_TX_REPORT_TIME 0x04f0 -#define REG_DUMMY 0x04fc - -/* 0x0500 ~ 0x05FF EDCA Configuration */ -#define REG_EDCA_VO_PARAM 0x0500 -#define REG_EDCA_VI_PARAM 0x0504 -#define REG_EDCA_BE_PARAM 0x0508 -#define REG_EDCA_BK_PARAM 0x050c -#define EDCA_PARAM_ECW_MIN_SHIFT 8 -#define EDCA_PARAM_ECW_MAX_SHIFT 12 -#define EDCA_PARAM_TXOP_SHIFT 16 -#define REG_BEACON_TCFG 0x0510 -#define REG_PIFS 0x0512 -#define REG_RDG_PIFS 0x0513 -#define REG_SIFS_CCK 0x0514 -#define REG_SIFS_OFDM 0x0516 -#define REG_TSFTR_SYN_OFFSET 0x0518 -#define REG_AGGR_BREAK_TIME 0x051a -#define REG_SLOT 0x051b -#define REG_TX_PTCL_CTRL 0x0520 -#define REG_TXPAUSE 0x0522 -#define REG_DIS_TXREQ_CLR 0x0523 -#define REG_RD_CTRL 0x0524 -#define REG_TBTT_PROHIBIT 0x0540 -#define REG_RD_NAV_NXT 0x0544 -#define REG_NAV_PROT_LEN 0x0546 - -#define REG_BEACON_CTRL 0x0550 -#define REG_BEACON_CTRL_1 0x0551 -#define BEACON_ATIM BIT(0) -#define BEACON_CTRL_MBSSID BIT(1) -#define BEACON_CTRL_TX_BEACON_RPT BIT(2) -#define BEACON_FUNCTION_ENABLE BIT(3) -#define BEACON_DISABLE_TSF_UPDATE BIT(4) - -#define REG_MBID_NUM 0x0552 -#define REG_DUAL_TSF_RST 0x0553 -#define DUAL_TSF_RESET_TSF0 BIT(0) -#define DUAL_TSF_RESET_TSF1 BIT(1) -#define DUAL_TSF_RESET_P2P BIT(4) -#define DUAL_TSF_TX_OK BIT(5) - -/* The same as REG_MBSSID_BCN_SPACE */ -#define REG_BCN_INTERVAL 0x0554 -#define REG_MBSSID_BCN_SPACE 0x0554 - -#define REG_DRIVER_EARLY_INT 0x0558 -#define DRIVER_EARLY_INT_TIME 5 - -#define REG_BEACON_DMA_TIME 0x0559 -#define BEACON_DMA_ATIME_INT_TIME 2 - -#define REG_ATIMWND 0x055a -#define REG_USTIME_TSF_8723B 0x055c -#define REG_BCN_MAX_ERR 0x055d -#define REG_RXTSF_OFFSET_CCK 0x055e -#define REG_RXTSF_OFFSET_OFDM 0x055f -#define REG_TSFTR 0x0560 -#define REG_TSFTR1 0x0568 -#define REG_INIT_TSFTR 0x0564 -#define REG_ATIMWND_1 0x0570 -#define REG_PSTIMER 0x0580 -#define REG_TIMER0 0x0584 -#define REG_TIMER1 0x0588 -#define REG_ACM_HW_CTRL 0x05c0 -#define ACM_HW_CTRL_BK BIT(0) -#define ACM_HW_CTRL_BE BIT(1) -#define ACM_HW_CTRL_VI BIT(2) -#define ACM_HW_CTRL_VO BIT(3) -#define REG_ACM_RST_CTRL 0x05c1 -#define REG_ACMAVG 0x05c2 -#define REG_VO_ADMTIME 0x05c4 -#define REG_VI_ADMTIME 0x05c6 -#define REG_BE_ADMTIME 0x05c8 -#define REG_EDCA_RANDOM_GEN 0x05cc -#define REG_SCH_TXCMD 0x05d0 - -/* define REG_FW_TSF_SYNC_CNT 0x04a0 */ -#define REG_SCH_TX_CMD 0x05f8 -#define REG_FW_RESET_TSF_CNT_1 0x05fc -#define REG_FW_RESET_TSF_CNT_0 0x05fd -#define REG_FW_BCN_DIS_CNT 0x05fe - -/* 0x0600 ~ 0x07FF WMAC Configuration */ -#define REG_APSD_CTRL 0x0600 -#define APSD_CTRL_OFF BIT(6) -#define APSD_CTRL_OFF_STATUS BIT(7) -#define REG_BW_OPMODE 0x0603 -#define BW_OPMODE_20MHZ BIT(2) -#define BW_OPMODE_5G BIT(1) -#define BW_OPMODE_11J BIT(0) - -#define REG_TCR 0x0604 - -/* Receive Configuration Register */ -#define REG_RCR 0x0608 -#define RCR_ACCEPT_AP BIT(0) /* Accept all unicast packet */ -#define RCR_ACCEPT_PHYS_MATCH BIT(1) /* Accept phys match packet */ -#define RCR_ACCEPT_MCAST BIT(2) -#define RCR_ACCEPT_BCAST BIT(3) -#define RCR_ACCEPT_ADDR3 BIT(4) /* Accept address 3 match - packet */ -#define RCR_ACCEPT_PM BIT(5) /* Accept power management - packet */ -#define RCR_CHECK_BSSID_MATCH BIT(6) /* Accept BSSID match packet */ -#define RCR_CHECK_BSSID_BEACON BIT(7) /* Accept BSSID match packet - (Rx beacon, probe rsp) */ -#define RCR_ACCEPT_CRC32 BIT(8) /* Accept CRC32 error packet */ -#define RCR_ACCEPT_ICV BIT(9) /* Accept ICV error packet */ -#define RCR_ACCEPT_DATA_FRAME BIT(11) /* Accept all data pkt or use - REG_RXFLTMAP2 */ -#define RCR_ACCEPT_CTRL_FRAME BIT(12) /* Accept all control pkt or use - REG_RXFLTMAP1 */ -#define RCR_ACCEPT_MGMT_FRAME BIT(13) /* Accept all mgmt pkt or use - REG_RXFLTMAP0 */ -#define RCR_HTC_LOC_CTRL BIT(14) /* MFC<--HTC=1 MFC-->HTC=0 */ -#define RCR_UC_DATA_PKT_INT_ENABLE BIT(16) /* Enable unicast data packet - interrupt */ -#define RCR_BM_DATA_PKT_INT_ENABLE BIT(17) /* Enable broadcast data packet - interrupt */ -#define RCR_TIM_PARSER_ENABLE BIT(18) /* Enable RX beacon TIM parser*/ -#define RCR_MFBEN BIT(22) -#define RCR_LSIG_ENABLE BIT(23) /* Enable LSIG TXOP Protection - function. Search KEYCAM for - each rx packet to check if - LSIGEN bit is set. */ -#define RCR_MULTI_BSSID_ENABLE BIT(24) /* Enable Multiple BssId */ -#define RCR_FORCE_ACK BIT(26) -#define RCR_ACCEPT_BA_SSN BIT(27) /* Accept BA SSN */ -#define RCR_APPEND_PHYSTAT BIT(28) -#define RCR_APPEND_ICV BIT(29) -#define RCR_APPEND_MIC BIT(30) -#define RCR_APPEND_FCS BIT(31) /* WMAC append FCS after */ - -#define REG_RX_PKT_LIMIT 0x060c -#define REG_RX_DLK_TIME 0x060d -#define REG_RX_DRVINFO_SZ 0x060f - -#define REG_MACID 0x0610 -#define REG_BSSID 0x0618 -#define REG_MAR 0x0620 -#define REG_MBIDCAMCFG 0x0628 - -#define REG_USTIME_EDCA 0x0638 -#define REG_MAC_SPEC_SIFS 0x063a - -/* 20100719 Joseph: Hardware register definition change. (HW datasheet v54) */ - /* [15:8]SIFS_R2T_OFDM, [7:0]SIFS_R2T_CCK */ -#define REG_R2T_SIFS 0x063c - /* [15:8]SIFS_T2T_OFDM, [7:0]SIFS_T2T_CCK */ -#define REG_T2T_SIFS 0x063e -#define REG_ACKTO 0x0640 -#define REG_CTS2TO 0x0641 -#define REG_EIFS 0x0642 - -/* WMA, BA, CCX */ -#define REG_NAV_CTRL 0x0650 -/* In units of 128us */ -#define REG_NAV_UPPER 0x0652 -#define NAV_UPPER_UNIT 128 - -#define REG_BACAMCMD 0x0654 -#define REG_BACAMCONTENT 0x0658 -#define REG_LBDLY 0x0660 -#define REG_FWDLY 0x0661 -#define REG_RXERR_RPT 0x0664 -#define REG_WMAC_TRXPTCL_CTL 0x0668 -#define WMAC_TRXPTCL_CTL_BW_MASK (BIT(7) | BIT(8)) -#define WMAC_TRXPTCL_CTL_BW_20 0 -#define WMAC_TRXPTCL_CTL_BW_40 BIT(7) -#define WMAC_TRXPTCL_CTL_BW_80 BIT(8) - -/* Security */ -#define REG_CAM_CMD 0x0670 -#define CAM_CMD_POLLING BIT(31) -#define CAM_CMD_WRITE BIT(16) -#define CAM_CMD_KEY_SHIFT 3 -#define REG_CAM_WRITE 0x0674 -#define CAM_WRITE_VALID BIT(15) -#define REG_CAM_READ 0x0678 -#define REG_CAM_DEBUG 0x067c -#define REG_SECURITY_CFG 0x0680 -#define SEC_CFG_TX_USE_DEFKEY BIT(0) -#define SEC_CFG_RX_USE_DEFKEY BIT(1) -#define SEC_CFG_TX_SEC_ENABLE BIT(2) -#define SEC_CFG_RX_SEC_ENABLE BIT(3) -#define SEC_CFG_SKBYA2 BIT(4) -#define SEC_CFG_NO_SKMC BIT(5) -#define SEC_CFG_TXBC_USE_DEFKEY BIT(6) -#define SEC_CFG_RXBC_USE_DEFKEY BIT(7) - -/* Power */ -#define REG_WOW_CTRL 0x0690 -#define REG_PSSTATUS 0x0691 -#define REG_PS_RX_INFO 0x0692 -#define REG_LPNAV_CTRL 0x0694 -#define REG_WKFMCAM_CMD 0x0698 -#define REG_WKFMCAM_RWD 0x069c - -/* - * RX Filters: each bit corresponds to the numerical value of the subtype. - * If it is set the subtype frame type is passed. The filter is only used when - * the RCR_ACCEPT_DATA_FRAME, RCR_ACCEPT_CTRL_FRAME, RCR_ACCEPT_MGMT_FRAME bit - * in the RCR are low. - * - * Example: Beacon subtype is binary 1000 which is decimal 8 so we have to set - * bit 8 (0x100) in REG_RXFLTMAP0 to enable reception. - */ -#define REG_RXFLTMAP0 0x06a0 /* Management frames */ -#define REG_RXFLTMAP1 0x06a2 /* Control frames */ -#define REG_RXFLTMAP2 0x06a4 /* Data frames */ - -#define REG_BCN_PSR_RPT 0x06a8 -#define REG_CALB32K_CTRL 0x06ac -#define REG_PKT_MON_CTRL 0x06b4 -#define REG_BT_COEX_TABLE1 0x06c0 -#define REG_BT_COEX_TABLE2 0x06c4 -#define REG_BT_COEX_TABLE3 0x06c8 -#define REG_BT_COEX_TABLE4 0x06cc -#define REG_WMAC_RESP_TXINFO 0x06d8 - -#define REG_MACID1 0x0700 -#define REG_BSSID1 0x0708 - -/* - * This seems to be 8723bu specific - */ -#define REG_BT_CONTROL_8723BU 0x0764 -#define BT_CONTROL_BT_GRANT BIT(12) - -#define REG_PORT_CONTROL_8710B 0x076d -#define REG_WLAN_ACT_CONTROL_8723B 0x076e - -#define REG_FPGA0_RF_MODE 0x0800 -#define FPGA_RF_MODE BIT(0) -#define FPGA_RF_MODE_JAPAN BIT(1) -#define FPGA_RF_MODE_CCK BIT(24) -#define FPGA_RF_MODE_OFDM BIT(25) - -#define REG_FPGA0_TX_INFO 0x0804 -#define FPGA0_TX_INFO_OFDM_PATH_A BIT(0) -#define FPGA0_TX_INFO_OFDM_PATH_B BIT(1) -#define FPGA0_TX_INFO_OFDM_PATH_C BIT(2) -#define FPGA0_TX_INFO_OFDM_PATH_D BIT(3) -#define REG_FPGA0_PSD_FUNC 0x0808 -#define REG_FPGA0_TX_GAIN 0x080c -#define REG_FPGA0_RF_TIMING1 0x0810 -#define REG_FPGA0_RF_TIMING2 0x0814 -#define REG_FPGA0_POWER_SAVE 0x0818 -#define FPGA0_PS_LOWER_CHANNEL BIT(26) -#define FPGA0_PS_UPPER_CHANNEL BIT(27) - -#define REG_FPGA0_XA_HSSI_PARM1 0x0820 /* RF 3 wire register */ -#define FPGA0_HSSI_PARM1_PI BIT(8) -#define REG_FPGA0_XA_HSSI_PARM2 0x0824 -#define REG_FPGA0_XB_HSSI_PARM1 0x0828 -#define REG_FPGA0_XB_HSSI_PARM2 0x082c -#define FPGA0_HSSI_3WIRE_DATA_LEN 0x800 -#define FPGA0_HSSI_3WIRE_ADDR_LEN 0x400 -#define FPGA0_HSSI_PARM2_ADDR_SHIFT 23 -#define FPGA0_HSSI_PARM2_ADDR_MASK 0x7f800000 /* 0xff << 23 */ -#define FPGA0_HSSI_PARM2_CCK_HIGH_PWR BIT(9) -#define FPGA0_HSSI_PARM2_EDGE_READ BIT(31) - -#define REG_TX_AGC_B_RATE18_06 0x0830 -#define REG_TX_AGC_B_RATE54_24 0x0834 -#define REG_TX_AGC_B_CCK1_55_MCS32 0x0838 -#define REG_TX_AGC_B_MCS03_MCS00 0x083c - -#define REG_FPGA0_XA_LSSI_PARM 0x0840 -#define REG_FPGA0_XB_LSSI_PARM 0x0844 -#define FPGA0_LSSI_PARM_ADDR_SHIFT 20 -#define FPGA0_LSSI_PARM_ADDR_MASK 0x0ff00000 -#define FPGA0_LSSI_PARM_DATA_MASK 0x000fffff - -#define REG_TX_AGC_B_MCS07_MCS04 0x0848 -#define REG_TX_AGC_B_MCS11_MCS08 0x084c - -#define REG_FPGA0_XCD_SWITCH_CTRL 0x085c - -#define REG_FPGA0_XA_RF_INT_OE 0x0860 /* RF Channel switch */ -#define REG_FPGA0_XB_RF_INT_OE 0x0864 -#define FPGA0_INT_OE_ANTENNA_AB_OPEN 0x000 -#define FPGA0_INT_OE_ANTENNA_A BIT(8) -#define FPGA0_INT_OE_ANTENNA_B BIT(9) -#define FPGA0_INT_OE_ANTENNA_MASK (FPGA0_INT_OE_ANTENNA_A | \ - FPGA0_INT_OE_ANTENNA_B) - -#define REG_TX_AGC_B_MCS15_MCS12 0x0868 -#define REG_TX_AGC_B_CCK11_A_CCK2_11 0x086c - -#define REG_FPGA0_XAB_RF_SW_CTRL 0x0870 -#define REG_FPGA0_XA_RF_SW_CTRL 0x0870 /* 16 bit */ -#define REG_FPGA0_XB_RF_SW_CTRL 0x0872 /* 16 bit */ -#define REG_FPGA0_XCD_RF_SW_CTRL 0x0874 -#define REG_FPGA0_XC_RF_SW_CTRL 0x0874 /* 16 bit */ -#define REG_FPGA0_XD_RF_SW_CTRL 0x0876 /* 16 bit */ -#define FPGA0_RF_3WIRE_DATA BIT(0) -#define FPGA0_RF_3WIRE_CLOC BIT(1) -#define FPGA0_RF_3WIRE_LOAD BIT(2) -#define FPGA0_RF_3WIRE_RW BIT(3) -#define FPGA0_RF_3WIRE_MASK 0xf -#define FPGA0_RF_RFENV BIT(4) -#define FPGA0_RF_TRSW BIT(5) /* Useless now */ -#define FPGA0_RF_TRSWB BIT(6) -#define FPGA0_RF_ANTSW BIT(8) -#define FPGA0_RF_ANTSWB BIT(9) -#define FPGA0_RF_PAPE BIT(10) -#define FPGA0_RF_PAPE5G BIT(11) -#define FPGA0_RF_BD_CTRL_SHIFT 16 - -#define REG_FPGA0_XAB_RF_PARM 0x0878 /* Antenna select path in ODM */ -#define REG_FPGA0_XA_RF_PARM 0x0878 /* 16 bit */ -#define REG_FPGA0_XB_RF_PARM 0x087a /* 16 bit */ -#define REG_FPGA0_XCD_RF_PARM 0x087c -#define REG_FPGA0_XC_RF_PARM 0x087c /* 16 bit */ -#define REG_FPGA0_XD_RF_PARM 0x087e /* 16 bit */ -#define FPGA0_RF_PARM_RFA_ENABLE BIT(1) -#define FPGA0_RF_PARM_RFB_ENABLE BIT(17) -#define FPGA0_RF_PARM_CLK_GATE BIT(31) - -#define REG_FPGA0_ANALOG1 0x0880 -#define REG_FPGA0_ANALOG2 0x0884 -#define FPGA0_ANALOG2_20MHZ BIT(10) -#define REG_FPGA0_ANALOG3 0x0888 -#define REG_FPGA0_ANALOG4 0x088c - -#define REG_NHM_TH9_TH10_8723B 0x0890 -#define REG_NHM_TIMER_8723B 0x0894 -#define REG_NHM_TH3_TO_TH0_8723B 0x0898 -#define REG_NHM_TH7_TO_TH4_8723B 0x089c - -#define REG_FPGA0_XA_LSSI_READBACK 0x08a0 /* Tranceiver LSSI Readback */ -#define REG_FPGA0_XB_LSSI_READBACK 0x08a4 -#define REG_FPGA0_PSD_REPORT 0x08b4 -#define REG_HSPI_XA_READBACK 0x08b8 /* Transceiver A HSPI read */ -#define REG_HSPI_XB_READBACK 0x08bc /* Transceiver B HSPI read */ - -#define REG_FPGA1_RF_MODE 0x0900 - -#define REG_FPGA1_TX_INFO 0x090c -#define FPGA1_TX_ANT_MASK 0x0000000f -#define FPGA1_TX_ANT_L_MASK 0x000000f0 -#define FPGA1_TX_ANT_NON_HT_MASK 0x00000f00 -#define FPGA1_TX_ANT_HT1_MASK 0x0000f000 -#define FPGA1_TX_ANT_HT2_MASK 0x000f0000 -#define FPGA1_TX_ANT_HT_S1_MASK 0x00f00000 -#define FPGA1_TX_ANT_NON_HT_S1_MASK 0x0f000000 -#define FPGA1_TX_OFDM_TXSC_MASK 0x30000000 - -#define REG_ANT_MAPPING1 0x0914 -#define REG_RFE_OPT 0x0920 -#define REG_DPDT_CTRL 0x092c /* 8723BU */ -#define REG_RFE_CTRL_ANTA_SRC 0x0930 /* 8723BU */ -#define REG_RFE_CTRL_ANT_SRC1 0x0934 -#define REG_RFE_CTRL_ANT_SRC2 0x0938 -#define REG_RFE_CTRL_ANT_SRC3 0x093c -#define REG_RFE_PATH_SELECT 0x0940 /* 8723BU */ -#define REG_RFE_BUFFER 0x0944 /* 8723BU */ -#define REG_S0S1_PATH_SWITCH 0x0948 /* 8723BU */ -#define REG_RX_DFIR_MOD_97F 0x0948 -#define REG_OFDM_RX_DFIR 0x954 -#define REG_RFE_OPT62 0x0968 - -#define REG_CCK0_SYSTEM 0x0a00 -#define CCK0_SIDEBAND BIT(4) - -#define REG_CCK0_AFE_SETTING 0x0a04 -#define CCK0_AFE_RX_MASK 0x0f000000 -#define CCK0_AFE_TX_MASK 0xf0000000 -#define CCK0_AFE_RX_ANT_A 0 -#define CCK0_AFE_RX_ANT_B BIT(26) -#define CCK0_AFE_RX_ANT_C BIT(27) -#define CCK0_AFE_RX_ANT_D (BIT(26) | BIT(27)) -#define CCK0_AFE_RX_ANT_OPTION_A 0 -#define CCK0_AFE_RX_ANT_OPTION_B BIT(24) -#define CCK0_AFE_RX_ANT_OPTION_C BIT(25) -#define CCK0_AFE_RX_ANT_OPTION_D (BIT(24) | BIT(25)) -#define CCK0_AFE_TX_ANT_A BIT(31) -#define CCK0_AFE_TX_ANT_B BIT(30) - -#define REG_CCK_ANTDIV_PARA2 0x0a04 -#define REG_BB_POWER_SAVE4 0x0a74 - -/* 8188eu */ -#define REG_LNA_SWITCH 0x0b2c -#define LNA_SWITCH_DISABLE_CSCG BIT(22) -#define LNA_SWITCH_OUTPUT_CG BIT(31) - -#define REG_CCK_PD_THRESH 0x0a0a -#define CCK_PD_TYPE1_LV0_TH 0x40 -#define CCK_PD_TYPE1_LV1_TH 0x83 -#define CCK_PD_TYPE1_LV2_TH 0xcd -#define CCK_PD_TYPE1_LV3_TH 0xdd -#define CCK_PD_TYPE1_LV4_TH 0xed - -#define REG_CCK0_TX_FILTER1 0x0a20 -#define REG_CCK0_TX_FILTER2 0x0a24 -#define REG_CCK0_DEBUG_PORT 0x0a28 /* debug port and Tx filter3 */ -#define REG_AGC_RPT 0xa80 -#define AGC_RPT_CCK BIT(7) -#define REG_CCK0_TX_FILTER3 0x0aac - -#define REG_CONFIG_ANT_A 0x0b68 -#define REG_CONFIG_ANT_B 0x0b6c - -#define REG_OFDM0_TRX_PATH_ENABLE 0x0c04 -#define OFDM_RF_PATH_RX_MASK 0x0f -#define OFDM_RF_PATH_RX_A BIT(0) -#define OFDM_RF_PATH_RX_B BIT(1) -#define OFDM_RF_PATH_RX_C BIT(2) -#define OFDM_RF_PATH_RX_D BIT(3) -#define OFDM_RF_PATH_TX_MASK 0xf0 -#define OFDM_RF_PATH_TX_A BIT(4) -#define OFDM_RF_PATH_TX_B BIT(5) -#define OFDM_RF_PATH_TX_C BIT(6) -#define OFDM_RF_PATH_TX_D BIT(7) - -#define REG_OFDM0_TR_MUX_PAR 0x0c08 - -#define REG_OFDM0_FA_RSTC 0x0c0c - -#define REG_DOWNSAM_FACTOR 0x0c10 - -#define REG_OFDM0_XA_RX_AFE 0x0c10 -#define REG_OFDM0_XA_RX_IQ_IMBALANCE 0x0c14 -#define REG_OFDM0_XB_RX_IQ_IMBALANCE 0x0c1c - -#define REG_OFDM0_ENERGY_CCA_THRES 0x0c4c - -#define REG_OFDM0_RX_D_SYNC_PATH 0x0c40 -#define OFDM0_SYNC_PATH_NOTCH_FILTER BIT(1) - -#define REG_OFDM0_XA_AGC_CORE1 0x0c50 -#define REG_OFDM0_XA_AGC_CORE2 0x0c54 -#define REG_OFDM0_XB_AGC_CORE1 0x0c58 -#define REG_OFDM0_XB_AGC_CORE2 0x0c5c -#define REG_OFDM0_XC_AGC_CORE1 0x0c60 -#define REG_OFDM0_XC_AGC_CORE2 0x0c64 -#define REG_OFDM0_XD_AGC_CORE1 0x0c68 -#define REG_OFDM0_XD_AGC_CORE2 0x0c6c -#define OFDM0_X_AGC_CORE1_IGI_MASK 0x0000007F - -#define REG_OFDM0_AGC_PARM1 0x0c70 - -#define REG_OFDM0_AGC_RSSI_TABLE 0x0c78 - -#define REG_OFDM0_XA_TX_IQ_IMBALANCE 0x0c80 -#define REG_OFDM0_XB_TX_IQ_IMBALANCE 0x0c88 -#define REG_OFDM0_XC_TX_IQ_IMBALANCE 0x0c90 -#define REG_OFDM0_XD_TX_IQ_IMBALANCE 0x0c98 - -#define REG_OFDM0_XC_TX_AFE 0x0c94 -#define REG_OFDM0_XD_TX_AFE 0x0c9c - -#define REG_OFDM0_RX_IQ_EXT_ANTA 0x0ca0 - -/* 8188eu */ -#define REG_ANTDIV_PARA1 0x0ca4 - -#define REG_RXIQB_EXT 0x0ca8 - -/* 8723bu */ -#define REG_OFDM0_TX_PSDO_NOISE_WEIGHT 0x0ce4 - -#define REG_OFDM1_LSTF 0x0d00 -#define OFDM_LSTF_PRIME_CH_LOW BIT(10) -#define OFDM_LSTF_PRIME_CH_HIGH BIT(11) -#define OFDM_LSTF_PRIME_CH_MASK (OFDM_LSTF_PRIME_CH_LOW | \ - OFDM_LSTF_PRIME_CH_HIGH) -#define OFDM_LSTF_CONTINUE_TX BIT(28) -#define OFDM_LSTF_SINGLE_CARRIER BIT(29) -#define OFDM_LSTF_SINGLE_TONE BIT(30) -#define OFDM_LSTF_MASK 0x70000000 - -#define REG_OFDM1_TRX_PATH_ENABLE 0x0d04 -#define REG_OFDM1_CFO_TRACKING 0x0d2c -#define CFO_TRACKING_ATC_STATUS BIT(11) -#define REG_OFDM1_CSI_FIX_MASK1 0x0d40 -#define REG_OFDM1_CSI_FIX_MASK2 0x0d44 - -#define REG_ANAPWR1 0x0d94 - -#define REG_TX_AGC_A_RATE18_06 0x0e00 -#define REG_TX_AGC_A_RATE54_24 0x0e04 -#define REG_TX_AGC_A_CCK1_MCS32 0x0e08 -#define REG_TX_AGC_A_MCS03_MCS00 0x0e10 -#define REG_TX_AGC_A_MCS07_MCS04 0x0e14 -#define REG_TX_AGC_A_MCS11_MCS08 0x0e18 -#define REG_TX_AGC_A_MCS15_MCS12 0x0e1c - -#define REG_NP_ANTA 0x0e20 - -#define REG_TAP_UPD_97F 0x0e24 - -#define REG_FPGA0_IQK 0x0e28 - -#define REG_TX_IQK_TONE_A 0x0e30 -#define REG_RX_IQK_TONE_A 0x0e34 -#define REG_TX_IQK_PI_A 0x0e38 -#define REG_RX_IQK_PI_A 0x0e3c - -#define REG_TX_IQK 0x0e40 -#define REG_RX_IQK 0x0e44 -#define REG_IQK_AGC_PTS 0x0e48 -#define REG_IQK_AGC_RSP 0x0e4c -#define REG_TX_IQK_TONE_B 0x0e50 -#define REG_RX_IQK_TONE_B 0x0e54 -#define REG_TX_IQK_PI_B 0x0e58 -#define REG_RX_IQK_PI_B 0x0e5c -#define REG_IQK_AGC_CONT 0x0e60 - -#define REG_BLUETOOTH 0x0e6c -#define REG_RX_WAIT_CCA 0x0e70 -#define REG_TX_CCK_RFON 0x0e74 -#define REG_TX_CCK_BBON 0x0e78 -#define REG_TX_OFDM_RFON 0x0e7c -#define REG_TX_OFDM_BBON 0x0e80 -#define REG_TX_TO_RX 0x0e84 -#define REG_TX_TO_TX 0x0e88 -#define REG_RX_CCK 0x0e8c - -#define REG_TX_POWER_BEFORE_IQK_A 0x0e94 -#define REG_IQK_RPT_TXA 0x0e98 -#define REG_TX_POWER_AFTER_IQK_A 0x0e9c - -#define REG_RX_POWER_BEFORE_IQK_A 0x0ea0 -#define REG_RX_POWER_BEFORE_IQK_A_2 0x0ea4 -#define REG_RX_POWER_AFTER_IQK_A 0x0ea8 -#define REG_IQK_RPT_RXA 0x0ea8 -#define REG_RX_POWER_AFTER_IQK_A_2 0x0eac - -#define REG_TX_POWER_BEFORE_IQK_B 0x0eb4 -#define REG_IQK_RPT_TXB 0x0eb8 -#define REG_TX_POWER_AFTER_IQK_B 0x0ebc - -#define REG_RX_POWER_BEFORE_IQK_B 0x0ec0 -#define REG_RX_POWER_BEFORE_IQK_B_2 0x0ec4 -#define REG_RX_POWER_AFTER_IQK_B 0x0ec8 -#define REG_IQK_RPT_RXB 0x0ec8 -#define REG_RX_POWER_AFTER_IQK_B_2 0x0ecc - -#define REG_RX_OFDM 0x0ed0 -#define REG_RX_WAIT_RIFS 0x0ed4 -#define REG_RX_TO_RX 0x0ed8 -#define REG_STANDBY 0x0edc -#define REG_SLEEP 0x0ee0 -#define REG_PMPD_ANAEN 0x0eec - -#define REG_FW_START_ADDRESS 0x1000 -#define REG_FW_START_ADDRESS_8192F 0x4000 - -#define REG_SW_GPIO_SHARE_CTRL_0 0x1038 -#define REG_SW_GPIO_SHARE_CTRL_1 0x103c -#define REG_GPIO_A0 0x1050 -#define REG_GPIO_B0 0x105b - -#define REG_USB_INFO 0xfe17 -#define REG_USB_HIMR 0xfe38 -#define USB_HIMR_TIMEOUT2 BIT(31) -#define USB_HIMR_TIMEOUT1 BIT(30) -#define USB_HIMR_PSTIMEOUT BIT(29) -#define USB_HIMR_GTINT4 BIT(28) -#define USB_HIMR_GTINT3 BIT(27) -#define USB_HIMR_TXBCNERR BIT(26) -#define USB_HIMR_TXBCNOK BIT(25) -#define USB_HIMR_TSF_BIT32_TOGGLE BIT(24) -#define USB_HIMR_BCNDMAINT3 BIT(23) -#define USB_HIMR_BCNDMAINT2 BIT(22) -#define USB_HIMR_BCNDMAINT1 BIT(21) -#define USB_HIMR_BCNDMAINT0 BIT(20) -#define USB_HIMR_BCNDOK3 BIT(19) -#define USB_HIMR_BCNDOK2 BIT(18) -#define USB_HIMR_BCNDOK1 BIT(17) -#define USB_HIMR_BCNDOK0 BIT(16) -#define USB_HIMR_HSISR_IND BIT(15) -#define USB_HIMR_BCNDMAINT_E BIT(14) -/* RSVD BIT(13) */ -#define USB_HIMR_CTW_END BIT(12) -/* RSVD BIT(11) */ -#define USB_HIMR_C2HCMD BIT(10) -#define USB_HIMR_CPWM2 BIT(9) -#define USB_HIMR_CPWM BIT(8) -#define USB_HIMR_HIGHDOK BIT(7) /* High Queue DMA OK - Interrupt */ -#define USB_HIMR_MGNTDOK BIT(6) /* Management Queue DMA OK - Interrupt */ -#define USB_HIMR_BKDOK BIT(5) /* AC_BK DMA OK Interrupt */ -#define USB_HIMR_BEDOK BIT(4) /* AC_BE DMA OK Interrupt */ -#define USB_HIMR_VIDOK BIT(3) /* AC_VI DMA OK Interrupt */ -#define USB_HIMR_VODOK BIT(2) /* AC_VO DMA Interrupt */ -#define USB_HIMR_RDU BIT(1) /* Receive Descriptor - Unavailable */ -#define USB_HIMR_ROK BIT(0) /* Receive DMA OK Interrupt */ - -#define REG_USB_ACCESS_TIMEOUT 0xfe4c - -#define REG_USB_SPECIAL_OPTION 0xfe55 -#define USB_SPEC_USB_AGG_ENABLE BIT(3) /* Enable USB aggregation */ -#define USB_SPEC_INT_BULK_SELECT BIT(4) /* Use interrupt endpoint to - deliver interrupt packet. - 0: Use int, 1: use bulk */ -#define REG_USB_HRPWM 0xfe58 -#define REG_USB_DMA_AGG_TO 0xfe5b -#define REG_USB_AGG_TIMEOUT 0xfe5c -#define REG_USB_AGG_THRESH 0xfe5d - -#define REG_NORMAL_SIE_VID 0xfe60 /* 0xfe60 - 0xfe61 */ -#define REG_NORMAL_SIE_PID 0xfe62 /* 0xfe62 - 0xfe63 */ -#define REG_NORMAL_SIE_OPTIONAL 0xfe64 -#define REG_NORMAL_SIE_EP 0xfe65 /* 0xfe65 - 0xfe67 */ -#define REG_NORMAL_SIE_EP_TX 0xfe66 -#define NORMAL_SIE_EP_TX_HIGH_MASK 0x000f -#define NORMAL_SIE_EP_TX_NORMAL_MASK 0x00f0 -#define NORMAL_SIE_EP_TX_LOW_MASK 0x0f00 - -#define REG_NORMAL_SIE_PHY 0xfe68 /* 0xfe68 - 0xfe6b */ -#define REG_NORMAL_SIE_OPTIONAL2 0xfe6c -#define REG_NORMAL_SIE_GPS_EP 0xfe6d /* RTL8723 only */ -#define REG_NORMAL_SIE_MAC_ADDR 0xfe70 /* 0xfe70 - 0xfe75 */ -#define REG_NORMAL_SIE_STRING 0xfe80 /* 0xfe80 - 0xfedf */ - -/* - * 8710B register addresses between 0x00 and 0xff must have 0x8000 - * added to them. We take care of that in the rtl8xxxu_read{8,16,32} - * and rtl8xxxu_write{8,16,32} functions. - */ -#define REG_SYS_FUNC_8710B 0x0004 -#define REG_AFE_CTRL_8710B 0x0050 -#define REG_WL_RF_PSS_8710B 0x005c -#define REG_EFUSE_INDIRECT_CTRL_8710B 0x006c -#define NORMAL_REG_READ_OFFSET 0x83000000 -#define NORMAL_REG_WRITE_OFFSET 0x84000000 -#define EFUSE_READ_OFFSET 0x85000000 -#define EFUSE_WRITE_OFFSET 0x86000000 -#define REG_HIMR0_8710B 0x0080 -#define REG_HISR0_8710B 0x0084 -/* - * 8710B uses this instead of REG_MCU_FW_DL, but at least bits - * 0-7 have the same meaning. - */ -#define REG_8051FW_CTRL_V1_8710B 0x0090 -#define REG_USB_HOST_INDIRECT_DATA_8710B 0x009c -#define REG_WL_STATUS_8710B 0x00f0 -#define REG_USB_HOST_INDIRECT_ADDR_8710B 0x00f8 - -/* - * 8710B registers which must be accessed through rtl8710b_read_syson_reg - * and rtl8710b_write_syson_reg. - */ -#define SYSON_REG_BASE_ADDR_8710B 0x40000000 -#define REG_SYS_XTAL_CTRL0_8710B 0x060 -#define REG_SYS_EEPROM_CTRL0_8710B 0x0e0 -#define REG_SYS_SYSTEM_CFG0_8710B 0x1f0 -#define REG_SYS_SYSTEM_CFG1_8710B 0x1f4 -#define REG_SYS_SYSTEM_CFG2_8710B 0x1f8 - -/* RF6052 registers */ -#define RF6052_REG_AC 0x00 -#define RF6052_REG_IQADJ_G1 0x01 -#define RF6052_REG_IQADJ_G2 0x02 -#define RF6052_REG_BS_PA_APSET_G1_G4 0x03 -#define RF6052_REG_BS_PA_APSET_G5_G8 0x04 -#define RF6052_REG_POW_TRSW 0x05 -#define RF6052_REG_GAIN_RX 0x06 -#define RF6052_REG_GAIN_TX 0x07 -#define RF6052_REG_TXM_IDAC 0x08 -#define RF6052_REG_IPA_G 0x09 -#define RF6052_REG_TXBIAS_G 0x0a -#define RF6052_REG_TXPA_AG 0x0b -#define RF6052_REG_IPA_A 0x0c -#define RF6052_REG_TXBIAS_A 0x0d -#define RF6052_REG_BS_PA_APSET_G9_G11 0x0e -#define RF6052_REG_BS_IQGEN 0x0f -#define RF6052_REG_MODE1 0x10 -#define RF6052_REG_MODE2 0x11 -#define RF6052_REG_RX_AGC_HP 0x12 -#define RF6052_REG_TX_AGC 0x13 -#define RF6052_REG_BIAS 0x14 -#define RF6052_REG_IPA 0x15 -#define RF6052_REG_TXBIAS 0x16 -#define RF6052_REG_POW_ABILITY 0x17 -#define RF6052_REG_MODE_AG 0x18 /* RF channel and BW switch */ -#define MODE_AG_CHANNEL_MASK 0x3ff -#define MODE_AG_CHANNEL_20MHZ BIT(10) -#define MODE_AG_BW_MASK (BIT(10) | BIT(11)) -#define MODE_AG_BW_20MHZ_8723B (BIT(10) | BIT(11)) -#define MODE_AG_BW_40MHZ_8723B BIT(10) -#define MODE_AG_BW_80MHZ_8723B 0 - -#define RF6052_REG_TOP 0x19 -#define RF6052_REG_RX_G1 0x1a -#define RF6052_REG_RX_G2 0x1b -#define RF6052_REG_RX_BB2 0x1c -#define RF6052_REG_RX_BB1 0x1d -#define RF6052_REG_RCK1 0x1e -#define RF6052_REG_RCK2 0x1f -#define RF6052_REG_TX_G1 0x20 -#define RF6052_REG_TX_G2 0x21 -#define RF6052_REG_TX_G3 0x22 -#define RF6052_REG_TX_BB1 0x23 -#define RF6052_REG_T_METER 0x24 -#define RF6052_REG_SYN_G1 0x25 /* RF TX Power control */ -#define RF6052_REG_SYN_G2 0x26 /* RF TX Power control */ -#define RF6052_REG_SYN_G3 0x27 /* RF TX Power control */ -#define RF6052_REG_SYN_G4 0x28 /* RF TX Power control */ -#define RF6052_REG_SYN_G5 0x29 /* RF TX Power control */ -#define RF6052_REG_SYN_G6 0x2a /* RF TX Power control */ -#define RF6052_REG_SYN_G7 0x2b /* RF TX Power control */ -#define RF6052_REG_SYN_G8 0x2c /* RF TX Power control */ - -#define RF6052_REG_RCK_OS 0x30 /* RF TX PA control */ - -#define RF6052_REG_TXPA_G1 0x31 /* RF TX PA control */ -#define RF6052_REG_TXPA_G2 0x32 /* RF TX PA control */ -#define RF6052_REG_TXPA_G3 0x33 /* RF TX PA control */ - -/* - * NextGen regs: 8723BU - */ -#define RF6052_REG_GAIN_P1 0x35 -#define RF6052_REG_T_METER_8723B 0x42 -#define RF6052_REG_UNKNOWN_43 0x43 -#define RF6052_REG_UNKNOWN_55 0x55 -#define RF6052_REG_PAD_TXG 0x56 -#define RF6052_REG_TXMOD 0x58 -#define RF6052_REG_RXG_MIX_SWBW 0x87 -#define RF6052_REG_S0S1 0xb0 -#define RF6052_REG_GAIN_CCA 0xdf -#define RF6052_REG_UNKNOWN_ED 0xed -#define RF6052_REG_WE_LUT 0xef -#define RF6052_REG_GAIN_CTRL 0xf5 -- cgit v1.2.3 From 949f6f3aeb8721ad092d704ef10f5c5e79472d64 Mon Sep 17 00:00:00 2001 From: Ping-Ke Shih Date: Mon, 29 Apr 2024 10:47:11 +0800 Subject: wifi: rtl8xxxu: cleanup includes Remove unnecessary includes from driver. The first step is to add necessary includes to driver's header files to make them can be included individually. Then, driver's C files include driver's header files first, and check if still missed header files of kernel. The results show that most C files only include driver's header files. Only core.c needs to include additional linux/firmware.h. Also sort includes in alphabetic order. Compile tested only. Signed-off-by: Ping-Ke Shih Link: https://msgid.link/20240429024711.30992-1-pkshih@realtek.com --- drivers/net/wireless/realtek/rtl8xxxu/8188e.c | 14 +------------- drivers/net/wireless/realtek/rtl8xxxu/8188f.c | 14 +------------- drivers/net/wireless/realtek/rtl8xxxu/8192c.c | 14 +------------- drivers/net/wireless/realtek/rtl8xxxu/8192e.c | 14 +------------- drivers/net/wireless/realtek/rtl8xxxu/8192f.c | 14 +------------- drivers/net/wireless/realtek/rtl8xxxu/8710b.c | 14 +------------- drivers/net/wireless/realtek/rtl8xxxu/8723a.c | 14 +------------- drivers/net/wireless/realtek/rtl8xxxu/8723b.c | 14 +------------- drivers/net/wireless/realtek/rtl8xxxu/core.c | 13 +------------ drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h | 3 ++- 10 files changed, 11 insertions(+), 117 deletions(-) (limited to 'drivers/net/wireless/realtek/rtl8xxxu') diff --git a/drivers/net/wireless/realtek/rtl8xxxu/8188e.c b/drivers/net/wireless/realtek/rtl8xxxu/8188e.c index 60fb0bffd4ed..3d04df0f5bf4 100644 --- a/drivers/net/wireless/realtek/rtl8xxxu/8188e.c +++ b/drivers/net/wireless/realtek/rtl8xxxu/8188e.c @@ -13,20 +13,8 @@ * additional 8xxx chips like the 8192cu, 8188cus, etc. */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "rtl8xxxu.h" #include "regs.h" +#include "rtl8xxxu.h" static const struct rtl8xxxu_reg8val rtl8188e_mac_init_table[] = { {0x026, 0x41}, {0x027, 0x35}, {0x040, 0x00}, {0x421, 0x0f}, diff --git a/drivers/net/wireless/realtek/rtl8xxxu/8188f.c b/drivers/net/wireless/realtek/rtl8xxxu/8188f.c index 296370414134..bd5a0603b4a2 100644 --- a/drivers/net/wireless/realtek/rtl8xxxu/8188f.c +++ b/drivers/net/wireless/realtek/rtl8xxxu/8188f.c @@ -11,20 +11,8 @@ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "rtl8xxxu.h" #include "regs.h" +#include "rtl8xxxu.h" static const struct rtl8xxxu_reg8val rtl8188f_mac_init_table[] = { {0x024, 0xDF}, {0x025, 0x07}, {0x02B, 0x1C}, {0x283, 0x20}, diff --git a/drivers/net/wireless/realtek/rtl8xxxu/8192c.c b/drivers/net/wireless/realtek/rtl8xxxu/8192c.c index b1c5a9971617..0abb1b092bc2 100644 --- a/drivers/net/wireless/realtek/rtl8xxxu/8192c.c +++ b/drivers/net/wireless/realtek/rtl8xxxu/8192c.c @@ -13,20 +13,8 @@ * additional 8xxx chips like the 8192cu, 8188cus, etc. */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "rtl8xxxu.h" #include "regs.h" +#include "rtl8xxxu.h" #ifdef CONFIG_RTL8XXXU_UNTESTED static struct rtl8xxxu_power_base rtl8192c_power_base = { diff --git a/drivers/net/wireless/realtek/rtl8xxxu/8192e.c b/drivers/net/wireless/realtek/rtl8xxxu/8192e.c index 562173176c60..8e123bbfc665 100644 --- a/drivers/net/wireless/realtek/rtl8xxxu/8192e.c +++ b/drivers/net/wireless/realtek/rtl8xxxu/8192e.c @@ -13,20 +13,8 @@ * additional 8xxx chips like the 8192cu, 8188cus, etc. */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "rtl8xxxu.h" #include "regs.h" +#include "rtl8xxxu.h" static const struct rtl8xxxu_reg8val rtl8192e_mac_init_table[] = { {0x011, 0xeb}, {0x012, 0x07}, {0x014, 0x75}, {0x303, 0xa7}, diff --git a/drivers/net/wireless/realtek/rtl8xxxu/8192f.c b/drivers/net/wireless/realtek/rtl8xxxu/8192f.c index 843ff0269b39..cd2156b7a57a 100644 --- a/drivers/net/wireless/realtek/rtl8xxxu/8192f.c +++ b/drivers/net/wireless/realtek/rtl8xxxu/8192f.c @@ -11,20 +11,8 @@ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "rtl8xxxu.h" #include "regs.h" +#include "rtl8xxxu.h" static const struct rtl8xxxu_reg8val rtl8192f_mac_init_table[] = { {0x420, 0x00}, {0x422, 0x78}, {0x428, 0x0a}, {0x429, 0x10}, diff --git a/drivers/net/wireless/realtek/rtl8xxxu/8710b.c b/drivers/net/wireless/realtek/rtl8xxxu/8710b.c index ea1cb0d8554e..11c63c320eae 100644 --- a/drivers/net/wireless/realtek/rtl8xxxu/8710b.c +++ b/drivers/net/wireless/realtek/rtl8xxxu/8710b.c @@ -11,20 +11,8 @@ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "rtl8xxxu.h" #include "regs.h" +#include "rtl8xxxu.h" static const struct rtl8xxxu_reg8val rtl8710b_mac_init_table[] = { {0x421, 0x0F}, {0x428, 0x0A}, {0x429, 0x10}, {0x430, 0x00}, diff --git a/drivers/net/wireless/realtek/rtl8xxxu/8723a.c b/drivers/net/wireless/realtek/rtl8xxxu/8723a.c index 9f03bf163c97..ecbc324e4609 100644 --- a/drivers/net/wireless/realtek/rtl8xxxu/8723a.c +++ b/drivers/net/wireless/realtek/rtl8xxxu/8723a.c @@ -13,20 +13,8 @@ * additional 8xxx chips like the 8192cu, 8188cus, etc. */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "rtl8xxxu.h" #include "regs.h" +#include "rtl8xxxu.h" static struct rtl8xxxu_power_base rtl8723a_power_base = { .reg_0e00 = 0x0a0c0c0c, diff --git a/drivers/net/wireless/realtek/rtl8xxxu/8723b.c b/drivers/net/wireless/realtek/rtl8xxxu/8723b.c index 0880049373b0..cc2e60b06f64 100644 --- a/drivers/net/wireless/realtek/rtl8xxxu/8723b.c +++ b/drivers/net/wireless/realtek/rtl8xxxu/8723b.c @@ -13,20 +13,8 @@ * additional 8xxx chips like the 8192cu, 8188cus, etc. */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "rtl8xxxu.h" #include "regs.h" +#include "rtl8xxxu.h" static const struct rtl8xxxu_reg8val rtl8723b_mac_init_table[] = { {0x02f, 0x30}, {0x035, 0x00}, {0x039, 0x08}, {0x04e, 0xe0}, diff --git a/drivers/net/wireless/realtek/rtl8xxxu/core.c b/drivers/net/wireless/realtek/rtl8xxxu/core.c index cda05a6e4772..89a841b4e8d5 100644 --- a/drivers/net/wireless/realtek/rtl8xxxu/core.c +++ b/drivers/net/wireless/realtek/rtl8xxxu/core.c @@ -13,20 +13,9 @@ * additional 8xxx chips like the 8192cu, 8188cus, etc. */ -#include -#include -#include -#include -#include -#include -#include -#include -#include #include -#include -#include -#include "rtl8xxxu.h" #include "regs.h" +#include "rtl8xxxu.h" #define DRIVER_NAME "rtl8xxxu" diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h index c28ff9dde625..f42463e595cc 100644 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h +++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h @@ -5,8 +5,9 @@ * Register definitions taken from original Realtek rtl8723au driver */ -#include #include +#include +#include #define RTL8XXXU_DEBUG_REG_WRITE 0x01 #define RTL8XXXU_DEBUG_REG_READ 0x02 -- cgit v1.2.3