From cbd06cdedf779b8bb0d2fd8f468a21b8e85db9c2 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 10 Nov 2022 22:22:41 +0300 Subject: phy: qcom-qmp-ufs: split UFS-specific v2 PCS registers to a separate header Follow other QMP headers, split and rename UFS-specific PCS registers to ease comparing regs differences. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20221110192248.873973-7-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v2.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v2.h (limited to 'drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v2.h') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v2.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v2.h new file mode 100644 index 000000000000..af870669a904 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v2.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_PCS_UFS_V2_H_ +#define QCOM_PHY_QMP_PCS_UFS_V2_H_ + +#define QPHY_V2_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x034 +#define QPHY_V2_PCS_UFS_TX_LARGE_AMP_POST_EMP_LVL 0x038 +#define QPHY_V2_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x03c +#define QPHY_V2_PCS_UFS_TX_SMALL_AMP_POST_EMP_LVL 0x040 + +#define QPHY_V2_PCS_UFS_RX_MIN_STALL_NOCONFIG_TIME_CAP 0x0cc +#define QPHY_V2_PCS_UFS_RX_SYM_RESYNC_CTRL 0x13c +#define QPHY_V2_PCS_UFS_RX_MIN_HIBERN8_TIME 0x140 +#define QPHY_V2_PCS_UFS_RX_SIGDET_CTRL2 0x148 +#define QPHY_V2_PCS_UFS_RX_PWM_GEAR_BAND 0x154 + +#endif -- cgit v1.2.3 From 3b4bf465dd34d57cec2b1757d1e2b2395fe08f6a Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 10 Nov 2022 22:22:42 +0300 Subject: phy: qcom-qmp-ufs: rework regs layout arrays Use symbolic names for the values inside reg layout arrays. New register names are added following the PCS register layout that is used by the particular PHY. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20221110192248.873973-8-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v2.h | 5 +++++ drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v3.h | 3 +++ drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 18 +++++++++--------- 3 files changed, 17 insertions(+), 9 deletions(-) (limited to 'drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v2.h') diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v2.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v2.h index af870669a904..a0803a8783d2 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v2.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v2.h @@ -6,6 +6,9 @@ #ifndef QCOM_PHY_QMP_PCS_UFS_V2_H_ #define QCOM_PHY_QMP_PCS_UFS_V2_H_ +#define QPHY_V2_PCS_UFS_PHY_START 0x000 +#define QPHY_V2_PCS_UFS_POWER_DOWN_CONTROL 0x004 + #define QPHY_V2_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x034 #define QPHY_V2_PCS_UFS_TX_LARGE_AMP_POST_EMP_LVL 0x038 #define QPHY_V2_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x03c @@ -17,4 +20,6 @@ #define QPHY_V2_PCS_UFS_RX_SIGDET_CTRL2 0x148 #define QPHY_V2_PCS_UFS_RX_PWM_GEAR_BAND 0x154 +#define QPHY_V2_PCS_UFS_READY_STATUS 0x168 + #endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v3.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v3.h index ba1ea29d2884..adea13c3a9e6 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v3.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v3.h @@ -6,12 +6,15 @@ #ifndef QCOM_PHY_QMP_PCS_UFS_V3_H_ #define QCOM_PHY_QMP_PCS_UFS_V3_H_ +#define QPHY_V3_PCS_UFS_PHY_START 0x000 +#define QPHY_V3_PCS_UFS_POWER_DOWN_CONTROL 0x004 #define QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x02c #define QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x034 #define QPHY_V3_PCS_UFS_RX_SYM_RESYNC_CTRL 0x134 #define QPHY_V3_PCS_UFS_RX_MIN_HIBERN8_TIME 0x138 #define QPHY_V3_PCS_UFS_RX_SIGDET_CTRL1 0x13c #define QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2 0x140 +#define QPHY_V3_PCS_UFS_READY_STATUS 0x160 #define QPHY_V3_PCS_UFS_TX_MID_TERM_CTRL1 0x1bc #define QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1 0x1c4 diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index b352d38b9e31..7ccd7f0b7311 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -70,21 +70,21 @@ enum qphy_reg_layout { }; static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { - [QPHY_START_CTRL] = 0x00, - [QPHY_PCS_READY_STATUS] = 0x168, - [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, + [QPHY_START_CTRL] = QPHY_V2_PCS_UFS_PHY_START, + [QPHY_PCS_READY_STATUS] = QPHY_V2_PCS_UFS_READY_STATUS, + [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_UFS_POWER_DOWN_CONTROL, }; static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { - [QPHY_START_CTRL] = 0x00, - [QPHY_PCS_READY_STATUS] = 0x160, - [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, + [QPHY_START_CTRL] = QPHY_V3_PCS_UFS_PHY_START, + [QPHY_PCS_READY_STATUS] = QPHY_V3_PCS_UFS_READY_STATUS, + [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_UFS_POWER_DOWN_CONTROL, }; static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { - [QPHY_START_CTRL] = 0x00, - [QPHY_PCS_READY_STATUS] = 0x168, - [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, + [QPHY_START_CTRL] = QPHY_V2_PCS_UFS_PHY_START, + [QPHY_PCS_READY_STATUS] = QPHY_V2_PCS_UFS_READY_STATUS, + [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_UFS_POWER_DOWN_CONTROL, }; static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { -- cgit v1.2.3