From 347ab9480313737c0f1aaa08e8f2e1a791235535 Mon Sep 17 00:00:00 2001 From: Phong Hoang Date: Tue, 19 Mar 2019 19:40:08 +0900 Subject: pwm: Fix deadlock warning when removing PWM device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch fixes deadlock warning if removing PWM device when CONFIG_PROVE_LOCKING is enabled. This issue can be reproceduced by the following steps on the R-Car H3 Salvator-X board if the backlight is disabled: # cd /sys/class/pwm/pwmchip0 # echo 0 > export # ls device export npwm power pwm0 subsystem uevent unexport # cd device/driver # ls bind e6e31000.pwm uevent unbind # echo e6e31000.pwm > unbind [ 87.659974] ====================================================== [ 87.666149] WARNING: possible circular locking dependency detected [ 87.672327] 5.0.0 #7 Not tainted [ 87.675549] ------------------------------------------------------ [ 87.681723] bash/2986 is trying to acquire lock: [ 87.686337] 000000005ea0e178 (kn->count#58){++++}, at: kernfs_remove_by_name_ns+0x50/0xa0 [ 87.694528] [ 87.694528] but task is already holding lock: [ 87.700353] 000000006313b17c (pwm_lock){+.+.}, at: pwmchip_remove+0x28/0x13c [ 87.707405] [ 87.707405] which lock already depends on the new lock. [ 87.707405] [ 87.715574] [ 87.715574] the existing dependency chain (in reverse order) is: [ 87.723048] [ 87.723048] -> #1 (pwm_lock){+.+.}: [ 87.728017] __mutex_lock+0x70/0x7e4 [ 87.732108] mutex_lock_nested+0x1c/0x24 [ 87.736547] pwm_request_from_chip.part.6+0x34/0x74 [ 87.741940] pwm_request_from_chip+0x20/0x40 [ 87.746725] export_store+0x6c/0x1f4 [ 87.750820] dev_attr_store+0x18/0x28 [ 87.754998] sysfs_kf_write+0x54/0x64 [ 87.759175] kernfs_fop_write+0xe4/0x1e8 [ 87.763615] __vfs_write+0x40/0x184 [ 87.767619] vfs_write+0xa8/0x19c [ 87.771448] ksys_write+0x58/0xbc [ 87.775278] __arm64_sys_write+0x18/0x20 [ 87.779721] el0_svc_common+0xd0/0x124 [ 87.783986] el0_svc_compat_handler+0x1c/0x24 [ 87.788858] el0_svc_compat+0x8/0x18 [ 87.792947] [ 87.792947] -> #0 (kn->count#58){++++}: [ 87.798260] lock_acquire+0xc4/0x22c [ 87.802353] __kernfs_remove+0x258/0x2c4 [ 87.806790] kernfs_remove_by_name_ns+0x50/0xa0 [ 87.811836] remove_files.isra.1+0x38/0x78 [ 87.816447] sysfs_remove_group+0x48/0x98 [ 87.820971] sysfs_remove_groups+0x34/0x4c [ 87.825583] device_remove_attrs+0x6c/0x7c [ 87.830197] device_del+0x11c/0x33c [ 87.834201] device_unregister+0x14/0x2c [ 87.838638] pwmchip_sysfs_unexport+0x40/0x4c [ 87.843509] pwmchip_remove+0xf4/0x13c [ 87.847773] rcar_pwm_remove+0x28/0x34 [ 87.852039] platform_drv_remove+0x24/0x64 [ 87.856651] device_release_driver_internal+0x18c/0x21c [ 87.862391] device_release_driver+0x14/0x1c [ 87.867175] unbind_store+0xe0/0x124 [ 87.871265] drv_attr_store+0x20/0x30 [ 87.875442] sysfs_kf_write+0x54/0x64 [ 87.879618] kernfs_fop_write+0xe4/0x1e8 [ 87.884055] __vfs_write+0x40/0x184 [ 87.888057] vfs_write+0xa8/0x19c [ 87.891887] ksys_write+0x58/0xbc [ 87.895716] __arm64_sys_write+0x18/0x20 [ 87.900154] el0_svc_common+0xd0/0x124 [ 87.904417] el0_svc_compat_handler+0x1c/0x24 [ 87.909289] el0_svc_compat+0x8/0x18 [ 87.913378] [ 87.913378] other info that might help us debug this: [ 87.913378] [ 87.921374] Possible unsafe locking scenario: [ 87.921374] [ 87.927286] CPU0 CPU1 [ 87.931808] ---- ---- [ 87.936331] lock(pwm_lock); [ 87.939293] lock(kn->count#58); [ 87.945120] lock(pwm_lock); [ 87.950599] lock(kn->count#58); [ 87.953908] [ 87.953908] *** DEADLOCK *** [ 87.953908] [ 87.959821] 4 locks held by bash/2986: [ 87.963563] #0: 00000000ace7bc30 (sb_writers#6){.+.+}, at: vfs_write+0x188/0x19c [ 87.971044] #1: 00000000287991b2 (&of->mutex){+.+.}, at: kernfs_fop_write+0xb4/0x1e8 [ 87.978872] #2: 00000000f739d016 (&dev->mutex){....}, at: device_release_driver_internal+0x40/0x21c [ 87.988001] #3: 000000006313b17c (pwm_lock){+.+.}, at: pwmchip_remove+0x28/0x13c [ 87.995481] [ 87.995481] stack backtrace: [ 87.999836] CPU: 0 PID: 2986 Comm: bash Not tainted 5.0.0 #7 [ 88.005489] Hardware name: Renesas Salvator-X board based on r8a7795 ES1.x (DT) [ 88.012791] Call trace: [ 88.015235] dump_backtrace+0x0/0x190 [ 88.018891] show_stack+0x14/0x1c [ 88.022204] dump_stack+0xb0/0xec [ 88.025514] print_circular_bug.isra.32+0x1d0/0x2e0 [ 88.030385] __lock_acquire+0x1318/0x1864 [ 88.034388] lock_acquire+0xc4/0x22c [ 88.037958] __kernfs_remove+0x258/0x2c4 [ 88.041874] kernfs_remove_by_name_ns+0x50/0xa0 [ 88.046398] remove_files.isra.1+0x38/0x78 [ 88.050487] sysfs_remove_group+0x48/0x98 [ 88.054490] sysfs_remove_groups+0x34/0x4c [ 88.058580] device_remove_attrs+0x6c/0x7c [ 88.062671] device_del+0x11c/0x33c [ 88.066154] device_unregister+0x14/0x2c [ 88.070070] pwmchip_sysfs_unexport+0x40/0x4c [ 88.074421] pwmchip_remove+0xf4/0x13c [ 88.078163] rcar_pwm_remove+0x28/0x34 [ 88.081906] platform_drv_remove+0x24/0x64 [ 88.085996] device_release_driver_internal+0x18c/0x21c [ 88.091215] device_release_driver+0x14/0x1c [ 88.095478] unbind_store+0xe0/0x124 [ 88.099048] drv_attr_store+0x20/0x30 [ 88.102704] sysfs_kf_write+0x54/0x64 [ 88.106359] kernfs_fop_write+0xe4/0x1e8 [ 88.110275] __vfs_write+0x40/0x184 [ 88.113757] vfs_write+0xa8/0x19c [ 88.117065] ksys_write+0x58/0xbc [ 88.120374] __arm64_sys_write+0x18/0x20 [ 88.124291] el0_svc_common+0xd0/0x124 [ 88.128034] el0_svc_compat_handler+0x1c/0x24 [ 88.132384] el0_svc_compat+0x8/0x18 The sysfs unexport in pwmchip_remove() is completely asymmetric to what we do in pwmchip_add_with_polarity() and commit 0733424c9ba9 ("pwm: Unexport children before chip removal") is a strong indication that this was wrong to begin with. We should just move pwmchip_sysfs_unexport() where it belongs, which is right after pwmchip_sysfs_unexport_children(). In that case, we do not need separate functions anymore either. We also really want to remove sysfs irrespective of whether or not the chip will be removed as a result of pwmchip_remove(). We can only assume that the driver will be gone after that, so we shouldn't leave any dangling sysfs files around. This warning disappears if we move pwmchip_sysfs_unexport() to the top of pwmchip_remove(), pwmchip_sysfs_unexport_children(). That way it is also outside of the pwm_lock section, which indeed doesn't seem to be needed. Moving the pwmchip_sysfs_export() call outside of that section also seems fine and it'd be perfectly symmetric with pwmchip_remove() again. So, this patch fixes them. Signed-off-by: Phong Hoang [shimoda: revise the commit log and code] Fixes: 76abbdde2d95 ("pwm: Add sysfs interface") Fixes: 0733424c9ba9 ("pwm: Unexport children before chip removal") Signed-off-by: Yoshihiro Shimoda Tested-by: Hoan Nguyen An Reviewed-by: Geert Uytterhoeven Reviewed-by: Simon Horman Reviewed-by: Uwe Kleine-König Signed-off-by: Thierry Reding --- drivers/pwm/core.c | 10 +++++----- drivers/pwm/sysfs.c | 14 +------------- 2 files changed, 6 insertions(+), 18 deletions(-) (limited to 'drivers/pwm') diff --git a/drivers/pwm/core.c b/drivers/pwm/core.c index 3149204567f3..8c9200a0df5e 100644 --- a/drivers/pwm/core.c +++ b/drivers/pwm/core.c @@ -311,10 +311,12 @@ int pwmchip_add_with_polarity(struct pwm_chip *chip, if (IS_ENABLED(CONFIG_OF)) of_pwmchip_add(chip); - pwmchip_sysfs_export(chip); - out: mutex_unlock(&pwm_lock); + + if (!ret) + pwmchip_sysfs_export(chip); + return ret; } EXPORT_SYMBOL_GPL(pwmchip_add_with_polarity); @@ -348,7 +350,7 @@ int pwmchip_remove(struct pwm_chip *chip) unsigned int i; int ret = 0; - pwmchip_sysfs_unexport_children(chip); + pwmchip_sysfs_unexport(chip); mutex_lock(&pwm_lock); @@ -368,8 +370,6 @@ int pwmchip_remove(struct pwm_chip *chip) free_pwms(chip); - pwmchip_sysfs_unexport(chip); - out: mutex_unlock(&pwm_lock); return ret; diff --git a/drivers/pwm/sysfs.c b/drivers/pwm/sysfs.c index ceb233dd6048..13d9bd54dfce 100644 --- a/drivers/pwm/sysfs.c +++ b/drivers/pwm/sysfs.c @@ -409,19 +409,6 @@ void pwmchip_sysfs_export(struct pwm_chip *chip) } void pwmchip_sysfs_unexport(struct pwm_chip *chip) -{ - struct device *parent; - - parent = class_find_device(&pwm_class, NULL, chip, - pwmchip_sysfs_match); - if (parent) { - /* for class_find_device() */ - put_device(parent); - device_unregister(parent); - } -} - -void pwmchip_sysfs_unexport_children(struct pwm_chip *chip) { struct device *parent; unsigned int i; @@ -439,6 +426,7 @@ void pwmchip_sysfs_unexport_children(struct pwm_chip *chip) } put_device(parent); + device_unregister(parent); } static int __init pwm_sysfs_init(void) -- cgit v1.2.3 From 44481955eab7029b58c956d64485fece6f12a53f Mon Sep 17 00:00:00 2001 From: Nathan Chancellor Date: Thu, 7 Mar 2019 15:36:28 -0700 Subject: pwm: img: Turn final 'else if' into 'else' in img_pwm_config When building with -Wsometimes-uninitialized, Clang warns: drivers/pwm/pwm-img.c:126:13: error: variable 'timebase' is used uninitialized whenever 'if' condition is false [-Werror,-Wsometimes-uninitialized] The final else if functions as an else; make that explicit so that Clang understands that timebase cannot be used uninitialized. Link: https://github.com/ClangBuiltLinux/linux/issues/400 Signed-off-by: Nathan Chancellor Reviewed-by: Nick Desaulniers Signed-off-by: Thierry Reding --- drivers/pwm/pwm-img.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/pwm') diff --git a/drivers/pwm/pwm-img.c b/drivers/pwm/pwm-img.c index 815f5333bb8f..1cc5fbe1e1d3 100644 --- a/drivers/pwm/pwm-img.c +++ b/drivers/pwm/pwm-img.c @@ -123,7 +123,7 @@ static int img_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, } else if (mul <= max_timebase * 512) { div = PWM_CTRL_CFG_SUB_DIV0_DIV1; timebase = DIV_ROUND_UP(mul, 512); - } else if (mul > max_timebase * 512) { + } else { dev_err(chip->dev, "failed to configure timebase steps/divider value\n"); return -EINVAL; -- cgit v1.2.3 From b00ef53053191d3025c15e8041699f8c9d132daf Mon Sep 17 00:00:00 2001 From: Christoph Vogtländer Date: Tue, 12 Mar 2019 14:38:46 +0530 Subject: pwm: tiehrpwm: Update shadow register for disabling PWMs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It must be made sure that immediate mode is not already set, when modifying shadow register value in ehrpwm_pwm_disable(). Otherwise modifications to the action-qualifier continuous S/W force register(AQSFRC) will be done in the active register. This may happen when both channels are being disabled. In this case, only the first channel state will be recorded as disabled in the shadow register. Later, when enabling the first channel again, the second channel would be enabled as well. Setting RLDCSF to zero, first, ensures that the shadow register is updated as desired. Fixes: 38dabd91ff0b ("pwm: tiehrpwm: Fix disabling of output of PWMs") Signed-off-by: Christoph Vogtländer [vigneshr@ti.com: Improve commit message] Signed-off-by: Vignesh Raghavendra Signed-off-by: Thierry Reding --- drivers/pwm/pwm-tiehrpwm.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/pwm') diff --git a/drivers/pwm/pwm-tiehrpwm.c b/drivers/pwm/pwm-tiehrpwm.c index f7b8a86fa5c5..ad4a40c0f27c 100644 --- a/drivers/pwm/pwm-tiehrpwm.c +++ b/drivers/pwm/pwm-tiehrpwm.c @@ -382,6 +382,8 @@ static void ehrpwm_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) } /* Update shadow register first before modifying active register */ + ehrpwm_modify(pc->mmio_base, AQSFRC, AQSFRC_RLDCSF_MASK, + AQSFRC_RLDCSF_ZRO); ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val); /* * Changes to immediate action on Action Qualifier. This puts -- cgit v1.2.3 From efc80fb3746609aa6beed8bc33751f29ee18fed7 Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Tue, 12 Mar 2019 14:46:29 +0530 Subject: pwm: tiehrpwm: Enable compilation for ARCH_K3 K3 devices have the same EHRPWM IP as OMAP SoCs. Enable the driver to be built for K3 devices. Also, drop reference to AM33xx in help text, as IP is found on multiple TI SoCs. Signed-off-by: Vignesh Raghavendra Signed-off-by: Thierry Reding --- drivers/pwm/Kconfig | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'drivers/pwm') diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 54f8238aac0d..c054bd1dba36 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -467,10 +467,9 @@ config PWM_TIECAP config PWM_TIEHRPWM tristate "EHRPWM PWM support" - depends on ARCH_OMAP2PLUS || ARCH_DAVINCI_DA8XX + depends on ARCH_OMAP2PLUS || ARCH_DAVINCI_DA8XX || ARCH_K3 help - PWM driver support for the EHRPWM controller found on AM33XX - TI SOC + PWM driver support for the EHRPWM controller found on TI SOCs To compile this driver as a module, choose M here: the module will be called pwm-tiehrpwm. -- cgit v1.2.3 From 9ff06679e109a216fc4a0cf5b4069a5305df141c Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Tue, 12 Mar 2019 10:25:47 +0100 Subject: pwm: sysfs: fix typo "its" -> "it's" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Uwe Kleine-König Signed-off-by: Thierry Reding --- drivers/pwm/sysfs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/pwm') diff --git a/drivers/pwm/sysfs.c b/drivers/pwm/sysfs.c index 13d9bd54dfce..719f8fada0a7 100644 --- a/drivers/pwm/sysfs.c +++ b/drivers/pwm/sysfs.c @@ -398,7 +398,7 @@ void pwmchip_sysfs_export(struct pwm_chip *chip) /* * If device_create() fails the pwm_chip is still usable by - * the kernel its just not exported. + * the kernel it's just not exported. */ parent = device_create(&pwm_class, chip->dev, MKDEV(0, 0), chip, "pwmchip%d", chip->base); -- cgit v1.2.3 From 51496e4446875726d50a5617a6e0e0dabbc2e6da Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Mon, 1 Apr 2019 20:18:16 +0200 Subject: pwm: meson: Consider 128 a valid pre-divider MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The pre-divider allows configuring longer PWM periods compared to using the input clock directly. The pre-divider is 7 bit wide, meaning it's maximum value is 128 (the register value is off-by-one: 0x7f or 127). Change the loop to also allow for the maximum possible value to be considered valid. Fixes: 211ed630753d2f ("pwm: Add support for Meson PWM Controller") Signed-off-by: Martin Blumenstingl Acked-by: Uwe Kleine-König Reviewed-by: Neil Armstrong Signed-off-by: Thierry Reding --- drivers/pwm/pwm-meson.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/pwm') diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c index c1ed641b3e26..aaae48ab484e 100644 --- a/drivers/pwm/pwm-meson.c +++ b/drivers/pwm/pwm-meson.c @@ -184,7 +184,7 @@ static int meson_pwm_calc(struct meson_pwm *meson, do_div(fin_ps, fin_freq); /* Calc pre_div with the period */ - for (pre_div = 0; pre_div < MISC_CLK_DIV_MASK; pre_div++) { + for (pre_div = 0; pre_div <= MISC_CLK_DIV_MASK; pre_div++) { cnt = DIV_ROUND_CLOSEST_ULL((u64)period * 1000, fin_ps * (pre_div + 1)); dev_dbg(meson->chip.dev, "fin_ps=%llu pre_div=%u cnt=%u\n", @@ -193,7 +193,7 @@ static int meson_pwm_calc(struct meson_pwm *meson, break; } - if (pre_div == MISC_CLK_DIV_MASK) { + if (pre_div > MISC_CLK_DIV_MASK) { dev_err(meson->chip.dev, "unable to get period pre_div\n"); return -EINVAL; } -- cgit v1.2.3 From a279345807e1e0ae79567a52cfdd9d30c9174a3c Mon Sep 17 00:00:00 2001 From: Bichao Zheng Date: Mon, 1 Apr 2019 20:18:17 +0200 Subject: pwm: meson: Don't disable PWM when setting duty repeatedly There is an abnormally low about 20ms,when setting duty repeatedly. Because setting the duty will disable PWM and then enable. Delete this operation now. Fixes: 211ed630753d2f ("pwm: Add support for Meson PWM Controller") Signed-off-by: Bichao Zheng [ Dropped code instead of hiding it behind a comment ] Signed-off-by: Martin Blumenstingl Reviewed-by: Neil Armstrong Signed-off-by: Thierry Reding --- drivers/pwm/pwm-meson.c | 5 ----- 1 file changed, 5 deletions(-) (limited to 'drivers/pwm') diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c index aaae48ab484e..2ab3d216b35a 100644 --- a/drivers/pwm/pwm-meson.c +++ b/drivers/pwm/pwm-meson.c @@ -314,11 +314,6 @@ static int meson_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, if (state->period != channel->state.period || state->duty_cycle != channel->state.duty_cycle || state->polarity != channel->state.polarity) { - if (channel->state.enabled) { - meson_pwm_disable(meson, pwm->hwpwm); - channel->state.enabled = false; - } - if (state->polarity != channel->state.polarity) { if (state->polarity == PWM_POLARITY_NORMAL) meson->inverter_mask |= BIT(pwm->hwpwm); -- cgit v1.2.3 From f173747fffdf037c791405ab4f1ec0eb392fc48e Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Mon, 1 Apr 2019 19:57:48 +0200 Subject: pwm: meson: Use the spin-lock only to protect register modifications MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Holding the spin-lock for all of the code in meson_pwm_apply() can result in a "BUG: scheduling while atomic". This can happen because clk_get_rate() (which is called from meson_pwm_calc()) may sleep. Only hold the spin-lock when modifying registers to solve this. The reason why we need a spin-lock in the driver is because the REG_MISC_AB register is shared between the two channels provided by one PWM controller. The only functions where REG_MISC_AB is modified are meson_pwm_enable() and meson_pwm_disable() so the register reads/writes in there need to be protected by the spin-lock. The original code also used the spin-lock to protect the values in struct meson_pwm_channel. This could be necessary if two consumers can use the same PWM channel. However, PWM core doesn't allow this so we don't need to protect the values in struct meson_pwm_channel with a lock. Fixes: 211ed630753d2f ("pwm: Add support for Meson PWM Controller") Signed-off-by: Martin Blumenstingl Reviewed-by: Uwe Kleine-König Reviewed-by: Neil Armstrong Signed-off-by: Thierry Reding --- drivers/pwm/pwm-meson.c | 25 +++++++++++++++++-------- 1 file changed, 17 insertions(+), 8 deletions(-) (limited to 'drivers/pwm') diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c index 2ab3d216b35a..e247ab632530 100644 --- a/drivers/pwm/pwm-meson.c +++ b/drivers/pwm/pwm-meson.c @@ -111,6 +111,10 @@ struct meson_pwm { const struct meson_pwm_data *data; void __iomem *base; u8 inverter_mask; + /* + * Protects register (write) access to the REG_MISC_AB register + * that is shared between the two PWMs. + */ spinlock_t lock; }; @@ -235,6 +239,7 @@ static void meson_pwm_enable(struct meson_pwm *meson, { u32 value, clk_shift, clk_enable, enable; unsigned int offset; + unsigned long flags; switch (id) { case 0: @@ -255,6 +260,8 @@ static void meson_pwm_enable(struct meson_pwm *meson, return; } + spin_lock_irqsave(&meson->lock, flags); + value = readl(meson->base + REG_MISC_AB); value &= ~(MISC_CLK_DIV_MASK << clk_shift); value |= channel->pre_div << clk_shift; @@ -267,11 +274,14 @@ static void meson_pwm_enable(struct meson_pwm *meson, value = readl(meson->base + REG_MISC_AB); value |= enable; writel(value, meson->base + REG_MISC_AB); + + spin_unlock_irqrestore(&meson->lock, flags); } static void meson_pwm_disable(struct meson_pwm *meson, unsigned int id) { u32 value, enable; + unsigned long flags; switch (id) { case 0: @@ -286,9 +296,13 @@ static void meson_pwm_disable(struct meson_pwm *meson, unsigned int id) return; } + spin_lock_irqsave(&meson->lock, flags); + value = readl(meson->base + REG_MISC_AB); value &= ~enable; writel(value, meson->base + REG_MISC_AB); + + spin_unlock_irqrestore(&meson->lock, flags); } static int meson_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, @@ -296,19 +310,16 @@ static int meson_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, { struct meson_pwm_channel *channel = pwm_get_chip_data(pwm); struct meson_pwm *meson = to_meson_pwm(chip); - unsigned long flags; int err = 0; if (!state) return -EINVAL; - spin_lock_irqsave(&meson->lock, flags); - if (!state->enabled) { meson_pwm_disable(meson, pwm->hwpwm); channel->state.enabled = false; - goto unlock; + return 0; } if (state->period != channel->state.period || @@ -324,7 +335,7 @@ static int meson_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, err = meson_pwm_calc(meson, channel, pwm->hwpwm, state->duty_cycle, state->period); if (err < 0) - goto unlock; + return err; channel->state.polarity = state->polarity; channel->state.period = state->period; @@ -336,9 +347,7 @@ static int meson_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, channel->state.enabled = true; } -unlock: - spin_unlock_irqrestore(&meson->lock, flags); - return err; + return 0; } static void meson_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, -- cgit v1.2.3 From 1347c94f73e33a7d1edab6728a34bedd55b2d588 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Mon, 1 Apr 2019 05:24:02 +0000 Subject: pwm: imx27: Use devm_platform_ioremap_resource() to simplify code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use the new helper devm_platform_ioremap_resource() which wraps the platform_get_resource() and devm_ioremap_resource() together, to simplify the code. Signed-off-by: Anson Huang Acked-by: Uwe Kleine-König Reviewed-by: Mukesh Ojha Signed-off-by: Thierry Reding --- drivers/pwm/pwm-imx27.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'drivers/pwm') diff --git a/drivers/pwm/pwm-imx27.c b/drivers/pwm/pwm-imx27.c index 806130654211..434a351fb626 100644 --- a/drivers/pwm/pwm-imx27.c +++ b/drivers/pwm/pwm-imx27.c @@ -291,7 +291,6 @@ MODULE_DEVICE_TABLE(of, pwm_imx27_dt_ids); static int pwm_imx27_probe(struct platform_device *pdev) { struct pwm_imx27_chip *imx; - struct resource *r; imx = devm_kzalloc(&pdev->dev, sizeof(*imx), GFP_KERNEL); if (imx == NULL) @@ -326,8 +325,7 @@ static int pwm_imx27_probe(struct platform_device *pdev) imx->chip.of_xlate = of_pwm_xlate_with_flags; imx->chip.of_pwm_n_cells = 3; - r = platform_get_resource(pdev, IORESOURCE_MEM, 0); - imx->mmio_base = devm_ioremap_resource(&pdev->dev, r); + imx->mmio_base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(imx->mmio_base)) return PTR_ERR(imx->mmio_base); -- cgit v1.2.3 From 738a1cfec2edb4a6c53ac34fcb29447227dd135e Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Thu, 9 May 2019 13:29:29 +0000 Subject: pwm: Add i.MX TPM PWM driver support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit i.MX7ULP has TPM(Low Power Timer/Pulse Width Modulation Module) inside, it can support multiple PWM channels, all the channels share same counter and period setting, but each channel can configure its duty and polarity independently. There are several TPM modules in i.MX7ULP, the number of channels in TPM modules are different, it can be read from each TPM module's PARAM register. Signed-off-by: Anson Huang Reviewed-by: Uwe Kleine-König Signed-off-by: Thierry Reding --- drivers/pwm/Kconfig | 11 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-imx-tpm.c | 449 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 461 insertions(+) create mode 100644 drivers/pwm/pwm-imx-tpm.c (limited to 'drivers/pwm') diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index c054bd1dba36..1311b54089be 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -210,6 +210,17 @@ config PWM_IMX27 To compile this driver as a module, choose M here: the module will be called pwm-imx27. +config PWM_IMX_TPM + tristate "i.MX TPM PWM support" + depends on ARCH_MXC || COMPILE_TEST + depends on HAVE_CLK && HAS_IOMEM + help + Generic PWM framework driver for i.MX7ULP TPM module, TPM's full + name is Low Power Timer/Pulse Width Modulation Module. + + To compile this driver as a module, choose M here: the module + will be called pwm-imx-tpm. + config PWM_JZ4740 tristate "Ingenic JZ47xx PWM support" depends on MACH_INGENIC diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 448825e892bc..c368599d36c0 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_PWM_HIBVT) += pwm-hibvt.o obj-$(CONFIG_PWM_IMG) += pwm-img.o obj-$(CONFIG_PWM_IMX1) += pwm-imx1.o obj-$(CONFIG_PWM_IMX27) += pwm-imx27.o +obj-$(CONFIG_PWM_IMX_TPM) += pwm-imx-tpm.o obj-$(CONFIG_PWM_JZ4740) += pwm-jz4740.o obj-$(CONFIG_PWM_LP3943) += pwm-lp3943.o obj-$(CONFIG_PWM_LPC18XX_SCT) += pwm-lpc18xx-sct.o diff --git a/drivers/pwm/pwm-imx-tpm.c b/drivers/pwm/pwm-imx-tpm.c new file mode 100644 index 000000000000..e8385c1cf342 --- /dev/null +++ b/drivers/pwm/pwm-imx-tpm.c @@ -0,0 +1,449 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2018-2019 NXP. + * + * Limitations: + * - The TPM counter and period counter are shared between + * multiple channels, so all channels should use same period + * settings. + * - Changes to polarity cannot be latched at the time of the + * next period start. + * - Changing period and duty cycle together isn't atomic, + * with the wrong timing it might happen that a period is + * produced with old duty cycle but new period settings. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PWM_IMX_TPM_PARAM 0x4 +#define PWM_IMX_TPM_GLOBAL 0x8 +#define PWM_IMX_TPM_SC 0x10 +#define PWM_IMX_TPM_CNT 0x14 +#define PWM_IMX_TPM_MOD 0x18 +#define PWM_IMX_TPM_CnSC(n) (0x20 + (n) * 0x8) +#define PWM_IMX_TPM_CnV(n) (0x24 + (n) * 0x8) + +#define PWM_IMX_TPM_PARAM_CHAN GENMASK(7, 0) + +#define PWM_IMX_TPM_SC_PS GENMASK(2, 0) +#define PWM_IMX_TPM_SC_CMOD GENMASK(4, 3) +#define PWM_IMX_TPM_SC_CMOD_INC_EVERY_CLK FIELD_PREP(PWM_IMX_TPM_SC_CMOD, 1) +#define PWM_IMX_TPM_SC_CPWMS BIT(5) + +#define PWM_IMX_TPM_CnSC_CHF BIT(7) +#define PWM_IMX_TPM_CnSC_MSB BIT(5) +#define PWM_IMX_TPM_CnSC_MSA BIT(4) + +/* + * The reference manual describes this field as two separate bits. The + * semantic of the two bits isn't orthogonal though, so they are treated + * together as a 2-bit field here. + */ +#define PWM_IMX_TPM_CnSC_ELS GENMASK(3, 2) +#define PWM_IMX_TPM_CnSC_ELS_INVERSED FIELD_PREP(PWM_IMX_TPM_CnSC_ELS, 1) +#define PWM_IMX_TPM_CnSC_ELS_NORMAL FIELD_PREP(PWM_IMX_TPM_CnSC_ELS, 2) + + +#define PWM_IMX_TPM_MOD_WIDTH 16 +#define PWM_IMX_TPM_MOD_MOD GENMASK(PWM_IMX_TPM_MOD_WIDTH - 1, 0) + +struct imx_tpm_pwm_chip { + struct pwm_chip chip; + struct clk *clk; + void __iomem *base; + struct mutex lock; + u32 user_count; + u32 enable_count; + u32 real_period; +}; + +struct imx_tpm_pwm_param { + u8 prescale; + u32 mod; + u32 val; +}; + +static inline struct imx_tpm_pwm_chip * +to_imx_tpm_pwm_chip(struct pwm_chip *chip) +{ + return container_of(chip, struct imx_tpm_pwm_chip, chip); +} + +/* + * This function determines for a given pwm_state *state that a consumer + * might request the pwm_state *real_state that eventually is implemented + * by the hardware and the necessary register values (in *p) to achieve + * this. + */ +static int pwm_imx_tpm_round_state(struct pwm_chip *chip, + struct imx_tpm_pwm_param *p, + struct pwm_state *real_state, + struct pwm_state *state) +{ + struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip); + u32 rate, prescale, period_count, clock_unit; + u64 tmp; + + rate = clk_get_rate(tpm->clk); + tmp = (u64)state->period * rate; + clock_unit = DIV_ROUND_CLOSEST_ULL(tmp, NSEC_PER_SEC); + if (clock_unit <= PWM_IMX_TPM_MOD_MOD) + prescale = 0; + else + prescale = ilog2(clock_unit) + 1 - PWM_IMX_TPM_MOD_WIDTH; + + if ((!FIELD_FIT(PWM_IMX_TPM_SC_PS, prescale))) + return -ERANGE; + p->prescale = prescale; + + period_count = (clock_unit + ((1 << prescale) >> 1)) >> prescale; + p->mod = period_count; + + /* calculate real period HW can support */ + tmp = (u64)period_count << prescale; + tmp *= NSEC_PER_SEC; + real_state->period = DIV_ROUND_CLOSEST_ULL(tmp, rate); + + /* + * if eventually the PWM output is inactive, either + * duty cycle is 0 or status is disabled, need to + * make sure the output pin is inactive. + */ + if (!state->enabled) + real_state->duty_cycle = 0; + else + real_state->duty_cycle = state->duty_cycle; + + tmp = (u64)p->mod * real_state->duty_cycle; + p->val = DIV_ROUND_CLOSEST_ULL(tmp, real_state->period); + + real_state->polarity = state->polarity; + real_state->enabled = state->enabled; + + return 0; +} + +static void pwm_imx_tpm_get_state(struct pwm_chip *chip, + struct pwm_device *pwm, + struct pwm_state *state) +{ + struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip); + u32 rate, val, prescale; + u64 tmp; + + /* get period */ + state->period = tpm->real_period; + + /* get duty cycle */ + rate = clk_get_rate(tpm->clk); + val = readl(tpm->base + PWM_IMX_TPM_SC); + prescale = FIELD_GET(PWM_IMX_TPM_SC_PS, val); + tmp = readl(tpm->base + PWM_IMX_TPM_CnV(pwm->hwpwm)); + tmp = (tmp << prescale) * NSEC_PER_SEC; + state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, rate); + + /* get polarity */ + val = readl(tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm)); + if ((val & PWM_IMX_TPM_CnSC_ELS) == PWM_IMX_TPM_CnSC_ELS_INVERSED) + state->polarity = PWM_POLARITY_INVERSED; + else + /* + * Assume reserved values (2b00 and 2b11) to yield + * normal polarity. + */ + state->polarity = PWM_POLARITY_NORMAL; + + /* get channel status */ + state->enabled = FIELD_GET(PWM_IMX_TPM_CnSC_ELS, val) ? true : false; +} + +/* this function is supposed to be called with mutex hold */ +static int pwm_imx_tpm_apply_hw(struct pwm_chip *chip, + struct imx_tpm_pwm_param *p, + struct pwm_state *state, + struct pwm_device *pwm) +{ + struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip); + bool period_update = false; + bool duty_update = false; + u32 val, cmod, cur_prescale; + unsigned long timeout; + struct pwm_state c; + + if (state->period != tpm->real_period) { + /* + * TPM counter is shared by multiple channels, so + * prescale and period can NOT be modified when + * there are multiple channels in use with different + * period settings. + */ + if (tpm->user_count > 1) + return -EBUSY; + + val = readl(tpm->base + PWM_IMX_TPM_SC); + cmod = FIELD_GET(PWM_IMX_TPM_SC_CMOD, val); + cur_prescale = FIELD_GET(PWM_IMX_TPM_SC_PS, val); + if (cmod && cur_prescale != p->prescale) + return -EBUSY; + + /* set TPM counter prescale */ + val &= ~PWM_IMX_TPM_SC_PS; + val |= FIELD_PREP(PWM_IMX_TPM_SC_PS, p->prescale); + writel(val, tpm->base + PWM_IMX_TPM_SC); + + /* + * set period count: + * if the PWM is disabled (CMOD[1:0] = 2b00), then MOD register + * is updated when MOD register is written. + * + * if the PWM is enabled (CMOD[1:0] ≠ 2b00), the period length + * is latched into hardware when the next period starts. + */ + writel(p->mod, tpm->base + PWM_IMX_TPM_MOD); + tpm->real_period = state->period; + period_update = true; + } + + pwm_imx_tpm_get_state(chip, pwm, &c); + + /* polarity is NOT allowed to be changed if PWM is active */ + if (c.enabled && c.polarity != state->polarity) + return -EBUSY; + + if (state->duty_cycle != c.duty_cycle) { + /* + * set channel value: + * if the PWM is disabled (CMOD[1:0] = 2b00), then CnV register + * is updated when CnV register is written. + * + * if the PWM is enabled (CMOD[1:0] ≠ 2b00), the duty length + * is latched into hardware when the next period starts. + */ + writel(p->val, tpm->base + PWM_IMX_TPM_CnV(pwm->hwpwm)); + duty_update = true; + } + + /* make sure MOD & CnV registers are updated */ + if (period_update || duty_update) { + timeout = jiffies + msecs_to_jiffies(tpm->real_period / + NSEC_PER_MSEC + 1); + while (readl(tpm->base + PWM_IMX_TPM_MOD) != p->mod + || readl(tpm->base + PWM_IMX_TPM_CnV(pwm->hwpwm)) + != p->val) { + if (time_after(jiffies, timeout)) + return -ETIME; + cpu_relax(); + } + } + + /* + * polarity settings will enabled/disable output status + * immediately, so if the channel is disabled, need to + * make sure MSA/MSB/ELS are set to 0 which means channel + * disabled. + */ + val = readl(tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm)); + val &= ~(PWM_IMX_TPM_CnSC_ELS | PWM_IMX_TPM_CnSC_MSA | + PWM_IMX_TPM_CnSC_MSB); + if (state->enabled) { + /* + * set polarity (for edge-aligned PWM modes) + * + * ELS[1:0] = 2b10 yields normal polarity behaviour, + * ELS[1:0] = 2b01 yields inversed polarity. + * The other values are reserved. + */ + val |= PWM_IMX_TPM_CnSC_MSB; + val |= (state->polarity == PWM_POLARITY_NORMAL) ? + PWM_IMX_TPM_CnSC_ELS_NORMAL : + PWM_IMX_TPM_CnSC_ELS_INVERSED; + } + writel(val, tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm)); + + /* control the counter status */ + if (state->enabled != c.enabled) { + val = readl(tpm->base + PWM_IMX_TPM_SC); + if (state->enabled) { + if (++tpm->enable_count == 1) + val |= PWM_IMX_TPM_SC_CMOD_INC_EVERY_CLK; + } else { + if (--tpm->enable_count == 0) + val &= ~PWM_IMX_TPM_SC_CMOD; + } + writel(val, tpm->base + PWM_IMX_TPM_SC); + } + + return 0; +} + +static int pwm_imx_tpm_apply(struct pwm_chip *chip, + struct pwm_device *pwm, + struct pwm_state *state) +{ + struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip); + struct imx_tpm_pwm_param param; + struct pwm_state real_state; + int ret; + + ret = pwm_imx_tpm_round_state(chip, ¶m, &real_state, state); + if (ret) + return ret; + + mutex_lock(&tpm->lock); + ret = pwm_imx_tpm_apply_hw(chip, ¶m, &real_state, pwm); + mutex_unlock(&tpm->lock); + + return ret; +} + +static int pwm_imx_tpm_request(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip); + + mutex_lock(&tpm->lock); + tpm->user_count++; + mutex_unlock(&tpm->lock); + + return 0; +} + +static void pwm_imx_tpm_free(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct imx_tpm_pwm_chip *tpm = to_imx_tpm_pwm_chip(chip); + + mutex_lock(&tpm->lock); + tpm->user_count--; + mutex_unlock(&tpm->lock); +} + +static const struct pwm_ops imx_tpm_pwm_ops = { + .request = pwm_imx_tpm_request, + .free = pwm_imx_tpm_free, + .get_state = pwm_imx_tpm_get_state, + .apply = pwm_imx_tpm_apply, + .owner = THIS_MODULE, +}; + +static int pwm_imx_tpm_probe(struct platform_device *pdev) +{ + struct imx_tpm_pwm_chip *tpm; + int ret; + u32 val; + + tpm = devm_kzalloc(&pdev->dev, sizeof(*tpm), GFP_KERNEL); + if (!tpm) + return -ENOMEM; + + platform_set_drvdata(pdev, tpm); + + tpm->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(tpm->base)) + return PTR_ERR(tpm->base); + + tpm->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(tpm->clk)) { + ret = PTR_ERR(tpm->clk); + if (ret != -EPROBE_DEFER) + dev_err(&pdev->dev, + "failed to get PWM clock: %d\n", ret); + return ret; + } + + ret = clk_prepare_enable(tpm->clk); + if (ret) { + dev_err(&pdev->dev, + "failed to prepare or enable clock: %d\n", ret); + return ret; + } + + tpm->chip.dev = &pdev->dev; + tpm->chip.ops = &imx_tpm_pwm_ops; + tpm->chip.base = -1; + tpm->chip.of_xlate = of_pwm_xlate_with_flags; + tpm->chip.of_pwm_n_cells = 3; + + /* get number of channels */ + val = readl(tpm->base + PWM_IMX_TPM_PARAM); + tpm->chip.npwm = FIELD_GET(PWM_IMX_TPM_PARAM_CHAN, val); + + mutex_init(&tpm->lock); + + ret = pwmchip_add(&tpm->chip); + if (ret) { + dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret); + clk_disable_unprepare(tpm->clk); + } + + return ret; +} + +static int pwm_imx_tpm_remove(struct platform_device *pdev) +{ + struct imx_tpm_pwm_chip *tpm = platform_get_drvdata(pdev); + int ret = pwmchip_remove(&tpm->chip); + + clk_disable_unprepare(tpm->clk); + + return ret; +} + +static int __maybe_unused pwm_imx_tpm_suspend(struct device *dev) +{ + struct imx_tpm_pwm_chip *tpm = dev_get_drvdata(dev); + + if (tpm->enable_count > 0) + return -EBUSY; + + clk_disable_unprepare(tpm->clk); + + return 0; +} + +static int __maybe_unused pwm_imx_tpm_resume(struct device *dev) +{ + struct imx_tpm_pwm_chip *tpm = dev_get_drvdata(dev); + int ret = 0; + + ret = clk_prepare_enable(tpm->clk); + if (ret) + dev_err(dev, + "failed to prepare or enable clock: %d\n", + ret); + + return ret; +} + +static SIMPLE_DEV_PM_OPS(imx_tpm_pwm_pm, + pwm_imx_tpm_suspend, pwm_imx_tpm_resume); + +static const struct of_device_id imx_tpm_pwm_dt_ids[] = { + { .compatible = "fsl,imx7ulp-pwm", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, imx_tpm_pwm_dt_ids); + +static struct platform_driver imx_tpm_pwm_driver = { + .driver = { + .name = "imx7ulp-tpm-pwm", + .of_match_table = imx_tpm_pwm_dt_ids, + .pm = &imx_tpm_pwm_pm, + }, + .probe = pwm_imx_tpm_probe, + .remove = pwm_imx_tpm_remove, +}; +module_platform_driver(imx_tpm_pwm_driver); + +MODULE_AUTHOR("Anson Huang "); +MODULE_DESCRIPTION("i.MX TPM PWM Driver"); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From e926b12c611c2095c7976e2ed31753ad6eb5ff1a Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Mon, 25 Mar 2019 10:49:33 +0100 Subject: pwm: Clear chip_data in pwm_put() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit After a PWM is disposed by its user the per chip data becomes invalid. Clear the data in common code instead of the device drivers to get consistent behaviour. Before this patch only three of nine drivers cleaned up here. Signed-off-by: Uwe Kleine-König Signed-off-by: Thierry Reding --- drivers/pwm/core.c | 1 + drivers/pwm/pwm-berlin.c | 1 - drivers/pwm/pwm-pca9685.c | 1 - drivers/pwm/pwm-samsung.c | 1 - 4 files changed, 1 insertion(+), 3 deletions(-) (limited to 'drivers/pwm') diff --git a/drivers/pwm/core.c b/drivers/pwm/core.c index 8c9200a0df5e..3998ebd51db4 100644 --- a/drivers/pwm/core.c +++ b/drivers/pwm/core.c @@ -877,6 +877,7 @@ void pwm_put(struct pwm_device *pwm) if (pwm->chip->ops->free) pwm->chip->ops->free(pwm->chip, pwm); + pwm_set_chip_data(pwm, NULL); pwm->label = NULL; module_put(pwm->chip->ops->owner); diff --git a/drivers/pwm/pwm-berlin.c b/drivers/pwm/pwm-berlin.c index 7c8d6a168ceb..b91c477cc84b 100644 --- a/drivers/pwm/pwm-berlin.c +++ b/drivers/pwm/pwm-berlin.c @@ -84,7 +84,6 @@ static void berlin_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) { struct berlin_pwm_channel *channel = pwm_get_chip_data(pwm); - pwm_set_chip_data(pwm, NULL); kfree(channel); } diff --git a/drivers/pwm/pwm-pca9685.c b/drivers/pwm/pwm-pca9685.c index a7eaf962a95b..567f5e2771c4 100644 --- a/drivers/pwm/pwm-pca9685.c +++ b/drivers/pwm/pwm-pca9685.c @@ -176,7 +176,6 @@ static void pca9685_pwm_gpio_free(struct gpio_chip *gpio, unsigned int offset) pm_runtime_put(pca->chip.dev); mutex_lock(&pca->lock); pwm = &pca->chip.pwms[offset]; - pwm_set_chip_data(pwm, NULL); mutex_unlock(&pca->lock); } diff --git a/drivers/pwm/pwm-samsung.c b/drivers/pwm/pwm-samsung.c index 062f2cfc45ec..3762432dd6a7 100644 --- a/drivers/pwm/pwm-samsung.c +++ b/drivers/pwm/pwm-samsung.c @@ -238,7 +238,6 @@ static int pwm_samsung_request(struct pwm_chip *chip, struct pwm_device *pwm) static void pwm_samsung_free(struct pwm_chip *chip, struct pwm_device *pwm) { devm_kfree(chip->dev, pwm_get_chip_data(pwm)); - pwm_set_chip_data(pwm, NULL); } static int pwm_samsung_enable(struct pwm_chip *chip, struct pwm_device *pwm) -- cgit v1.2.3 From b05232d624425f8584b511f0e102c3b963b00323 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Mon, 25 Mar 2019 10:49:34 +0100 Subject: pwm: samsung: Don't uses devm_*() functions in ->request() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit A call to ->request() is always paired by a call to ->free() before a given device is disposed. So the simplification that usually is possible when using devm_*() functions cannot be used here. So use plain kzalloc() and kfree() for improved runtime behaviour and reduced memory footprint. Signed-off-by: Uwe Kleine-König [thierry.reding@gmail.com: fix build failure] Signed-off-by: Thierry Reding --- drivers/pwm/pwm-samsung.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/pwm') diff --git a/drivers/pwm/pwm-samsung.c b/drivers/pwm/pwm-samsung.c index 3762432dd6a7..6674e1e80175 100644 --- a/drivers/pwm/pwm-samsung.c +++ b/drivers/pwm/pwm-samsung.c @@ -226,7 +226,7 @@ static int pwm_samsung_request(struct pwm_chip *chip, struct pwm_device *pwm) return -EINVAL; } - our_chan = devm_kzalloc(chip->dev, sizeof(*our_chan), GFP_KERNEL); + our_chan = kzalloc(sizeof(*our_chan), GFP_KERNEL); if (!our_chan) return -ENOMEM; @@ -237,7 +237,7 @@ static int pwm_samsung_request(struct pwm_chip *chip, struct pwm_device *pwm) static void pwm_samsung_free(struct pwm_chip *chip, struct pwm_device *pwm) { - devm_kfree(chip->dev, pwm_get_chip_data(pwm)); + kfree(pwm_get_chip_data(pwm)); } static int pwm_samsung_enable(struct pwm_chip *chip, struct pwm_device *pwm) -- cgit v1.2.3 From f41efceb46e697a750e93c19e4579dc50697effe Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 23 Apr 2019 15:36:45 +0200 Subject: pwm: meson: Add clock source configuration for Meson G12A For the PWM controller in the Meson G12A SoC, the EE domain and AO domain have different clock sources. This patch tries to describe them in the DT compatible data. The two AO PWM controller has different clock source, but the first AO controller (A & B) can reuse the AXG parents name. Signed-off-by: Neil Armstrong Reviewed-by: Martin Blumenstingl Signed-off-by: Thierry Reding --- drivers/pwm/pwm-meson.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) (limited to 'drivers/pwm') diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c index e247ab632530..ba748027ecbf 100644 --- a/drivers/pwm/pwm-meson.c +++ b/drivers/pwm/pwm-meson.c @@ -433,6 +433,24 @@ static const struct meson_pwm_data pwm_axg_ao_data = { .num_parents = ARRAY_SIZE(pwm_axg_ao_parent_names), }; +static const char * const pwm_g12a_ao_cd_parent_names[] = { + "aoclk81", "xtal", +}; + +static const struct meson_pwm_data pwm_g12a_ao_cd_data = { + .parent_names = pwm_g12a_ao_cd_parent_names, + .num_parents = ARRAY_SIZE(pwm_g12a_ao_cd_parent_names), +}; + +static const char * const pwm_g12a_ee_parent_names[] = { + "xtal", "hdmi_pll", "fclk_div4", "fclk_div3" +}; + +static const struct meson_pwm_data pwm_g12a_ee_data = { + .parent_names = pwm_g12a_ee_parent_names, + .num_parents = ARRAY_SIZE(pwm_g12a_ee_parent_names), +}; + static const struct of_device_id meson_pwm_matches[] = { { .compatible = "amlogic,meson8b-pwm", @@ -454,6 +472,18 @@ static const struct of_device_id meson_pwm_matches[] = { .compatible = "amlogic,meson-axg-ao-pwm", .data = &pwm_axg_ao_data }, + { + .compatible = "amlogic,meson-g12a-ee-pwm", + .data = &pwm_g12a_ee_data + }, + { + .compatible = "amlogic,meson-g12a-ao-pwm-ab", + .data = &pwm_axg_ao_data + }, + { + .compatible = "amlogic,meson-g12a-ao-pwm-cd", + .data = &pwm_g12a_ao_cd_data + }, {}, }; MODULE_DEVICE_TABLE(of, meson_pwm_matches); -- cgit v1.2.3