From 72c35543f8cf1316773ffbd9619575bb84ac44fb Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Wed, 27 Sep 2006 18:27:43 +0900 Subject: sh: Support for L2 cache on newer SH-4A CPUs. This implements preliminary support for the L2 caches found on newer SH-4A CPUs. Signed-off-by: Paul Mundt --- include/asm-sh/cpu-features.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/asm-sh/cpu-features.h') diff --git a/include/asm-sh/cpu-features.h b/include/asm-sh/cpu-features.h index e1260aae3ee3..4bccd7c032f9 100644 --- a/include/asm-sh/cpu-features.h +++ b/include/asm-sh/cpu-features.h @@ -19,5 +19,6 @@ #define CPU_HAS_PERF_COUNTER 0x0010 /* Hardware performance counters */ #define CPU_HAS_PTEA 0x0020 /* PTEA register */ #define CPU_HAS_LLSC 0x0040 /* movli.l/movco.l */ +#define CPU_HAS_L2_CACHE 0x0080 /* Secondary cache / URAM */ #endif /* __ASM_SH_CPU_FEATURES_H */ -- cgit v1.2.3