From 846307185f0ffbbe6b34d53b97c31c0fc392cff0 Mon Sep 17 00:00:00 2001 From: Michael Tretter Date: Fri, 6 Oct 2023 17:07:05 +0200 Subject: drm/bridge: samsung-dsim: update PLL reference clock The PLL requires a clock frequency in a certain platform-dependent range after the pre-divider. The reference clock for the PLL may change due to changes to it's parent clock. Thus, the frequency may be out of range or unsuited for generating the high speed clock for MIPI DSI. Try to keep the pre-devider small, and set the reference clock close to the upper limit before recalculating the PLL configuration. Use a divider with a power of two for the reference clock as this seems to work best in my tests. Reviewed-by: Marco Felsch Tested-by: Frieder Schrempf # Kontron BL i.MX8MM + Waveshare 10.1inch HDMI LCD (E) Signed-off-by: Michael Tretter Tested-by: Marek Szyprowski Link: https://lore.kernel.org/r/20230818-samsung-dsim-v2-3-846603df0e0a@pengutronix.de Signed-off-by: Neil Armstrong Link: https://patchwork.freedesktop.org/patch/msgid/20230818-samsung-dsim-v2-3-846603df0e0a@pengutronix.de --- include/drm/bridge/samsung-dsim.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/drm/bridge') diff --git a/include/drm/bridge/samsung-dsim.h b/include/drm/bridge/samsung-dsim.h index 757f87337fe5..e0c105051246 100644 --- a/include/drm/bridge/samsung-dsim.h +++ b/include/drm/bridge/samsung-dsim.h @@ -61,6 +61,8 @@ struct samsung_dsim_driver_data { unsigned int num_bits_resol; unsigned int pll_p_offset; const unsigned int *reg_values; + unsigned int pll_fin_min; + unsigned int pll_fin_max; u16 m_min; u16 m_max; }; -- cgit v1.2.3