From 5b9979fda3058c786706d86b6e0ecb8e71be5a84 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Mon, 22 Apr 2024 13:53:50 +0300 Subject: dt-bindings: clock: r9a07g054-cpg: Add power domain IDs Add power domain IDs for the RZ/V2L (R9A07G054) SoC. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Acked-by: Rob Herring Reviewed-by: Ulf Hansson Link: https://lore.kernel.org/r/20240422105355.1622177-4-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- include/dt-bindings/clock/r9a07g054-cpg.h | 58 +++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) (limited to 'include/dt-bindings/clock/r9a07g054-cpg.h') diff --git a/include/dt-bindings/clock/r9a07g054-cpg.h b/include/dt-bindings/clock/r9a07g054-cpg.h index 43f4dbda872c..2c99f89397c4 100644 --- a/include/dt-bindings/clock/r9a07g054-cpg.h +++ b/include/dt-bindings/clock/r9a07g054-cpg.h @@ -226,4 +226,62 @@ #define R9A07G054_TSU_PRESETN 83 #define R9A07G054_STPAI_ARESETN 84 +/* Power domain IDs. */ +#define R9A07G054_PD_ALWAYS_ON 0 +#define R9A07G054_PD_GIC 1 +#define R9A07G054_PD_IA55 2 +#define R9A07G054_PD_MHU 3 +#define R9A07G054_PD_CORESIGHT 4 +#define R9A07G054_PD_SYC 5 +#define R9A07G054_PD_DMAC 6 +#define R9A07G054_PD_GTM0 7 +#define R9A07G054_PD_GTM1 8 +#define R9A07G054_PD_GTM2 9 +#define R9A07G054_PD_MTU 10 +#define R9A07G054_PD_POE3 11 +#define R9A07G054_PD_GPT 12 +#define R9A07G054_PD_POEGA 13 +#define R9A07G054_PD_POEGB 14 +#define R9A07G054_PD_POEGC 15 +#define R9A07G054_PD_POEGD 16 +#define R9A07G054_PD_WDT0 17 +#define R9A07G054_PD_WDT1 18 +#define R9A07G054_PD_SPI 19 +#define R9A07G054_PD_SDHI0 20 +#define R9A07G054_PD_SDHI1 21 +#define R9A07G054_PD_3DGE 22 +#define R9A07G054_PD_ISU 23 +#define R9A07G054_PD_VCPL4 24 +#define R9A07G054_PD_CRU 25 +#define R9A07G054_PD_MIPI_DSI 26 +#define R9A07G054_PD_LCDC 27 +#define R9A07G054_PD_SSI0 28 +#define R9A07G054_PD_SSI1 29 +#define R9A07G054_PD_SSI2 30 +#define R9A07G054_PD_SSI3 31 +#define R9A07G054_PD_SRC 32 +#define R9A07G054_PD_USB0 33 +#define R9A07G054_PD_USB1 34 +#define R9A07G054_PD_USB_PHY 35 +#define R9A07G054_PD_ETHER0 36 +#define R9A07G054_PD_ETHER1 37 +#define R9A07G054_PD_I2C0 38 +#define R9A07G054_PD_I2C1 39 +#define R9A07G054_PD_I2C2 40 +#define R9A07G054_PD_I2C3 41 +#define R9A07G054_PD_SCIF0 42 +#define R9A07G054_PD_SCIF1 43 +#define R9A07G054_PD_SCIF2 44 +#define R9A07G054_PD_SCIF3 45 +#define R9A07G054_PD_SCIF4 46 +#define R9A07G054_PD_SCI0 47 +#define R9A07G054_PD_SCI1 48 +#define R9A07G054_PD_IRDA 49 +#define R9A07G054_PD_RSPI0 50 +#define R9A07G054_PD_RSPI1 51 +#define R9A07G054_PD_RSPI2 52 +#define R9A07G054_PD_CANFD 53 +#define R9A07G054_PD_ADC 54 +#define R9A07G054_PD_TSU 55 + #endif /* __DT_BINDINGS_CLOCK_R9A07G054_CPG_H__ */ -- cgit v1.2.3