From fb91526b5fb04133799bc708661b467226caa032 Mon Sep 17 00:00:00 2001 From: Rex-BC Chen Date: Mon, 23 May 2022 17:33:40 +0800 Subject: dt-bindings: reset: mediatek: Add infra_ao reset index for MT8192/MT8195 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To support reset of infra_ao, add the index of infra_ao reset of thermal/svs/pcei for MT8192 and thermal/svs for MT8195. Signed-off-by: Rex-BC Chen Acked-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Nícolas F. R. A. Prado [Nícolas: Test for MT8192] Tested-by: Nícolas F. R. A. Prado Link: https://lore.kernel.org/r/20220523093346.28493-14-rex-bc.chen@mediatek.com Signed-off-by: Stephen Boyd --- include/dt-bindings/reset/mt8192-resets.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'include/dt-bindings/reset/mt8192-resets.h') diff --git a/include/dt-bindings/reset/mt8192-resets.h b/include/dt-bindings/reset/mt8192-resets.h index 764ca9910fa9..12e2087c90a3 100644 --- a/include/dt-bindings/reset/mt8192-resets.h +++ b/include/dt-bindings/reset/mt8192-resets.h @@ -7,6 +7,7 @@ #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192 #define _DT_BINDINGS_RESET_CONTROLLER_MT8192 +/* TOPRGU resets */ #define MT8192_TOPRGU_MM_SW_RST 1 #define MT8192_TOPRGU_MFG_SW_RST 2 #define MT8192_TOPRGU_VENC_SW_RST 3 @@ -30,4 +31,11 @@ /* MMSYS resets */ #define MT8192_MMSYS_SW0_RST_B_DISP_DSI0 15 +/* INFRA resets */ +#define MT8192_INFRA_RST0_THERM_CTRL_SWRST 0 +#define MT8192_INFRA_RST2_PEXTP_PHY_SWRST 1 +#define MT8192_INFRA_RST3_THERM_CTRL_PTP_SWRST 2 +#define MT8192_INFRA_RST4_PCIE_TOP_SWRST 3 +#define MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST 4 + #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */ -- cgit v1.2.3