From 029e9f73667f9b4661ac9886f706d75d26850260 Mon Sep 17 00:00:00 2001 From: Thomas Renninger Date: Thu, 21 Jul 2011 11:54:54 +0200 Subject: cpupower: Do detect IDA (opportunistic processor performance) via cpuid IA32-Intel Devel guide Volume 3A - 14.3.2.1 ------------------------------------------- ... Opportunistic processor performance operation can be disabled by setting bit 38 of IA32_MISC_ENABLES. This mechanism is intended for BIOS only. If IA32_MISC_ENABLES[38] is set, CPUID.06H:EAX[1] will return 0. Better detect things via cpuid, this cleans up the code a bit and the MSR parts were not working correctly anyway. Signed-off-by: Thomas Renninger CC: lenb@kernel.org CC: linux@dominikbrodowski.net CC: cpufreq@vger.kernel.org Signed-off-by: Dominik Brodowski --- tools/power/cpupower/utils/helpers/cpuid.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'tools/power/cpupower/utils/helpers/cpuid.c') diff --git a/tools/power/cpupower/utils/helpers/cpuid.c b/tools/power/cpupower/utils/helpers/cpuid.c index a97f091fcf2b..906895d21cce 100644 --- a/tools/power/cpupower/utils/helpers/cpuid.c +++ b/tools/power/cpupower/utils/helpers/cpuid.c @@ -130,6 +130,12 @@ out: cpu_info->caps |= CPUPOWER_CAP_AMD_CBP; } + if (cpu_info->vendor == X86_VENDOR_INTEL) { + if (cpuid_level >= 6 && + (cpuid_eax(6) & (1 << 1))) + cpu_info->caps |= CPUPOWER_CAP_INTEL_IDA; + } + if (cpu_info->vendor == X86_VENDOR_INTEL) { /* Intel's perf-bias MSR support */ if (cpuid_level >= 6 && (cpuid_ecx(6) & (1 << 3))) -- cgit v1.2.3