// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2023 Dario Binacchi <dario.binacchi@amarulasolutions.com>
 */

#include "stm32f746.dtsi"

/ {
	soc {
		can3: can@40003400 {
			compatible = "st,stm32f4-bxcan";
			reg = <0x40003400 0x200>;
			interrupts = <104>, <105>, <106>, <107>;
			interrupt-names = "tx", "rx0", "rx1", "sce";
			resets = <&rcc STM32F7_APB1_RESET(CAN3)>;
			clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
			st,gcan = <&gcan3>;
			status = "disabled";
		};

		gcan3: gcan@40003600 {
			compatible = "st,stm32f4-gcan", "syscon";
			reg = <0x40003600 0x200>;
			clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
		};

		dsi: dsi@40016c00 {
			compatible = "st,stm32-dsi";
			reg = <0x40016c00 0x800>;
			clocks = <&rcc 1 CLK_F769_DSI>, <&clk_hse>;
			clock-names = "pclk", "ref";
			resets = <&rcc STM32F7_APB2_RESET(DSI)>;
			reset-names = "apb";
			status = "disabled";
		};
	};
};