summaryrefslogtreecommitdiff
path: root/drivers/iio/frequency/admv1013.c
blob: c0cd5d9844fe9d1c28f217e8f94348cc8425f03b (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
// SPDX-License-Identifier: GPL-2.0-only
/*
 * ADMV1013 driver
 *
 * Copyright 2021 Analog Devices Inc.
 */

#include <linux/bitfield.h>
#include <linux/bits.h>
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/iio/iio.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/notifier.h>
#include <linux/property.h>
#include <linux/regulator/consumer.h>
#include <linux/spi/spi.h>
#include <linux/units.h>

#include <asm/unaligned.h>

/* ADMV1013 Register Map */
#define ADMV1013_REG_SPI_CONTROL		0x00
#define ADMV1013_REG_ALARM			0x01
#define ADMV1013_REG_ALARM_MASKS		0x02
#define ADMV1013_REG_ENABLE			0x03
#define ADMV1013_REG_LO_AMP_I			0x05
#define ADMV1013_REG_LO_AMP_Q			0x06
#define ADMV1013_REG_OFFSET_ADJUST_I		0x07
#define ADMV1013_REG_OFFSET_ADJUST_Q		0x08
#define ADMV1013_REG_QUAD			0x09
#define ADMV1013_REG_VVA_TEMP_COMP		0x0A

/* ADMV1013_REG_SPI_CONTROL Map */
#define ADMV1013_PARITY_EN_MSK			BIT(15)
#define ADMV1013_SPI_SOFT_RESET_MSK		BIT(14)
#define ADMV1013_CHIP_ID_MSK			GENMASK(11, 4)
#define ADMV1013_CHIP_ID			0xA
#define ADMV1013_REVISION_ID_MSK		GENMASK(3, 0)

/* ADMV1013_REG_ALARM Map */
#define ADMV1013_PARITY_ERROR_MSK		BIT(15)
#define ADMV1013_TOO_FEW_ERRORS_MSK		BIT(14)
#define ADMV1013_TOO_MANY_ERRORS_MSK		BIT(13)
#define ADMV1013_ADDRESS_RANGE_ERROR_MSK	BIT(12)

/* ADMV1013_REG_ENABLE Map */
#define ADMV1013_VGA_PD_MSK			BIT(15)
#define ADMV1013_MIXER_PD_MSK			BIT(14)
#define ADMV1013_QUAD_PD_MSK			GENMASK(13, 11)
#define ADMV1013_BG_PD_MSK			BIT(10)
#define ADMV1013_MIXER_IF_EN_MSK		BIT(7)
#define ADMV1013_DET_EN_MSK			BIT(5)

/* ADMV1013_REG_LO_AMP Map */
#define ADMV1013_LOAMP_PH_ADJ_FINE_MSK		GENMASK(13, 7)
#define ADMV1013_MIXER_VGATE_MSK		GENMASK(6, 0)

/* ADMV1013_REG_OFFSET_ADJUST Map */
#define ADMV1013_MIXER_OFF_ADJ_P_MSK		GENMASK(15, 9)
#define ADMV1013_MIXER_OFF_ADJ_N_MSK		GENMASK(8, 2)

/* ADMV1013_REG_QUAD Map */
#define ADMV1013_QUAD_SE_MODE_MSK		GENMASK(9, 6)
#define ADMV1013_QUAD_FILTERS_MSK		GENMASK(3, 0)

/* ADMV1013_REG_VVA_TEMP_COMP Map */
#define ADMV1013_VVA_TEMP_COMP_MSK		GENMASK(15, 0)

/* ADMV1013 Miscellaneous Defines */
#define ADMV1013_READ				BIT(7)
#define ADMV1013_REG_ADDR_READ_MSK		GENMASK(6, 1)
#define ADMV1013_REG_ADDR_WRITE_MSK		GENMASK(22, 17)
#define ADMV1013_REG_DATA_MSK			GENMASK(16, 1)

enum {
	ADMV1013_IQ_MODE,
	ADMV1013_IF_MODE
};

enum {
	ADMV1013_RFMOD_I_CALIBPHASE,
	ADMV1013_RFMOD_Q_CALIBPHASE,
};

enum {
	ADMV1013_SE_MODE_POS = 6,
	ADMV1013_SE_MODE_NEG = 9,
	ADMV1013_SE_MODE_DIFF = 12
};

struct admv1013_state {
	struct spi_device	*spi;
	struct clk		*clkin;
	/* Protect against concurrent accesses to the device and to data */
	struct mutex		lock;
	struct notifier_block	nb;
	unsigned int		input_mode;
	unsigned int		quad_se_mode;
	bool			det_en;
	u8			data[3] __aligned(IIO_DMA_MINALIGN);
};

static int __admv1013_spi_read(struct admv1013_state *st, unsigned int reg,
			       unsigned int *val)
{
	int ret;
	struct spi_transfer t = {0};

	st->data[0] = ADMV1013_READ | FIELD_PREP(ADMV1013_REG_ADDR_READ_MSK, reg);
	st->data[1] = 0x0;
	st->data[2] = 0x0;

	t.rx_buf = &st->data[0];
	t.tx_buf = &st->data[0];
	t.len = 3;

	ret = spi_sync_transfer(st->spi, &t, 1);
	if (ret)
		return ret;

	*val = FIELD_GET(ADMV1013_REG_DATA_MSK, get_unaligned_be24(&st->data[0]));

	return ret;
}

static int admv1013_spi_read(struct admv1013_state *st, unsigned int reg,
			     unsigned int *val)
{
	int ret;

	mutex_lock(&st->lock);
	ret = __admv1013_spi_read(st, reg, val);
	mutex_unlock(&st->lock);

	return ret;
}

static int __admv1013_spi_write(struct admv1013_state *st,
				unsigned int reg,
				unsigned int val)
{
	put_unaligned_be24(FIELD_PREP(ADMV1013_REG_DATA_MSK, val) |
			   FIELD_PREP(ADMV1013_REG_ADDR_WRITE_MSK, reg), &st->data[0]);

	return spi_write(st->spi, &st->data[0], 3);
}

static int admv1013_spi_write(struct admv1013_state *st, unsigned int reg,
			      unsigned int val)
{
	int ret;

	mutex_lock(&st->lock);
	ret = __admv1013_spi_write(st, reg, val);
	mutex_unlock(&st->lock);

	return ret;
}

static int __admv1013_spi_update_bits(struct admv1013_state *st, unsigned int reg,
				      unsigned int mask, unsigned int val)
{
	int ret;
	unsigned int data, temp;

	ret = __admv1013_spi_read(st, reg, &data);
	if (ret)
		return ret;

	temp = (data & ~mask) | (val & mask);

	return __admv1013_spi_write(st, reg, temp);
}

static int admv1013_spi_update_bits(struct admv1013_state *st, unsigned int reg,
				    unsigned int mask, unsigned int val)
{
	int ret;

	mutex_lock(&st->lock);
	ret = __admv1013_spi_update_bits(st, reg, mask, val);
	mutex_unlock(&st->lock);

	return ret;
}

static int admv1013_read_raw(struct iio_dev *indio_dev,
			     struct iio_chan_spec const *chan,
			     int *val, int *val2, long info)
{
	struct admv1013_state *st = iio_priv(indio_dev);
	unsigned int data, addr;
	int ret;

	switch (info) {
	case IIO_CHAN_INFO_CALIBBIAS:
		switch (chan->channel) {
		case IIO_MOD_I:
			addr = ADMV1013_REG_OFFSET_ADJUST_I;
			break;
		case IIO_MOD_Q:
			addr = ADMV1013_REG_OFFSET_ADJUST_Q;
			break;
		default:
			return -EINVAL;
		}

		ret = admv1013_spi_read(st, addr, &data);
		if (ret)
			return ret;

		if (!chan->channel)
			*val = FIELD_GET(ADMV1013_MIXER_OFF_ADJ_P_MSK, data);
		else
			*val = FIELD_GET(ADMV1013_MIXER_OFF_ADJ_N_MSK, data);

		return IIO_VAL_INT;
	default:
		return -EINVAL;
	}
}

static int admv1013_write_raw(struct iio_dev *indio_dev,
			      struct iio_chan_spec const *chan,
			      int val, int val2, long info)
{
	struct admv1013_state *st = iio_priv(indio_dev);
	unsigned int addr, data, msk;

	switch (info) {
	case IIO_CHAN_INFO_CALIBBIAS:
		switch (chan->channel2) {
		case IIO_MOD_I:
			addr = ADMV1013_REG_OFFSET_ADJUST_I;
			break;
		case IIO_MOD_Q:
			addr = ADMV1013_REG_OFFSET_ADJUST_Q;
			break;
		default:
			return -EINVAL;
		}

		if (!chan->channel) {
			msk = ADMV1013_MIXER_OFF_ADJ_P_MSK;
			data = FIELD_PREP(ADMV1013_MIXER_OFF_ADJ_P_MSK, val);
		} else {
			msk = ADMV1013_MIXER_OFF_ADJ_N_MSK;
			data = FIELD_PREP(ADMV1013_MIXER_OFF_ADJ_N_MSK, val);
		}

		return admv1013_spi_update_bits(st, addr, msk, data);
	default:
		return -EINVAL;
	}
}

static ssize_t admv1013_read(struct iio_dev *indio_dev,
			     uintptr_t private,
			     const struct iio_chan_spec *chan,
			     char *buf)
{
	struct admv1013_state *st = iio_priv(indio_dev);
	unsigned int data, addr;
	int ret;

	switch ((u32)private) {
	case ADMV1013_RFMOD_I_CALIBPHASE:
		addr = ADMV1013_REG_LO_AMP_I;
		break;
	case ADMV1013_RFMOD_Q_CALIBPHASE:
		addr = ADMV1013_REG_LO_AMP_Q;
		break;
	default:
		return -EINVAL;
	}

	ret = admv1013_spi_read(st, addr, &data);
	if (ret)
		return ret;

	data = FIELD_GET(ADMV1013_LOAMP_PH_ADJ_FINE_MSK, data);

	return sysfs_emit(buf, "%u\n", data);
}

static ssize_t admv1013_write(struct iio_dev *indio_dev,
			      uintptr_t private,
			      const struct iio_chan_spec *chan,
			      const char *buf, size_t len)
{
	struct admv1013_state *st = iio_priv(indio_dev);
	unsigned int data;
	int ret;

	ret = kstrtou32(buf, 10, &data);
	if (ret)
		return ret;

	data = FIELD_PREP(ADMV1013_LOAMP_PH_ADJ_FINE_MSK, data);

	switch ((u32)private) {
	case ADMV1013_RFMOD_I_CALIBPHASE:
		ret = admv1013_spi_update_bits(st, ADMV1013_REG_LO_AMP_I,
					       ADMV1013_LOAMP_PH_ADJ_FINE_MSK,
					       data);
		if (ret)
			return ret;
		break;
	case ADMV1013_RFMOD_Q_CALIBPHASE:
		ret = admv1013_spi_update_bits(st, ADMV1013_REG_LO_AMP_Q,
					       ADMV1013_LOAMP_PH_ADJ_FINE_MSK,
					       data);
		if (ret)
			return ret;
		break;
	default:
		return -EINVAL;
	}

	return ret ? ret : len;
}

static int admv1013_update_quad_filters(struct admv1013_state *st)
{
	unsigned int filt_raw;
	u64 rate = clk_get_rate(st->clkin);

	if (rate >= (5400 * HZ_PER_MHZ) && rate <= (7000 * HZ_PER_MHZ))
		filt_raw = 15;
	else if (rate >= (5400 * HZ_PER_MHZ) && rate <= (8000 * HZ_PER_MHZ))
		filt_raw = 10;
	else if (rate >= (6600 * HZ_PER_MHZ) && rate <= (9200 * HZ_PER_MHZ))
		filt_raw = 5;
	else
		filt_raw = 0;

	return __admv1013_spi_update_bits(st, ADMV1013_REG_QUAD,
					ADMV1013_QUAD_FILTERS_MSK,
					FIELD_PREP(ADMV1013_QUAD_FILTERS_MSK, filt_raw));
}

static int admv1013_update_mixer_vgate(struct admv1013_state *st, int vcm)
{
	unsigned int mixer_vgate;

	if (vcm <= 1800000)
		mixer_vgate = (2389 * vcm / 1000000 + 8100) / 100;
	else if (vcm > 1800000 && vcm <= 2600000)
		mixer_vgate = (2375 * vcm / 1000000 + 125) / 100;
	else
		return -EINVAL;

	return __admv1013_spi_update_bits(st, ADMV1013_REG_LO_AMP_I,
				 ADMV1013_MIXER_VGATE_MSK,
				 FIELD_PREP(ADMV1013_MIXER_VGATE_MSK, mixer_vgate));
}

static int admv1013_reg_access(struct iio_dev *indio_dev,
			       unsigned int reg,
			       unsigned int write_val,
			       unsigned int *read_val)
{
	struct admv1013_state *st = iio_priv(indio_dev);

	if (read_val)
		return admv1013_spi_read(st, reg, read_val);
	else
		return admv1013_spi_write(st, reg, write_val);
}

static const struct iio_info admv1013_info = {
	.read_raw = admv1013_read_raw,
	.write_raw = admv1013_write_raw,
	.debugfs_reg_access = &admv1013_reg_access,
};

static const char * const admv1013_vcc_regs[] = {
	 "vcc-drv", "vcc2-drv", "vcc-vva", "vcc-amp1", "vcc-amp2",
	 "vcc-env", "vcc-bg", "vcc-bg2", "vcc-mixer", "vcc-quad"
};

static int admv1013_freq_change(struct notifier_block *nb, unsigned long action, void *data)
{
	struct admv1013_state *st = container_of(nb, struct admv1013_state, nb);
	int ret;

	if (action == POST_RATE_CHANGE) {
		mutex_lock(&st->lock);
		ret = notifier_from_errno(admv1013_update_quad_filters(st));
		mutex_unlock(&st->lock);
		return ret;
	}

	return NOTIFY_OK;
}

#define _ADMV1013_EXT_INFO(_name, _shared, _ident) { \
		.name = _name, \
		.read = admv1013_read, \
		.write = admv1013_write, \
		.private = _ident, \
		.shared = _shared, \
}

static const struct iio_chan_spec_ext_info admv1013_ext_info[] = {
	_ADMV1013_EXT_INFO("i_calibphase", IIO_SEPARATE, ADMV1013_RFMOD_I_CALIBPHASE),
	_ADMV1013_EXT_INFO("q_calibphase", IIO_SEPARATE, ADMV1013_RFMOD_Q_CALIBPHASE),
	{ },
};

#define ADMV1013_CHAN_PHASE(_channel, _channel2, _admv1013_ext_info) {		\
	.type = IIO_ALTVOLTAGE,					\
	.output = 0,						\
	.indexed = 1,						\
	.channel2 = _channel2,					\
	.channel = _channel,					\
	.differential = 1,					\
	.ext_info = _admv1013_ext_info,				\
	}

#define ADMV1013_CHAN_CALIB(_channel, rf_comp) {	\
	.type = IIO_ALTVOLTAGE,					\
	.output = 0,						\
	.indexed = 1,						\
	.channel = _channel,					\
	.channel2 = IIO_MOD_##rf_comp,				\
	.info_mask_separate = BIT(IIO_CHAN_INFO_CALIBBIAS),	\
	}

static const struct iio_chan_spec admv1013_channels[] = {
	ADMV1013_CHAN_PHASE(0, 1, admv1013_ext_info),
	ADMV1013_CHAN_CALIB(0, I),
	ADMV1013_CHAN_CALIB(0, Q),
	ADMV1013_CHAN_CALIB(1, I),
	ADMV1013_CHAN_CALIB(1, Q),
};

static int admv1013_init(struct admv1013_state *st, int vcm_uv)
{
	int ret;
	unsigned int data;
	struct spi_device *spi = st->spi;

	/* Perform a software reset */
	ret = __admv1013_spi_update_bits(st, ADMV1013_REG_SPI_CONTROL,
					 ADMV1013_SPI_SOFT_RESET_MSK,
					 FIELD_PREP(ADMV1013_SPI_SOFT_RESET_MSK, 1));
	if (ret)
		return ret;

	ret = __admv1013_spi_update_bits(st, ADMV1013_REG_SPI_CONTROL,
					 ADMV1013_SPI_SOFT_RESET_MSK,
					 FIELD_PREP(ADMV1013_SPI_SOFT_RESET_MSK, 0));
	if (ret)
		return ret;

	ret = __admv1013_spi_read(st, ADMV1013_REG_SPI_CONTROL, &data);
	if (ret)
		return ret;

	data = FIELD_GET(ADMV1013_CHIP_ID_MSK, data);
	if (data != ADMV1013_CHIP_ID) {
		dev_err(&spi->dev, "Invalid Chip ID.\n");
		return -EINVAL;
	}

	ret = __admv1013_spi_write(st, ADMV1013_REG_VVA_TEMP_COMP, 0xE700);
	if (ret)
		return ret;

	data = FIELD_PREP(ADMV1013_QUAD_SE_MODE_MSK, st->quad_se_mode);

	ret = __admv1013_spi_update_bits(st, ADMV1013_REG_QUAD,
					 ADMV1013_QUAD_SE_MODE_MSK, data);
	if (ret)
		return ret;

	ret = admv1013_update_mixer_vgate(st, vcm_uv);
	if (ret)
		return ret;

	ret = admv1013_update_quad_filters(st);
	if (ret)
		return ret;

	return __admv1013_spi_update_bits(st, ADMV1013_REG_ENABLE,
					  ADMV1013_DET_EN_MSK |
					  ADMV1013_MIXER_IF_EN_MSK,
					  st->det_en |
					  st->input_mode);
}

static void admv1013_powerdown(void *data)
{
	unsigned int enable_reg, enable_reg_msk;

	/* Disable all components in the Enable Register */
	enable_reg_msk = ADMV1013_VGA_PD_MSK |
			ADMV1013_MIXER_PD_MSK |
			ADMV1013_QUAD_PD_MSK |
			ADMV1013_BG_PD_MSK |
			ADMV1013_MIXER_IF_EN_MSK |
			ADMV1013_DET_EN_MSK;

	enable_reg = FIELD_PREP(ADMV1013_VGA_PD_MSK, 1) |
			FIELD_PREP(ADMV1013_MIXER_PD_MSK, 1) |
			FIELD_PREP(ADMV1013_QUAD_PD_MSK, 7) |
			FIELD_PREP(ADMV1013_BG_PD_MSK, 1) |
			FIELD_PREP(ADMV1013_MIXER_IF_EN_MSK, 0) |
			FIELD_PREP(ADMV1013_DET_EN_MSK, 0);

	admv1013_spi_update_bits(data, ADMV1013_REG_ENABLE, enable_reg_msk, enable_reg);
}

static int admv1013_properties_parse(struct admv1013_state *st)
{
	int ret;
	const char *str;
	struct spi_device *spi = st->spi;

	st->det_en = device_property_read_bool(&spi->dev, "adi,detector-enable");

	ret = device_property_read_string(&spi->dev, "adi,input-mode", &str);
	if (ret)
		st->input_mode = ADMV1013_IQ_MODE;

	if (!strcmp(str, "iq"))
		st->input_mode = ADMV1013_IQ_MODE;
	else if (!strcmp(str, "if"))
		st->input_mode = ADMV1013_IF_MODE;
	else
		return -EINVAL;

	ret = device_property_read_string(&spi->dev, "adi,quad-se-mode", &str);
	if (ret)
		st->quad_se_mode = ADMV1013_SE_MODE_DIFF;

	if (!strcmp(str, "diff"))
		st->quad_se_mode = ADMV1013_SE_MODE_DIFF;
	else if (!strcmp(str, "se-pos"))
		st->quad_se_mode = ADMV1013_SE_MODE_POS;
	else if (!strcmp(str, "se-neg"))
		st->quad_se_mode = ADMV1013_SE_MODE_NEG;
	else
		return -EINVAL;

	ret = devm_regulator_bulk_get_enable(&st->spi->dev,
					     ARRAY_SIZE(admv1013_vcc_regs),
					     admv1013_vcc_regs);
	if (ret) {
		dev_err_probe(&spi->dev, ret,
			      "Failed to request VCC regulators\n");
		return ret;
	}

	return 0;
}

static int admv1013_probe(struct spi_device *spi)
{
	struct iio_dev *indio_dev;
	struct admv1013_state *st;
	int ret, vcm_uv;

	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
	if (!indio_dev)
		return -ENOMEM;

	st = iio_priv(indio_dev);

	indio_dev->info = &admv1013_info;
	indio_dev->name = "admv1013";
	indio_dev->channels = admv1013_channels;
	indio_dev->num_channels = ARRAY_SIZE(admv1013_channels);

	st->spi = spi;

	ret = admv1013_properties_parse(st);
	if (ret)
		return ret;

	ret = devm_regulator_get_enable_read_voltage(&spi->dev, "vcm");
	if (ret < 0)
		return dev_err_probe(&spi->dev, ret,
				     "failed to get the common-mode voltage\n");

	vcm_uv = ret;

	st->clkin = devm_clk_get_enabled(&spi->dev, "lo_in");
	if (IS_ERR(st->clkin))
		return dev_err_probe(&spi->dev, PTR_ERR(st->clkin),
				     "failed to get the LO input clock\n");

	st->nb.notifier_call = admv1013_freq_change;
	ret = devm_clk_notifier_register(&spi->dev, st->clkin, &st->nb);
	if (ret)
		return ret;

	mutex_init(&st->lock);

	ret = admv1013_init(st, vcm_uv);
	if (ret) {
		dev_err(&spi->dev, "admv1013 init failed\n");
		return ret;
	}

	ret = devm_add_action_or_reset(&spi->dev, admv1013_powerdown, st);
	if (ret)
		return ret;

	return devm_iio_device_register(&spi->dev, indio_dev);
}

static const struct spi_device_id admv1013_id[] = {
	{ "admv1013", 0 },
	{}
};
MODULE_DEVICE_TABLE(spi, admv1013_id);

static const struct of_device_id admv1013_of_match[] = {
	{ .compatible = "adi,admv1013" },
	{},
};
MODULE_DEVICE_TABLE(of, admv1013_of_match);

static struct spi_driver admv1013_driver = {
	.driver = {
		.name = "admv1013",
		.of_match_table = admv1013_of_match,
	},
	.probe = admv1013_probe,
	.id_table = admv1013_id,
};
module_spi_driver(admv1013_driver);

MODULE_AUTHOR("Antoniu Miclaus <antoniu.miclaus@analog.com");
MODULE_DESCRIPTION("Analog Devices ADMV1013");
MODULE_LICENSE("GPL v2");