diff options
| author | Atish Patra <atish.patra@wdc.com> | 2020-05-10 02:47:24 +0300 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2020-05-10 07:29:20 +0300 |
| commit | aef9a60d521a7810557d1caf826311bc349691ac (patch) | |
| tree | eb81d072b85951e695c8e8f74658fb76b44c7185 | |
| parent | 63a513edeccee1758bbfe5111ccc4fbec8f18a12 (diff) | |
| download | opensbi-aef9a60d521a7810557d1caf826311bc349691ac.tar.xz | |
lib: Add csr detect support
As RISC-V ISA allows many CSRs such as pmp, s/mcounteren to be optional
in hardware, OpenSBI should provide an option to dynamically detect
these csr access capability at run time.
Implement a csr read/write access check helper macros.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Tested-by: Jonathan Balkind <jbalkind@cs.princeton.edu>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
| -rw-r--r-- | include/sbi/sbi_csr_detect.h | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/include/sbi/sbi_csr_detect.h b/include/sbi/sbi_csr_detect.h new file mode 100644 index 0000000..f294888 --- /dev/null +++ b/include/sbi/sbi_csr_detect.h @@ -0,0 +1,50 @@ +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2020 Western Digital Corporation or its affiliates. + * + * Authors: + * Atish Patra <atish.patra@wdc.com> + */ + +#ifndef __SBI_CSR_DETECT__H +#define __SBI_CSR_DETECT__H + +#include <sbi/riscv_encoding.h> +#include <sbi/sbi_hart.h> + +#define csr_read_allowed(csr_num, trap) \ + ({ \ + register ulong tinfo asm("a3") = (ulong)trap; \ + register ulong ttmp asm("a4"); \ + register ulong mtvec = sbi_hart_expected_trap_addr(); \ + register ulong ret = 0; \ + asm volatile( \ + "add %[ttmp], %[tinfo], zero\n" \ + "csrrw %[mtvec], " STR(CSR_MTVEC) ", %[mtvec]\n" \ + "csrr %[ret], %[csr]\n" \ + "csrw " STR(CSR_MTVEC) ", %[mtvec]" \ + : [mtvec] "+&r"(mtvec), [tinfo] "+&r"(tinfo), \ + [ttmp] "+&r"(ttmp), [ret] "=&r" (ret) \ + : [csr] "i" (csr_num) \ + : "memory"); \ + ret; \ + }) \ + +#define csr_write_allowed(csr_num, trap, value) \ + ({ \ + register ulong tinfo asm("a3") = (ulong)trap; \ + register ulong ttmp asm("a4"); \ + register ulong mtvec = sbi_hart_expected_trap_addr(); \ + asm volatile( \ + "add %[ttmp], %[tinfo], zero\n" \ + "csrrw %[mtvec], " STR(CSR_MTVEC) ", %[mtvec]\n" \ + "csrw %[csr], %[val]\n" \ + "csrw " STR(CSR_MTVEC) ", %[mtvec]" \ + : [mtvec] "+&r"(mtvec), \ + [tinfo] "+&r"(tinfo), [ttmp] "+&r"(ttmp) \ + : [csr] "i" (csr_num), [val] "r" (value) \ + : "memory"); \ + }) \ + +#endif |