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| author | Xiang W <wxjstz@126.com> | 2022-03-15 19:22:38 +0300 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2022-03-27 06:22:19 +0300 |
| commit | 2dfbd3c0e226c21b978e0a5a1c58893ee6679d15 (patch) | |
| tree | f7cca3eeac48dc6744572a37c365d1c725bd262c | |
| parent | 4998a712b2ab504eff306110879ee05af6050177 (diff) | |
| download | opensbi-2dfbd3c0e226c21b978e0a5a1c58893ee6679d15.tar.xz | |
lib: pmp_set/pmp_get moved errors from runtime to compile time
pmp_set/pmp_get calculates the location of the CSR register separately
through conditional compilation. In the case of non-32-bit and 64-bit,
we can report an error directly through #error without putting it at
runtime
Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
| -rw-r--r-- | lib/sbi/riscv_asm.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/sbi/riscv_asm.c b/lib/sbi/riscv_asm.c index 847bdba..5eab1ed 100644 --- a/lib/sbi/riscv_asm.c +++ b/lib/sbi/riscv_asm.c @@ -261,7 +261,7 @@ int pmp_set(unsigned int n, unsigned long prot, unsigned long addr, pmpcfg_csr = (CSR_PMPCFG0 + (n >> 2)) & ~1; pmpcfg_shift = (n & 7) << 3; #else - return SBI_ENOTSUPP; +# error "Unexpected __riscv_xlen" #endif pmpaddr_csr = CSR_PMPADDR0 + n; @@ -312,7 +312,7 @@ int pmp_get(unsigned int n, unsigned long *prot_out, unsigned long *addr_out, pmpcfg_csr = (CSR_PMPCFG0 + (n >> 2)) & ~1; pmpcfg_shift = (n & 7) << 3; #else - return SBI_ENOTSUPP; +# error "Unexpected __riscv_xlen" #endif pmpaddr_csr = CSR_PMPADDR0 + n; |