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| author | Zong Li <zong.li@sifive.com> | 2019-09-27 06:14:02 +0300 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2019-09-28 15:53:13 +0300 |
| commit | 1ed9eb255d865e75be2d2a87d9ef670c502294cc (patch) | |
| tree | 88ab46b6c41ace4f91300df1368c3e92075f939d | |
| parent | 0a482e2edbc4e0d0a88199b76de5591cc99a11ab (diff) | |
| download | opensbi-1ed9eb255d865e75be2d2a87d9ef670c502294cc.tar.xz | |
Write MSIP by using memory-mapped control register
The machine-level MSIP bits are written by accesses to memory-mapped
control registers. Only use CSR instruction for SSIP and USIP.
There is no effect that using CSR instruction to write MSIP when testing
on unleashed board and QEMU.
Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
| -rw-r--r-- | lib/sbi/sbi_hart.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c index 6bf0e13..018fe85 100644 --- a/lib/sbi/sbi_hart.c +++ b/lib/sbi/sbi_hart.c @@ -341,7 +341,7 @@ void sbi_hart_wait_for_coldboot(struct sbi_scratch *scratch, u32 hartid) spin_unlock(&coldboot_wait_bitmap_lock); } while (!(mipval & MIP_MSIP)); - csr_clear(CSR_MIP, MIP_MSIP); + sbi_platform_ipi_clear(plat, hartid); } void sbi_hart_wake_coldboot_harts(struct sbi_scratch *scratch, u32 hartid) |