lib: Use CSR_<FOO> instead of <foo> for csr_*()

Some older toolchains may not have all the csr's defined. Update all
the csr functions to use the CSR_ #define values instead of the
toolchain defined values.

Suggested-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Atish Patra <atish.patra@wdc.com>

11 files changed, 84 insertions, 76 deletions

diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h
index b441c8e..3f1676c 100644
--- a/include/sbi/riscv_encoding.h
+++ b/include/sbi/riscv_encoding.h
@@ -195,10 +195,18 @@
 #define RISCV_PGSHIFT			12
 #define RISCV_PGSIZE			(1 << RISCV_PGSHIFT)
 
+#define CSR_USTATUS			0x0
 #define CSR_FFLAGS			0x1
 #define CSR_FRM				0x2
 #define CSR_FCSR			0x3
 #define CSR_CYCLE			0xc00
+#define CSR_UIE				0x4
+#define CSR_UTVEC			0x5
+#define CSR_USCRATCH			0x40
+#define CSR_UEPC			0x41
+#define CSR_UCAUSE			0x42
+#define CSR_UTVAL			0x43
+#define CSR_UIP				0x44
 #define CSR_TIME			0xc01
 #define CSR_INSTRET			0xc02
 #define CSR_HPMCOUNTER3			0xc03
diff --git a/include/sbi/riscv_fp.h b/include/sbi/riscv_fp.h
index 7143023..9e2e082 100644
--- a/include/sbi/riscv_fp.h
+++ b/include/sbi/riscv_fp.h
@@ -43,12 +43,12 @@
   ulong offset = SHIFT_RIGHT(insn, (pos)-3) & 0xf8; \
   ulong tmp; \
   asm volatile ("1: auipc %0, %%pcrel_hi(put_f64_reg); add %0, %0, %2; jalr t0, %0, %%pcrel_lo(1b)" : "=&r"(tmp) : "r"(value), "r"(offset) : "t0"); })
-#define GET_FCSR() csr_read(fcsr)
-#define SET_FCSR(value) csr_write(fcsr, (value))
-#define GET_FRM() csr_read(frm)
-#define SET_FRM(value) csr_write(frm, (value))
-#define GET_FFLAGS() csr_read(fflags)
-#define SET_FFLAGS(value) csr_write(fflags, (value))
+#define GET_FCSR() csr_read(CSR_FCSR)
+#define SET_FCSR(value) csr_write(CSR_FCSR, (value))
+#define GET_FRM() csr_read(CSR_FRM)
+#define SET_FRM(value) csr_write(CSR_FRM, (value))
+#define GET_FFLAGS() csr_read(CSR_FFLAGS)
+#define SET_FFLAGS(value) csr_write(CSR_FFLAGS, (value))
 
 #define SET_FS_DIRTY() ((void) 0)
 
diff --git a/include/sbi/sbi_scratch.h b/include/sbi/sbi_scratch.h
index e4c648c..ff6aed0 100644
--- a/include/sbi/sbi_scratch.h
+++ b/include/sbi/sbi_scratch.h
@@ -61,7 +61,7 @@ struct sbi_scratch {
 
 /** Get pointer to sbi_scratch for current HART */
 #define sbi_scratch_thishart_ptr()	\
-((struct sbi_scratch *)csr_read(mscratch))
+((struct sbi_scratch *)csr_read(CSR_MSCRATCH))
 
 /** Get Arg1 of next booting stage for current HART */
 #define sbi_scratch_thishart_arg1_ptr()	\
diff --git a/include/sbi/sbi_unpriv.h b/include/sbi/sbi_unpriv.h
index 11ece0d..930babd 100644
--- a/include/sbi/sbi_unpriv.h
+++ b/include/sbi/sbi_unpriv.h
@@ -20,9 +20,9 @@ static inline type load_##type(const type *addr, ulong mepc)		\
 	register ulong __mepc asm ("a2") = mepc;			\
 	register ulong __mstatus asm ("a3");				\
 	type val;							\
-	asm ("csrrs %0, mstatus, %3\n"					\
+	asm ("csrrs %0, "STR(CSR_MSTATUS)", %3\n"					\
 		#insn " %1, %2\n"					\
-		"csrw mstatus, %0"					\
+		"csrw "STR(CSR_MSTATUS)", %0"					\
 	: "+&r" (__mstatus), "=&r" (val)				\
 	: "m" (*addr), "r" (MSTATUS_MPRV), "r" (__mepc));		\
 	return val;							\
@@ -33,9 +33,9 @@ static inline void store_##type(type *addr, type val, ulong mepc)	\
 {									\
 	register ulong __mepc asm ("a2") = mepc;			\
 	register ulong __mstatus asm ("a3");				\
-	asm volatile ("csrrs %0, mstatus, %3\n"				\
+	asm volatile ("csrrs %0, "STR(CSR_MSTATUS)", %3\n"				\
 		#insn " %1, %2\n"					\
-		"csrw mstatus, %0"					\
+		"csrw "STR(CSR_MSTATUS)", %0"					\
 	: "+&r" (__mstatus)						\
 	: "r" (val), "m" (*addr), "r" (MSTATUS_MPRV), "r" (__mepc));	\
 }
@@ -76,18 +76,18 @@ static inline ulong get_insn(ulong mepc, ulong *mstatus)
 	register ulong __mstatus asm ("a3");
 	ulong val;
 #ifndef __riscv_compressed
-	asm ("csrrs %[mstatus], mstatus, %[mprv]\n"
+	asm ("csrrs %[mstatus], "STR(CSR_MSTATUS)", %[mprv]\n"
 #if __riscv_xlen == 64
 		STR(LWU) " %[insn], (%[addr])\n"
 #else
 		STR(LW) " %[insn], (%[addr])\n"
 #endif
-		"csrw mstatus, %[mstatus]"
+		"csrw "STR(CSR_MSTATUS)", %[mstatus]"
 		: [mstatus] "+&r" (__mstatus), [insn] "=&r" (val)
 		: [mprv] "r" (MSTATUS_MPRV | MSTATUS_MXR), [addr] "r" (__mepc));
 #else
 	ulong rvc_mask = 3, tmp;
-	asm ("csrrs %[mstatus], mstatus, %[mprv]\n"
+	asm ("csrrs %[mstatus], "STR(CSR_MSTATUS)", %[mprv]\n"
 		"and %[tmp], %[addr], 2\n"
 		"bnez %[tmp], 1f\n"
 #if __riscv_xlen == 64
@@ -107,7 +107,7 @@ static inline ulong get_insn(ulong mepc, ulong *mstatus)
 		"lhu %[tmp], 2(%[addr])\n"
 		"sll %[tmp], %[tmp], 16\n"
 		"add %[insn], %[insn], %[tmp]\n"
-		"2: csrw mstatus, %[mstatus]"
+		"2: csrw "STR(CSR_MSTATUS)", %[mstatus]"
 	: [mstatus] "+&r" (__mstatus), [insn] "=&r" (val), [tmp] "=&r" (tmp)
 	: [mprv] "r" (MSTATUS_MPRV | MSTATUS_MXR), [addr] "r" (__mepc),
 	[rvc_mask] "r" (rvc_mask), [xlen_minus_16] "i" (__riscv_xlen - 16));
diff --git a/lib/sbi_emulate_csr.c b/lib/sbi_emulate_csr.c
index 1d52aac..bdc2c67 100644
--- a/lib/sbi_emulate_csr.c
+++ b/lib/sbi_emulate_csr.c
@@ -23,13 +23,13 @@ int sbi_emulate_csr_read(int csr_num,
 	ulong cen = -1UL;
 
 	if (EXTRACT_FIELD(mstatus, MSTATUS_MPP) == PRV_U)
-		cen = csr_read(scounteren);
+		cen = csr_read(CSR_SCOUNTEREN);
 
 	switch (csr_num) {
 	case CSR_CYCLE:
 		if (!((cen >> (CSR_CYCLE - CSR_CYCLE)) & 1))
 			return -1;
-		*csr_val = csr_read(mcycle);
+		*csr_val = csr_read(CSR_MCYCLE);
 		break;
 	case CSR_TIME:
 		if (!((cen >> (CSR_TIME - CSR_CYCLE)) & 1))
@@ -39,23 +39,23 @@ int sbi_emulate_csr_read(int csr_num,
 	case CSR_INSTRET:
 		if (!((cen >> (CSR_INSTRET - CSR_CYCLE)) & 1))
 			return -1;
-		*csr_val = csr_read(minstret);
+		*csr_val = csr_read(CSR_MINSTRET);
 		break;
 	case CSR_MHPMCOUNTER3:
 		if (!((cen >> (3 + CSR_MHPMCOUNTER3 - CSR_MHPMCOUNTER3)) & 1))
 			return -1;
-		*csr_val = csr_read(mhpmcounter3);
+		*csr_val = csr_read(CSR_MHPMCOUNTER3);
 		break;
 	case CSR_MHPMCOUNTER4:
 		if (!((cen >> (3 + CSR_MHPMCOUNTER4 - CSR_MHPMCOUNTER3)) & 1))
 			return -1;
-		*csr_val = csr_read(mhpmcounter4);
+		*csr_val = csr_read(CSR_MHPMCOUNTER4);
 		break;
 #if __riscv_xlen == 32
 	case CSR_CYCLEH:
 		if (!((cen >> (CSR_CYCLE - CSR_CYCLE)) & 1))
 			return -1;
-		*csr_val = csr_read(mcycleh);
+		*csr_val = csr_read(CSR_MCYCLEH);
 		break;
 	case CSR_TIMEH:
 		if (!((cen >> (CSR_TIME - CSR_CYCLE)) & 1))
@@ -65,24 +65,24 @@ int sbi_emulate_csr_read(int csr_num,
 	case CSR_INSTRETH:
 		if (!((cen >> (CSR_INSTRET - CSR_CYCLE)) & 1))
 			return -1;
-		*csr_val = csr_read(minstreth);
+		*csr_val = csr_read(CSR_MINSTRETH);
 		break;
 	case CSR_MHPMCOUNTER3H:
 		if (!((cen >> (3 + CSR_MHPMCOUNTER3 - CSR_MHPMCOUNTER3)) & 1))
 			return -1;
-		*csr_val = csr_read(mhpmcounter3h);
+		*csr_val = csr_read(CSR_MHPMCOUNTER3H);
 		break;
 	case CSR_MHPMCOUNTER4H:
 		if (!((cen >> (3 + CSR_MHPMCOUNTER4 - CSR_MHPMCOUNTER3)) & 1))
 			return -1;
-		*csr_val = csr_read(mhpmcounter4h);
+		*csr_val = csr_read(CSR_MHPMCOUNTER4H);
 		break;
 #endif
 	case CSR_MHPMEVENT3:
-		*csr_val = csr_read(mhpmevent3);
+		*csr_val = csr_read(CSR_MHPMEVENT3);
 		break;
 	case CSR_MHPMEVENT4:
-		*csr_val = csr_read(mhpmevent4);
+		*csr_val = csr_read(CSR_MHPMEVENT4);
 		break;
 	default:
 		sbi_printf("%s: hartid%d: invalid csr_num=0x%x\n",
@@ -100,36 +100,36 @@ int sbi_emulate_csr_write(int csr_num,
 {
 	switch (csr_num) {
 	case CSR_CYCLE:
-		csr_write(mcycle, csr_val);
+		csr_write(CSR_MCYCLE, csr_val);
 		break;
 	case CSR_INSTRET:
-		csr_write(minstret, csr_val);
+		csr_write(CSR_MINSTRET, csr_val);
 		break;
 	case CSR_MHPMCOUNTER3:
-		csr_write(mhpmcounter3, csr_val);
+		csr_write(CSR_MHPMCOUNTER3, csr_val);
 		break;
 	case CSR_MHPMCOUNTER4:
-		csr_write(mhpmcounter4, csr_val);
+		csr_write(CSR_MHPMCOUNTER4, csr_val);
 		break;
 #if __riscv_xlen == 32
 	case CSR_CYCLEH:
-		csr_write(mcycleh, csr_val);
+		csr_write(CSR_MCYCLEH, csr_val);
 		break;
 	case CSR_INSTRETH:
-		csr_write(minstreth, csr_val);
+		csr_write(CSR_MINSTRETH, csr_val);
 		break;
 	case CSR_MHPMCOUNTER3H:
-		csr_write(mhpmcounter3h, csr_val);
+		csr_write(CSR_MHPMCOUNTER3H, csr_val);
 		break;
 	case CSR_MHPMCOUNTER4H:
-		csr_write(mhpmcounter4h, csr_val);
+		csr_write(CSR_MHPMCOUNTER4H, csr_val);
 		break;
 #endif
 	case CSR_MHPMEVENT3:
-		csr_write(mhpmevent3, csr_val);
+		csr_write(CSR_MHPMEVENT3, csr_val);
 		break;
 	case CSR_MHPMEVENT4:
-		csr_write(mhpmevent4, csr_val);
+		csr_write(CSR_MHPMEVENT4, csr_val);
 		break;
 	default:
 		sbi_printf("%s: hartid%d: invalid csr_num=0x%x\n",
diff --git a/lib/sbi_hart.c b/lib/sbi_hart.c
index ae11a52..e3b2219 100644
--- a/lib/sbi_hart.c
+++ b/lib/sbi_hart.c
@@ -23,7 +23,7 @@
  */
 unsigned int sbi_current_hartid()
 {
-	return (u32)csr_read(mhartid);
+	return (u32)csr_read(CSR_MHARTID);
 }
 
 static void mstatus_init(struct sbi_scratch *scratch, u32 hartid)
@@ -32,21 +32,21 @@ static void mstatus_init(struct sbi_scratch *scratch, u32 hartid)
 
 	/* Enable FPU */
 	if (misa_extension('D') || misa_extension('F'))
-		csr_write(mstatus, MSTATUS_FS);
+		csr_write(CSR_MSTATUS, MSTATUS_FS);
 
 	/* Enable user/supervisor use of perf counters */
 	if (misa_extension('S') &&
 	     sbi_platform_has_scounteren(plat))
-		csr_write(scounteren, -1);
+		csr_write(CSR_SCOUNTEREN, -1);
 	if (sbi_platform_has_mcounteren(plat))
-		csr_write(mcounteren, -1);
+		csr_write(CSR_MCOUNTEREN, -1);
 
 	/* Disable all interrupts */
-	csr_write(mie, 0);
+	csr_write(CSR_MIE, 0);
 
 	/* Disable S-mode paging */
 	if (misa_extension('S'))
-		csr_write(sptbr, 0);
+		csr_write(CSR_SATP, 0);
 }
 
 static int fp_init(u32 hartid)
@@ -60,17 +60,17 @@ static int fp_init(u32 hartid)
 	if (!misa_extension('D') && !misa_extension('F'))
 		return 0;
 
-	if (!(csr_read(mstatus) & MSTATUS_FS))
+	if (!(csr_read(CSR_MSTATUS) & MSTATUS_FS))
 		return SBI_EINVAL;
 
 #ifdef __riscv_flen
 	for (i = 0; i < 32; i++)
 		init_fp_reg(i);
-	csr_write(fcsr, 0);
+	csr_write(CSR_FCSR, 0);
 #else
 	fd_mask = (1 << ('F' - 'A')) | (1 << ('D' - 'A'));
-	csr_clear(misa, fd_mask);
-	if (csr_read(misa) & fd_mask)
+	csr_clear(CSR_MISA, fd_mask);
+	if (csr_read(CSR_MISA) & fd_mask)
 		return SBI_ENOTSUPP;
 #endif
 
@@ -96,12 +96,12 @@ static int delegate_traps(struct sbi_scratch *scratch, u32 hartid)
 			      (1U << CAUSE_LOAD_PAGE_FAULT) |
 			      (1U << CAUSE_STORE_PAGE_FAULT);
 
-	csr_write(mideleg, interrupts);
-	csr_write(medeleg, exceptions);
+	csr_write(CSR_MIDELEG, interrupts);
+	csr_write(CSR_MEDELEG, exceptions);
 
-	if (csr_read(mideleg) != interrupts)
+	if (csr_read(CSR_MIDELEG) != interrupts)
 		return SBI_EFAIL;
-	if (csr_read(medeleg) != exceptions)
+	if (csr_read(CSR_MEDELEG) != exceptions)
 		return SBI_EFAIL;
 
 	return 0;
@@ -230,22 +230,22 @@ void __attribute__((noreturn)) sbi_hart_switch_mode(unsigned long arg0,
 		sbi_hart_hang();
 	}
 
-	val = csr_read(mstatus);
+	val = csr_read(CSR_MSTATUS);
 	val = INSERT_FIELD(val, MSTATUS_MPP, next_mode);
 	val = INSERT_FIELD(val, MSTATUS_MPIE, 0);
 
-	csr_write(mstatus, val);
-	csr_write(mepc, next_addr);
+	csr_write(CSR_MSTATUS, val);
+	csr_write(CSR_MEPC, next_addr);
 
 	if (next_mode == PRV_S) {
-		csr_write(stvec, next_addr);
-		csr_write(sscratch, 0);
-		csr_write(sie, 0);
-		csr_write(satp, 0);
+		csr_write(CSR_STVEC, next_addr);
+		csr_write(CSR_SSCRATCH, 0);
+		csr_write(CSR_SIE, 0);
+		csr_write(CSR_SATP, 0);
 	} else if (next_mode == PRV_U) {
-		csr_write(utvec, next_addr);
-		csr_write(uscratch, 0);
-		csr_write(uie, 0);
+		csr_write(CSR_UTVEC, next_addr);
+		csr_write(CSR_USCRATCH, 0);
+		csr_write(CSR_UIE, 0);
 	}
 
 	register unsigned long a0 asm ("a0") = arg0;
@@ -304,7 +304,7 @@ void sbi_hart_wait_for_coldboot(struct sbi_scratch *scratch, u32 hartid)
 		sbi_hart_hang();
 	
 	/* Set MSIE bit to receive IPI */
-	csr_set(mie, MIP_MSIP);
+	csr_set(CSR_MIE, MIP_MSIP);
 
 	do {
 		spin_lock(&coldboot_wait_bitmap_lock);
@@ -312,14 +312,14 @@ void sbi_hart_wait_for_coldboot(struct sbi_scratch *scratch, u32 hartid)
 		spin_unlock(&coldboot_wait_bitmap_lock);
 
 		wfi();
-		mipval = csr_read(mip);
+		mipval = csr_read(CSR_MIP);
 
 		spin_lock(&coldboot_wait_bitmap_lock);
 		coldboot_wait_bitmap &= ~(1UL << hartid);
 		spin_unlock(&coldboot_wait_bitmap_lock);
 	} while (!(mipval && MIP_MSIP));
 
-	csr_clear(mip, MIP_MSIP);
+	csr_clear(CSR_MIP, MIP_MSIP);
 }
 
 void sbi_hart_wake_coldboot_harts(struct sbi_scratch *scratch, u32 hartid)
diff --git a/lib/sbi_illegal_insn.c b/lib/sbi_illegal_insn.c
index 3f7f4ea..58567f4 100644
--- a/lib/sbi_illegal_insn.c
+++ b/lib/sbi_illegal_insn.c
@@ -127,7 +127,7 @@ int sbi_illegal_insn_handler(u32 hartid, ulong mcause,
 
 	if (unlikely((insn & 3) != 3)) {
 		if (insn == 0) {
-			mstatus = csr_read(mstatus);
+			mstatus = csr_read(CSR_MSTATUS);
 			insn = get_insn(regs->mepc, &mstatus);
 		}
 		if ((insn & 3) != 3)
diff --git a/lib/sbi_ipi.c b/lib/sbi_ipi.c
index 316b2a0..0e9fb30 100644
--- a/lib/sbi_ipi.c
+++ b/lib/sbi_ipi.c
@@ -27,7 +27,7 @@ int sbi_ipi_send_many(struct sbi_scratch *scratch,
 	struct sbi_platform *plat = sbi_platform_ptr(scratch);
 
 	if (pmask)
-		mask &= load_ulong(pmask, csr_read(mepc));
+		mask &= load_ulong(pmask, csr_read(CSR_MEPC));
 
 	/* send IPIs to everyone */
 	for (i = 0, m = mask; m; i++, m >>= 1) {
@@ -46,7 +46,7 @@ int sbi_ipi_send_many(struct sbi_scratch *scratch,
 
 void sbi_ipi_clear_smode(struct sbi_scratch *scratch)
 {
-	csr_clear(mip, MIP_SSIP);
+	csr_clear(CSR_MIP, MIP_SSIP);
 }
 
 void sbi_ipi_process(struct sbi_scratch *scratch)
@@ -64,7 +64,7 @@ void sbi_ipi_process(struct sbi_scratch *scratch)
 		ipi_event = __ffs(ipi_type);
 		switch (ipi_event) {
 		case SBI_IPI_EVENT_SOFT:
-			csr_set(mip, MIP_SSIP);
+			csr_set(CSR_MIP, MIP_SSIP);
 			break;
 		case SBI_IPI_EVENT_FENCE_I:
 			__asm__ __volatile("fence.i");
@@ -83,7 +83,7 @@ void sbi_ipi_process(struct sbi_scratch *scratch)
 int sbi_ipi_init(struct sbi_scratch *scratch, bool cold_boot)
 {
 	/* Enable software interrupts */
-	csr_set(mie, MIP_MSIP);
+	csr_set(CSR_MIE, MIP_MSIP);
 
 	return sbi_platform_ipi_init(sbi_platform_ptr(scratch),
 				     cold_boot);
diff --git a/lib/sbi_misaligned_ldst.c b/lib/sbi_misaligned_ldst.c
index 8522255..8ab01c1 100644
--- a/lib/sbi_misaligned_ldst.c
+++ b/lib/sbi_misaligned_ldst.c
@@ -26,7 +26,7 @@ int sbi_misaligned_load_handler(u32 hartid, ulong mcause,
 				struct sbi_scratch *scratch)
 {
 	union reg_data val;
-	ulong mstatus = csr_read(mstatus);
+	ulong mstatus = csr_read(CSR_MSTATUS);
 	ulong insn = get_insn(regs->mepc, &mstatus);
 	ulong addr = csr_read(CSR_MTVAL);
 	int i, fp = 0, shift = 0, len = 0;
@@ -112,7 +112,7 @@ int sbi_misaligned_store_handler(u32 hartid, ulong mcause,
 				 struct sbi_scratch *scratch)
 {
 	union reg_data val;
-	ulong mstatus = csr_read(mstatus);
+	ulong mstatus = csr_read(CSR_MSTATUS);
 	ulong insn = get_insn(regs->mepc, &mstatus);
 	ulong addr = csr_read(CSR_MTVAL);
 	int i, len = 0;
diff --git a/lib/sbi_timer.c b/lib/sbi_timer.c
index a72c280..a687a5f 100644
--- a/lib/sbi_timer.c
+++ b/lib/sbi_timer.c
@@ -56,14 +56,14 @@ void sbi_timer_event_start(struct sbi_scratch *scratch, u64 next_event)
 {
 	sbi_platform_timer_event_start(sbi_platform_ptr(scratch),
 				       next_event);
-	csr_clear(mip, MIP_STIP);
-	csr_set(mie, MIP_MTIP);
+	csr_clear(CSR_MIP, MIP_STIP);
+	csr_set(CSR_MIE, MIP_MTIP);
 }
 
 void sbi_timer_process(struct sbi_scratch *scratch)
 {
-	csr_clear(mie, MIP_MTIP);
-	csr_set(mip, MIP_STIP);
+	csr_clear(CSR_MIE, MIP_MTIP);
+	csr_set(CSR_MIP, MIP_STIP);
 }
 
 int sbi_timer_init(struct sbi_scratch *scratch, bool cold_boot)
diff --git a/lib/sbi_trap.c b/lib/sbi_trap.c
index fb9ca4f..ba597d8 100644
--- a/lib/sbi_trap.c
+++ b/lib/sbi_trap.c
@@ -94,7 +94,7 @@ int sbi_trap_redirect(struct sbi_trap_regs *regs,
 	csr_write(CSR_SCAUSE, cause);
 
 	/* Set MEPC to S-mode exception vector base */
-	regs->mepc = csr_read(stvec);
+	regs->mepc = csr_read(CSR_STVEC);
 
 	/* Initial value of new MSTATUS */
 	new_mstatus = regs->mstatus;
@@ -141,7 +141,7 @@ void sbi_trap_handler(struct sbi_trap_regs *regs,
 	int rc = SBI_ENOTSUPP;
 	const char *msg = "trap handler failed";
 	u32 hartid = sbi_current_hartid();
-	ulong mcause = csr_read(mcause);
+	ulong mcause = csr_read(CSR_MCAUSE);
 
 	if (mcause & (1UL << (__riscv_xlen - 1))) {
 		mcause &= ~(1UL << (__riscv_xlen - 1));