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| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2023-01-13 19:47:19 +0300 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2023-01-23 08:59:03 +0300 |
| commit | dea0922f867f3d681ad3191fb562a082ea4a339f (patch) | |
| tree | cce4b055c10a9f4eee4fd2276a32afdb5c9f4dcf | |
| parent | 230278dcf127e2a336d54748f03b5bc280656498 (diff) | |
| download | opensbi-dea0922f867f3d681ad3191fb562a082ea4a339f.tar.xz | |
platform: renesas/rzfive: Configure Local memory regions as part of root domain
Renesas RZ/Five RISC-V SoC has Instruction local memory and Data local
memory (ILM & DLM) mapped between region 0x30000 - 0x4FFFF. When a
virtual address falls within this range, the MMU doesn't trigger a page
fault; it assumes the virtual address is a physical address which can
cause undesired behaviours for statically linked applications/libraries.
To avoid this, add the ILM/DLM memory regions to the root domain region
of the PMPU with permissions set to 0x0 for S/U modes so that any access
to these regions gets blocked and for M-mode we grant full access (R/W/X).
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
| -rw-r--r-- | platform/generic/renesas/rzfive/rzfive.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/platform/generic/renesas/rzfive/rzfive.c b/platform/generic/renesas/rzfive/rzfive.c index ca182e3..ee9c9c4 100644 --- a/platform/generic/renesas/rzfive/rzfive.c +++ b/platform/generic/renesas/rzfive/rzfive.c @@ -5,8 +5,27 @@ */ #include <platform_override.h> +#include <sbi/sbi_domain.h> #include <sbi_utils/fdt/fdt_helper.h> +int renesas_rzfive_early_init(bool cold_boot, const struct fdt_match *match) +{ + /* + * Renesas RZ/Five RISC-V SoC has Instruction local memory and + * Data local memory (ILM & DLM) mapped between region 0x30000 + * to 0x4FFFF. When a virtual address falls within this range, + * the MMU doesn't trigger a page fault; it assumes the virtual + * address is a physical address which can cause undesired + * behaviours for statically linked applications/libraries. To + * avoid this, add the ILM/DLM memory regions to the root domain + * region of the PMPU with permissions set to 0x0 for S/U modes + * so that any access to these regions gets blocked and for M-mode + * we grant full access. + */ + return sbi_domain_root_add_memrange(0x30000, 0x20000, 0x1000, + SBI_DOMAIN_MEMREGION_M_RWX); +} + static const struct fdt_match renesas_rzfive_match[] = { { .compatible = "renesas,r9a07g043f01" }, { /* sentinel */ } @@ -14,4 +33,5 @@ static const struct fdt_match renesas_rzfive_match[] = { const struct platform_override renesas_rzfive = { .match_table = renesas_rzfive_match, + .early_init = renesas_rzfive_early_init, }; |