diff options
| author | Bin Meng <bmeng.cn@gmail.com> | 2019-03-14 11:12:44 +0300 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2019-03-18 15:48:16 +0300 |
| commit | e921fc26911bd27cf715483b60c22920812aab21 (patch) | |
| tree | 87b66c90e5c3992f1ad2c7c121f8e4b6686f3105 | |
| parent | 6c39ea99ee681de9e33004aa0075771be351a8cb (diff) | |
| download | opensbi-e921fc26911bd27cf715483b60c22920812aab21.tar.xz | |
platform: plic: Fix comments of programming the interrupt enable register
The codes that currently program the interrupt enable register for
S-mode disagrees with what the comments say. Fix the comments.
While we are here, add one line comment to describe what is done
for M-mode too.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| -rw-r--r-- | platform/common/irqchip/plic.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/platform/common/irqchip/plic.c b/platform/common/irqchip/plic.c index 51e1926..a9ff560 100644 --- a/platform/common/irqchip/plic.c +++ b/platform/common/irqchip/plic.c @@ -86,12 +86,13 @@ int plic_warm_irqchip_init(u32 target_hart, if (plic_hart_count <= target_hart) return -1; + /* By default, disable all IRQs for M-mode of target HART */ if (m_cntx_id > -1) { for (i = 0; i < ie_words; i++) plic_set_ie(m_cntx_id, i, 0); } - /* By default, enable all IRQs for S-mode of target HART */ + /* By default, disable all IRQs for S-mode of target HART */ if (s_cntx_id > -1) { for (i = 0; i < ie_words; i++) plic_set_ie(s_cntx_id, i, 0); |