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| author | Anup Patel <anup.patel@wdc.com> | 2020-05-28 06:07:42 +0300 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2020-06-08 13:11:23 +0300 |
| commit | 1b8c0128f1d79d69ea0a46b758fef4be8dc0a73e (patch) | |
| tree | f7f5a322710d6cd9638444b1130b1662c883f459 /docs | |
| parent | 51f0e4a0533fe8b5d713379ab3a6cb676add82da (diff) | |
| download | opensbi-1b8c0128f1d79d69ea0a46b758fef4be8dc0a73e.tar.xz | |
lib: Add RISC-V hypervisor v0.6.1 support
To support RISC-V hypervisor v0.6.1, we:
1. Don't need to explicitly forward WFI traps from VS/VU-mode
2. Have to delegate virtual instruction trap to HS-mode
3. Have to update trap redirection for changes in HSTATUS CSR
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Diffstat (limited to 'docs')
0 files changed, 0 insertions, 0 deletions