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author | Anup Patel <anup.patel@wdc.com> | 2018-12-31 10:07:28 +0300 |
---|---|---|
committer | Anup Patel <anup@brainfault.org> | 2019-01-02 07:27:12 +0300 |
commit | dc7be34d523f93d2834f4aff49d640cdec16a509 (patch) | |
tree | 1c4951680b3eb2347701a29adf7d91426961735d /firmware/fw_base.S | |
parent | 5ed3cf37073125a38ac839ad11de687f20286b33 (diff) | |
download | opensbi-dc7be34d523f93d2834f4aff49d640cdec16a509.tar.xz |
include: Move RISCV_TRAP_REGS_xyz defines to sbi_trap.h
The struct sbi_trap_regs related defines RISCV_TRAP_REGS_xyz should
be in sbi_trap.h so that we can keep these defines in-sync with changes
in struct sbi_trap_regs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Diffstat (limited to 'firmware/fw_base.S')
-rw-r--r-- | firmware/fw_base.S | 139 |
1 files changed, 70 insertions, 69 deletions
diff --git a/firmware/fw_base.S b/firmware/fw_base.S index d927c3e..ab67a70 100644 --- a/firmware/fw_base.S +++ b/firmware/fw_base.S @@ -11,6 +11,7 @@ #include <sbi/riscv_encoding.h> #include <sbi/sbi_platform.h> #include <sbi/sbi_scratch.h> +#include <sbi/sbi_trap.h> .align 3 .section .entry, "ax", %progbits @@ -236,18 +237,18 @@ _trap_handler: csrrw sp, mscratch, sp /* Setup exception stack */ - add sp, sp, -(RISCV_TRAP_REGS_SIZE) + add sp, sp, -(SBI_TRAP_REGS_SIZE) /* Save RA, T0, T1, and T2 */ - REG_S ra, RISCV_TRAP_REGS_OFFSET(ra)(sp) - REG_S t0, RISCV_TRAP_REGS_OFFSET(t0)(sp) - REG_S t1, RISCV_TRAP_REGS_OFFSET(t1)(sp) - REG_S t2, RISCV_TRAP_REGS_OFFSET(t2)(sp) + REG_S ra, SBI_TRAP_REGS_OFFSET(ra)(sp) + REG_S t0, SBI_TRAP_REGS_OFFSET(t0)(sp) + REG_S t1, SBI_TRAP_REGS_OFFSET(t1)(sp) + REG_S t2, SBI_TRAP_REGS_OFFSET(t2)(sp) /* Save original SP and restore MSCRATCH */ - add t0, sp, RISCV_TRAP_REGS_SIZE + add t0, sp, SBI_TRAP_REGS_SIZE csrrw t0, mscratch, t0 - REG_S t0, RISCV_TRAP_REGS_OFFSET(sp)(sp) + REG_S t0, SBI_TRAP_REGS_OFFSET(sp)(sp) /* Save MEPC and MSTATUS CSRs */ csrr t0, mepc @@ -261,37 +262,37 @@ _trap_handler: */ /* Save MEPC and MSTATUS CSRs */ - REG_S t0, RISCV_TRAP_REGS_OFFSET(mepc)(sp) - REG_S t1, RISCV_TRAP_REGS_OFFSET(mstatus)(sp) + REG_S t0, SBI_TRAP_REGS_OFFSET(mepc)(sp) + REG_S t1, SBI_TRAP_REGS_OFFSET(mstatus)(sp) /* Save all general regisers except SP, RA, T0, T1, and T2 */ - REG_S zero, RISCV_TRAP_REGS_OFFSET(zero)(sp) - REG_S gp, RISCV_TRAP_REGS_OFFSET(gp)(sp) - REG_S tp, RISCV_TRAP_REGS_OFFSET(tp)(sp) - REG_S s0, RISCV_TRAP_REGS_OFFSET(s0)(sp) - REG_S s1, RISCV_TRAP_REGS_OFFSET(s1)(sp) - REG_S a0, RISCV_TRAP_REGS_OFFSET(a0)(sp) - REG_S a1, RISCV_TRAP_REGS_OFFSET(a1)(sp) - REG_S a2, RISCV_TRAP_REGS_OFFSET(a2)(sp) - REG_S a3, RISCV_TRAP_REGS_OFFSET(a3)(sp) - REG_S a4, RISCV_TRAP_REGS_OFFSET(a4)(sp) - REG_S a5, RISCV_TRAP_REGS_OFFSET(a5)(sp) - REG_S a6, RISCV_TRAP_REGS_OFFSET(a6)(sp) - REG_S a7, RISCV_TRAP_REGS_OFFSET(a7)(sp) - REG_S s2, RISCV_TRAP_REGS_OFFSET(s2)(sp) - REG_S s3, RISCV_TRAP_REGS_OFFSET(s3)(sp) - REG_S s4, RISCV_TRAP_REGS_OFFSET(s4)(sp) - REG_S s5, RISCV_TRAP_REGS_OFFSET(s5)(sp) - REG_S s6, RISCV_TRAP_REGS_OFFSET(s6)(sp) - REG_S s7, RISCV_TRAP_REGS_OFFSET(s7)(sp) - REG_S s8, RISCV_TRAP_REGS_OFFSET(s8)(sp) - REG_S s9, RISCV_TRAP_REGS_OFFSET(s9)(sp) - REG_S s10, RISCV_TRAP_REGS_OFFSET(s10)(sp) - REG_S s11, RISCV_TRAP_REGS_OFFSET(s11)(sp) - REG_S t3, RISCV_TRAP_REGS_OFFSET(t3)(sp) - REG_S t4, RISCV_TRAP_REGS_OFFSET(t4)(sp) - REG_S t5, RISCV_TRAP_REGS_OFFSET(t5)(sp) - REG_S t6, RISCV_TRAP_REGS_OFFSET(t6)(sp) + REG_S zero, SBI_TRAP_REGS_OFFSET(zero)(sp) + REG_S gp, SBI_TRAP_REGS_OFFSET(gp)(sp) + REG_S tp, SBI_TRAP_REGS_OFFSET(tp)(sp) + REG_S s0, SBI_TRAP_REGS_OFFSET(s0)(sp) + REG_S s1, SBI_TRAP_REGS_OFFSET(s1)(sp) + REG_S a0, SBI_TRAP_REGS_OFFSET(a0)(sp) + REG_S a1, SBI_TRAP_REGS_OFFSET(a1)(sp) + REG_S a2, SBI_TRAP_REGS_OFFSET(a2)(sp) + REG_S a3, SBI_TRAP_REGS_OFFSET(a3)(sp) + REG_S a4, SBI_TRAP_REGS_OFFSET(a4)(sp) + REG_S a5, SBI_TRAP_REGS_OFFSET(a5)(sp) + REG_S a6, SBI_TRAP_REGS_OFFSET(a6)(sp) + REG_S a7, SBI_TRAP_REGS_OFFSET(a7)(sp) + REG_S s2, SBI_TRAP_REGS_OFFSET(s2)(sp) + REG_S s3, SBI_TRAP_REGS_OFFSET(s3)(sp) + REG_S s4, SBI_TRAP_REGS_OFFSET(s4)(sp) + REG_S s5, SBI_TRAP_REGS_OFFSET(s5)(sp) + REG_S s6, SBI_TRAP_REGS_OFFSET(s6)(sp) + REG_S s7, SBI_TRAP_REGS_OFFSET(s7)(sp) + REG_S s8, SBI_TRAP_REGS_OFFSET(s8)(sp) + REG_S s9, SBI_TRAP_REGS_OFFSET(s9)(sp) + REG_S s10, SBI_TRAP_REGS_OFFSET(s10)(sp) + REG_S s11, SBI_TRAP_REGS_OFFSET(s11)(sp) + REG_S t3, SBI_TRAP_REGS_OFFSET(t3)(sp) + REG_S t4, SBI_TRAP_REGS_OFFSET(t4)(sp) + REG_S t5, SBI_TRAP_REGS_OFFSET(t5)(sp) + REG_S t6, SBI_TRAP_REGS_OFFSET(t6)(sp) /* Call C routine */ add a0, sp, zero @@ -299,36 +300,36 @@ _trap_handler: call sbi_trap_handler /* Restore all general regisers except SP, RA, T0, T1, T2, and T3 */ - REG_L gp, RISCV_TRAP_REGS_OFFSET(gp)(sp) - REG_L tp, RISCV_TRAP_REGS_OFFSET(tp)(sp) - REG_L s0, RISCV_TRAP_REGS_OFFSET(s0)(sp) - REG_L s1, RISCV_TRAP_REGS_OFFSET(s1)(sp) - REG_L a0, RISCV_TRAP_REGS_OFFSET(a0)(sp) - REG_L a1, RISCV_TRAP_REGS_OFFSET(a1)(sp) - REG_L a2, RISCV_TRAP_REGS_OFFSET(a2)(sp) - REG_L a3, RISCV_TRAP_REGS_OFFSET(a3)(sp) - REG_L a4, RISCV_TRAP_REGS_OFFSET(a4)(sp) - REG_L a5, RISCV_TRAP_REGS_OFFSET(a5)(sp) - REG_L a6, RISCV_TRAP_REGS_OFFSET(a6)(sp) - REG_L a7, RISCV_TRAP_REGS_OFFSET(a7)(sp) - REG_L s2, RISCV_TRAP_REGS_OFFSET(s2)(sp) - REG_L s3, RISCV_TRAP_REGS_OFFSET(s3)(sp) - REG_L s4, RISCV_TRAP_REGS_OFFSET(s4)(sp) - REG_L s5, RISCV_TRAP_REGS_OFFSET(s5)(sp) - REG_L s6, RISCV_TRAP_REGS_OFFSET(s6)(sp) - REG_L s7, RISCV_TRAP_REGS_OFFSET(s7)(sp) - REG_L s8, RISCV_TRAP_REGS_OFFSET(s8)(sp) - REG_L s9, RISCV_TRAP_REGS_OFFSET(s9)(sp) - REG_L s10, RISCV_TRAP_REGS_OFFSET(s10)(sp) - REG_L s11, RISCV_TRAP_REGS_OFFSET(s11)(sp) - REG_L t3, RISCV_TRAP_REGS_OFFSET(t3)(sp) - REG_L t4, RISCV_TRAP_REGS_OFFSET(t4)(sp) - REG_L t5, RISCV_TRAP_REGS_OFFSET(t5)(sp) - REG_L t6, RISCV_TRAP_REGS_OFFSET(t6)(sp) + REG_L gp, SBI_TRAP_REGS_OFFSET(gp)(sp) + REG_L tp, SBI_TRAP_REGS_OFFSET(tp)(sp) + REG_L s0, SBI_TRAP_REGS_OFFSET(s0)(sp) + REG_L s1, SBI_TRAP_REGS_OFFSET(s1)(sp) + REG_L a0, SBI_TRAP_REGS_OFFSET(a0)(sp) + REG_L a1, SBI_TRAP_REGS_OFFSET(a1)(sp) + REG_L a2, SBI_TRAP_REGS_OFFSET(a2)(sp) + REG_L a3, SBI_TRAP_REGS_OFFSET(a3)(sp) + REG_L a4, SBI_TRAP_REGS_OFFSET(a4)(sp) + REG_L a5, SBI_TRAP_REGS_OFFSET(a5)(sp) + REG_L a6, SBI_TRAP_REGS_OFFSET(a6)(sp) + REG_L a7, SBI_TRAP_REGS_OFFSET(a7)(sp) + REG_L s2, SBI_TRAP_REGS_OFFSET(s2)(sp) + REG_L s3, SBI_TRAP_REGS_OFFSET(s3)(sp) + REG_L s4, SBI_TRAP_REGS_OFFSET(s4)(sp) + REG_L s5, SBI_TRAP_REGS_OFFSET(s5)(sp) + REG_L s6, SBI_TRAP_REGS_OFFSET(s6)(sp) + REG_L s7, SBI_TRAP_REGS_OFFSET(s7)(sp) + REG_L s8, SBI_TRAP_REGS_OFFSET(s8)(sp) + REG_L s9, SBI_TRAP_REGS_OFFSET(s9)(sp) + REG_L s10, SBI_TRAP_REGS_OFFSET(s10)(sp) + REG_L s11, SBI_TRAP_REGS_OFFSET(s11)(sp) + REG_L t3, SBI_TRAP_REGS_OFFSET(t3)(sp) + REG_L t4, SBI_TRAP_REGS_OFFSET(t4)(sp) + REG_L t5, SBI_TRAP_REGS_OFFSET(t5)(sp) + REG_L t6, SBI_TRAP_REGS_OFFSET(t6)(sp) /* Load T0 and T1 with MEPC and MSTATUS */ - REG_L t0, RISCV_TRAP_REGS_OFFSET(mepc)(sp) - REG_L t1, RISCV_TRAP_REGS_OFFSET(mstatus)(sp) + REG_L t0, SBI_TRAP_REGS_OFFSET(mepc)(sp) + REG_L t1, SBI_TRAP_REGS_OFFSET(mstatus)(sp) /* * Note: Jump here after fast trap handling @@ -342,12 +343,12 @@ _trap_handler: csrw mstatus, t1 /* Restore RA, T0, T1, and T2 */ - REG_L ra, RISCV_TRAP_REGS_OFFSET(ra)(sp) - REG_L t0, RISCV_TRAP_REGS_OFFSET(t0)(sp) - REG_L t1, RISCV_TRAP_REGS_OFFSET(t1)(sp) - REG_L t2, RISCV_TRAP_REGS_OFFSET(t2)(sp) + REG_L ra, SBI_TRAP_REGS_OFFSET(ra)(sp) + REG_L t0, SBI_TRAP_REGS_OFFSET(t0)(sp) + REG_L t1, SBI_TRAP_REGS_OFFSET(t1)(sp) + REG_L t2, SBI_TRAP_REGS_OFFSET(t2)(sp) /* Restore SP */ - REG_L sp, RISCV_TRAP_REGS_OFFSET(sp)(sp) + REG_L sp, SBI_TRAP_REGS_OFFSET(sp)(sp) mret |