diff options
| author | Atish Patra <atish.patra@wdc.com> | 2019-03-07 02:18:29 +0300 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2019-03-07 05:37:18 +0300 |
| commit | 007a6b26d9a22a9dc49ede12115a8704f634dad0 (patch) | |
| tree | eac6b3c56b4f262ae5a60e0fa42b4a809b87e1cf /firmware | |
| parent | b225583881c82eaab3059af9277c091432d50266 (diff) | |
| download | opensbi-007a6b26d9a22a9dc49ede12115a8704f634dad0.tar.xz | |
firmware: Reset all registers and flush icache
A warm reset using reset button may put icache and registers
in non-coherent state.
Flush the icache and reset all registers for every hart.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Diffstat (limited to 'firmware')
| -rw-r--r-- | firmware/fw_base.S | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/firmware/fw_base.S b/firmware/fw_base.S index dccaef1..cf2c6a0 100644 --- a/firmware/fw_base.S +++ b/firmware/fw_base.S @@ -25,6 +25,8 @@ _start: csrr a6, CSR_MHARTID blt zero, a6, _wait_for_boot_hart + li ra, 0 + call _reset_regs /* Zero-out BSS */ la a4, _bss_start la a5, _bss_end @@ -392,6 +394,8 @@ _trap_handler_all_mode: .globl _reset_regs _reset_regs: + /* flush the instruction cache */ + fence.i /* Reset all registers except ra, a0,a1 */ li sp, 0 li gp, 0 |