diff options
| author | Atish Patra <atish.patra@wdc.com> | 2019-03-05 01:08:17 +0300 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2019-03-06 06:29:54 +0300 |
| commit | 27fae182dc54e08314034a03eeb583b94c64f4c8 (patch) | |
| tree | 2bd0736758f12b7b49e87179afc44dac1e2ff52d /firmware | |
| parent | d4dd2b37f3a80fc99345930879721499cf9e0c8a (diff) | |
| download | opensbi-27fae182dc54e08314034a03eeb583b94c64f4c8.tar.xz | |
firmware: Reset all the general purpose registers to zero.
A warm reset by pressing the reset button may not initialize all the
registers to zero. Do it for every hart during warm boot.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Diffstat (limited to 'firmware')
| -rw-r--r-- | firmware/fw_base.S | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/firmware/fw_base.S b/firmware/fw_base.S index 83fe2aa..1725a92 100644 --- a/firmware/fw_base.S +++ b/firmware/fw_base.S @@ -120,6 +120,9 @@ _wait_for_boot_hart: beqz a5, _wait_for_boot_hart _start_warm: + li ra, 0 + call _reset_regs + /* Disable and clear all interrupts */ csrw CSR_MIE, zero csrw CSR_MIP, zero @@ -380,3 +383,41 @@ _trap_handler_all_mode: REG_L sp, SBI_TRAP_REGS_OFFSET(sp)(sp) mret + + .align 3 + .section .entry, "ax", %progbits + .globl _reset_regs +_reset_regs: + + /* Reset all registers except ra, a0,a1 */ + li sp, 0 + li gp, 0 + li tp, 0 + li t0, 0 + li t1, 0 + li t2, 0 + li s0, 0 + li s1, 0 + li a2, 0 + li a3, 0 + li a4, 0 + li a5, 0 + li a6, 0 + li a7, 0 + li s2, 0 + li s3, 0 + li s4, 0 + li s5, 0 + li s6, 0 + li s7, 0 + li s8, 0 + li s9, 0 + li s10, 0 + li s11, 0 + li t3, 0 + li t4, 0 + li t5, 0 + li t6, 0 + csrw CSR_MSCRATCH, 0 + + ret |