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| author | Atish Patra <atish.patra@wdc.com> | 2019-01-21 10:23:28 +0300 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2019-01-22 07:33:49 +0300 |
| commit | 312b6bf32f51e530dd22746fe2a36d6459e29588 (patch) | |
| tree | f7f9270897139dce8886b1db11f02cc087559f9f /include/sbi/riscv_asm.h | |
| parent | 784a4657c0957e7f9561fd2d87930ba008643c1e (diff) | |
| download | opensbi-312b6bf32f51e530dd22746fe2a36d6459e29588.tar.xz | |
lib: Add atomic bit set/clear operations.
Add addtional functionlities for set/clear bits
atomically.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Diffstat (limited to 'include/sbi/riscv_asm.h')
| -rw-r--r-- | include/sbi/riscv_asm.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/sbi/riscv_asm.h b/include/sbi/riscv_asm.h index 6e1bff7..b7a8d4e 100644 --- a/include/sbi/riscv_asm.h +++ b/include/sbi/riscv_asm.h @@ -30,6 +30,7 @@ #define LGREG __REG_SEL(3, 2) #if __SIZEOF_POINTER__ == 8 +#define BITS_PER_LONG 64 #ifdef __ASSEMBLY__ #define RISCV_PTR .dword #define RISCV_SZPTR 8 @@ -40,6 +41,7 @@ #define RISCV_LGPTR "3" #endif #elif __SIZEOF_POINTER__ == 4 +#define BITS_PER_LONG 32 #ifdef __ASSEMBLY__ #define RISCV_PTR .word #define RISCV_SZPTR 4 |